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FUJITSU SEMICONDUCTOR MB90460 Series handbook

1. Dimensions in mm inches MB90460 Series 64 Plastic LQFP FPT 64P M09 Note Pins width and pins thickness include plating thickness 14 00 0 20 551 008 SQ 12 00 0 10 472 004 SQ uu 0 145 0 055 0057 0022 5 O ze E CU e 0 10 004 Em Details of A part o 1 502010 rm 059555 Mounting height 0 25 010 INDEX LI Fra HEHHRHBHBEHHBHHH u 0 50 0 20 0 10 0 10 N 020 008 004 004 m Stand off 0 65 026 0 32 0 05 024 006 0 13 005 013 002 2001 FUJITSU LIMITED F64018S c 2 4 Dimensions in mm inches 83 MB90460 Series 84 64 pin Plastic SH DIP DIP 64P M01 Note Pins width and pins thickness include plating thickness
2. The current value is preliminary value may be subject to change for enhanced characteristics without previous notice The power supply current is measured with an external clock 67 MB90460 Series 68 4 AC Characteristics 1 Clock Timings Vcc 5 0 V 10 Vss AVss 0 0 V TA 40 C to 85 C Parameter Remarks Crystal oscillator Clock frequency External clock 2 Clock cycle time Frequency fluctuation rate locked Recommened duty ratio of Input clock pulse width 30 to 70 Input clock rise fall time External clock operation Internal operating clock Main clock operation Internal operating clock cycle time Main clock operation 1 The frequency fluctuation rate is the maximum deviation rate of the preset center frequency when the multiplied PLL signal is locked 2 Internal operating clock frequency must not be over 16 MHz Center la Af x 100 frequency o MB90460 Series Relationship between internal operating clock frequency and power supply voltage A Operation guarantee range of MB90F462 i Operation guarantee range of MB90462 MB90467 MB90V460 Power supply voltage Vcc V i 1 3 8 12 16 Internal clock MHz Relationship between oscillating frequency and internal operating clock frequency Multipl
3. Standby control SPL 1 Block diagram of Port 6 pins euJeju Resource output Resource input r Resource output enable i Standby control SPL 1 MI External interrupt enable 35 MB90460 Series 3 Timebase Timer The timebase timer is an 18 bit free running counter timebase counter that counts up in synchronization to the internal count clock main oscillator clock divided by 2 Features of timebase timer Interrupt generated when counter overflow El OS supported e Interval timer function An interrupt generated at four different time intervals Clock supply function Four different clocks can be selected as a watchdog timer s count clock Supply clock for oscillation stabilization Block Diagram TO watchdog Timebase timer timer counter Divide by two HCLK OF Counter clear gt Setting time selector gt J in the clock control Counter section clear circuit To the oscillation Power on reset Stop mode start CKSCR MCS 1 to 0 1 Interval timer selector TBOF clear Timebase timer interrupt signal 36 24 2 set Timebase timer interrpt register TBTC rete TER 1 OF Overflow HCLK Oscillation clock 1 Switching of the machine
4. O Available x Not available Note For more information about each package see section BI PACKAGE DIMENSIONS DIFFERENCES AMONG PRODUCTS Memory Size In evaluation with an evaluation product note the difference between the evaluation product and the product actually used The following items must be taken into consideration The MB90V460 does not have an internal ROM however operations equivalent to chips with an internal ROM can be evaluated by using a dedicated development tool enabling selection of ROM size by settings of the development tool In the MB90V460 images from FF4000u to FFFFFFu are mapped to bank 00 and 0000 to are mapped to bank FF only This setting can be changed by configuring the development tool In the MB90462 F462 467 images from FF40004 to FFFFFFH are mapped to bank 00 and 0000 to FF3FFFH are mapped to bank FF only MB90460 Series PIN ASSIGNMENT TOP VIEW GELER 68666 2552970 EEEEE LLLA TERRE O Q OR OD st st xr CO 9 CO eo ot CO o XO CO CO LO LO LO LO LO LO LO LO P44 SNI1 2 P30 1 RTO0 P45 SNI2 2 Vss P46 PPG2 P27 IN3 P50 AN0 P26 IN2 P51 AN1 P25 IN1 P52 AN2 P24 INO P53 AN3 P23 PWO1 P54 AN4 P22 PWI1 P55 AN5 P21 TO1 P56 AN6 P20 TIN1 P57 AN7 P17 FRCK AVcc P16 INT6 TO0 AVR P15 INT5 TINO A
5. MB90460 Series 7 Multi functional 16 bit multi functional timer module consists of one 16 bit free running timer four input capture circuits six output comparators and one channel of 16 bit PPG timer This module allows six independent waveforms generated by PPG timer or waveform generator to be outputted With the 16 bit free run timer and the input capture circuit a input pulse width measurement and external clock cycle measurement can be done 1 16 bit free running timer 1 channel The 16 bit free running timer consists of a 16 bit up up down counter control register 16 bit compare clear register with buffer register and a prescaler 8 types of counter operation clock p 2 0 4 0 8 0 16 0 32 0 64 6 128 can be selected is the machine clock Two types of interrupt causes Compare clear interrupt is generated when there is a comparing match with compare clear register and 16 bit free run timer Zero detection interrupt is generated while 16 bit free running timer is detected as zero in count value El2OS supported The compare clear register has a selectable buffer register into which data is written for transfer to the compare clear register When the timer is stopped transfer occurs immediately when the data is written to the buffer When the timer is operation data transfer from the buffer occurs when the timer value is detected to be zero Reset so
6. Low power mode control register LPMCR set ner mo car ooo es Pin high impedance Pin Hi z control control circuit Internal reset generation Internal reset circuit CPU intermittent operation selecter Select intermittent cycles Release reset RST Standby control Stop and sleep signals circuit CPU clock CPU clock control circuit Cancel interrupt Stop signal Peripheral clock nae Peripheral clock control circuit Machine clock Oscillation stabilization Clock generator wait is passed Clock selector Oscillation stabilization wait interval selector EE EE Clock selection register CKSCR x1 Pin System clock Timebase timer generation circuit 31 32 MB90460 Series 2 Ports 1 Outline of I O ports When data register serving for control output is read the data output from it as a control output is read regardless of the value in the direction register Note that if a read modify write instruction such as a bit set instruction is used to preset output data in the data register when changing its setting from input to output the data read is not the data register latched value but the input data from the pin Ports 0 to 4 and 6 are input output ports which serve as inputs when the direction register value is 0 or as outputs when the value is
7. Vcc power input pin for analog circuits Reference voltage input pin for the A D converter This volt age must not exceed Vcc and AVcc Reference voltage is fixed to AVss Vss power input pin for analog circuits General purpose I O ports Serial data input pin for UART channel 1 While UART channel 1 is operating for input the input of this pin is used as required and must not be used for any other in put General purpose I O ports Serial data output pin for UART channel 1 This function is en abled when UART channel 1 enables data output Continued 11 MB90460 Series 12 Continued UO circuit Function General purpose I O port Serial clock I O pin for UART channel 1 This function is enabled when UART channel 1 enables clock output General purpose I O port Usable as interrupt request input channel 7 Input is enabled when 1 is set in EN7 in standby mode Input pin for operation mode specification Connect this pin di rectly to Vcc or Vss Input pin for operation mode specification Connect this pin di rectly to Vcc or Vss Power 0 V input pin Power 5 V input pin 1 4 FPT 64P M09 8 MB90V460 MB90F462 MB90462 only FPT 64P M06 DIP 64P MO1 Capacity pin for power stabilization Please connect to an ap proximately 0 1 uF ceramic capacitor They do
8. FUJITSU SEMICONDUCTOR DATA SHEET DS07 13714 1E 16 bit Proprietary Microcontroller CMOS F MC 16LX MB90460 Series MB90462 467 F462 V460 DESCRIPTION The MB90460 series is a line of general purpose Fujitsu 16 bit microcontrollers designed for process control applications which require high speed real time processing such as consumer products While inheriting the AT architecture of the F MC family the instruction set for the FFMC 16LX CPU core of the MB90460 series incorporates additional instructions for high level languages supports extended addressing modes and contains enhanced multiplication and division instructions as well as a substantial collection of improved bit manipulation instructions In addition the MB90460 has an on chip 32 bit accumulator which enables processing of long word data The peripheral resources integrated in the MB90460 series include an 8 10 bit A D converter UARTs SCI 0 to 1 16 bit PPG timer a multi functional timer 16 bit free run timer input capture units ICUs 0 to 3 output compare units OCUs 0 and 5 16 bit PPG timer a waveform generator a multi pulse generator 16 bit PPG timer 16 bit reload timer waveform sequencer PWC 0 to 1 16 bit reload timer and DTP external interrupt F2MC stands for FUJITSU Flexible Microcontroller a registered trademark of FUJITSU LIMITED FEATURES Minimum execution time 62 5 ns 4 MHz oscillation Us
9. P04 FPT 64P M09 1 Heavy current pins 2 MB90V460 MB90F462 MB90462 only They do not exist on MB90467 because there are not PWC ch 0 16 bit PPG ch 1 and waveform sequencer Continued MB90460 Series Continued P36 PPG1 2 P37 PPGO P40 SINO P41 SOTO P42 SCKO P43 SNI0 2 P44 SNI1 2 P45 SNI2 2 P46 PPG2 P50 ANO P51 AN1 P52 AN2 P53 AN3 P54 AN4 P55 AN5 P56 AN6 P57 AN7 AVcc AVR AVss P60 SIN1 P61 SOT1 P62 SCK1 P63 INT7 1 Heavy current pins 2 MB90V460 MB90F462 MB90462 TOP VIEW P35 1 RTO5 Z P34 1 RTO4 W P33 1 RTO3 Y P32 1 RTO2 V P31 1 RTO1 X P30 1 RTOO Vss P27 IN3 P26 IN2 P25 IN1 P24 INO P23 PWO1 P22 PWI1 P21 TO1 P20 TIN1 P17 FRCK P16 INT6 TOO P15 INT5 TINO P14 INTA P13 INT3 P12 INT2 DTTI1 2 P11 INT1 P10 INTO DTTIO PO7 PWO0 2 P06 PWI0 2 P05 1 OPT5 2 P04 1 OPT4 2 P03 1 OPT3 2 P02 1 OPT2 2 01 1 1 2 P00 1 OPT0 2 DIP 64P M01 They do not exist on MB90467 because there are not PWC ch 0 16 bit PPG ch 1 and waveform sequencer MB90460 Series PIN DESCRIPTION SDIP RST y o circuit Function Oscillation input pins External reset input pin P00 to P05 OPTO to 5 General purpose ports Output terminals OPTO to 5 of the waveform sequencer These pins output the waveforms specified at the output data registers of the waveform sequen
10. Flash Memory Control status Address 0000 INTE lu nas sha LPM1 LMP0 Read write R W R W R W R Initial value gt 0 0 0 1 b iu lt Bit number FMCS MB90460 Series 2 Sector configuration of 512Kbit flash memory The 512 Kbit flash memory has the sector configuration illustrated below The addresses in the illustration are the upper and lower addresses of each sector When accessed from the CPU SA0 to SA3 are allocated in the FF bank registers respectively Flash memory SA3 16 Kbytes SA2 8 Kbytes SA1 8 Kbytes 32 Kbytes Programmer addresses correspond to CPU addresses when data is programmed in flash memory by a parallel programmer Programmer addresses are used to program erase data using a general purpose programmer 62 CPU address FFFFFFH FFC000H FFBFFFH FFA000H FF9FFFH FF8000H FF7FFFH FF0000H Writer address 7FFFFH 7C000H 7BFFFH 7A000H 79FFFH 78000H 77FFFH 70000H ELECTRICAL CHARACTERISTICS 1 Absolute Maximum Ratings Parameter Power supply voltage Rating Min Max Unit MB90460 Series Vss AVss 0 0 V Remarks Vss 6 0 Vcc gt AVcc Vss 6 0 AVcc 2 AVR AVR 2 AVss Input voltage Vss 6 0 2 Output voltage Vss 6 0 2 Maximum clamp current cLAMP 2 0 4 Total maximum clamp current gt L level
11. Abbrevia tion SMR0 Register Serial mode register 0 Byte access R W MB90460 Series Word access R W 0000214 SCRO Serial control register 0 R W R W 000022 000023 SIDRO SODRO SSRO Input data register 0 output data register O Serial status register 0 R W R W Resource name Initial value 000000008 000001 00s UARTO XXXXXXXXB 000010008 0000244 SMR1 Serial mode register 1 000025 SCR1 Serial control register 1 000026 SIDR1 SODR1 Input data register 1 output data register 1 000027H SSR1 Status register 1 00000000 00000100 UART1 XXXXXXXXB 000010008 0000284 0000294 PWCSL1 PWCSH1 PWC control status register CH1 00002 00002 PWC1 PWC data buffer register CH1 00002 DIV1 Divide ratio control register CH1 R W 00000000 00000000 XXXXXXXXB XXXXXXXXB PWC timer CH1 000020 2FH Prohibited area 000030 000031 ENIR EIRR Interrupt DTP enable register Interrupt DTP cause register R W R W 000032H ELVRL Request level setting register Lower Byte R W 000033 ELVRH Request level setting register Higher Byte 00000000 DTP external interrupt 000000005 000000008 0000344 ADCSO A D control status register 0 000035H ADCS1 A D
12. FFFF74H Continued MB90460 Series Continued Interrupt control register Priority 2 Number Address ICR Address Input capture channels 2 3 FFFF70H Timebase timer FFFF6CH UART1 receive FFFF68u UART1 send FFFF64u UARTO receive FFFF60u UARTO send FFFF5CH Flash memory status FFFF58H EI20S Interrupt vector Interrupt cause support 0000 0000 0 0000 0000 Delayed interrupt generator module FFFF54u O x A Can be used and support the EI OS stop request Can be used and interrupt request flag is cleared by EI OS interrupt clear signal Cannot be used Usable when an interrupt cause that shares the ICR is not used 29 MB90460 Series PERIPHERAL RESOURCES 1 Low Power Consumption Control Circuit The MB90460 series has the following CPU operating mode configured by selection of an operating clock and clock operation control Clock mode PLL clock mode A PLL clock that is a multiple of the oscillation clock HCLK frequency is used to operate the CPU and peripheral functions Main clock mode The main clock with a frequency one half that of the oscillation clock HCLK is used to operate the CPU and peripheral functions In main clock mode the PLL multiplier circuit is inactive CPU intermittent operation mode CPU intermittent operation mode causes the CPU to operate intermittently while high speed clock
13. NCCR Register P15 INT5 TINO P43 SNIO Pin POSITION P44 SNI1 DETECT CIRCUIT Pin P45 SNI2 Pin ee dq e ee WTS0 COMPARE MATCH INTERRUPT gt Interrupt 28 MB90460 Series 9 PWC PWC pulse width count timer is 16 bit multi function up counter with reload timer functions input signal pulse width count functions as well The PWC timer consists of a 16 bit counter on input pulse divider a divide ratio control register a count input pin a pulse output pin and a 16 bit control register The PWC timer has the following features Interrupt generated when timer overflow or end of PWC measurement El OS supported Timer functions Generates an interrupt request at set time intervals Outputs pulse signals synchronized with the timer cycle Selects the counter clock from among three internal clocks Pulse width count functions Counts the time between external pulse input events Selects the counter clock from among three internal clocks Count mode H pulse width rising edge to falling edge L pulse width falling edge to rising edge Rising edge cycle rising edge to falling edge Falling edge cycle falling edge to rising edge Count between edges rising or falling edge to falling or rising edge Capable of counting cycles by dividing input pulses by 2 2 25 28 using an 8 bit input divider
14. Serial status register 0 1 Pin SOTO 1 Start of transmission EPOS generation signal to CPU 54 11 DTP External Interrupts The DTP external interrupt circuit is activated by the signal supplied to a DTP external interrupt pin The CPU accepts the signal using the same procedure it uses for normal hardware interrupts and generates external MB90460 Series interrupts or activates the extended intelligent service EI OS Features of DTP External Interrupt Total 8 external interrupt channels e Two request levels CH and L are provided for the intelligent I O service Four request levels rising edge falling edge level and L level are provided for external interrupt requests Block Diagram Request level setting register ELVR EE EEE EEE 2 EEE P63 INT7 P16 INT6 TO0 Y B i 2 2 X2 Wa 4 P10 INTO DTTIO P15 INT5 TINO Y Y P14 INT4 Interru pt request number 20 14 22 16 25 19 27 1 55 MB90460 Series 12 Delayed Interrupt Generation Module The delayed interrupt generation module is used to generate a task switching interrupt Interrupt requests to the F2MC 16LX CPU can be gener
15. 000068H 000069H PICSL01 PICSH01 PPG output control Input capture control status register 01 lower PPG output control Input capture control status register 01 upper 00006 ICSL23 Input capture control status register 23 lower 00006 ICSH23 Input capture control status register 23 upper Resource name Initial value XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB 16 bit input capture CH0 to CH3 00000000 00000000 00000000 00006Cu to 6 Prohibited area 00006 ROMM ROM mirroring function selection register W ROM mirroring function 000070 000071 OCCPBO OCCPO Output compare buffer register output compare register 0 000072 000073 1 Output compare buffer register output compare register 1 0000744 000075 OCCPB2 OCCP2 Output compare buffer register output compare register 2 000076 000077 Output compare buffer register output compare register 3 000078 000079 OCCPB4 OCCP4 Output compare buffer register output compare register 4 00007 00007 5 5 Output compare buffer register output compare register 5 XXXXXXXXB Output compare CHO to CH5 Continued 23 24 MB90460 Series Address 0000
16. SCK T 5 valid SIN hold time SCKOto SCK1 SINO to SIN1 80 pF 1 TTL for an output pin of external shift clock mode Note These are AC ratings in the CLK synchronous mode CL is the load capacitance value connected to pins while testing is machine cycle time unit ns MB90460 Series Internal shift clock mode SCK SOT SIN External shift clock mode SCK SOT SIN tsLsH 0 2 Vcc 0 2 Vcc 73 MB90460 Series 5 Resources Input Timing Value Parameter Symbol Pin name Condition Min Max Input pulse width Vcc 5 0 V 10 Vss AVss 0 0 V TA 40 C to 85 IN0 to IN3 SNI0 to SNI2 TINO to TIN1 PWIO to PWI1 DTTIO DTTI1 Remarks 1 0 7 for PWIO input pin 2 0 3 for PWIO Input pin 0 8 Vcc 0 2 2 0 2 Vcc 6 Trigger Input Timimg Condition Value Vcc 5 0 V 10 Vss AVss 0 0 V TA 40 C to 85 C ml pen Min Max TRGL 74 5 A D Converter Electrical Characteristics 3 0 V lt AVR AVss Vcc AVcc 5 0 V 10 Vss AVss 0 0 V TA 40 C to 85 C Parameter Resolution MB90460 Series Remarks Total error For MB90F462 MB90462 MB90467 For MB90V460 Non linear error Differentia
17. The conversion can be activated by software 16 bit reload timer 1 rising edge and 16 bit free running timer zero detection edge 58 MB90460 Series Block Diagram AVcc AVR AVss lt m D A converter Sequential compare register Data register ADCR0 1 Input circuit Comparator Sample and hold circuit A D control register 0 A D control register 1 Operation clock Prescaler ADCS0 1 16 bit reload timer 1 16 bit free running timer zero detection Machine clock F2MC 16LX bus MB90460 Series 14 ROM Correction Function In the case that the address of the instruction after the one that a program is currently processing matches the address configured in the detection address configuration register the program forces the next instruction to be processed into an INT9 instruction and branches to the interrupt process program Since processing can be conducted using INT9 interrupts programs can be repaired using batch processing eOverview of the Rom correction Function The address of the instruction after the one that a program is currently processing is always stored in an address latch via the internal data bus Address match detection constantly compares the address stored in the address latch with the one configured in the detection address configuration register If the two compared addresses matc
18. Features of the 16 bit reload timer Interrupt generated when timer underflow El OS supported nternal clock operating mode Three internal count clocks can be selected Counter can be activated by software or exteranl trigger singal at TIN1 TINO pin Counter can be reloaded or stopped when underflow after activated Event count operating mode Counter counts down by one when specified edge at TIN1 TINO pin Counter can be reloaded or stopped when underflow MB90460 Series Block Diagram F2MC 16LX Bus TMRD0 1 lt TMRD1 gt 16 bit reload register TMRO lt TMR1 gt Reload signal Reload control circuit 16 bit timer register Count clock generation circuit Valid clock judgment circuit Machine clock Prescaler To UARTO and UART1 1 lt To the A D converter gt Internal clock Output signal Input Clock generation control selector circuit P15 TINO circuit EN P16 TOO lt P20 TIN1 gt xtarnal clock lt P21 TO1 gt Output control circuit Operation control circuit EE EE Function selection 1 Timer control status register TMCSRO lt TMCSR1 gt Interrupt request signal lt gt 30 1EH 2 lt 32 20H gt 1 This register includes channel 0 and channel 1 The register enclosed in lt and gt indicates the channel 1 register
19. y o circuit Function General purpose ports Can be used as interrupt request input channels 6 Input is en abled when 1 is set in EN6 in standby mode Event output pin for reload timer O General purpose ports External clock input pin for free running timer General purpose ports External clock input pin for reload timer 1 General purpose ports Event output pin for reload timer 1 General purpose ports PWC 1 signal input pin General purpose ports PWC 1 signal output pin General purpose ports Trigger input pins for input capture channels 0 to 3 When input capture channels 0 to 3 are used for input operation these pins are enabled as required and must not be used for any other PPG1 4 General purpose ports Waveform generator output pins These pins output the wave forms specified at the waveform generator Output is generated when waveform generator output is enabled U to Z show the coils that control 3 phase motor General purpose ports Output pins for PPG channels 1 This function is enabled when PPG channels 1 enable output 4 P37 General purpose ports Output pins for PPG channels 0 This function is enabled when PPG channels 0 enable output General purpose ports Serial data input pin for UART channel 0 While UART channel 0 is opera
20. 14 4 Output compare channel 1 match O 15 ICRO2 0000 2 16 bit PPG timer 1 O 16 10n FFFFBCH Output compare channel 2 match O 17 FFFFB8H ICR03 0000B3x 16 bit reload timer 1 underflow O 18 12H 4 Output compare channel 3 match O 19 13 FFFFBOn DTP ext interrupt channels 0 1 detection O ICRO4 0000 20 14 DTTIO A Output compare channel 4 match O 21 15 FFFFA8H DTP ext interrupt channels 2 3 detection O ICRO5 0000 5 22 164 FFFFA4u DTTH Output compare channel 5 match O 23 17 End of measurement PWC1 timer ICR06 0000 6 PWC1 timer overflow S EES DTP ext interrupt channels 4 5 detection O 25 19H FFFF98H i ICR07 0000 7 Waveform sequencer timer compare match 26 1 H write timing DTP ext interrupt channels 6 7 detection O 27 1 FFFF9On iti ICRO8 0000 8 Waveform sequencer position detect O 28 1 FFFF8Cu compare interrupt Waveform generator 16 bit timer 0 1 2 A 29 1Du FFFF88u EE ICRO9 0000B9 16 bit reload timer 0 underflow O 30 1 FFFF84n 16 bit free running timer zero detect A 31 1 FFFF80H ICR10 0000 16 bit PPG timer 2 O 32 20 FFFF7CH Input capture channels 0 1 O 33 21H FFFF78H ICR11 0000 16 bit free running timer compare clear A 34 22
21. P30 to P35 Vcc 4 5 V lo 12 0 mA 0 4 H level input voltage L level input voltage to P07 P30 to P37 P50 to P57 P10 to P17 P20 to P27 P40 to P46 P60 to P63 RST MD pins P00 to P07 P30 to P37 P50 to P57 P10 to P17 P20 to P27 P40 to P46 P60 to P63 RST MD pins Vcc 3 0 5 5 V MB90462 Voc 4 5 V to 5 5 V MB90F462 Vcc 0 3 CMOS input pin Vcc 0 3 CMOS hyster esis input pin Vcc 0 3 MD pin input CMOS input pin CMOS hyster esis input pin Vss 0 3 MD pin input Input leakage current All input pins 5 5 V Vss lt Vi lt 5 Power supply current 66 Vcc 5 0 V Internal opera tion at 16 MHz Normal operation Vcc 5 0 V Internal opera tion at 16 MHz When data writ ten in flash mode programming of erasing Vcc 5 0 V Internal opera tion at 16 MHz In sleep mode Continued Continued Parameter Power supply current Pin name MB90460 Series Vcc 5 0 V 10 Vss AVss 0 0 V TA 40 C to 85 C Condition 5 0 V Internal opera tion at 16 MHz In Timer mode 25 Remarks In stop mode Ta 25 Input capacitance Except AVcc AVss Vcc and Vss Pull up resistance Pull down resistance P00 to PO7 P10 to P17 RST
22. 1 Port 5 are input output ports as other port when ADER is 00 Block Diagram Block diagram of Port 0 pins Resource output Direct resource input Pull up resistor About 50 KQ snq Standby control SPL 1 Continued Block diagram of Port 1 pins MB90460 Series sng Block diagram of Port 2 pins Resource output Resource input Resource output enable Standby control SPL 1 Pull up resistor About 50 KQ sng Resource output Resource input Resource output enable 7 777 Standby control SPL 1 Continued 33 MB90460 Series Block diagram of Port 3 pins euJeju Port data register PDR Resource output Resource output enable Block diagram of Port 4 pins Standby control SPL 1 34 snq Port data register PDR read Resource output Resource input Resource output enable 7 77 Standby control SPL 1 Continued Continued Block diagram of Port 5 pins MB90460 Series su lt isss snq euJeju Analog input
23. 2 Interrupt number 39 MB90460 Series 40 6 16 bit Timer x 3 The 16 bit PPG timer consists of a 16 bit down counter prescaler 16 bit period setting buffer register 16 bit duty setting buffer register 16 bit control register and a PPG output pin This module can be used to output pulses synchronized by software trigger or GATE signal from Multi functional timer refer to Multi functional Timer Features of 16 bit PPG Timer Two operating mode PWM and One shot types of counter operation clock 0 2 6 4 6 8 0 16 6 32 0 64 0 128 can be selected Interrupt generated when trigger signal arrived or counter borrow or change of PPG output El OS supported Block Diagram F2MC 16LX Bus Duty Setting Buffer Register 0 1 2 Period Setting Buffer Register 0 1 2 Prescaler KS2 Period Setting Duty Setting Register 0 1 2 Register 0 1 2 O T CLK LOAD 16 bit down counter P37 PPG0 or Comparator posepens osei roe STOP P36 PPG1 or START BORROW P46 PPG2 Machine clock PPGO multi functional timer oN or PPG1 multi pulse generator 82 or 0 PPG2 E 9 88 Interrupt 14 16 32 GATE from multi functional timer for PPG ch 0 only Edge detection for PPG 1 amp 2 Gebake
24. 3 channels 3 phase waveform or dead time Multi pulse generator for DC motor control 16 bit PPG timer 1 channel 16 bit reload timer operation toggle output one shot output select able Event counter function 1 channel built in A waveform sequencer includes 16 bit timer with buffer and com pare clear function 8 10 bit A D converter 8 10 bit resolution 8 channels Conversion time Less than 6 13 uS 16 MHz internal clock DTP External interrupt 8 independent channels Selectable causes Rising edge falling edge L level or H level Lower power consumption Stop mode Sleep mode CPU intermittent operation mode Continued MB90460 Series Continued Part number MB90V460 MB90F462 MB90462 MB90467 LQFP 64 64 9 0 65 mm pitch Package PGA256 QFP 64 FPT 64P M06 1 00 mm pitch SDIP 64 DIP 64P M01 1 78 mm pitch Power supply voltage for operation Process CMOS Varies with conditions such as the operating frequency See section BI ELECTRICAL CHARACTERISTICS Assurance for the MB90V460 is given only for operation with a tool at a power supply voltage of 4 5 V to 5 5 V an operating temperature of 0 to 25 C and an operating frequency of 1 MHz to 16 MHz 4 5 V to 5 5 V PACKAGE AND CORRESPONDING PRODUCTS Package MB90V460 MB90F462 MB90462 MB90467 PGA256 FPT 64P M09 FTP 64P M06 DIP 64P M01
25. 58 00 os 2 283 022 n nnnnnnnnnnnnnnnnn nnnnnnnnnhlfhfl INDEX 1 C 17 00 0 25 669 010 INDEX 2 G 4 95 020 195 2008 028 0 VAL 0 20 1 0 27 0 10 3 30 030 011 004 130 1378040 ll 1 778 0700 0 4740 10 1 00 29 9543 0 019 004 19 10 25 010 039 25 2001 FUJITSU LIMITED D64001S c 4 5 19 05 750 Dimensions in mm inches MB90460 Series FUJITSU LIMITED For further information please contact Japan FUJITSU LIMITED Marketing Division Electronic Devices Shinjuku Dai Ichi Seimei Bldg 7 1 Nishishinjuku 2 chome Shinjuku ku Tokyo 163 0721 Japan Tel 81 3 5322 3353 Fax 81 3 5322 3386 http edevice fujitsu com North and South America FUJITSU MICROELECTRONICS AMERICA INC 3545 North First Street San Jose CA 95134 1804 U S A Tel 1 408 922 9000 Fax 1 408 922 9179 Customer Response Center Mon Fri 7 am 5 pm PST Tel 1 800 866 8608 Fax 1 408 922 9179 http www fma fujitsu com Europe FUJITSU MICROELECTRONICS EUROPE GmbH Am Siebenstein 6 10 D 63303 Dreieich Buchschlag Germany Tel 49 6103 690 0 Fax 49 6103 690 122 http www fme fujitsu com As
26. K 125 K 62 5 Kbps Assuming internal machine clock frequencies of 6 8 10 12 and 16 MHz Error detection functions parity framing overrun NRZ Non Return to Zero Signal format Interrupt request Receive interrupt receive complete receive error detection Transmit interrupt transmission complete Transmit receive conforms to extended intelligent I O service 5 Flexible data length 7 bit to 9 bit selective without a parity bit 6 bit to 8 bit selective with a parity bit 53 MB90460 Series Block Diagram Dedicated baud rate generator Clock 16 bit reload timer selector Pin SCK0 1 Reception clock Reception Control bus control Start bit detection circuit Reception bit counter Reception parity counter Pin SIN0 1 Y Reception shift register Reception status determination circuit Serial input qata register 0 1 Send clock send control circuit Send start circuit lt gt Reception interrupt request output lt gt Send interrupt request output Send bit counter Send parity counter Send shift register End of reception Serial output data register 0 1 Communication prescaler control register Serial mode register 0 1 Serial control register 0 1 ma
27. control status register 1 000036H 000037H ADCR0 ADCR1 data register 0 A D data register 1 000000008 000000008 00000 8 10 bit 000038 000039 PPG0 down counter register 00003Au 00003 PCSR0 PPGO period setting register 00003CH 00003Du PDUTO PPGO duty setting register 00003 PCNTL0 00003FH PCNTHO PPGO control status register 111111118 111111118 000000 00000000 Continued 16 bit PPG timer CH0 21 22 MB90460 Series Address 000040 000041 Abbrevia tion PDCR1 Register PPG1 down counter register Byte access Word access 000042 000043 PCSR1 PPG1 period setting register 000044 000045 PDUT1 PPG1 duty setting register 000046 PCNTL1 000047H PCNTH1 PPG1 control status register Resource name 16 bit PPG timer CH1 Initial value 11111111 11111111 XXXXXXXXB XXXXXXXXB 000000 00000000 000048 000049 PDCR2 PPG2 down counter register 00004 00004 PCSR2 PPG2 period setting register 00004 00004Du PDUT2 PPG2 duty setting register 00004 00004 PCNTL2 PCNTH2 PPG2 control status registe
28. edge and both edge of the external input signal can be selected and there is indication bit to show the trigger edge is rising or falling 4 input captures can be operated independently Two independent interrupts are generated when detecting a valid edge from external input EIOS supported 4 16 bit PPG timer x 1 The 16 bit PPG timer 0 is used to provide a PPG signal for waveform generator 42 MB90460 Series 5 Generator module The waveform generator consists of three 16 bit timer registers three timer control registers and 16 bit waveform control register With waveform generator it is possible to generate real time output 16 bit PPG waveform output non overlap 3 phase waveform output for inverter control and DC chopper waveform output It is possible to generate a non overlap waveform output based on dead time of 16 bit timer Dead time timer function It is possible to generate a non overlap waveform output when realtime output is operated in 2 channel mode Dead time timer function By detecting realtime output compare match GATE signal of the PPG timer operation will be generated to start or stop PPG timer operation GATE function When a match is detected by realtime output compare the 16 bit timer is activated The PPG timer can be started or stopped easily by generating a GATE signal for PPG operation until the 16 bit timer stops GATE function Forced
29. gt lt Access not allowed In Single chip mode the mirror function is supported Parts No MB90462 467 Address 1 0000 Address 2 004000 Address 3 000900 90 462 0000 004000 000900 90 460 FF0000 004000 002100 Note The ROM data of bank FF is reflected in the upper address of bank 00 realizing effective use of the compiler small model The lower 16 bit is assigned to the same address enabling reference of the table on the ROM without stating far For example if an attempt has been made to access 00 000 the contents of the ROM at 00 are accessed actually Since the ROM area of the FF bank exceeds 48 Kbytes the whole area cannot be reflected in the image for the 00 bank The ROM data at FF4000x to FFFFFFu looks therefore as if it were the image for 0040004 to OOFFFFu Thus it is recommended that the ROM data table be stored in the area of FF4000x to FFFFFFu 19 20 MB90460 Series I O MAP Address 000000 Abbrevia tion Register Port 0 data register Byte access Word access Resource name Initial value XXXXXXXXB 000001 Port 1 data register XXXXXXXXB 000002H Port 2 data register 000003 Port 3 data register XXXXXXXXB 000004 Port 4 data register 000005 0000064 PDR6 Port 5 data reg
30. maximum output lo current 4 8 L level average output loLav Current Average output current operating current x operating efficiency L level total maximum Output current L level total average output current Ss Average output current operating current x operating efficiency H level maximum output lou current 3 H level average output current H level total maximum output current SS Average output current operating current x operating efficiency H level total average output current Ylouav Average output current operating current x operating efficiency Power consumption Po Operating temperature TA Storage temperature 1 AVcc shall never exceed Vcc when power 2 Vi and Vo shall never exceed Vcc 0 3 V 3 The maximum output current is a peak value for a corresponding pin 4 e Applicable to pins POO to P07 P10 to P17 P20 to P27 P30 to P37 P40 to P46 P60 to P63 Use within recommended operating conditions e Use at DC voltage current The B signal should always be applied with a limiting resistance placed between the B signal and the microcontroller The value of the limiting resistance should be set so that when the B signal is applied the input current to the microcontroller pin does not exceed rated values either instantaneously or for prolo
31. not exist on MB90467 because there are not PWC ch 0 16 bit PPG ch 1 and waveform sequencer O CIRCUIT TYPE MB90460 Series Classification Remarks Xout Main clock main clock crystal oscillator A At an oscillation feedback resistor of approximately 1 lt Standby mode control Hysteresis input Pull up resistor B approximately 50 kQ CMOS output Hysteresis input P ch i Pull up control Selectable pull up resistor T approximately 50 UE pout Jo 4 mA C Standby control available Nout Hysteresis input S tandby mode control CMOS output CMOS input P ch i Pull up control Selectable pull up resistor T approximately 50 kQ 1 pem Pout Standby control available D lo 12 mA Nout CMOS input Standby mode control Continued 13 14 MB90460 Series mm s s c6 saa v jua Classification P ch S Pull up control pohn Pout Remarks CMOS output CMOS input Selectable pull up resistor approximately 50 kQ Standby control available lo 4 mA Standby mode control CMOS output Hysteresis input Standby control available lo 4 mA 1 Lo o Pout CMOS input Standby mode control CMOS output CMOS input Standb
32. the A D converter supply and analog inputs In this case make sure thatthe voltage of AVR dose not exceed AVcc turning on off the analog and digital power supplies simultaneously is acceptable MB90460 Series 7 Connection of Unused Pins of A D Converter Connect unused pin of A D converter to AVcc Vec AVss AVR Vss 8 N C Pin The N C internally connected pin must be opened for use 9 Notes on Energization To prevent the internal regulator circuit from malfunctioning set the voltage rise time during energization at 50 us or more 10 Initialization In the device there are internal registers which are initialized only by a power on reset To initialize these registers please turn on the power again 11 Return from standby state If the power supply voltage goes below the standby RAM holding voltage in the standby state the device may fail to return from the standby state In this case reset the device via the external reset pin to return to the normal state MB90460 Series BLOCK DIAGRAM p Other pins X0 V 2 Vi 1 MD0 2 Clock F MC 16LX series core SS AVEC LMD EC X1 Watch dog timer Delayed interrupt generator Multi functional Timer P37 PPGO 16 bit PPG P11 INT1 Cho P13 INT3 to 2 P14 INT4 16 bit input capture 4 P24 INO to T Ch0 1 2 3 P27 IN3 P41 SOTO P42 SCKO 16 bit free run P17 FR
33. 0 bank F2MC 16LX bus 60 MB90460 Series 16 512 Kbit Flash Memory 512 Kbit flash memory is allocated in the FEK to banks on the CPU memory map Like masked ROM flash memory is read accessible and program accessible to the CPU using the flash memory interface circuit The flash memory can be programmed erased by the instruction from the CPU via the flash memory interface circuit The flash memory can therefore be reprogrammed updated while still on the circuit board under inte grated CPU control allowing program code and data to be improved efficiently Note that sector operations such as enable sector protect cannot be used Features of 512 Kbit flash memory 64 kwords x 8 bits 32 kwords x 16 bits 16 k 8 k 8 k 32 k sector configuration Automatic program algorithm same as the Embedded Algorithm MBM29F400TA Installation of the deletion temporary stop delete restart function Write delete completion detected by the data polling or toggle bit Write delete completion detected by the CPU interrupt Compatlibility with the JEDEC standard type command Each sector deletion can be executed can be freely combined Flash security feature Number of write delete operations 10 000 times guaranteed Flash reading cycle time Min 2 machine cycles Embedded Algorithm is a trademark of Advanced Micro Devices Inc 1 Register configuration
34. 0000008 000000008 000000008 000000008 000000008 000000008 000090u to 9 00009 Prohibited area Program address detect control status register Rom correction 00000000 00009 Delayed interrupt cause clear register R W Delayed interrupt 0000 0 Low power consumption mode register R W 0000 1 selection register HAN Low power consumption control register 00011000 11111100 0000 2 to A7u Prohibited area 0000 8 Watchdog control register R W Watchdog timer 111 0000 9 Timebase timer control register R W Timebase timer 1 00100 Continued Address 0000 to ADu Abbrevia tion Register Byte access Prohibited area MB90460 Series Word access Resource Initial val tial value 0000 Flash memory control status register HAN Flash memory interface circuit 00010000 0000AFH 0000B0u Interrupt control register 00 Prohibited area RAN 000001118 0000 1 Interrupt control register 01 R W 000001118 0000B2u Interrupt control register 02 R W 000001118 0000B3u Interrupt control register 03 HAN 000001118 0000 4 Interrupt control register 04 R W 000001118 0000B5u 0000B6u Interrupt control register 05 Interrupt control register 06 R W R W 00
35. 0001118 000001118 0000 7 Interrupt control register 07 R W Interrupt 000001118 0000B8u Interrupt control register 08 R W controller 000001118 0000B9u Interrupt control register 09 R W 000001118 0000BAH Interrupt control register 10 R W 000001118 0000 0000 Interrupt control register 11 Interrupt control register 12 R W R W 000001118 000001118 0000BDH Interrupt control register 13 R W 000001118 0000BEH Interrupt control register 14 R W 000001118 0000 Interrupt control register 15 R W 000001118 0000 0 to External area 001 0 001 1 PADR0L PADR0M Program address detection register 0 Lower Byte Program address detection register 0 Middle Byte R W R W XXXXXXXXB XXXXXXXXB 001FF2u PADROH Program address detection register 0 Higher Byte R W XXXXXXXXs Rom correction 001FF3u PADR1L Program address detection register 1 Lower Byte R W XXXXXXXXB 001 PADR1M Program address detection register 1 Middle Byte R W XXXXXXXXB 001FF5u PADR1H Program address detection register 1 Higher Byte HAN XXXXXXXXB Continued 25 MB90460 Series Continued Abbrevia Byte Word Resource tion access access name 003 00000000 OPDBRO Output da
36. 7 Abbrevia tion Register Compare control register 0 Byte access Word access 00007Du Compare control register 1 00007 00007 OCS3 Compare control register 2 Compare control register 3 000080 OCS4 Compare control register 4 0000814 OCS5 Compare control register 5 Resource name Outputcompare CHO to CH5 Initial value 000000008 0000000 00000000 0000000 00000000 0000000 000082 TMCSRL0 Timer control status register CH0 lower 000083H TMCSRH0 Timer control status register CH0 upper 000084 000085 TMRD0 16 bit timer register CH0 16 bit reload register CH0 16 bit reload timer CH0 00000000 0000 000086 TMCSRL1 Timer control status register CH1 lower 000087 TMCSRH1 Timer control status register CH1 upper 000088H 000089 1 TMRD1 16 bit timer register CH1 16 bit reload register CH1 16 bit reload timer CH1 00000000 0000 XXXXXXXXB XXXXXXXXB 00008 00008 OPCLR Output control lower register Output control upper register 00008 Input control lower register 00008Du Input control upper register 00008 control status register 00008 Noise cancellation control register Waveform sequencer 00
37. CK timer P30 RTOO U P36 PPG1 2 P31 RTO1 X Cho to 5 2 2 V P15 INT5 TINO 9 P34 RTO4 W P16 INT6 TO0 P35 RTO5 Z Waveform P43 SNIO 2 to 3 generator P10 INTO DTTIO P45 SNI2 2 P00 OPT0 2 gt LL PO1 OPT1 2 Waves 16 bit reload timer P20 TIN1 PO2 OPT2 2 sequencer ent P21 TO1 P04 OPT4 PWC P22 PWI1 P05 OPT5 2 cht P23 PWO1 P12 INT2 DTTI1 2 P60 SIN1 P06 PWI0 2 Pwo FI UART P61 SOT1 PO7 PWOO 2 Ch0 Ch1 P62 SCK1 i P63 INT7 16 bit PPG P46 PPG2 Ch2 CMOS VO port 1 2 3 6 CMOS I O port 0 1 3 4 CMOS I O port 5 P50 ANO P51 AN1 mw KGR ANI BO Di P55 AN5 ROM correction P57 AN7 ROM mirroring Note POO to 7 8 channels With registers that can be used as input pull up resistors P10 to P17 8 channels With registers that can be used as input pull up resistors 1 Only MB90V460 MB90F462 and MB90462 have PWC ch 0 16 bit PPG ch 1 and waveform sequencer They do not exist on MB90467 2 The multi pulse generator function can be used only by MB90V460 MB90F462 and 90462 This function can not be used by MB90467 18 MEMORY MB90460 Series FFFFFFH Address 1 FCO000H 010000 ROM area FF bank image Address 2 004000 003FEOH Address 3 000100 0000C0H Peripheral area 000000 Internal access memory
38. Free running timer Capture register 0 2 Capture register 1 3 F2MC 16LX BUS Interrupt ICP1 ICEO 33 35 s33 35 Continued 46 Continued Block diagram of waveform generator MB90460 Series F2MC 16LX BUS PICSH01 PGEN1 PGENO CH DTTIO control circuit Noise Cancellation DTTIO RT1 RT2 RT3 RT4 RT5 PPGO DTCROLIMD2 TMD1 TMDO GTEN1 GTENO GATE 0 1 GATE to PPGO Waveform control 5 Selector O RTOO U 5 O L RTO1 x 16 bit timer register 0 Dead time generator X DTCR1LIMD2 TMD1 TMDO GTEN1 GTENO GATE 2 3 PICSH01 PGEN3 PGEN2 TO2 Waveform control TO3 9 Selector V 5 V Y 16 bit timer register 1 Dead time generator fe i Y DTCR2 LIMD2 TMD1 0 GTEN1 GTENO GATE 4 5 PICSHO1 PGEN5 PGEN4 TO4 Waveform control Selector RTO4 W O RTO5 Z 16 bit timer register 2 Dead time generator 47 MB90460 Series 8 Multi Pulse Generator The Multi pulse Generator consists of a 16 bit PPG timer a 16 bit reload timer and a waveform sequencer By using the waveform sequencer 16 bit PPG timer output signal can be directed to Mul
39. GO GATE underflow Input capture 0 1 Input capture 2 3 U 16 bit timer 0 1 2 DTTIO falling edge detect X V Y 44 Continued Block diagram of 16 bit free running timer MB90460 Series F2MC 16LX BUS STOP UP CLR UP DOWN 16 bit free running timer CK Prescaler Zero detect circuit Zero detect to output compare To Input Capture amp transfer 16 bit compare clear register 16 bit compare clear buffer register Compare circuit Output Compare I Compare clear match to output compare Interrupt 34 22H A D trigger Interrupt 431 1FH Continued 45 MB90460 Series Block diagram of 16 bit output compare Count value from Free running timer Compare buffer BUFO BTSO register 0 2 4 Zero detect from Transfer C Ofree running timer Compare register 0 2 4 o Compare clear match from free running timer BUF1 BTS1 F2MC 16LX BUS Compare buffer register 1 3 5 transfer Compare register 1 3 5 CMOD RT0 2 4 Waveform generator RT1 3 5 Waveform generator IOP1 IOE1 IOE0 Interrupt 12 17 21 15 19 23 Block diagram of 16 bit input capture Count value from
40. Generates an interrupt request upon the completion of count operation Selects single or consecutive count operation 52 MB90460 Series Block Diagram F2MC 16LX bus PWC read detection 16 FE 16 Reload N Data transfer 16 Write enabled Overflow Overflow Clock 16 bit up count timer lt CKS1 CKS0 Divider clear P07 PWO0 P23 PWO1 divider 23 Internal clock machine clock 4 divider Count enabled Control circuit Start edge End edge Divider ON OFF _ selection selection 5 o ES edge 122 Edge NET get Es Count start edge Count end interrupt request CKS0 Overflow interrupt request 1 15 Division PWCS ee selection 2 gt P06 PWI0 P22 PWI1 MB90460 Series 10 UART The UART is a serial I O port for asynchronous start stop communication or clock synchronous communication The UART has the following features Full duplex double buffering Capable of asynchronous start stop bit and CLK synchronous communications Support for the multiprocessor mode Various method of baud rate generation External clock input possible Internal clock a clock supplied from 16 bit reload timer can be used Embedded dedicated baud rate generator Asynchronous 31250 96 15 4808 2404 1202 bps CLK synchronous 2 M 500 K 250
41. LE CHARACTERISTICS Power Suppy Current of MB90462 MB90467 mA Vcc mV VS Voc TA 25 C external clock input 40 1 Fc 16 MHz 35 30 Fc 12 MHz 25 Fc 10 MHz 20 Fc 8 MHz 15 A 10 Fc 4 MHz Fc 2 MHz 5 0 2 3 4 5 6 Vcc V Vcc vs Ta 25 Vcc 4 5 V 1000 900 800 700 600 500 400 300 200 100 0 Iccs mA V MB90460 Series Ices vs Voc 25 C external clock input Vo vs lo 25 Vcc 4 5 V 0 2 4 6 lot mA 10 79 MB90460 Series Power Suppy Current of MB90F462 vs Vcc vs Voc Ta 25 C external clock input Ta 25 C external clock input 40 20 35 16 MHz 18 30 16 16 12 MHz 14 Fc 12 MHz lt 10 MHz ale Mel 40 10 MHz no 8 MHz F Fc 8 MHz 6 Fc 4 MHz 4 MHz 4 Fc 2 MHz Fc 2 MHZ 2 0 2 3 4 5 6 E 3 4 5 6 Ves V Vcc V Vcc vs Vo vs lo 25 C Vc
42. MHz operation UART 2 channels 16 bit PPG 3 channels Mode switching function provided PWM mode or one shot mode Can be worked with a multi functional timer a multi pulse generator or individually 16 bit reload timer 2 channels Can be worked with multi pulse generator or individually 16 bit PWC timer 2 channels A multi functional timer Input capture 4 channels Output compare with selectable buffer 6 channels Free run timer with up or up down mode selection and selectable buffer 1 channel 16 bit PPG 1 channel A waveform generator 16 bit timer 3 channels 3 phase waveform or dead time A multi pulse generator 16 bit PPG 1 channel 16 bit reload timer 1 channel Waveform sequencer 16 bit timer with buffer and compare clear function Time base counter watchdog timer 18 bit MB90460 Series Low power consumption mode Sleep mode Stop mode CPU intermittent operation mode Package QFP 64 64 9 0 65 mm pitch QFP 64 FPT 64P MO6 1 00 mm pitch SDIP 64 DIP 64P MO1 1 78 mm pitch CMOS technology MB90460 Series PRODUCT LINEUP Part number Classification MB90V460 MB90F462 MB90462 MB90467 Mass produced products Mask ROM Mass produced products Flash ROM Development evaluation product ROM size 64 KBytes RAM size 8 KBytes 2 KBytes CPU function Number of Instruction 351 Minimum exec
43. NI2 Pin P44 SNI1 Pin P43 SNIO Pin P15 INT5 TINO Pin WAVEFORM SEQUENCER 16 BIT PPG TIMER 1 PPG Interrupt 22 Interrupt 26 16 BIT RELOAD TIMER 0 Interrupt 28 POS OPT5 04 4 PO2 OPT2 PO1 OPT1 POO OPTO INTERRUPT 22 INTERRUPT 26 INTERRUPT 28 P16 INT6 TOO Continued 49 50 MB90460 Series Continued Block diagram of waveform sequencer F2MC 16LX Bus Interrupt 22 WRITE TIMING INTERRUPT OPCR Register POSITION DETECTION D p Interrupt L PDIRT SEET to 0 Registers li 52 51 50 IPCR Register OUTPUT DATA BUFFER REGISTER x 12 16 BIT TIMER DATA WRITE CONTROL UNIT 3 E Y TINOO TINOO DECODER OPDR Register OP x 1 OP x 0 CIRCUIT DTTI1 Control Circuit From SYN Circuit WTS WTS OUTPUT CONTROL Noise Filter COMPARE CLEAR INTERRUPT Pin Pin PO1 OPT1 Pin 2 2 Pin Pin 04 4 Pin POS OPT5 P12 INT2 DTTI1 PPG1 1 0 O CCIRT WTIN1 WTINO WTINO COMPARISON CIRCUIT Ka ser seo 11 10 pt po
44. R Read only W Write only Explanation of initial values The bit is initialized to 0 The bit is initialized to 1 The initial value of the bit is undefined The bit is not used Its initial value is undefined The Instruction using IO addressing e g MOV A io is not supported for registers area 003FEOu to 003F FF gt x o Note For bits that is initialized by an reset operation the initial value set by the reset operation is listed as an initial value Note that the values are different from reading results For LPMCR CKSCR WDTC there are cases where initialization is performed or not performed depending on the types of the reset However initial value for resets that initializes the value is listed 28 MB90460 Series INTERRUPT FACTORS INTERRUPT VECTORS INTERRUPT CONTROL REGISTER Interrupt control Interrupt vector Interrupt cause EFOS p register Priority support 2 Number Address Address Reset x 08 08 FFFFDCu High INT9 instruction x 09 09 FFFFD8H Exception processing x 10 4 A D converter conversion termination O 11 FFFFDOn ICROO 0000 0 Output compare channel 0 match O 12 OCH End of measurement by PWCO timer PWCO timer overflow TIS PEPE GD ICRO1 0000B14 16 bit PPG timer 0 O
45. Vss P14 INT4 P6O SIN1 P13 INT3 P61 SOT1 P12 INT2 DTTI1 P62 SCK1 P11 INT1 P63 INT7 P10 INTO DTTIO N Q o oo GQ Oo gt DD st D Gi De SEN h h K 90900909095 SEN HDS S EEOSE n nnn nun FPT 64P M06 1 Heavy current pins 2 MB90V460 MB90F462 MB90462 only They do not exist on MB90467 because there are not PWC ch 0 16 bit PPG ch 1 and waveform sequencer Continued MB90460 Series TOP VIEW NESSES e 6500000 oo ot 5355222 EESESE 6600610 TON rok O O LO TON om st st O CO 0 CO CO CO D pp DD D DO Spoo oo gt O F lt O iO C O O CO LO LO LO LO LO LO LO LO LO LO P45 SNI2 2 1 1 P27 IN3 P46 PPG2 L 12 P26 IN2 P50 ANO P25 IN1 P51 AN1 L 14 P24 INO P52 AN2 CO 5 P23 PWO1 P53 AN3 CT 6 P22 PWI1 P54 AN4 L 17 P21 TO1 P55 AN5 18 P20 TIN1 P56 AN6 Ld 9 P17 FRCK P57 AN7 LLL 10 P16 INT6 TOO AVcc LLL 11 P15 INT5 TINO 3112 P14 INT4 AVss 113 P13 INT3 P12 INT2 DTTI1 2 P11 INT1 P10 INTO DTTIO P60 SIN1 14 P61 SOT1 15 P62 SCK1 L 116 25 40 22 23 Vss 24 OPTO CI 25 OPT1 CI 26 CI 18 OPT2 2 J27 RST LLL 19 MD1 LLL 20 MD2 LLL 21 OPT3 CZ 28 4 2 CZ 29 P63 INT7 CI 17 P05 1 OPT5 2 2130 PO6 PWI0 Ca PO7 PWOO CZ P00 P01 P02
46. ated and cleared by software using this module Block Diagram Delayed interrupt cause issuance cancellation decoder F2MC 16LX bus Interrupt cause latch 56 MB90460 Series 13 A D Converter The converter converts the analog voltage input to an analog input pin input voltage to digital value The converter has the following features The minimum conversion time is 6 13 us for a machine clock of 16 MHz includes the sampling time The minimum sampling time is 2 0 us for a machine clock of 16 MHz The converter uses the RC type successive approximation conversion method with a sample hold circuit Aresolution of 10 bits or 8 bits can be selected Up to eight channels for analog input pins can be selected by a program Various conversion mode Single conversion mode Selectively convert one channel Scan conversion mode Continuously convert multiple channels Maximum of 8 program selectable channels Continuous conversion mode Repeatedly convert specified channels Stop conversion mode Convert one channel then halt until the next activation Enables synchronization of the conversion start timing At the end of A D conversion an interrupt request can be generated and EI OS can be activated Inthe interrupt enabled state the conversion data protection function prevents any part of the data from being lost through continuous conversion
47. c 4 5 V Ta 25 C Vcc 2 4 5 V 1000 1000 900 900 800 800 700 700 2 600 600 5 gt 500 500 9 400 gt 400 gt 300 300 200 200 100 100 0 0 0 2 4 6 8 10 12 0 2 4 6 8 10 12 mA lot mA 80 MB90460 Series ORDERING INFORMATION Part number Package Remarks MB90F462PFM MB90462PFM MB90467PFM MB90F462PF MB90462PF MB90467PF MB90F462P SH MB90462P SH MB90467P SH 64 pin Plastic LQFP FPT 64P M09 64 pin Plastic QFP FPT 64P M06 64 pin Plastic SH DIP DIP 64P M01 81 MB90460 Series PACKAGE DIMENSIONS 64 pin Plastic QFP FPT 64P M06 Note Pins width and pins thickness include plating thickness 24 70 0 40 972 016 a 20 00 0 20 787 008 2 0 1740 06 007 002 1 Li A AAM R 5 CC l r mm 18 70 0 40 736 016 mm C 14 00 0 20 Details of A part r 551 008 0 35 Ce INDEX j 3 009 Mounting height or 7 i 118 200 KE QSS 20 ane 1 00 039 4 017 007 b 0 20 008 02948 1 20 0 20 la 010 008 p 047 008 Stand off SU A A Le 0 10 004 2001 FUJITSU LIMITED 640135 4 4
48. cer circuit Output is generated when OPEO to 5 of OPCR is enabled 4 P06 PWI0 4 General purpose ports PWC 0 signal input pin 4 PO7 PWO0 4 General purpose ports PWC 0 signal output pin 4 P10 INTO DTTIO General purpose ports Can be used as interrupt request input channels 0 Input is en abled when 1 is set in ENO in standby mode RTOO to 5 pins for fixed level input This function is enabled when the waveform generator enables its input bits P11 General purpose ports Can be used as interrupt request input channels 1 Input is en abled when 1 is set in EN1 in standby mode P12 INT2 DTTH 4 General purpose ports Can be used as interrupt request input channels 2 Input is en abled when 1 is set in EN2 in standby mode OPTO to 5 pins for fixed level input This function is enabled when the waveform sequencer enables its input bit 4 P13 to P14 INT3 to INT4 General purpose ports Can be used as interrupt request input channels 3 to 4 Input is enabled when 1 is set in EN3 to EN4 in standby mode P15 INT5 TINO General purpose ports Can be used as interrupt request input channel 5 Input is en abled when 1 is set in EN5 in standby mode External clock input pin for reload timer 0 Continued MB90460 Series SDIP
49. clock from the oscillation clock to the PLL clock 2 Interrupt number 36 MB90460 Series 4 Watchdog watchdog timer is 2 bit counter that uses the timebase timer s supply clock as the count clock After activation if the watchdog timer is not cleared within a given period the CPU will be reset Features of Watchdog Timer Reset CPU at four different time intervals Status bits to indicate the reset causes Block Diagram Watchdog timer control register WDTC timer Activation with CLR To the 2 bit Watchdog internal counter reset generator reset generator Start of sleep mode Counter Count Start of hold status mode jclear control clock Start of stop mode circuit selector Timebase timer counter One half of HCLK HCLK Oscillation clock 37 MB90460 Series mm ssasa un 5 16 bit reload timer x 2 The 16 bit reload timer provides two operating mode internal clock mode and event count mode In each operating mode the 16 bit down counter can be reloaded reload mode or stopped when underflow one shot mode Output pins TO1 TOO are able to output different waveform accroding to the counter operating mode TO1 TOO toggles when counter underflow if counter is operated as reload mode TO1 TOO output specified level H or L when counter is counting if the counter is in one shot mode
50. es PLL clock multiplication maximum multiplier 4 Maximum memory space 16 Mbyte Linear bank access Continued PACKAGES 64 pin plastic QFP 64 pin plastic LQFP 64 pin plastic SH DIP FPT 64P M06 6 09 DIP 64P M01 FUJITSU MB90460 Series Continued Instruction set optimized for controller applications Supported data types bit byte word and long word types Standard addressing modes 23 types 32 bit accumulator enhancing high precision operations Signed multiplication division and extended RETI instructions Enhanced high level language C and multi tasking support instructions Use of a system stack pointer Symmetrical instruction set and barrel shift instructions Program patch function for two address pointers Enhanced execution speed 4 byte instruction queue Enhanced interrupt function Up to eight programmable priority levels External interrupt inputs 8 lines Automatic data transmission function independent of CPU operation Up to 16 channels for the extended intelligent I O service DTP request inputs 8 lines Internal ROM FLASH 64 Kbyte with flash security MASKROM 64 Kbyte Internal RAM EVA 8 Kbyte FLASH 2 Kbyte MASKROM 2 Kbyte General purpose ports Up to 51 channels Input pull up resistor settable for 16 channels A D Converter RC 8 ch 8 10 bit resolution selectable Conversion time 6 13 us Min 16
51. ftware clear compare match with compare clear register in up count mode will reset the counter value to 0000 Supply clock to output compare module The prescaler ouptut is acted as the count clock of the output compare 2 Output compare module 6 channels The output compare module consists of six 16 bit compare registers with selectable buffer register compare output latch and compare control registers An interrupt is generated and output level is inverted when the value of 16 bit free running timer and compare register are matched 6 compare registers can be operated independently Output pins and interrupt flag are corresponding to each compare register Inverts output pins by using 2 compare registers together 2 compare registers can be paired to control the output pins Setting the initial value for each output pin is possible Interrupt generated when there is a comparing match with output compare register and 16 bit free run timer EIOS supported 3 Input capture module 4 channels Input capture consists of 4 independent external input pins the corresponding capture register and capture control register By detecting any edge of the input signal from the external pin the value of the 16 bit free running timer can be stored in the capture register and an interrupt is generated simultaneously Operation synchronized with the 16 bit free run timer s count clock 3 types of trigger edge rising edge falling
52. h the CPU forcibly changes this instruction into an INT9 instruction and executes an interrupt processing program There are two detection address configuration registers PADRO and PADR1 Each register provides an interrupt enable bit This allows you to individually configure each register to enable prohibit the generation of interrupts when the address stored in the address latch matches the one configured in the detection address configuration register Block Diagram Address latch PADRO 24 bit INT instruction INT9 interrupt generation Comparator PADR 24 bit Internal data bus Detection address configuration register 1 PACSR Re Re Re Re Re Re Address detection control register PACSR Reseved Make sure this is always set to 01 Address latch Stores value of address output to internal data bus Address detection control register PACSR Set this register to enable prohibit interrupt output when an address match is detected Detection address configuration register PADRO PADR1 Configure an address with which to compare the address latch value 59 MB90460 Series 15 ROM Mirroring Function Selection Module The ROM mirroring function selection module can select what the FF bank allocated the ROM and see through the 00 bank according to register settings Block Diagram ROM mirroring register Address area FF bank 0
53. ia Pacific FUJITSU MICROELECTRONICS ASIA PTE LTD 05 08 151 Lorong Chuan New Tech Park Singapore 556741 Tel 65 281 0770 Fax 65 281 0220 http www fmal fujitsu com Korea FUJITSU MICROELECTRONICS KOREA LTD 1702 KOSMO TOWER 1002 Daechi Dong Kangnam Gu Seoul 135 280 Korea Tel 82 2 3484 7100 Fax 82 2 3484 7111 F0112 FUJITSU LIMITED Printed in Japan All Rights Reserved The contents of this document are subject to change without notice Customers are advised to consult with FUJITSU sales representatives before ordering The information and circuit diagrams in this document are presented as examples of semiconductor device applications and are not intended to be incorporated in devices for actual use Also FUJITSU is unable to assume responsibility for infringement of any patent rights or other rights of third parties arising from the use of this information or circuit diagrams The products described in this document are designed developed and manufactured as contemplated for general use including without limitation ordinary industrial use general office use personal use and household use but are not designed developed and manufactured as contemplated 1 for use accompanying fatal risks or dangers that unless extremely high safety is secured could have a serious effect to the public and could lead directly to death personal injury severe physical damage or other loss i e n
54. ied Multiplied Multiplied Multiplied 16 SC Not multiplied Internal clock fcP MHz Oscillation clock fc MHz The AC ratings are measured for the following measurement reference voltages Input signal waveform e Output signal waveform Hysteresis Input Pin Output Pin 24V 0 8V 69 MB90460 Series 2 Reset Input Timing Vcc 5 0 V 10 Vss AVss 0 0 V TA 40 C to 85 Parameter i Condition Remarks 4 tcp Under normal operation Reset input time Oscillation time of oscillator 4 ter In stop mode Oscillation time of oscillator is time that amplitude reached the 90 In the crystal oscillator the oscillation time is between several ms to tens of ms In FAR ceramic oscillator the oscillation time is between handreds us to several ms In the external clock the oscillation time is 0 ms In stop mode 90 of amplitude Internal operation clock 4 tep re Oscillation time of oscillator Oscillation setting time Internal reset Instruction execution 70 MB90460 Series 3 Power on Reset Vcc 5 0 V 10 Vss AVss 0 0 V TA 40 C to 85 Parameter Pin name Condition Remarks Power supply rising time Power supply cut off time poale operations Note Vcc must be kept lo
55. ister Port 6 data register HAN XXXXXXXXB XXXXB 000007 Prohibited area 000008 PWCSL0 000009 PWCSH0 PWC control status register CH0 R W R W 00000 00000 PWC0 PWC data buffer register CHO Divide ratio control register CHO R W PWC timer CHO 000000008 000000008 00000Du to Prohibited area 000010 Port 0 direction register R W 00000000 000011 Port 1 direction register R W 000000008 0000124 Port 2 direction register R W 000000008 0000134 0000144 Port 3 direction register Port 4 direction register RAV R W Port 4 000000008 0000000 000015 Port 5 direction register R W Port 5 00000000 0000164 Port 6 direction register HAN Port 6 0000 000017 Analog input enable register R W Port 5 A D 111111118 000018H Prohibited area 000019 00001 An Clock division control register 0 R W Prohibited area Communication prescaler 0 00001 Clock division control register 1 R W Communication prescaler 1 0 0000 00001 Port 0 pull up resistor setting register R W Port 0 00000000 00001Du Port 1 pull up resistor setting register HAN Port 1 00000000 00001En to 1Fn Prohibited area Continued Address 000020
56. l linearity error Zero transition voltage For MB90F462 MB90462 MB90467 For MB90V460 Full scale transition voltage For MB90F462 MB90462 MB90467 For MB90V460 Conversion time Actual value is specified as a sum of values specified in ADCRO CT1 CTO and ADCRO ST1 STO Be sure that the setting value is greater than the min value Sampling period Actual value is specified in ADCRO ST1 STO bits Be sure that the set ting value is greater than the min val ue Analog port input current Analog input voltage Reference voltage Power supply current For MB90F462 MB90462 MB90467 For MB90V460 Reference voltage supply current For MB90F462 MB90462 MB90467 For MB90V460 Offset between channels The current when the A D converter is not operating or the CPU is in stop mode for Vcc AVcc AVR 5 0 V 75 76 MB90460 Series 6 A D Converter Glossary Resolution Analog changes that are identifiable with the A D converter Linearity error The deviation of the straight line connecting the zero transition point 00 0000 0000 lt gt 000000 0001 with the full scale transition point 11 1111 1110 lt gt 11 1111 1111 from actual conversion characteristics Differential linearity error The deviation of input voltage needed to change the output code by 1 LSB from the theoretical
57. le leaving the X1 pin open See the illustration below MB90460 series Open 71 Power Supply Pins Vcc Vss In products with multiple Vcc or Vss pins the pins of a same potential are internally connected in the device to avoid abnormal operations including latch up However connect the pins external power and ground lines to lower the electro magnetic emission level to prevent abnormal operation of strobe signals caused by the rise in the ground level and to conform to the total current rating Make sure to connect Vcc and Vss pins via the lowest impedance to power lines It is recommended to provide a bypass capacitor of around 0 1 uF between Vcc and Vss pins near the device Crystal Oscillator Circuit Noise around or X1 pins may cause abnormal operations Make sure to provide bypass capacitors via the shortest distance from X1 pins crystal oscillator or ceramic resonator and ground lines and make sure to the utmost effort that lines of oscillation circuit not cross the lines of other circuits It is highly recommended to provide a printed circuit board art work surrounding and X1 pins with the ground area for stabilizing the operation Turning on Sequence of Power Supply to A D Converter and Analog Inputs Make sure to turn on the A D converter power supply AVcc AVss AVR and analog inputs ANO to AN7 after turning on the digital power supply Voc Turn off the digital power after turning off
58. nged periods Continued 63 MB90460 Series Continued e Note that when the microcontroller drive current is low such as in the power saving modes the B input potential may pass through the protective diode and increase the potential at the Vcc pin and this may affect other devices e Note that if a B signal is input when the microcontroller current is off not fixed at 0 V the power supply is provided from the pins so that incomplete operation may result e Note that if the B input is applied during power on the power supply is provided from the pins and the resulting supply voltage may not be sufficient to operate the power on reset e Care must be taken not to leave the B input pin open e Note that analog system input output pins other than the A D input pins LCD drive pins comparator input pins etc cannot accept B signal input e Sample recommended circuits Input Output Equivalent circuits m Vcc Limiting een resistance B input 0 V to 16 V AM 1 N ch Z WARNING Semiconductor devices can be permanently damaged by application of stress voltage current temperature etc in excess of absolute maximum ratings Do not exceed these ratings 64 MB90460 Series 2 Recommended Operating Conditions Vss AVss 0 0 V Parameter Remarks Normal operation MB90462 MB90467 MB90V460 Power sup
59. o 0014 Vest Voltage at transition of digital output from to 77 MB90460 Series 7 Notes on Using A D Converter Select the output impedance value for the external circuit of analog input according to the following conditions Output impedance values of the external circuit recommends about 5 kQ or lower sampling period 2 0 us machine clock of 16 MHz When capacitors are connected to external pins the capacitance of several thousand times the internal capacitor value is recommended to minimized the effect of voltage distribution between the external capacitor and internal capacitor When the output impedance of the external circuit is too high the sampling period for analog voltages may not be sufficient Analog input circuit model Analog input i MB90462 MB90F462 MB90467 R 2 6 C 28 pF MB90V460 R 9 2 C 30 pF Note Listed values must be considered as standards Error The smaller the absolute value of AVR AVss the greater the error would become relatively 8 Flash Memory Program and Erase Performances Parameter Condition Remarks Excludes 00H programming prior erasure Ta 25 Excludes 00 H program Vcc 3 0 V ming prior erasure Word 16 bit width Excludes programming time system level overhead Erase Program cycle 10 000 Sector erase time Chip erase time 78 EXAMP
60. ply i Normal operation MB90F462 voltage Retains status at the time of operation stop Use a ceramic capacitor or a capacitor with equiva Smoothing lent frequency characteristics The smoothing capac capacitor itor to be connected to the Vcc pin must have a capacitance value higher than Cs Operating temperature C pin connection circuit Cs 1 1 WARNING recommended operating conditions required order ensure the normal operation the semiconductor device All of the device s electrical characteristics are warranted when the device is operated within these ranges Always use semiconductor devices within their recommended operating condition ranges Operation outside these ranges may adversely affect reliability and could result in device failure No warranty is made with respect to uses operating conditions or combinations not represented on the data sheet Users considering application outside the listed conditions are advised to contact their FUJITSU representatives beforehand 65 MB90460 Series 3 DC Characteristics Parameter H level output voltage Pin name All output pins Vcc 5 0 V 10 Vss AVss 0 0 V TA 40 C to 85 Condition Vcc 4 5 V lou 4 0 mA Remarks L level output voltage All pins except P00to 05 and P30 to P35 Vcc 4 5 V lo 4 0 mA P00 to P05
61. pulses are supplied to peripheral functions reducing power consumption In CPU intermittent operation mode intermittent clock pulses are only applied to the CPU when it is accessing a register internal memory a peripheral function or an external unit Standby mode In standby mode the low power consumption control circuit stops supplying the clock to the CPU sleep mode or the CPU and peripheral functions timebase timer mode or stops the oscillation clock itself stop mode reducing power consumption PLL sleep mode PLL sleep mode is activated to stop the CPU operating clock when the microcontroller enters PLL clock mode other components continue to operate on the PLL clock Main sleep mode Main sleep mode is activated to stop the CPU operating clock when the microcontroller enters main clock mode other components continue to operate on the main clock PLL timebase timer mode PLL timebase timer mode causes microcontroller operation with the exception of the oscillation clock PLL clock and timebase timer to stop All functions other than the timebase timer are deactivated Main timebase timer mode Main timebase timer mode causes microcontroller operation with the exception of the oscillation clock main clock and the timebase timer to stop All functions other than the timebase timer are deactivated Stop mode Stop mode causes the source oscillation to stop All functions are deactivated MB90460 Series Block Diagram
62. r 16 bit PPG timer CH2 111111118 111111118 XXXXXXXXB XXXXXXXXB XXXXXXXXB 000000 00000000 000050 000051 16 bit timer register 0 000052 000053 TMRR1 16 bit timer register 1 000054 000055 TMRR2 16 bit timer register 2 000056 DTCRO 16 bit timer control register 0 000057 DTCR1 16 bit timer control register 1 000058H DTCR2 16 bit timer control register 2 000059 SIGCR Waveform control register Waveform generator XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB 000000008 000000008 000000008 000000008 00005 00005 CPCLRB CPCLR Compare clear buffer register Compare clear register lower 00005 00005Du TCDT Timer data register lower 00005 TCCSL Timer control status register lower 00005 TCCSH Timer control status register upper 16 bit free running timer 11111111 11111111 00000000 00000000 00000000 0000000 Continued Address 000060 000061 Abbrevia tion IPCP0 Register Input capture data register CH0 Byte access MB90460 Series Word access R 000062H 000063H IPCP1 Input capture data register CH1 000064 000065 IPCP2 Input capture data register CH2 000066 000067 IPCP3 Input capture data register CH3
63. ta buffer register 0 003 1 00000000 003 2 00000000 OPDBR1 Output data buffer register 1 003FE3H 00000000 003FE4H 00000000 OPDBR2 Output data buffer register 2 003FE5H 00000000 003FE6H I 00000000 OPDBR3 Output data buffer register 3 003FE7H 00000000 003 78 00000000 OPDBR4 Output data buffer register 4 003FE9H 00000000 00000000 OPDBR5 Output data buffer register 5 003FEBn 00000000 003FECH 00000000 OPEBR6 Output data buffer register 6 003FEDH 000000005 00000000 OPEBR7 Output data buffer register 7 Waveform P Address Register Initial value 003FEFH sequencer 00000000 003FF0H 00000000 OPEBR8 Output data buffer register 8 003FF 1 000000008 003FF2H 00000000 OPEBR9 Output data buffer register 9 003FF3H 00000000 003FF4H 00000000 OPEBRA data buffer register 00000000 003FF6H 000000005 OPEBRB Output data buffer register B 003FF7H 00000000 003FF8H OPDR Output data register 003FF9H 0000XXXXs 003FFAH CPCR Compare clear register O03FFBu XXXXXXXXs 003FFCH 00000000 Timer buffer register 003FFDH 000000008 003FFEH to Prohibited area 00 26 MB90460 Series Meaning of abbreviations used for reading and writing R W Read and write enabled
64. ti pulse Generator output OPT5 to 0 according to the input signal of Multi pulse Generator SNI2 to 0 Meanwhile the OPT5 to 0 output signal can be hardware terminated input DTTI1 in case of emergency The OPT5 to 0 output signals are synchronized with the PPG signal in order to eliminate the unwanted glitch The Multi pulse generator has the following features Output Signal Control 12 output data buffer registers are provided Output data register can be updated by any one of output data buffer registers when 1 an effective edge detected at SNI2 SNIO pin 2 16 bit reload timer underflow 3 output data buffer register OPDBRO is written Output data register OPDR determines which OPT terminals OPT5 0 output the 16 bit PPG waveform Waveform sequencer is provided with a 16 bit timer to measure the speed of motor The 16 bit timer can be used to disable the OPT output when the position detection is missing Input Position Detect Control SNI2 SNIO input can be used to detect the rotor position controllable noise filter is provided to the SNI2 SNIO input PPG Synchronization for Output signal OPT output is able to synchronize the edge of PPG waveform to avoid a short pulse or glitch appearance Vaious interrupt generation causes EIOS supported Block Diagram Block diagram of Multi pulse generator MB90460 Series F sss F2MC 16LX Bus lt gt P12 INT2 DTTI1 Pin P45 S
65. ting for input the input of this pin is used as required and must not be used for any other input General purpose ports Serial data output pin for UART channel 0 This function is en abled when UART channel 0 enables data output MB90460 Series Continued SDIP s UO circuit Continued Function General purpose I O ports Serial clock I O pin for UART channel 0 This function is enabled when UART channel 0 enables clock output SNIO 4 General purpose I O ports Trigger input pins for position detection of the waveform se quencer When this pin is used for input operation it is enabled as required and must be used for any other I P 4 P44 SNI1 4 General purpose I O ports Trigger input pins for position detection of the Multi pulse gener ator When this pin is used for input operation it is enabled as required and must not be used for any other I P 4 P45 SNI2 4 General purpose I O ports Trigger input pins for position detection of the Multi pulse gener ator When this pin is used for input operation it is enabled as required and must not be used for any other I P 4 P46 General purpose I O ports Output pins for PPG channel 2 This function is enabled when PPG channel 2 enables output General purpose I O ports A D converter analog input pins This function is enabled when the analog input specification is enabled ADER
66. to stop output waveform using DTTIO pin input Interrupt generated when DTTIO active or 16 bit tmer underflow EIOS supported MCU to 3 phase Motor Interface Circuit RTOO U RTOS Z RTO1 X RTOO 0 RTO4 W are called UPPER ARM RTO1 X Y RTOS Z are called LOWER ARM RTOO U and RTO1 X are called non overlapping output pair V and RTOS Y are called non overlapping output pair RTO4 W and RTO5 Z are called non overlapping output pair U V W are the 3 phase coil connection 3 phase Motor Coil Connection Circuit U Star Connection Circuit Delta Connection Circuit MB90460 Series MB90460 Series a Block Diagram Block Diagram of Multi functional Timer Real time I O Interrupt 12 Interrupt 15 Interrupt 1 7 Interrupt 19 Interrupt 21 Interrupt 23 16 bit Output Compare to 5 counter value buffer transfer Interrupt 31 Interrupt 34 16 bit free A D trigger running timer F2MC 16LX Bus counter value Interrupt 33 Interrupt 35 16 bit Input Capture output compare 0 output compare 1 output compare 2 output compare 3 output compare 4 output compare 5 Zero detect Compare clear A D trigger RTO0 RTO1 RTO2 RTO3 RTO to 5 Waveform generator RTO4 RTO5 DTTI Interrupt 29 Interrupt 20 PP
67. uclear reaction control in nuclear facility aircraft flight control air traffic control mass transport control medical life support system missile launch control in weapon system or 2 for use requiring extremely high reliability i e submersible repeater and artificial satellite Please note that Fujitsu will not be liable against you and or any third party for any claims or damages arising in connection with above mentioned uses of the products Any semiconductor devices have an inherent chance of failure You must protect against injury damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy fire protection and prevention of over current levels and other abnormal operating conditions If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Law of Japan the prior authorization by Japanese government will be required for export of those products from Japan
68. ution time 62 5 ns 4 MHz PLL x 4 Addressing mode 23 Data bit length 1 8 16 bits Maximum memory space 16 MBytes port I O port CMOS 51 Pulse width counter Pulse widih counter timer 2 channels 1 timer 1ch Timer function select the counter timer from three internal clocks Various Pulse width measuring function H pulse width L pulse width rising edge to fall ing edge period falling edge to rising edge period rising edge to rising edge period and falling edge to falling edge period UART 2 channels With full duplex double buffer 8 bit length Clock asynchronized or clock synchronized transmission with start and stop bits can be selectively used Transmission can be one to one bi directional commuication or one to n Master Slave communication 16 bit reload timer Reload timer 2 channels Reload mode single shot mode or event count mode selectable Can be worked with a multi pulse generator or individually 16 bit PPG timer PPG timer 3 channels PPG timer 2ch PWM mode or single shot mode selectable Can be worked with multi functional timer multi pulse generator or individually Multi functional timer for AC DC motor control 16 bit free running timer with up or up down mode selection and buffer 1 channel 16 bit output compare 6 channels 16 bit input capture 4 channels 16 bit PPG timer 1 channel Waveform generator 16 bit timer
69. value Total error The total error is defined as a difference between the actual value and the theoretical value which includes zero transition error full scale transition error and linearity error Total error 3FF 3FE Actual conversion 777 ael value 3FD 5 5 5 o 004 003 se Actual conversion value 002 Theoretical characteristics 001 AVss AVR Analog input Var 1 LSBx N 1 0 5 LSB Total error for digital output N AVR AVss 1 LSB Theoretical value 1024 V Vor Theoretical value AVss 0 5 LSB V Vest Theoretical value AVR 1 5 LSB V Voltage at a transition of digital output from N 1 to N LSB Continued MB90460 Series Continued Linearity error Differential linearity error 3FF ee Actual conversion characteristics value S ARE 1 LSB x N 1 1 conversion 3FD Measured 3 value 2 N 5 5 o 004 measured value 8 i o a Actual conversion 003 Es value N 1 002 Theoretical characteristics N 2 001 value Vor Measured value AVss AVR AVss AVR Analog input Analog input Linearity error of _ Mur 1 LSBx N 1 LSB digital output N 1 LSB Differential linearity error _ V N i 1 LSB of digital output N 1 LSB Vest Vor 1LSB V 1022 Vor Voltage at transition of digital output from 0004 t
70. wer than 0 2 V before power on The above values are used for causing a power on reset Some registers in the device are initialized only upon a power on reset To initialize these registers turn the power supply using the above values Vcc toFF Sudden changes in the power supply voltage may cause a power on reset To change the power supply voltage while the device is in operation it is recommended to raise the voltage smoothly to suppress fluctuations as shown below In this case change the supply voltage with the PLL clock not used If the voltage drop is 1 V or fewer per second however you can use the PLL clock It is recommended to keep the eS rising speed of the supply voltage es RAM data Hold at 50 mV ms or slower 71 MB90460 Series 72 4 to UART1 Parameter Serial clock cycle time Vcc 5 0 V 10 Vss AVss 0 0 V TA 40 C to 85 Pin name SCKO to SCK1 SCK gt SOT delay time SCKO to SCK1 SOTO to SOT1 Valid SIN SCK T SCKO to SCK1 SINO to SIN1 T gt valid SIN hold time SCKOto SCK1 SINO to SIN1 Condition 80 pF 1 TTL for an output pin of internal shift clock mode Remarks Serial clock H pulse width Serial clock L pulse width SCKO to SCK1 SCKO to SCK1 SCK SOT delay time SCKOto SCK1 SOTO to SOT1 Valid SIN SCK T SCKOto SCK1 SINO to SIN1
71. y control available lo 12 mA 1 La e Pout CMOS input Standby mode control CMOS output CMOS input Standby control available lo 4 mA Continued Continued Classification MB90460 Series Remarks CMOS output CMOS input Analog input lo 4 mA Hysteresis input 15 MB90460 Series HANDLING DEVICES 1 Preventing Latchup CMOS ICs may cause latchup in the following situations When a voltage higher than Vcc or lower than Vss is applied to input or output pins When a voltage exceeding the rating is applied between Vcc and Vss When AVcc power is supplied prior to the Vcc voltage If latchup occurs the power supply current increases rapidly sometimes resulting in thermal breakdown of the device Use meticulous care not to let it occur For the same reason also be careful not to let the analog power supply voltage exceed the digital power supply voltage Handling unused input pins Unused input pins left open may cause abnormal operation or latch up leading to permanent damage Unused input pins should be pulled up or pulled down through at least 2 kO resistance Unused input output pins may be left open in the output state but if such pins are in the input state they should be handled in the same way as input pins Use of the external clock When the device uses an external clock drive only the pin whi

FUJITSU SEMICONDUCTOR MB90460 Series handbook

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