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Samsung K4S643232F Data Sheet

1. Version Parameter Symbol Unit 45 50 55 60 70 Row active to row active delay tRRD min 9 10 11 12 14 ns RAS to CAS delay tRCD min 18 15 16 5 18 20 ns Row precharge time tRP min 18 15 16 5 18 20 ns tRAS min 40 5 40 38 5 42 49 ns Row active time tRAS max 100 us Row cycle time tRC min 58 5 55 55 60 70 ns 2 Minimum delay is required to complete write 3 All parts allow every cycle column address change 4 In case of row precharge interrupt auto precharge and read burst stop AC CHARACTERISTICS Ac operating conditions unless otherwise noted 45 50 55 60 70 Parameter Symbol Unit Note Min Max Min Max Min Max Min Max Min Max CAS Latency 3 4 5 5 5 5 6 7 CLK cycle time tcc 1000 1000 1000 1000 1000 ns 1 CAS Latency 2 10 10 10 10 10 i CAS Latency 3 4 0 4 5 5 0 5 5 5 5 CLK Mess y ns 1 2 output delay CAS Latency 2 6 1 6 6 6 s 6 Output data hold time tOH 2 2 2 2 2 ns 2 i CAS Latency 3 1 75 2 2 2 5 3 eats pulse y icn T 3 wit CAS Latency 2 3 3 3 3 3 CAS Latency 3 1 75 2 2 2 5 3 see h ns 3 pulse widt CAS Latency 2 3 3 3 3 3 CAS Latency 3 1 2 1 5 1 5 1 5 175 Input setup time tss ns 3 CAS Latency 2 2 5 2 5 2 5 2 5 2 5 Input hold time tsH 1 i 1 1 1 1 ns 3 CLK to output in Low Z 1512 1 1 1 1 1 ns 2 CAS latency 3 4 0 4 5 5 0 5 5
2. 30pF Z M coa 7 Fig 1 DC output load circuit Fig 2 AC output load circuit Notes 1 The Vpp condition of K4S643232F 45 50 55 60 is 3 135V 3 6V OPERATING AC PARAMETER AC operating conditions unless otherwise noted output data CAS Latency 2 Version Parameter Symbol Unit Note 45 50 55 60 70 CAS Latency CL 3 2 3 2 3 3 2 3 2 CLK CLK cycle time tCC min 4 5 10 5 10 5 5 10 6 10 7 10 ns Row active to row active delay tRRD min 2 CLK 1 RAS to CAS delay tRCD min 4 2 3 2 3 2 3 2 3 2 CLK 1 Row precharge time TRP min 4 2 3 2 3 2 2 3 2 CLK 1 tRAS min 9 5 8 5 7 5 7 5 7 5 CLK 1 Row active time tRAS max 100 us Row cycle time tRC min 13 7 11 7 10 7 10 7 10 7 CLK 1 Last data in to row precharge tRDL 2 CLK 2 Last data in to new col address delay tCDL min 1 CLK 2 Last data in to burst stop tBDL min 1 CLK 2 Col address to col address delay tCCD min 1 CLK 3 Mode Register Set cycle time tMRS min 2 CLK Number of valid CAS Latency 3 2 1 ea 4 Note 1 The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and then rounding off to the next higher integer Refer to the following ns unit based AC table ELECTRONICS Rev 1 0 Jan 2002
3. CLK lt Vit max too 2 Input signals stable Active Standby Current Icc3P lt ViL max tcc 15ns 4 power down mode IccaPS lt ViL max tcc eo 4 IccaN gt Vin min 5 gt ViH min tcc 15ns 40 Active Standby Current Input signals are changed one time during 30ns in non power down mode mA One Bank Active IccaNS gt Vin min CLK lt Vit max ee 35 Input signals are stable Operating Current lo 2 0 Page Burst 3 180 170 160 150 140 mA 2 Burst Mode All bank Activated tccp tccp min 2 120 3 150 150 150 140 120 Refresh Current lccs tRC gt tRc min mA 3 2 120 2 mA 4 Self Refresh Current locs x 0 2V 450 uA 5 Notes 1 Unless otherwise notes Input level is CMOS VIH VIL VDDQ VSSQ in LVTTL 2 Measured with outputs open 3 Refresh period is 64ms 4 KAS643232F TC 5 K4S643232F TL Rev 1 0 Jan 2002 ELECTRONICS AC OPERATING TEST CONDITIONS voo 3 3V 0 3V Ta 0 to 70 Parameter Value Unit AC input levels Vih Vil 2 4 0 4 V Input timing measurement reference level 1 4 V Input rise and fall time tr tf 1 1 ns Output timing measurement reference level 1 4 V Output load condition See Fig 2 3 3V Vit 1 4V 12002 500 0 b DC 2 4V 2mA 0 GED b utput VoL DC 0 4V lot 2mA utput 20 502 8700 30pF
4. 5 5 nd output y ieee ns CAS latency 2 6 6 6 6 6 Note 1 Parameters depend on programmed CAS latency 2 If clock rising time is longer than 1ns tr 2 0 5 ns should be added to the parameter 3 Assumed input rise and fall time tr amp tf 1ns If tr amp tf is longer than 1ns transient time compensation should be considered i e tr tf 2 1 ns should be added to the parameter ELECTRONICS Rev 1 0 Jan 2002 K4S643232F CMOS SDRAM SIMPLIFIED TRUTH TABLE Command CKEn 1 CKEn CS RAS CAS WE DQM 8 0 1 A10 AP As Ao Note Register Mode register set H X L L L L X OP code 1 2 Auto refresh H 3 H L L L H X X Entry L 3 Refresh Self refresh Exit L H ey X I H X X X 3 Bank active amp row addr H X L L H H X V Row address Read amp Auto precharge disable T x 7 T 1 ii x Y L 4 aadress column address Auto precharge enable H Ao A7 4 5 Write amp Auto precharge disable B x i 7 L x T L Sa 4 aadress column address Auto precharge enable H Wo7A 4 5 Burst Stop H X L H H L X X 6 Bank selection V L Precharge H X L L H L X X All banks X H H X X X Clock suspend or Entry H L L u X x active power down Exit L H X X X X X H X X X Entry H L X L H H H Pre
5. 31 Data input output Data inputs outputs are multiplexed on the same pins Vpp Vss Power supply ground Power and ground for the input buffers and the core logic Vppa Vssa Data output power ground an supply and ground for the output buffers to provide improved noise NC No Connection This pin is recommended to be left No connection on the device ELECTRONICS Rev 1 0 Jan 2002 K4S643232F CMOS SDRAM ABSOLUTE MAXIMUM RATINGS Parameter Symbol Value Unit Voltage on any pin relative to Vss VIN VOUT 1 0 4 6 V Voltage on supply relative to Vss VDD VDDQ 1 0 4 6 V Storage temperature TSTG 55 150 C Power dissipation Pp 1 w Short circuit current los 50 mA Note Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded Functional operation should be restricted to recommended operating condition Exposure to higher than recommended voltage for extended periods of time could affect device reliability DC OPERATING CONDITIONS Recommended operating conditions Voltage referenced to Vss OV TA 0 to 70 Parameter Symbol Min Typ Max Unit Note Supply voltage VDD VDDQ 3 0 3 3 3 6 Input logic high voltage VIH 2 0 3 0 VppQ 0 3 V 1 Input logic low voltage VIL 0 3 0 0 8 V 2 Output logic high voltage 2 4 V loH 2mA Output logic low voltage VoL 0 4 V loL 2mA Input
6. VDDQ DQ26 DQ25 Vssa DQ24 Vss 86Pin TSOP II 400mil x 875mil 0 5 mm Pin pitch ELECTRONICS Rev 1 0 Jan 2002 K4S643232F CMOS SDRAM PIN FUNCTION DESCRIPTION Pin Name Input Function CLK System clock Active on the positive going edge to sample all inputs Disables or enables device operation by masking or enabling all inputs except em Mene CLK and DOM Masks system clock to freeze operation from the next clock cycle CKE Clock enable CKE should be enabled at least one cycle prior to new command Disables input buffers for power down mode Row column addresses are multiplexed on the same pins A1 A d adress Row address RAo RA10 Column address CA7 Selects bank to be activated during row address latch time 1 Bank sel i 0 ank Select adarass Selects bank for read write during column address latch time RAS Row address strobe Latches row addresses on the positive going edge of the CLK with RAS low Enables row access amp precharge TAS Colum address strobe Latches column addresses on the positive going edge of the CLK with CAS low Enables column access WE Enables write operation and row precharge WE W l e enable Latches data in starting from CAS WE active Makes data output Hi Z tsHz after the clock and masks the output MO D k PRIMI SS ala mpuroutputimas Blocks data input when DQM active
7. 9 is high during MRS cycle Burst Read Single Bit Write function will be enabled 2 RFU Reserved for future use should stay 0 during MRS cycle Rev 1 0 Jan 2002 ELECTRONICS CMOS SDRAM K4S643232F 4 BURST SEQUENCE BURST LENGTH Interleave Sequential Initial Address 8 BURST SEQUENCE BURST LENGTH Interleave Sequential Initial Address Rev 1 0 Jan 2002 12 ELECTRONICS
8. charge power down mode X H X X X Exit L H X L V V V DQM H X V X 7 H X X X No operation command H X X X L H H V Valid X Don t care H Logic high L Logic low Notes 1 OP Code Operand code Ao A10 amp BAo BA1 Program keys MRS 2 MRS can be issued only at all banks precharge state A new command can be issued after 2 CLK cycles of MRS 3 Auto refresh functions are as same as CBR refresh of DRAM The automatical precharge without row precharge command is meant by Auto Auto self refresh can be issued only at all banks precharge state 4 BAo BA1 Bank select addresses If both BAo and BA1 are Low at read write row active and precharge bank A is selected If both BAo is Low and BA is High at read write row active and precharge bank B is selected If both BAo is High and 1 is Low at read write row active and precharge bank C is selected If both BAo and BA are High at read write row active and precharge bank D is selected If A10 AP is High at row precharge BAo and BA is ignored and all banks are selected 5 During burst read or write with auto precharge new read write command can not be issued Another bank read write command can be issued after the end of burst New row active of the associated bank can be issued at tRP after the end of burst 6 Burst stop command is valid at every burst length 7 DQM sampled at positive going edge of a CLK and masks the data in at the very CLK Writ
9. e DQM latency is 0 but makes Hi Z state the data out of 2 CLK cycles after Read DQM latency is 2 Rev 1 0 Jan 2002 ELECTRONICS K4S643232F CMOS SDRAM MODE REGISTER FIELD TABLE TO PROGRAM MODES Register Programmed with MRS Test Mode CAS my Burst Type Burst Length Type EN NEN Ec mn Type A BT 0 BT 1 Mode Register Set Reserved Sequential Reserved Reserved Reserved 1 Interleave 2 3 Reserved 8 Reserved Reserved Reserved Reserved Reserved Write Burst Length Length Reserved Reserved Reserved Reserved Reserved Full Page Reserved Burst Single Bit Aj A 0 a o o O O O O Full Page Length x32 256 POWER UP SEQUENCE SDRAMs must be powered up and initialized in a predefined manner to prevent undefined operations 1 Apply power and start clock Must maintain CKE and the other pins are NOP condition at the inputs 2 Maintain stable power stable clock and NOP input condition for a minimum of 200us 3 Issue precharge commands for all banks of the devices 4 Issue 2 or more auto refresh commands 5 Issue a mode register set command to initialize the mode register cf Sequence of 4 amp 5 is regardless of the order The device is now ready for normal operation Note 1 If A
10. leakage current ILI 10 10 uA 3 Notes 1 ViH max 5 6V AC The overshoot voltage duration is lt 3ns 2 Vit min 2 0V AC The undershoot voltage duration is lt 3ns 3 Any input OV lt VIN lt VDDQ Input leakage currents include Hi Z output leakage for all bi directional buffers with Tri State outputs 4 The VoD condition of K4S643232F 45 50 55 60 is 3 135V 3 6V CAPACITANCE 3 3V Ta 23 f 1MHz VREF 1 4V 200 mV Pin Symbol Min Max Unit Clock CCLK 4 pF RAS CAS WE CS DQM CIN 4 5 pF Address CADD 4 5 pF DQ31 COUT 6 5 pF ELECTRONICS Rev 1 0 Jan 2002 K4S643232F CMOS SDRAM DC CHARACTERISTICS Recommended operating condition unless otherwise noted TA 0 to 70 C VIH min VIL max 2 0V 0 8V Parameter Symbol Test Condition Lat Unit Note atency 45 50 55 60 70 Operating Current lcct Burst Length 1 3 140 140 140 130 130 si One Bank Active tRC gt tRc min tcc 2 tcc min lo 2 110 Precharge Standby Current in ec2P s ViL max tcc 15ns 2 m power down mode 6605 amp CLK lt ViL max toc e 2 IccaN gt Vin min 5 gt ViH min tcc 15ns 12 Precharge Standby Current Input signals are changed one time during 30ns EN in non power down mode CKE gt
11. to be useful for a variety of high bandwidth high performance memory system applications ORDERING INFORMATION jus Mn i Part NO Max Freq Interface Package ous refresh Guty cycle K4S643232F TC L45 222MHz K4S643232F TC L50 200MHz 86 K4S643232F TC L55 183MHz LVTTL TSOP II K4S643232F TC L60 166MHz K4S643232F TC L70 143MHz FUNCTIONAL BLOCK DIAGRAM lt LWE Data Input Register 7 5 lt LDQM Bank Select P Y 2 gt gt 512K x 32 9 __ 512K x 32 S 8 gt gt gt lt gt amp oz 8 512K x 32 gt w CLK T a 8 g gt 512K x 32 x A 4008 d 20 Column Decoder cp Q gt m De Latency amp Burst Length g Programming Register LRAS LCBR LCAS LWCBR LDQM LWE Timing Register 2 CLK CKE CS RAS CAS DQM Samsung Electronics reserves the right to change products or specification without notice ELECTRONICS Rev 1 0 Jan 2002 K4S643232F CMOS SDRAM PIN CONFIGURATION Top view 0 Vss DQ15 Vssa DQ14 DQ13 VDDQ DQ12 DQ11 Vssa DQ10 DQ9 VDDQ DQ8 N C Vss DQM1 N C N C CLK CKE AQ A8 A7 A6 A5 A4 A3 DQM3 Vss N C DQ31 VDDQ DQ30 DQ29 Vssa DQ28 DQ27
12. z amp 18K4S643222F T C45 v R3 K4S643232F CMOS SDRAM 2M x 32 SDRAM 512K x 32bit x 4 Banks Synchronous DRAM LVTTL Hevision 1 0 January 2002 Samsung Electronics reserves the right to change products or specification without notice Rev 1 0 Jan 2002 ELECTRONICS K4S643232F CMOS SDRAM Revision History Revision 1 0 January 16 2002 Defined DC spec Revision 0 1 September 03 2001 Preliminary Added K4S643232F TC L55 Revision 0 0 September 03 2001 Target Spec Initial draft Rev 1 0 Jan 2002 ELECTRONICS K4S643232F CMOS SDRAM 512K x 32Bit x 4 Banks Synchronous DRAM FEATURES 3 3V power supply LVTTL compatible with multiplexed address Four banks operation MRS cycle with address key programs CAS latency 2 amp 3 Burst length 1 2 4 8 amp Full page Burst type Sequential amp Interleave All inputs are sampled at the positive going edge of the system clock Burst read single bit write operation DQM for masking GENERAL DESCRIPTION The K4S643232F is 67 108 864 bits synchronous high data rate Dynamic RAM organized as 4 x 524 288 words by 32 bits fabricated with SAMSUNG s high performance CMOS technol ogy Synchronous design allows precise cycle control with the use of system clock I O transactions are possible on every clock cycle Range of operating frequencies programmable burst length and programmable latencies allow the same device

Samsung K4S643232F Data Sheet

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