FUJITSU SEMICONDUCTOR MB90089 handbook
Contents
1. 4efsc Clock The value in the parentheses is applied at the final raster Vertical Timing Parameter NTSC Standard PAL M Standard PAL Standard Unit Remarks VPE VBLKE VBLKS Interlace VPS Non interlace The 0 5H in the above table indicate the count values of 1 2H on the horizontal sync signal 26 3749756 0027797 454 NH Fig 16 NTSC PAL PAL M Horizontal Timing Video signal Horizontal sync signal Horizontal blanking interval Burst flag Equalizing pulse Serrated pulse 27 3749756 0027798 390 Burzienb3 Jeon4oA OUAS JELIMA y Bi POS p 404 ves ECS eeS8 108 282 182 080 0 2 692 892 7090 990 590 90 690 zoz 190 092 652 TH Xem ur n n n n yl n j T g c pF L IL n L LE VW L n nn n Tae aysoduiog S x18A 3X18A SX 18A NM mm e R lemau asind Gurzipenb3 oe NEM E2I19A OUAS 821 Fig 17 NTSC Vertical T 892 0902 192 092 652 992 02 6L 8 4 9 S 6 929 eS 625 205 12 on Bul Buluueos reiuozuoH ms IH EN EN eubis eysoduioo 3749756 0027799 227 uang 28 Fi2. Color 6 Upper Level Veren Color 6 Lower Level Vorel Vour Vcc 5 0 V Color 5 Upper Level Color 5 Lower L Level Vets Vout Vee 5 0 V Color 4 Upper Level Color 4 Lower Level Vour 3749756 0027788 EM Vcc AVcc 5 0 V Continued 17 DC CHARACTERISTICS Recommended operating conditions unless otherwise noted Parameter Color 3 Upper Level Pin Port Color 3 Lower Level Condition Vcc 5 0V Remarks Color 2 Upper Level Color 2 Lower Level Vcc AVcc 5 0 V Color 1 Upper Level Color 1 Lower Level Color Burst Upper Level Color Burst Lower Level White Level Vcc AVcc 5 0 V Veco AVcc 5 0 V Black Level Gray Level 1 Gray Level 2 Gray Level 3 Gray Level 4 Gray Level 5 Gray Level 6 Vcc AVcc 5 0 V Vcc AVcc 5 0 V Vcc 5 0V 1 57 2 78 2 89 3 00 1 69 1 68 1 80 1 79 1 91 TE Pedestal Level SYNC Level Vni ER 3749756 0027785 188 Em Vcc AVcc 5 0 V Vcc AVcc 5 0 V lt lt lt lt lt lt lt Fig 11 Outputs on Vour Voren Vets 19 3749756 0027740 OTT EM 20 DC CHARACTERIS
3. Power supply pin for analog block The voltage level applied to this pin must be the same as Vcc Ground pin for analog block The ground level must be the same as Vss Input to the internal oscillator running with an external crystal resonator and capacitors for color burst clock NTSC 14 31818 MHz and PAL 17 734475 MHz Output from the internal oscillator running with an external crystal resonator and capacitors for color burst clock NTSC 14 31818 MHz and PAL 17 734475 MHz Input to the internal oscillator running with an external LC network circuit for display dot clock Output from the internal oscillator running with an external LC network circuit for display dot clock Test signal input pin Normally input a high level to this pin When a low level is input be sure not to issue commands Chip select pin A low level on the CS pin activates serial data transfer to the device Also this pin can be used to release the power on reset This pin is hysteresis input and pulled up internally SIN is for serial data input 8 bit serial data i including command data and character data is input to this pin while the CS is active This pin is hysteresis input and pulled up internally SCLK is for shift clock input to the internal register At the rising edge of SCLK data on the SIN pin is shifted into the internal register This pin is hysteresis input and pulled up internally Luminance signal Y sign
4. MB90089 PFT FUJITSU SEMICONDUCTOR DATA SHEET DS04 28821 1E DESCRIPTION The MB90089 CMOS On screen Display Controller OSDC is a peripheral LSI that displays 288 alphanumeric characters 24 rows x 12 lines and figures on TV screen by a microcontroller Since the MB90089 contains a character generator ROM CGROM which is capable to store 256 characters including special characters Kanji characters and Kana characters it can be used even for Japanese display in addition to the standard alphanumeric display The MB90089 contains a video signal generator for NTSC PAL system so that the characters and figures can be displayed synthesizing with this internally generated video signal even no external video signal present Also the MB90089 incorporates video signal analog switches to synthesize characters with a video signal Three video outputs are available on the MB90089 a composite video a Y C separate video and a RGB digital outputs Also the device has two video inputs a composite video and a Y C separate video inputs The superimposed display function is possible at either composite video input or Y C separate video input The MB90089 is fabricated by the silicon gate CMOS process and housed in a 28 pin plastic SOP Suffix PF package Because the MB90089 OSDC device has these powerful character display and control abilities it is suitable for on screen display on such applicable audio video eq
5. 1 play SW18A 2159 51889 3903 SdA SX18A 3159 jeasaquy as nd Burzenb3 jeasaqul Burgueq yung JEHA 2u s EIA ON Buruue s cle Of 606 80 ES 529 v29 29 09 159 1 oapia aysodwag u PLC mir G EI YV pm aseud ysunq 1002 Ploy 18114 ON L 29 3749756 0027800 879 PACKAGE DIMENSIONS MB90089PF 28 LEAD PLASTIC FLAT PACKAGE CASE 28 02 010 008 E 699 40 25 17 75 2020 HHH HAH EL 018 004 0 45 0 10 HH 650 16 51 REF 1991 FUJITSU LIMITED F28011S 4C 30 465 012 11 80 0 30 339 008 8 60 0 20 aN 4 005 0 13 9 MOUNTING HEIGHT 0 0 MIN r 110 2 80 MAX STAND OFF HEIGHT 402 012 10 20 0 30 TE 031 008 PE 0 80 0 20 006 002 Details of A part 008 0 20 024 0 60 007 0 18 MAX 027 0 68 Dimensions in inches millimeters 3749756 0027801 705
6. display memory via serial data transfer Table 2 lists the display control commands of the MB90089 Table 2 Display Contro Commands Com First Byte Command ID code Data mand No 67 b1 b0 Second Byte Data b7 b6 b5 b4 b3 b2 bi bo Preset VRAM address Set character and character background color Write character code to VRAM Sprite Control 1 Screen Control 1 Screen Control 2 Line Control Set vertical display start position Set horizontal display start position Set under color Reserved commands Sprite Control 2 Sprite Control 3 rs ee ee ee ee P soga E a aja Reserved commands Notice that Reserved Commands Command 9 11 14 and 15 are not effective for the device control Do not issue these commands 32749756 0027784 a 13 ANALOG SWITCH CIRCUIT Figure 9 shows a functionally equivalent circuit of the analog switch section used to synthesize character information with an externally input or internally generated video signal Fig 9 Equivalent Circuit of Analog Switch Block Composite video signal generator Luminance signal generator CMOS analog switch 14 EN 3749756 0027785 732 EM POWER ON RESET A power on reset means that the device generates a
7. is operating in external sync control mode superimposed color display is possible controlling the EXS pin input clock to match the signal phase between the output signal from this pin and the color burst signal of the externally input video signal This pin functions with the FO bit setting in the internal register by command 7 Horizontal sync signal output pin This pin is also used for composite sync signal output Furthermore by forcing the TEST pin low this pin outputs a fsc clock Vertical sync signal output pin Also by forcing the TEST pin low this pin outputs an oscillation clock for the dot clock External horizontal sync signal input pin This pin is also used for composite sync signal input This is a hysteresis input and internally pulled up EXVSYN External vertical sync signal input pin This is a hysteresis input and internally pulled up 374475 0027777 LLL DISPLAY FUNCTIONS The MB90089 provides two types of screen display external sync controlled operation and internal sync controlled operation External sync controlled operation is used for the superimposed display of an externally input video signal and characters Internal sync controlled operation is used to display characters after superimposing them with the internally generated video signal generated by the built in video signal generator In internal sync controlled operation the MB90089 allows 8 color co
8. signal On chip video signal generator conforming to NTSC and PAL systems Separate or composite sync signal input output 8 bit serial input to interface with microcontroller On chip two clock generators Display dot clock Color burst clock nternal color burst phase signal output to allow superimposed display in color adding the external compo nents Power on reset function Single 5 V power supply Wide operating temperature range 459 to 85 C Silicon gate CMOS process Package 28 pin plastic SOP Suffix PF MB90089 PF 28 PIN PLASTIC SOP 28 02 3749756 01027773 PIN ASSIGNMENT MB90089 PF YIN 10 CIN 2 27 VIN 3 26 AVcc 4 25 FSCO 5 24 VBLK 6 23 Voc 7 View 22 EXS 8 XS 9 HSYNC VSYNC 11 EXHSYN 12 17 EXVSYN 13 16 l A 3749756 0027774 957 BLOCK DIAGRAM 8 Bit Serial Data Interface Control To each control register H V Separator s NTSC PAL Signal m Generator Video Signal Generator Display Memory Control 4FSC Clock Oscillator Dot Clock Oscillator 174475 0027775 233 PIN DESCRIPTION Figure 1 and Table 1 show the pin assignment and pin description of the MB90089 Symbol Pin No Type Table 1 Pin Description Name amp Function Power ad Power supply pin Ground pin
9. the vertical direction line as shown in Figure 3 Also four types of character size are available on MB90089 A standard size which consists of 12 x 18 dot matrix and other 3 kinds of enlarged size These four types of character size can be specified for each line on the screen Figure 4 shows an example of character display with coexisting two types of size Fig 3 Character Dot Configuration Without pattern Background pattern displayed when pat terned background is specified Character pattern LES Labi BHJABCDEFGHLIEJKLMN Standard QOPQRSTUVWNYZabcdefehijkl E AS Pow EMO a Wu PESE NOM 4 1 Ney hF TO 1 2 34 T ABCDEFGHIJKL MNOPQRSTUVWX UPS SS pus op PE Bg D za Standard KEPTI vA EU Ae bF 2 Q ESA 4 5 T 3749756 0027780 150 EM 10 CONFIGURATION OF CGROM The Character Generator ROM CGROM is configured with 12 dots horizontal x 18 dots vertical It has a storage capacity for up to 256 character including the end code The CGROM s address is corresponding to the character s code Figure 5 shows the CGROM s configuration Fig 5 CGROM Configuration CGROM Address character code 12 x 18 dot matrix Character area Character area Character area End Code FFH Blank character CHARACTER DISPLAY FORMAT The MB90089 allows to select a character display format from character only patterne
10. to the conditions as detailed in the operational sections of this data sheet Exposure to absolute maximum rating conditions for extended periods may affect device reliability RECOMMENDED OPERATING CONDITIONS Parameter Condition Operation guaranteed range Power Supply Voltage Make sure no different voltage level between Vcc and AVcc Input High Voltage 0 8eVcc 40 3 Input Low Voltage Vss 0 3 0 2eVcc Analog input Voltage 0 Operating Ambient Temperature 40 BE 37453755 0027787 505 AN DC CHARACTERISTICS Recommended operating conditions unless otherwise noted Parameter Symbol Output High Voltage Von VOC2 1 Min Vcc 4 5 V lou 200 pA 4 0 4 4 Output Low Voltage 4 5 V lo 3 2 mA 0 2 0 6 SIN SCLK CS Unloaded Input Current l EXHSYN ry nd 14 60 pa EXVSYN TEST 5 5 fc 4fsc Supply Current lec Vcc 17 734475 MHz 45 60 mA foc 8 MHz Rvon VIN VOUT Mal dg 4 5V ON resistance Ryon YIN YOUT 2 yan pa CIN COUT uk 45V lvore VIN Mage oe z55V _ 25 o CIL ae lvorr YIN 5 55V _ a n Icorr CIN AVcc 5 5 V Ci 25 5V
11. TICS Recommended operating conditions unless otherwise noted Parameter Color 6 Upper Level Color 6 Lower Level Pin Port Condition Vee AVcc 5 0 V Unit Remarks Color 5 Upper Level Color 5 Lower Level Vcc 5 0 V Color 4 Upper Level Color 4 Lower Level Vcc AVcc 5 0 V Color 3 Upper Level Color 3 Lower Level Color 2 Upper Level Color 2 Lower Level Color 1 Upper Level Color 1 Lower Level Vcc AVcc 5 0 V Vcc AVcc 5 0 V Vcc AVcc 5 0 V Color Burst Upper Level Color Burst Lower Level Pedestal Level Vcc 5 0 V 3749756 0027741 NN Vcc 5 0 V lt lt lt lt lt lt lt lt lt lt lt lt lt DC CHARACTERISTICS Recommended operating conditions unless otherwise noted White Level Parameter Symbol Ywur Your com Min Vcc 5 0 V 2 78 Unit Remarks Black Level Pedestal Level Vcc 5 0V 1 46 1 57 1 SYNC Level Vcc AVcc 5 0V 0 84 1 00 V Vcc 5 0V 1 57 1 68 1 79 V Gray Level 1 Yonvi 1 69 1 80 1 91 V Gray Level 2 Yonv2 1 81 1 92 2 03 V Gray Level 3 Yary3 1 92 2 03 2 14 V
12. Your Vee 5 0 V Gray Level 4 Yanva 2 15 2 26 2 37 V GrayLevel5 Yonvs 227 238 249 V Gray Level 6 Yonve 2 38 2 49 2 60 V V V Ywur Yanvs Yanvs Yorys Yrs Cros Fig 12 Outputs on Cour and Your EN 2749756 0027732 972 Yerv Yeux 21 AC CHARACTERISTICS Recommended operating conditions unless otherwise noted Oscillator Characteristics Parameter Symbol Pin Port Remarks Display Dot Clock Input signal with duty Frequency 50 is required Input signal with duty 14 31818 5096 is required NTSC system Input signal with duty 17 734475 50 is required PAL system Input signal with duty 14 302446 5096 is required PAL M system Fig 13 Clock Circuit Configuration Dot clock Color burst clock EX4fsc 22 3749756 0027793 809 AC CHARACTERISTICS Recommended operating conditions unless otherwise noted Serial I O Interface Timing Parameter Shift Clock Cycle Time Symbol Remarks Shift Clock Pulse Width Shift Clock Rise Time Shift Clock Fall Time Shift Clock Start Time Data Setup Time Data Hold Time Chip Select End Tlme Chip Select Rise Time Chip Select Fall Time H
13. al input for the superimposed display A DC restored DC clamped 2 Vp p signal with sync tip level 1 V and pedestal level 1 57 V is input to this pin Chroma signal C signal input for the superimposed display Input a signal with a DC 1 57 V and color burst signal amplitude 0 57 Vp p Composite video signal input for the superimposed display Input a DC restored DC clamped 2 Vp p signal with sync tip level 1 V and pedestal level 1 57 V Continued 3749756 02777 727 Continued Symbol PinNo Type Name amp Function Analog I O Port Composite video signal output pin This pin outputs 2 Vp p signal with sync tip level 1 V and pedestal level 1 57 V Chroma signal output pin This pin outputs a signal with a DC 1 57 V and a color burst amplitude 0 57 Vp p Luminance signal output pin This pin outputs 2 Vp p signal with sync tip level 1 V and pedestal level 1 57 V Vertical blanking signal output pin This pin outputs a low level during the vertical blanking interval This is a character and its background signals output pin While this pin outputs a high level character and patterned or filled background information are output VOC2 VOC0 These are character signal output pins These pins output a character color character background color and under color Internal color burst phase signal output pin While the device
14. cal blanking interval zb 19 to 21 25 H Note 1 First equalizing pulse interval 3 2 5 H Note 1 Vertical sync pulse interval 3 2 5 H Note 1 Second equalizing pulse interval 3 2 5 H Note 1 Equalizing pulse width 2 29 to 2 54 2 30 0 1 2 35 50 1 us Equalizing pulse period 0 5 0 5 H 1 Serrated pulse width 3 81 to 5 34 47301 47302 us Serrated pulse period Horizontal sync signal period Horizontal sync signal pulse width H V Separation Sync Signal Input Timing Vertical sync signal frequency Horizontal blanking time 10 510 11 4 10 9 10 2 12 0 3 Note 1 H is counted in units of horizontal sync signal periods i e 1H one horizontal sync signal period Parameter NTSC 0 5 0 5 H 63 555 64 us 4 7 01 4 7 30 2 us us PAL M PAL 50 Vertical sync signal pulse width 1105 1104 Horizontal sync signal period Horizontal sync signal pulse width Note 1 H is counted in units of horizontal sync signal periods i e 1H one horizontal sync signal period 3749756 0027796 5150 MB 25 INTERNAL SYNC SIGNAL OUTPUT TIMING Horizontal Timing Parameter NTSC Standard PAL M Standard PAL Standard Unit Remarks 4efsc Clock See Figure 16 4efsc Clock 4efsc Clock 4efsc Clock 4efsc Clock 4efsc Clock 4efsc Clock 4efsc Clock 4efsc Clock 1050 4efsc Clock 1106 4efsc Clock 1135 1137
15. d background border filled background displays for each line and also character background displays for each character by setting the internal registers Figure 6 shows an example for each of the character display formats Example of character Fig 6 Character Display Format BC 0 character only display BC 1 0 patterned background BG 1 BK 1 filled background display E 3749756 0027741 097 SHADED BACKGROUND DISPLAY The 90089 also has the shaded background display shadowing background function that adds amp white line along the character s rectangle area to display the character like in three dimension The shaded background can be set for character unit The shaded background color black amp white can be exchanged reversed SPRITE CHARACTER DISPLAY The MB90089 has another unique function called sprite character display that makes a character motion smooth The sprite character can be displayed on screen synthesizing with the normal characters being displayed The Sprite character motion can be set in character dot unit and one character can be displayed on one screen The sprite character codes are specified in the CGROM codes 8Fu to FFu 8 kinds of color or 8 gray scale level can be specified for the sprite character CHARACTER DISPLAY START POSITION The MB90089 allows to choose from 64 display start positions in the horizontal and 32 positions in the
16. g 18 PAL Vertical Timing S L T 661 eui jo eseud eui sejeorpur 2 BON esind Burzijenbe ul uonisod ONASH sejeoipui SION SdA SIGA 3159 3X 18A 51589 3dO3 SX 18A 31S8 1 T 0 1 pemaju Buryuejq Isang a SS e le cs Pc uueg JLA jeasayul 2446 JEHA I Az v dE APTENT ON ull Buiuueos jeiuozuog ZI SLE PLE SLE SIE LIE OLE 606 jeubis oapia ausoduro L 509 09 629 229 129 Zee 968 GEE ee de i P 4 et ETE CL CL aseyd jsinq 1002 1 t t T T l L HOA SdA SX 18A S1S8 3X 18A S1S8 3dO4 SX 18A 3188 t D 7 2u s EIMA _ _ kt r e ON Buiuue s eiuozuo ele cle tie ole 606 808 ve 20 2 9 5 4 L 989 29 620 009 129 jeuBis capa aysoduio n n f igri gt fg gt ht aseud 16119 100 4 T 1 T 1 T 1 1 Play PAUL penau asind furzienb3 Burjuerq ising lemau Buyyuerg Ie313aA 2066 EIA ON eui Buruue s jejuozuoH L 409 09 629 cc9 gee see 026 618 81 ALE Ele cle IPS 60 jeuBis oapia aysoduio i ia NI a PM o n Ro qiu d AM aseyd 45114 1002
17. ith the least significant bit LSB The data is latched and shifted in on each rising edge of the shift clock input to the SCLK pin as shown in Figure 10 The transferred data is loaded into the internal FIFO First In First Out 1 byte buffer on the shift clock rising edge at the eighth bit The data is read from FIFO and processed at times other than the display memory write period Thus commands and data can be written to the MB90089 at any time regardless of its display operation i e asynchronously with display by using the FIFO buffer In serial transfer the number of received bits is counted by shift clock counts Serial transfer may be reset by forcing the CS pin High the reset can be cleared by driving the CS pin from High to Low so that the subsequent eight bits of data eight shift clock counts are handled as byte data this way byte synchronization can be maintained by using the CS pin If the CS signal goes High before eight bits of data are transferred the data becomes invalid Fig 8 Serial Transfer Timing LSB MSB LSB MSB First byte First byte or second byte or n th byte To maintain byte synchronization the CS pin should be temporarily returned High before serial data transfer and set Low level to initiate data transfer 12 3749756 0027753 SLT LIST OF CONTROL COMMANDS The MB90089 control display control is done by writing data to the internal registers and
18. lor display Figure 1 shows display examples in each video mode Fig 1 Video Modes INT SYNC CONTROL External sync controlled operation Internal sync controlled operation Superimposed display Color monochrome gray scale display Note For external sync controlled operation characters are always displayed with monochrome gray scale 27 475 0027778 5 2 DISPLAY SCREEN CONFIGURATION The MB90089 has a 288 character display memory VRAM so that when using the standard character size it can display characters in up to 24 rows x 12 lines 2 288 characters on one screen When using enlarged characters the number of characters that can be displayed on a screen is reduced depending on how much they are enlarged Four character sizes called standard size and 3 kinds of enlarged size can be set and specified either size for each line So the 90089 can display characters of four different sizes together on the same screen Figure 2 shows the display screen configuration Fig 2 Display Screen Configuration 24 rows 12 lines ER 2749756 0027779 439 B CHARACTER CONFIGURATION The 90089 incorporates character generator ROM CGROM that can store up to 256 characters including the end code Each character generated by CGROM consists of a 12 x 18 dot matrix Each character is displayed with a dot matrix consisting of 12 dots in the horizontal direction row and 18 dots in
19. n internal reset signal to initialize its operation upon detection of power on Input the CS signal four times to clear a power on reset Figure 10 shows a timing of how a power on reset is cleared Fig 10 Clearing Power on Reset Internal reset signal CS input DEVICE INITIALIZATION When reset at power on the MB90089 s screen control register has its IE internal external sync control bit and DC display control bit cleared to 0 and screen display is turned off under internal sync control After power on clear a power on reset first Then set the screen control registers DC bit to 1 to turn display on after setting all register data and all VRAM contents to be displayed 37u3 5b 0027766 b EUM 15 B ELECTRICAL CHARACTERISTICS ABSOLUTE MAXIMUM RATINGS See NOTE Parameter Condition Make sure no different voltage level between and Vcc Make sure no different voltage Power Supply Voltage level between AVcc and Make sure no different voltage level between AVcc and Vcc Should not exceed Vcc 40 3 V Input Voltage Should not exceed Vcc 0 3 V Output Voltage Should not exceed Vcc 0 3 V Power Dissipation Operating Ambient Temperature Storage Temperature NOTE Permanent device damage may occur if the above ABSOLUTE MAXIMUM RATINGS are exceeded Functional operation should be restricted
20. orizontal Sync Rise Time Horizontal Sync Fall Time Vertical Sync Rise Time Vertical Sync Fall Time EXHSYN EXVSYN EXVSYN Horizontal Sync Signal Pulse Width EXHSYN When H V separate sync signals are input Vertical Sync Signal Pulse Width EXVSYN When H V separate sync signals are input Horizontal Sync Signal Detective Pulse Width EXHSYN When H V composite sync signal is input Vertical Sync Signal Detective Pulse Width EXVSYN EN 3749756 When H V composite sync signal is input 23 0027794 745 EN Power On Reset Timing Parameter Power Supply Rising Required for the operation of the power Time on reset circuit Power Supply Shut off Required for the accurate circuit Time operation repeatly CS rise time after power supply rising See Figure 17 Power on reset release pulse width See Figure 17 Fig 14 Power On Reset Timing Power supply should be raised smoothly Fig 15 Power On Reset Release Timing Voc Internal 55 Reset 24 3749756 0027795 1 MN RECOMMENDED EXTERNAL SYNC SIGNAL INPUT TIMING Composite Sync Signal Input Timing Number of frame scanning lines Parameter NTSC PAL M 525 625 H Note 1 Remarks Field frequency 59 94 50 Hz Line frequency 15734 264 15625 Hz Verti
21. uipment as VCRs FEATURES Character display controller available for NTSC and PAL TV sets 24 rows x 12 lines screen format Max 288 characters screen 12 x 18 dot matrix high quality character format 256 character set capability in character generator ROM CGROM including the blank code FFn Programmable display control Character size 1 width x 1 height 1 width x 2 heights 2 widths x 1 height or 2 widths x 2 heights per line Character display position horizontal per 1 4 character vertical per 2 rasters line space per raster 0 to rasters 8 kinds of color monochrome for under color character by internal video signal generator Patterned Bordered or filled background character display Shaded background display Continued This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields However it is advised that normal precautions be taken to avoid application of any voltage higher than maximum rated voltages to this high impedance circuit 3749756 0027772 O84 Continued Sprite character display 8 characters can be specified as sprite character codes 8Fx to FF and one character can be displayed On chip display data RAM VRAM Analog Video Inputs Composite video signal Y C separate video signal Three channel Video Output Composite video signal Y C separate video signal RGB digital
22. vertical directions by setting each internal register Also line space can be set in raster unit 0 to 7 rasters By setting the appropriate display start positions depending on the screen configuration you can arrange character placement so it is balanced across the screen To set the display start position of characters specify the dot position at the upper left corner of the character at the upper left part of the screen The display start position can be set in units of 3 dots 1 4 character in the horizontal direction and in units of 2 dots 2 rasters in the vertical direction Figure 7 shows how the start position is specified in the horizontal and the vertical directions Fig 7 Character Display Start Position Vertical display start position Display Screen Horizontal display start position 3749756 0027782 T23 11 DATATRANSFER Display control commands and data are written to the MB90089 via 8 bit serial transfer block This serial transfer is done by using three signals CS chip select SCLK shift clock and SIN serial data input Figure 8 shows the timing of serial transfer The CS pin is for the chip select signal and is set Low for serial transfer The SCLK pin is for the shift clock signal for data reception The SIN pin is for the serial data input signal The data is eight bits length and sequentially shifted into the SIN pin beginning w
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FUJITSU SEMICONDUCTOR MB90089 handbook