ST M41ST84Y M41ST84W Manual
Contents
1. 8 Figure 10 Bus Timing Requirements Sequence 9 Table 2 AC Characteristies ey ORE xp Ua Pulp ter eee he 9 5 2 ere ee 10 Figure 11 Slave Address 10 Figure 12 READ Mode 1 10 Figure 13 Alternate READ Mode 11 WRITE MOd6G lll ERR e aimed ue 11 Data Retention 11 Figure 14 WRITE Mode Sequence 11 CLOCK OPERATION mpm oce 12 Power down 12 TIMEKEEPER 12 Table 3 TIMEKEEPERO Register Map 13 Calibrating the uu RR E AR mre e RR d ce 14 Figure 15 Crystal Accuracy Across Temperature 15 Figure 16 Clock Galibratiomi APER TRA E 15 Setti2. 1 Figure 1 16 SOIC 1 Figure 2 28 SOIC 1 SUMMARY 2 2 4 3 Logic Diagram de eR IRR LODS Ee E Re e 4 Table t Signal Names Ux Rx ex EAR E E RR ans 4 Figure 4 16 SOIC Connections 5 Figure 5 28 pin SOIC Connections 5 Figure 6 Block 1 5 Figure 7 Hardware 6 OPERATING MODES 2 542 14 7 2 Wire Bus 7 Bus notbusy cse 7 Start dataitranster RR Rex HORROR EROR UR RORIS E RR RR a 7 Slop data transfer RI QU Be 7 Data Valid ees or Rcx te 7 Acknowledge s sot auae tec Rake der 7 Figure 8 Serial Bus Data Transfer Sequence 8 Figure 9 Acknowledgement Sequence
3. 010023 D pw Dep o oae oror s 3 Dep e em ww m9 wes sues o _ 1 Ls em wr Www Aamo maes Amines _ wm v a fe yo wm 9 fe fe fe 9 m e o o xm o e fo 9 9650 mg o 696 fo Keys Sign Bit RBO RB1 Watchdog Resolution Bits FT Frequency Test Bit WDS Watchdog Steering Bit ST Stop Bit ABE Alarm in Battery Back Up Mode Enable Bit 0 Must be set to zero RPT1 RPT5 Alarm Repeat Mode Bits BL Battery Low Flag Read only WDF Watchdog flag Read only 4 Watchdog Multiplier Bits AF Alarm flag Read only CEB Century Enable Bit SQWE Square Wave Enable CB Century Bit 0 3 SQW Frequency OUT Output level HT Halt Update Bit AFE Alarm Flag Enable Flag TR trec Bit 13 81 M41ST84Y M41ST84W Calibrating the Clock The M41ST84Y W is driven by a quartz controlled oscillator with a nominal frequency of 32 768Hz The devices are tested not exceed 35 ppm parts per million oscillator frequency error at 25 C which equates to about 1 53 minutes per month When the Calibration circuit is properly em ployed accuracy i
4. 4 28 125 Lithium Battery 48mAh and Crystal SNAPHAT M4T32 BR12SH Lithium Battery 120mAh and Crystal SNAPHAT 29 31 M41ST84Y M41ST84W REVISION HISTORY Table 21 Document Revision History Dat Revision Details 24 Aug 00 Block Diagram added Figure 6 08 Sep 00 SO16 package measures change 18 Dec 00 2 0 Reformatted TOC added and PFI Input Leakage Current added Table 12 Addition of trec information table changed one added Tables 3 7 changes to 18 Jun 01 24 graphic see Figure 6 change to DC and AC Characteristics Order Information Tables 12 2 19 note added to Setting Alarm Clock Registers section added temp voltage info to tables Table 11 12 13 2 14 addition of Default Values Table 8 textual improvements 25 Jun 01 Special note added in CLOCK OPERATION page 12 26 Jul 01 Change in Product Maturity 07 Aug 01 Improve text for Setting the Alarm Clock section 20 Aug 01 Change Vprp values in document DC Characteristics changed PFI Hysteresis PFI Rising spec added and Crystal Electrical Characteristics Series Resistance spec changed Tables 12 13 3 03 Dec 01 3 4 Change READ WRITE Mode Sequence drawings Figure 12 14 change in Vprp lower limit for 5V M41ST84Y part only Table 12 19 14 Jan 02 Change Series Resistance Table 13 01 May 02 Change trec Definition Table 7 modify reflow time and temperature footnote Table 9 03 J
5. 0 0220 28 31 M41ST84Y M41ST84W PART NUMBERING Table 19 Ordering Information Scheme Example 415 84 6 Device 415 Supply Voltage and Write Protect Voltage 84Y Voc 4 5 to 5 5V 4 20V lt Vprp lt 4 50V 84W Voc 2 7 to 3 6V 2 55V lt Vpep lt 2 70V Package MQ SO16 1 2 SOH28 Temperature Range 6 40 to 85 Shipping Method For SO16 blank 2 Tubes Not for New Design Use E E Lead free Package ECO amp amp PACKS Tubes Lead free Package Tape amp Reel TR Tape amp Reel Not for New Design Use F For SOH28 blank Tubes Not for New Design Use E E Lead free Package ECO amp amp PACK Tubes Lead free Package Tape amp Reel TR Tape amp Reel Not for New Design Use F Note 1 The 28 pin SOIC package SOH28 requires the battery crystal package which is ordered separately under the number 4 125 in plastic tube or 4 125 in Tape amp Reel form see Table 20 2 Contact Local Sales Office Caution Do not place the SNAPHAT battery package 4 125 in conductive foam it will drain the lithium button cell bat tery For other options or for more information on any aspect of this device please contact the ST Sales Office nearest you Table 20 SNAPHAT Battery Table
6. To NMI 103680 6 31 OPERATING MODES The M41ST84Y W clock operates as a slave de vice on the serial bus Access is obtained by im plementing a start condition followed by the correct slave address DOh The 64 bytes con tained in the device can then be accessed sequen tially in the following order 1 Tenths Hundredths of a Second Register 2 Seconds Register 3 Minutes Register 4 Century Hours Register 5 Day Register 6 Date Register 7 Month Register 8 Year Register 9 Control Register 10 Watchdog Register 11 16 Alarm Registers 17 19 Reserved 20 Square Wave Register 21 64 User RAM The M41ST84Y W clock continually monitors Vcc for an out of tolerance condition Should Vcc fall below Vprp the device terminates an access in progress and resets the device address counter Inputs to the device will not be recognized at this time to prevent erroneous data from being written to the device from a an out of tolerance system When falls below Vso the device automati cally switches over to the battery and powers down into an ultra low current mode of operation to conserve battery life As system power returns and Vcc rises above Vso the battery is disconnected and the power supply is switched to external Vcc Write protection continues until Vcc reaches Vprp min plus min For more information on Battery Storage Life refer to Application Note AN1012
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8. power input is clock The M41ST84Y W slave receiver will send switched from the pin to the SNAPHAT or an acknowledge clock to the master transmitter af external battery and the clock registers and ter it has received the slave address see Figure SRAM are maintained from the attached battery 11 page 10 and again after it has received the supply word address and each data byte All outputs become high impedance On power up when Vcc returns to a nominal value write protec tion continues for The RST signal also re mains active during this time see Figure 21 page 24 For a further more detailed review of lifetime calcu lations please see Application Note AN1012 Figure 14 WRITE Mode Sequence BUS ACTIVITY 5 MASTER o WORD SDA LINE ADDRESS An DATAn DATA n 1 DATA n X i 5 5 5 5 5 USAC SLAVE ADDRESS 100591 11 31 M41ST84Y M41ST84W CLOCK OPERATION The eight byte clock register see Table 3 page 13 is used to both set the clock and to read the date and time from the clock in a binary coded decimal format Tenths Hundredths of Sec onds Seconds Minutes and Hours are contained within the first four registers Note A WRITE to any clock register will result in the Tenths Hundredths of Seconds being reset to 00 and Tenths Hundredths of Seconds cannot be written to any value other than 00 Bits D6 and
9. 85 C Vcc 2 7 to 3 6V or 4 5 to 5 5V except where noted 2 Pulse width less than 50ns will result in no RESET for noise immunity 3 Programmable see Table 8 page 21 19 31 M41ST84Y M41ST84W Power fail INPUT OUTPUT The Power Fail Input PFI is compared to an in ternal reference voltage 1 25V If PFl is less than the power fail threshold Vpri the Power Fail Output PFO will go low This function is intended for use as an under voltage detector to signal a failing power supply Typically is connected through an external voltage divider see Figure 7 page 6 to either the unregulated DC input if it is available or the regulated output of the Vcc reg ulator The voltage divider can be set up such that the voltage at PFI falls below Vpri several millisec onds before the regulated Vcc input to the M41ST84Y W or the microprocessor drops below the minimum operating voltage During battery back up the power fail comparator turns off and PFO goes or remains low This oc curs after Vcc drops below Vprp min When pow er returns PFO is forced high irrespective of Vpri for the write protect time which is the time from Vpep max until the inputs are recognized At the end of this time the power fail comparator is enabled and PFO follows PFI If the comparator is unused PFI should be connected to Vss and PFO left unconnected Century Bit Bits D7 and D6 of Clock Register O3h contain the CENTUR
10. D7 of Clock Register 03h Century Hours Register contain the CENTURY ENABLE Bit CEB and the CENTURY Bit CB Setting CEB to a 1 will cause CB to toggle either from 0 to 1 or from 1 to 0 at the turn of the century de pending upon its initial state If CEB is set to a 0 CB will not toggle Bits DO through D2 of Register 04h contain the Day day of week Registers 05h 06h and 07h contain the Date day of month Month and Years The ninth clock register is the Control Register this is described in the Clock Calibration section Bit D7 of Register 01h con tains the STOP Bit ST Setting this bit to a 1 will cause the oscillator to stop If the device is expect ed to spend a significant amount of time on the shelf the oscillator may be stopped to reduce cur rent drain When reset to a 0 the oscillator restarts within one second The eight clock registers may be read one byte at a time or in a sequential block The Control Reg ister Address location 08h may be accessed in dependently Provision has been made to assure that a clock update does not occur while any of the eight clock addresses are being read If a clock ad 12 31 dress is being read an update of the clock regis ters will be halted This will prevent a transition of data during the READ Power down Time Stamp When a power failure occurs the Halt Update Bit HT will automatically be set to a 1 This will pre vent the clock from updatin
11. data byte which was addressed will be transmitted and the master receiver will send an Acknowledge Bit to the slave transmitter The address pointer is only incremented on reception of Acknowledge Clock The M41ST84Y W slave transmitter will now place the data byte at address 1 on the bus the master receiver reads and acknowledges the new byte and the address pointer is incremented to 2 Figure 11 Slave Address Location 1 1 Figure 12 READ Mode Sequence tc BUS ACTIVITY 2 lt c c WORD ae SDA LINE ADDRESS An DATA DATA n 1 BUS ACTIVITY 5 Es 5 5 lt lt lt lt lt SLAVE SLAVE ADDRESS ADDRESS 02 v 0899 lt 2 START SLAVE ADDRESS In 11111011 01010 This cycle of reading consecutive addresses will continue until the master receiver sends a STOP condition to the slave transmitter see Figure 12 page 10 The system to user transfer of clock data will be halted whenever the address being read is a clock address 00h to 07h The update will resume ei ther due to a Stop Condition or when the pointer increments to a non clock or RAM address Note This is true both in READ Mode and WRITE Mode An alternate READ Mode may also be implement ed whereby the master reads the M41ST84Y W slave without first writing to the volatile address pointer The first address th
12. exceed 180 for between 90 to 150 seconds 2 For SO package Lead free Pb free lead finish Reflow at peak temperature of 260 C total thermal budget not to exceed 245 C for greater than 30 seconds CAUTION Negative undershoots below 0 3V are not allowed on any pin while in the Battery Back up mode CAUTION Do NOT wave solder SOIC to avoid damaging SNAPHAT sockets 571 21 31 M41ST84Y M41ST84W DC AND AC PARAMETERS This section summarizes the operating and mea ment Conditions listed in the relevant tables De surement conditions as well as the DC and AC signers should check that the operating conditions characteristics of the device The parameters in in their projects match the measurement condi the following DC and AC Characteristic tables are tions when using the quoted parameters derived from tests performed under the Measure Table 10 DC and AC Measurement Conditions 0 2 to 0 8Vcc 0 2 to 0 8 Input and Output Timing Ref Voltages 0 3 to 0 7Vcc 0 3 to 0 7Vcc Note Output Hi Z is defined as the point where data is no longer driven Figure 20 AC Testing Input Output Waveforms 102568 Note 50pF for M41ST84W Table 11 Capacitance Low pass filter input time constant SDA and SCL Note 1 Effective capacitance measured with power supply at 5V Sampled only not 100 tested 2 At 25 f 1MHz 3 Outputs deselected 22 31 M41ST84Y M41ST
13. mode 6 For rechargeable back up max may be considered Vcc Table 13 Crystal Electrical Characteristics Externally Resonant Frequency 32 768 cL Note 1 Load capacitors are integrated within the M41ST84Y W Circuit board layout considerations for the 32 768kHz crystal of minimum trace lengths and isolation from RF generating signals should be taken into account 2 STMicroelectronics recommends the KDS DT 38 1TA 1TC252bE127 Tuning Fork Type thru hole the DMX 26S 1TJS125FH2A212 SMD quartz crystal for industrial temperature operations can be contacted at kouhou kdsj co jp or ht tp www kdsj co jp for further information on this crystal type 23 31 M41ST84Y M41ST84W Figure 21 Power Down Up Mode Waveforms Vprp max Vprp min Vso INPUTS Y DON T CARE X RECOGNIZED RST HIGH Z OUTPUTS VALID ses VALID PER CONTROL INPUT PER CONTROL INPUT 103681 Table 14 Power Down Up Characteristics En EM NN NN NN EAM Vprp max to Vcc Fall Time trg tPFD to Vcc Rise Time Vss to Vprp min Vcc Rise Time Note 1 Valid for Ambient Operating Temperature TA 40 to 85 C Vcc 2 7 to 3 6V or 4 5 to 5 5V except where noted 2 Vprp max to VpFp min fall time of less than tF may result in deselect
14. ose bk AU RR 21 MAXIMUM RATING uou X9 RE uera a ex RU cn woe Eon 21 Table 9 Absolute Maximum 05 21 DC AND 65 22 Table 10 DC and AC Measurement Conditions 22 Figure 20 AC Testing Input Output 22 11 35 eO a RE EA es tide aah 22 Table 12 DC 23 Table 13 Crystal Electrical Characteristics Externally Supplied 23 Figure 21 Power Down Up Mode AC 24 Table 14 Power Down Up AC Characteristics 24 PACKAGE MECHANICAL 25 Figure 22 5016 16 lead Plastic Small Outline Package 25 Table 15 5016 16 lead Plastic Small Outline Package Mechanical Data 25 Figure 23 5 28 28 lead Plastic Small Outline Battery SNAPHAT Package Outline 26 Table 16 SOH28 28 lead Plastic Small Outline battery SNAPHAT Package Mechanical Data 26 Figure 24 SH 4 pin S
15. tion step in the calibration register Assuming that the oscillator is running at exactly 32 768Hz each of the 31 increments in the Calibration byte would represent 10 7 or 5 35 seconds per month 14 81 which corresponds to a total range of 45 5 or 2 75 minutes per month Two methods are available for ascertaining how much calibration a given M41ST84Y W may re quire The first involves setting the clock letting it run for a month and comparing it to a known accurate ref erence and recording deviation over a fixed period of time Calibration values including the number of seconds lost or gained in a given period can be found in Application Note AN934 TIMEKEEPER CALIBRATION This allows the designer to give the end user the ability to calibrate the clock as the environment requires even if the final product is packaged in a non user serviceable enclosure The designer could provide a simple utility that ac cesses the Calibration byte The second approach is better suited to a manu facturing environment and involves the use of the IRQ FT OUT pin The pin will toggle at 512Hz when the Stop Bit ST D7 of 01h is 0 the Fre quency Test Bit FT D6 of 08h is 1 the Alarm Flag Enable Bit AFE D7 of OAh is 0 and the Watchdog Steering Bit WDS D7 of 09h is or the Watchdog Register 09h 0 is reset Any deviation from 512Hz indicates the degree and direction of oscillator frequency shift at the test temperat
16. 00587 Figure 9 Acknowledgement Sequence CLOCK PULSE FOR START ACKNOWLEDGEMENT SCLK FROM MASTER 32 IS BY TRANSMITTER m iis DATA OUTPUT T BY RECEIVER 100601 8 31 M41ST84Y M41ST84W Figure 10 Bus Timing Requirements Sequence SDA tBUF tHD STA tHD STA SCL tSU DAT T tHD DAT tSU STO PARIETE EMEN Ld wm AI00589 Table 2 AC Characteristics sme emu ww 13 START Condition Hold Time 88 after this period the first clock pulse is generated Emme START Condition Setup Time only relevant for a repeated start condition Note 1 Valid for Ambient Operating Temperature TA 40 to 85 C Vcc 2 7 to 3 6V or 4 5 to 5 5V except where noted 2 Transmitter must internally provide a hold time to bridge the undefined region 300ns max of the falling edge of SCL 9 31 M41ST84Y M41ST84W READ Mode In this mode the master reads the M41ST84Y W slave after setting the slave address see Figure 11 page 10 Following the WRITE Mode Control Bit R W 0 and the Acknowledge Bit the word address An is written to the on chip address pointer Next the START condition and slave ad dress are repeated followed by the READ Mode Control Bit R W 1 At this point the master trans mitter becomes the master receiver The
17. 2 Wire Bus Characteristics The bus is intended for communication between different ICs It consists of two lines a bi direction al data signal SDA and a clock signal SCL Both the SDA and SCL lines must be connected to a positive supply voltage via a pull up resistor The following protocol has been defined Data transfer may be initiated only when the bus is not busy During data transfer the data line must remain stable whenever the clock line is High M41ST84Y M41ST84W Changesinthe data line while the clock line is High will be interpreted as control signals Accordingly the following bus conditions have been defined Bus not busy Both data and clock lines remain High Start data transfer A change in the state of the data line from High to Low while the clock is High defines the START condition Stop data transfer A change in the state of the data line from Low to High while the clock is High defines the STOP condition Data Valid The state of the data line represents valid data when after a start condition the data line is stable for the duration of the high period of the clock signal The data on the line may be changed during the Low period of the clock signal There is one clock pulse per bit of data Each data transfer is initiated with a start condition and terminated with a stop condition The number of data bytes transferred between the start and stop conditions is not limit
18. 7672 415 84 YZ M41ST84W 5 0 or 3 0V 512 bit 64 x8 Serial RTC with Supervisory Functions FEATURES SUMMARY m 5 0 OR 3 0V OPERATING VOLTAGE Figure 1 16 pin SOIC Package m SERIAL INTERFACE SUPPORTS I2C BUS 400kHz m OPTIMIZED FOR MINIMAL A INTERCONNECT TO MCU 16 m 2 5TO5 5V OSCILLATOR OPERATING id VOLTAGE m AUTOMATIC SWITCH OVER AND 5016 DESELECT CIRCUITRY m CHOICE OF POWER FAIL DESELECT VOLTAGES M41ST84Y Voc 4 5 to 5 5V 4 20V lt Vprp lt 4 50V Figure 2 28 pin SOIC M41ST84W 2 7 to 3 6V 2 55V lt Vprp lt 2 70V m 1 25V REFERENCE for PFI PFO m COUNTERS FOR TENTHS HUNDREDTHS OF SECONDS SECONDS MINUTES HOURS DAY DATE MONTH YEAR AND CENTURY m 44 BYTES OF GENERAL PURPOSE RAM m PROGRAMMABLE ALARM AND INTERRUPT FUNCTION VALID EVEN DURING BATTERY BACK UP MODE WATCHDOG TIMER MICROPROCESSOR POWER ON RESET BATTERY LOW FLAG POWER DOWN TIME STAMP HT Bit ULTRA LOW BATTERY SUPPLY CURRENT OF 500 nA max m OPTIONAL PACKAGING INCLUDES A 28 LEAD SOIC and TOP to be ordered separately m SNAPHAT PACKAGE PROVIDES DIRECT CONNECTION FOR A SNAPHAT TOP WHICH CONTAINS THE BATTERY AND CRYSTAL SNAPHAT SH Battery amp Crystal SOH28 MH Contact Local Sales Office October 2004 1 81 M41ST84Y M41ST84W TABLE 5 FEATURES SUMMARY enum nur cen Rua
19. 8 page 17 illustrates the back up mode alarm timing A103664 RPT5 RPT4 RPT3 RPT2 RPT1 Alarm Setting 1 5 16 31 Figure 18 Back Up Mode Alarm Waveform IRQ FT OUT 4 HIGH Z Watchdog Timer The watchdog timer can be used to detect an out of control microprocessor The user programs the watchdog timer by setting the desired amount of time out into the Watchdog Register address 09h Bits BMB4 BMBO store a binary multiplier and the two lower order bits RB1 RBO select the resolu tion where 00 1 16 second 01 1 4 second 10 1 second and 11 4 seconds The amount of time out is then determined to be the multiplica tion of the five bit multiplier value with the resolu tion For example writing 00001110 in the Watchdog Register 3 1 or 3 seconds Note Accuracy of timer is within the selected resolution If the processor does not reset the timer within the specified period the M41ST84Y W sets the WDF Watchdog Flag and generates a watchdog inter rupt or a microprocessor reset The most significant bit of the Watchdog Register is the Watchdog Steering Bit WDS When set to 0 the watchdog will activate the IRQ FT OUT pin when timed out When WDS is set to a 1 the watchdog will output a negative pulse on the RST pin for tagc The Watchdog register FT AFE ABE and SQWE Bits will reset to a 0 at the end of a Watchdog time out when the WDS B
20. 84W Table 12 DC Characteristics Test 415 84 M41ST84W Sym Parameter ien ON 5 Supply Current Supply Current f fe400kHz fe400kHz Supply Current SCL SDA CC2 Standby Voc 0 3V Input Leakage Current Leakage Input Leakage Current OV lt OV lt Iz Input Leakage Current 25 PFI Leak 4 EE UE ES veero v input Lov owe eme ow Output High Vttage low t 0mA eee Output Low Voltage Output Low Voltage Voltage 2 30 3 0mA VoL Open Drain Pull up Supply Voltage RST Open Drain Vero Power Fail Deselect Fail Deselect 440 2 60 PFI Input Threshold Yr 1 225 1 250 1 275 1 225 1 250 1 275 Vcc 3V V PFI Hysteresis PFI Hysteresis PFIRising Battery Back up Switchover Note 1 Valid for Ambient Operating Temperature TA 40 to 85 C Vcc 2 7 to 3 6V or 4 5 to 5 5V except where noted 2 RSTIN internally pulled up to Vcc through 100 resistor WDI internally pulled down to Vss through 100 resistor 3 Outputs deselected 4 5 For PFO and SQW pins CMOS For IRQ FT OUT RST pins Open Drain if pulled up to supply other than Vcc this supply must be equal to or less than 3 0V when Voc OV during battery back up
21. D data byte The M41ST84Y W has a built in power sense cir cuit which detects power failures and automatical ly switches to the battery supply when a power failure occurs The energy needed to sustain the SRAM and clock operations can be supplied by a small lithium button cell supply when a power fail ure occurs Functions available to the user include a non volatile time of day clock calendar Alarm interrupts Watchdog Timer and programmable Square Wave output Other features include a Power On Reset as well as an additional input RSTIN which can also generate an output Reset RST The eight clock address locations contain the century year month date day hour minute second and tenths hundredths of a second in 24 Figure 3 Logic Diagram VBat XI 1 xo RST SCL IRQ FT OUT M41ST84Y SDA M41ST84W SQW RSTIN PFO WDI PFI Vss 103677 Note 1 For 5016 package only 4 31 hour BCD format Corrections for 28 29 leap year valid until year 2100 30 and 31 day months are made automatically The MA1ST84 Y W is supplied in a 28 lead SOIC SNAPHAT package which integrates both crys tal and battery in a single SNAPHAT top or a 16 pin SOIC The 28 pin 330mil SOIC provides sock ets with gold plated contacts at both ends for direct connection to a separate SNAPHAT housing con taining the battery and crystal The unique design allows the SNAPHAT battery crystal package to be mounte
22. NAPHAT Housing for 48mAh Battery amp Crystal Package Outline 27 Table 17 SH 4 pin SNAPHAT Housing for 48mAh Battery amp Crystal Package Mechanical Data27 Figure 25 SH 4 pin SNAPHAT Housing for 120mAh Battery amp Crystal Package Outline 28 Table 18 SH 4 pin SNAPHAT Housing for 120mAh Battery amp Crystal Package Mech Data 28 PART NUMBERING r i EAEE 29 Table 19 Ordering Information 29 Table 20 SNAPHAT Battery 29 REVISION RISTORI aa E E be 30 Table 21 Document Revision 30 3 31 M41ST84Y M41ST84W SUMMARY DESCRIPTION The M41ST84Y W Serial supervisory TIMEKEEP ER SRAM is a low power 512 bit static CMOS SRAM organized as 64 words by 8 bits A built in 32 768kHz oscillator external crystal controlled and 8 bytes of the SRAM see Table 3 page 13 are used for the clock calendar function and are configured in binary coded decimal BCD format An additional 12 bytes of RAM provide status con trol of Alarm Watchdog and Square Wave func tions Addresses and data are transferred serially via a two line bi directional 12C interface The built in address register is incremented automati cally after each WRITE or REA
23. Y ENABLE Bit CEB and the CENTURY Bit CB Setting CEB to a 1 will cause CB to tog gle either from a 0 to 1 or from 1 to 0 at the turn of the century depending upon its initial state If CEB is set to a 0 CB will not toggle Output Driver Pin When the FT Bit AFE Bit and watchdog register are not set the IRQ FT OUT pin becomes an out put driver that reflects the contents of D7 of the Control Register In other words when D7 OUT Bit and D6 FT Bit of address location 08h are 9 then the IRQ FT OUT pin will be driven low Note The IRQ FT OUT pin is an open drain which requires an external pull up resistor Battery Low Warning The M41ST84Y W automatically performs battery voltage monitoring upon power up and at factory programmed time intervals of approximately 24 hours The Battery Low BL Bit Bit D4 of Flags Register OFh will be asserted if the battery voltage is found to be less than approximately 2 5V The 20 31 BL Bit will remain asserted until completion of bat tery replacement and subsequent battery low monitoring tests either during the next power up sequence or the next scheduled 24 hour interval If a battery low is generated during a power up se quence this indicates that the battery is below ap proximately 2 5 volts and may not be able to maintain data integrity in the SRAM Data should be considered suspect and verified as correct A fresh battery should be instal
24. at is read is the last one stored in the pointer see Figure 13 page 11 R W 1 Y Y e 0 100602 10 31 M41ST84Y M41ST84W Figure 13 Alternate READ Mode Sequence BUS ACTIVITY 15 MASTER SDA LINE DATAn DATA n 1 DATA n X BUS ACTIVITY ac 5 5 5 lt lt lt lt i i 9 SLAVE gt ADDRESS 100895 WRITE Mode Data Retention Mode In this mode the master transmitter transmits to With valid Vcc applied the M41ST84Y W can be the M41ST84Y W slave receiver Bus protocol is accessed as described above with READ or shown in Figure 14 page 11 Following the WRITE cycles Should the supply voltage decay START condition and slave address a logic 0 R the M41ST84Y W will automatically deselect W 0 is placed on the bus and indicates to the ad write protecting itself when Vcc falls between dressed device that word address An will follow Vprp max and Vprp min This is accomplished and is to be written to the on chip address pointer by internally inhibiting access to the clock regis The data word to be written to the memory is ters At this time the Reset pin RST is driven ac strobed in next and the internal address pointer is tive and will remain active until Vcc returns to incremented to the next memory location within nominal levels When Vcc falls below the Battery the RAM on the reception of an acknowledge Back up Switchover Voltage Vso
25. d on top of the SOIC package after the completion of the surface mount process Insertion of the SNAPHAT housing after reflow prevents potential battery and crystal damage due to the high temperatures required for device sur face mounting The SNAPHAT housing is also keyed to prevent reverse insertion The 28 pin SOIC and battery crystal packages are shipped separately in plastic anti static tubes or in Tape amp Reel form For the 28 lead SOIC the bat tery crystal package e g SNAPHAT part num ber is M4TXX BR12SH see 20 page 29 Caution Do not place the SNAPHAT battery crys tal top in conductive foam as this will drain the lith ium button cell battery Table 1 Signal Names SE aid Reset Output Open Drain Note 1 For SO16 package only M41ST84Y 415 84 Figure 4 16 SOIC Connections Figure 5 28 pin SOIC Connections 103678 103679 Figure 6 Block Diagram REAL TIME CLOCK CALENDAR 44 BYTES USER RAM RTC w ALARM amp CALIBRATION WATCHDOG SDA 2 SCL 32KHz Crystal LJ OSCILLATOR SQUARE WAVE SQW WDI wo POWER 2 65V for ST84W RSTIN PFI SER ys COMPARE PFO 25 Internal AI03931 Note 1 Open drain output ky 5 31 M41ST84Y M41ST84W Figure 7 Hardware Hookup Regulator M41ST84Y W Unregulated Voltage VN Vcc Voc RG FT OUT To INT To RST From MCU To LED Display
26. ed The information is transmitted byte wide and each receiver acknowl edges with a ninth bit By definition a device that gives out a message is called transmitter the receiving device that gets the message is called receiver The device that controls the message is called master The de vices that are controlled by the master are called slaves Acknowledge Each byte of eight bits is followed by one Acknowledge Bit This Acknowledge Bit is a low level put on the bus by the receiver whereas the master generates an extra acknowledge relat ed clock pulse A slave receiver which is ad dressed is obliged to generate an acknowledge after the reception of each byte that has been clocked out of the slave transmitter The device that acknowledges has to pull down the SDA line during the acknowledge clock pulse in such a way that the SDA line is a stable Low dur ing the High period of the acknowledge related clock pulse Of course setup and hold times must be taken into account A master receiver must sig nal an end of data to the slave transmitter by not generating an acknowledge on the last byte that has been clocked out of the slave In this case the transmitter must leave the data line High to enable the master to generate the STOP condition 7 91 M41ST84Y M41ST84W Figure 8 Serial Bus Data Transfer Sequence DATA LINE STABLE DATA VALID ge es uc ur START CHANGE OF STOP CONDITION DATA ALLOWED CONDITION 1
27. g Register TR FT AFE ABE and SQWE The following bits are set to a 1 state ST OUT and HT see Table 8 page 21 Table 7 trec Definitions trec Bit TR STOP Bit ST Note 1 Default Setting Table 8 Default Values M41ST84Y M41ST84W WATCHD Condition TR ST HT FT a Register Initial Power up Battery Attach for 5 0 Subsequent Power up with battery back up 9 Note 1 WDS 4 RBO RB1 2 State of other control bits undefined 3 UC Unchanged MAXIMUM RATING Stressing the device above the rating listed in the Absolute Maximum Ratings table may cause permanent damage to the device These are stress ratings only and operation of the device at these or any other conditions above those indicat ed in the Operating sections of this specification is Table 9 Absolute Maximum Ratings Storage Temperature Vcc Off Oscillator Off not implied Exposure to Absolute Maximum Rat ing conditions for extended periods may affect de vice reliability Refer also to the STMicroelectronics SURE Program and other rel evant quality documents 40 to 85 Ss SOIC 55 to 125 HEY Lead Solder Temperature for 10 seconds wma V Ce 1 Power Dissipation Supply Voltage Note 1 For SO package standard SnPb lead finish Reflow at peak temperature of 225 C total thermal budget not to
28. g the TIMEKEEPER registers and will allow the user to read the exact time of the power down event Resetting the HT Bit to a 0 will allow the clock to update the TIME KEEPER registers with the current time For more information see Application Note AN1572 TIMEKEEPER Registers The M41ST84Y W offers 12 additional internal registers which contain the Alarm Watchdog Flag Square Wave and Control data These reg isters are memory locations which contain external user accessible and internal copies of the data usually referred to as BIPORT TIMEKEEPER cells The external copies are independent of in ternal functions except that they are updated peri odically by the simultaneous transfer of the incremented internal copy The internal divider or clock chain will be reset upon the completion of a WRITE to any clock address The system to user transfer of clock data will be halted whenever the address being read is a clock address 00h to 07h The update will resume ei ther due to a Stop Condition or when the pointer increments to a non clock or RAM address TIMEKEEPER and Alarm Registers store data in BCD Control Watchdog and Square Wave Reg isters store data in Binary Format M41ST84Y M41ST84W Table 3 TIMEKEEPER Register Map Function Range em m 9 99 em 08 Hows a Hour Forman
29. he RS3 RSO Bits located in 13h estab lish the square wave output frequency These fre quencies are listed in Table 5 Once the selection Table 5 Square Wave Output Frequency Square Wave Bits 18 31 of the SQW frequency has been completed the SQW pin can be turned on and off under software control with the Square Wave Enable Bit SQWE located in Register OAh Power on Reset The M41ST84Y W continuously monitors Vcc When Vcc falls to the power fail detect trip point the RST pulls low open drain and remains low on power up for after Vcc passes Vprp max The RST pin is an open drain output and an appro priate pull up resistor should be chosen to control rise time Figure 19 RSTIN Timing Waveform Note With pull up resistor Table 6 Reset AC Characteristics M41ST84Y M41ST84W Reset Input RSTIN The M41ST84Y W provides an independent input which can generate an output reset The duration and function of this reset is identical to a reset gen erated by a power cycle Table 6 page 19 and Figure 19 page 19 illustrate the AC reset charac teristics of this function Pulses shorter than tni RH will not generate a reset condition RSTIN is inter nally pulled up to Vcc through a 100kQ resistor RSTIN tRLRH RST N tRHRSH 103682 tarry RSTIN Low to RSTIN High 200 RSTIN High to RST High Note 1 Valid for Ambient Operating Temperature TA 40 to
30. ion write protection not occurring until 20045 Vcc passes Vprp min 3 Vprp min to fall time of less than teg may cause corruption of RAM data 4 Programmable see Table 7 page 21 5 At 25 C when using SOH28 M4T28 BR12SH SNAPHAT top Vcc OV 24 31 M41ST84Y M41ST84W PACKAGE MECHANICAL INFORMATION Figure 22 5016 16 lead Plastic Small Outline Package Outline Note Drawing is not to scale Table 15 5016 16 lead Plastic Small Outline Package Mechanical Data inches 25 31 M41ST84Y M41ST84W Figure 23 SOH28 28 lead Plastic Small Outline Battery SNAPHAT Package Outline Note Drawing is not to scale Table 16 SOH28 28 lead Plastic Small Outline battery SNAPHAT Package Mechanical Data 26 31 M41ST84Y M41ST84W Figure 24 SH 4 pin SNAPHAT Housing for 48mAh Battery amp Crystal Package Outline Note Drawing is not to scale Table 17 SH 4 pin SNAPHAT Housing for 48mAh Battery amp Crystal Package Mechanical Data O Um m om ow LL e LL om sms sm EN Symbol 0 0220 27 31 M41ST84Y M41ST84W Figure 25 SH 4 SNAPHAT Housing for 120mAh Battery amp Crystal Package Outline SHTK A Note Drawing is not to scale Table 18 SH 4 pin SNAPHAT Housing for 120mAh Battery amp Crystal Package Mech Data
31. it is set to a 1 E M41ST84Y M41ST84W 4 ABE AFE Bits in Interrupt Register N AF bit in Flags Register 4 HIGH Z 103920 The watchdog timer can be reset by two methods 1 a transition high to low or low to high can be applied to the Watchdog Input WDI or 2 the microprocessor can perform a WRITE of the Watchdog Register The time out period then starts over Note The WDI pin should be tied to Vss if not used In order to perform a software reset of the watch dog timer the original time out period can be writ ten into the Watchdog Register effectively restarting the count down cycle Should the watchdog timer time out and the WDS Bitis programmed to output an interrupt a value of 00h needs to be written to the Watchdog Register in order to clear the IRQ FT OUT pin This will also disable the watchdog function until it is again pro grammed correctly A READ of the Flags Register will reset the Watchdog Flag Bit D7 Register OFh The watchdog function is automatically disabled upon power up and the Watchdog Register is cleared If the watchdog function is set to output to the IRQ FT OUT pin and the Frequency Test FT function is activated the watchdog function pre vails and the Frequency Test function is denied 17 31 M41ST84Y M41ST84W Square Wave Output The M41ST84Y W offers the user a programma ble square wave function which is output on the SQW pin T
32. led If a battery low indication is generated during the 24 hour interval check this indicates that the bat tery is near end of life However data is not com promised due to the fact that a nominal is supplied In order to insure data integrity during subsequent periods of battery back up mode the battery should be replaced The SNAPHAT top may be replaced while Vcc is applied to the de vice Note This will cause the clock to lose time during the interval the SNAPHAT battery crystal top is disconnected The M41ST84Y W only monitors the battery when a nominal Vcc is applied to the device Thus appli cations which require extensive durations in the battery back up mode should be powered up peri odically at least once every few months in order for this technique to be beneficial Additionally if a battery low is indicated data integrity should be verified upon power up via a checksum or other technique trec Bit Bit D7 of Clock Register 04h contains the trec Bit TR refers to the automatic continuation of the deselect time after Vcc reaches Vprp This al lows for a voltage setting time before WRITEs may again be performed to the device after a power down condition The trec Bit will allow the user to set the length of this deselect time as defined by Table 7 page 21 Initial Power on Defaults Upon initial application of power to the device the following register bits are set to a 0 state Watch do
33. mproves to better than 2 ppm at 25 C The oscillation rate of crystals changes with tem perature see Figure 15 page 15 Therefore the M41ST84Y W design employs periodic counter correction The calibration circuit adds or subtracts counts from the oscillator divider circuit at the di vide by 256 stage as shown in Figure 16 page 15 The number of times pulses which are blanked subtracted negative calibration or split added positive calibration depends upon the value loaded into the five Calibration bits found in the Control Register Adding counts speeds the clock up subtracting counts slows the clock down The Calibration bits occupy the five lower order bits D4 DO in the Control Register 08h These bits can be set to represent any value between 0 and 31 in binary form Bit D5 is a Sign Bit 1 indi cates positive calibration 0 indicates negative calibration Calibration occurs within a 64 minute cycle The first 62 minutes in the cycle may once per minute have one second either shortened by 128 or lengthened by 256 oscillator cycles If a bi nary 1 is loaded into the register only the first 2 minutes in the 64 minute cycle will be modified if a binary 6 is loaded the first 12 will be affected and so on Therefore each calibration step has the effect of adding 512 or subtracting 256 oscillator cycles for every 125 829 120 actual oscillator cycles that is 4 068 or 2 034 ppm of adjustment per calibra
34. ng Alarm Clock 16 Figure 17 Alarm Interrupt Reset 1 16 Table 4 Alarm Repeat 0 2 16 Figure 18 Back Up Mode Alarm 4 17 Watchdog Timer e tI 5 exi 17 2 31 1572 M41ST84Y M41ST84W Square Wave Output ee es eee WEE 18 Table 5 Square Wave Output 1 18 Power on Reset iR RR cid 19 Reset Input Ie ES ER RM REX RR RR 19 Figure 19 RSTIN Timing Waveform 19 Table 6 Reset AC 19 Power fail 20 Century Bit i e EE 20 Output Driver Pin 2 2 20s cece RR IE Rupe cm elo X4 RR IRI WIRE IER 20 Battery Low Warning iR E RE RR LERRA IEEE ERAT EIS 20 PIED MD 20 Initial Power on 20 4 Echec aus RE RE Ced 21 Table 8 Default Values csi
35. second mode to quickly alert the user of an incorrect alarm setting When the clock information matches the alarm clock settings based on the match criteria defined by RPT5 RPT1 the AF Alarm Flag is set If AFE Alarm Flag Enable is also set the alarm condi tion activates the IRQ FT OUT pin Note If the address pointer is allowed to incre ment to the Flag Register address an alarm con dition will not cause the Interrupt Flag to occur until the address pointer is moved to a different ad Figure 17 Alarm Interrupt Reset Waveform ACTIVE FLAG IRQ FT OUT Table 4 Alarm Repeat Modes dress It should also be noted that if the last ad dress written is the Alarm Seconds the address pointer will increment to the Flag address causing this situation to occur The IRQ FT OUT output is cleared by a READ to the Flags Register as shown in Figure 17 A sub sequent READ of the Flags Register is necessary to see that the value of the Alarm Flag has been reset to 0 The IRQ FT OUT pin can also be activated in the battery back up mode The IRQ FT OUT will go low if an alarm occurs and both ABE Alarm in Bat tery Back up Mode Enable and AFE are set The ABE and AFE Bits are reset during power up therefore an alarm generated during power up will only set AF The user can read the Flag Register at system boot up to determine if an alarm was generated while the M41ST84Y W was in the de select mode during power up Figure 1
36. ul 02 Modify DC and Crystal Electrical Characteristics footnotes Default Values Tables 12 13 8 01 Aug 02 Add marketing status Figure 2 Table 19 16 Jun 03 New Si changes Table 14 6 7 8 15 Jun 04 Reformatted added Lead free information update characteristics Figure 15 Table 9 12 19 18 Oct 04 60 Add Marketing Status Figure 2 Table 19 06 Sep 01 3 30 31 M41ST84Y M41ST84W Information furnished is believed to be accurate reliable However STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics Specifications mentioned in this publication are subject to change without notice This publication supersedes and replaces all information previously supplied STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics The ST logo is a registered trademark of STMicroelectronics All other names are the property of their respective owners 2004 STMicroelectronics All rights reserved STMicroelectronics group of companies Australia Belgium Brazil Canada China Czech Republic Finland France Germany Hong Kong India Israel Italy Japan Malaysia
37. ure For example a reading of 512 010124Hz would indicate a 20 ppm oscillator frequency error requiring 10 XX001010 to be loaded into the Calibration Byte for correction Note that setting or changing the Calibration Byte does not affect the Frequency test output frequen cy The IRQ FT OUT pin is an open drain output which requires a pull up resistor to Vcc for proper operation A 500 to 10k resistor is recommended in order to control the rise time The FT Bit is cleared on power down M41ST84Y M41ST84W Figure 15 Crystal Accuracy Across Temperature Frequency ppm n K x T To 0 036 2 0 006 ppm C 25 C 5 C 40 30 20 10 0 10 20 30 40 50 60 70 80 Temperature A100999b NORMAL POSITIVE CALIBRATION NEGATIVE CALIBRATION 100594 15 31 M41ST84Y M41ST84W Setting Alarm Clock Registers Address locations OAh OEh contain the alarm set tings The alarm can be configured to go off at a prescribed time on a specific month date hour minute or second or repeat every year month day hour minute or second It can also be pro grammed to go off while the M41ST84Y W is in the battery back up to serve as a system wake up call Bits RPT5 RPT1 put the alarm in the repeat mode of operation Table 4 page 16 shows the possible configurations Codes not listed in the table default to the once per
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