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ATMEL TS68882 handbook

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1. Parameter Min Max Min Max Min Max Min Max Unit Frequency of Operation 8 16 67 12 5 20 12 5 25 16 7 33 33 MHz 1 Clck Time 60 125 50 80 40 80 30 60 ns 2 3 Clock Pulse Width 24 95 20 54 15 59 14 66 ns 4 5 Rise and Fall Times 5 5 4 3 ns Note Timing measurements are referenced to and from a low voltage of 0 8V and a high volt age of 2 0V unless otherwise noted The voltage swing through this range should start outside and pass through the range such that the rise of fall will be linear between 0 8V and 2 0V 10 15868882 memme 2119A HIREL 04 02 a S69992 Table 7 AC Electrical Characteristics Read and Write Cycles Voc 5 0 Voc 10 GND 0 Vog Te 55 C 125 C or Tc 40 C 85 C see Figure 7 Figure 8 Figure 9 16 67 MHz 20 MHz 25 MHz 33 33 MHz N Parameter Min Max Min Max Min Max Min Max Unit 6 Address valid to AS asserted 15 10 5 5 ns Ga Address valid to DS asserted read 15 10 5 5 ns 6b Address valid to DS asserted write 50 50 35 26 ns 7 AS negated to address invalid 10 10 5 5 ns 7a DS negated to address invalid 10 10 5 5 ns CS asserted to AS asserted or AS asserted 8 to CS asserted 0 9 e de CS asserted to DS asserted or DS asserted 0 0 0 na to CS asserted read CS asserted to DS asserted or DS asserted 8b to CS asserted write 9 30 20 20 15 ns 9
2. BYTE INTEGER WORD INTEGER LONG INTEGER SINGLE REAL DOUBLE REAL EXTENDED REAL PACKED DECIMAL REAL The TS68882 instruction set is organized into six major classes Moves Between The TS68882 and Memory or The MPU In and Out Move Multiple Registers In and Out Monadic Operations Dyadic Operations Branch Set or Trap Conditionally and Miscellaneous POARGONm All moves from memory or from an MPU data register to the TS68882 cause data con version from the source data format to the internal extended precision format All moves from the TS68882 to memory or to an MPU data register cause data con version from the internal extended precision format to the destination data format 26 15868882 mmm 2119A HIREL 04 02 a SG8882 Move Multiples Monadic Operations 2119A HIREL 04 02 Note that data movement instructions perform arithmetic operations since the result is always rounded to the precision selected in the FPCR mode control byte The result is rounded using the selected rounding mode and is checked for overflow and underflow The syntax for the move is FMOVE fmt ea FPn Move to TS68882 FMOVE fmt FPm ea Move from TS68882 FMOVE X FPm FPn Move within TS68882 where ea is a TS68000 Family effective address operand and fmt is the data format size FPm and FPn are floating point data registers The floating point move multiple instructions on the TS68882 are much like th
3. Electrical Characteristics General Requirements Table 5 Static Characteristics The microcircuits shall meet all mechanical environmental requirements of either MIL STD 883 for class B devices The document defines the markings that are identified in the related reference docu ments Each microcircuit is legible and permanently marked with the following information as minimum e Atmel Grenoble Logo e Manufacturer s Part Number e Class B Identification e Date code of inspection lot e ESD Identifier if Available e Country of Manufacturing Is in accordance with MIL M 38510 and method 5005 of MIL STD 883 Group A and B inspections are performed on each production lot Group C and D inspection are per formed on a periodical basis All static and dynamic electrical characteristics specified and the relevant measurement conditions are given below For inspection purpose refer to relevant specification Static electrical characteristics for all electrical variants Dynamic electrical characteristics for 68882 16 16 67 MHz 68882 20 20 MHz 68882 25 25 MHz and 68882 33 33 MHz For static characteristics test methods refer to clause Test Load on page 13 hereafter of this specification Table 5 For dynamic characteristics Tables 6 and 7 test methods refer to IEC 748 2 method number where existing Vog 5 0 Vog 10 GND 0 Voo Te 55 125 C or 40 85 C Symbol Par
4. a SG8882 Package Mechanical Data Figure 23 68 lead CPGA TOP VIEW Index comer U E AS L_ 1 060 010 26 92 0 25 26 92 10 25 1 060 010 Notes 2 Positional tolerance for leads 168 places 0160 13 0 005 T A 5 IB 5 o 4 Controlling dimension INCH 2119A HIREL 04 02 BOTTOM VIEW 180 010 4 57 10 25 050 010 1 27 10 254 2 018 001 90 46 0 03 050 005 91 27 0 13 2 46 0 20 Dimensions A and B are datums and T S datum surface Dimensioning and tolerancing per ANSI Y14 5M 1982 AMEL Ae IO nn mo on gt 39 AMEL Figure 24 68 lead CQFP 1 133 1 147 28 78 29 13 950 006 24 13 0 152 Pin N 1 index o 85 yo gia QFP 68 a b Ss Sig A gal Le los ET 2119A HIREL 04 02 a SG8882 Ordering Information HI REL Product Commercial Atmel Temperature Range Frequency Part Number Norms Package Te C MHz Drawing Number TS68882MRB C16 MIL STD 883 PGA 68 55 125 16 67 TS68882MRB C20 MIL STD 883 PGA 68 55 125 20 TS68882MRB C25 MIL STD 883 PGA 68 55 125 25 TS68882MRB C33 MIL STD 883 PGA 68 55 125 33 TS68882MFB C16 MIL STD 883 CQFP 68 55 125 16 67 TS68882MFB C20 MIL STD 883 CQFP 68
5. must be connected to the sixteen most significant data pins D16 D31 when the TS68882 is configured to operate over a 16 bit data bus i e connect DO to D16 D1 to D17 and D15 to D31 The DSACK pins of the two devices are directly connected although it is not necessary to connect the DSACKO pin since the TS68882 never asserts it in this configuration Figure 20 illustrates the connection of a TS68882 to a TS68020 TS68030 as a co pro cessor over an 8 bit data bus The TS68882 is configured to operate over an 8 bit data bus when the SIZE pin is connected to GND The twenty four least significant data pins DO D23 must be connected to eight most significant data pins D24 D31 when the TS68882 is configured to operate over an 8 bit data bus i e connect DO to D8 D16 to D24 D1 to D9 D17 and D15 and D7 to D15 D23 and D31 The DSACK pins of the two devices are directly connected although it is not necessary to connect the DSACK1 pin since the TS68882 never asserts it in this configuration e TS68882 TS68000 TS68008 TS68010 Interfacing The following paragraphs describe how to connect the TS68882 to a TS68000 TS68008 or TS68010 processor for operation as a peripheral via an 8 or 16 bit data bus Figure 21 illustrates the connection of a TS68882 to a TS68000 or TS68010 as a periph eral processor over an 16 bit data bus The TS68882 is configured to operate over an 16 bit data bus when the SIZE pin is connected to Voc and t
6. AS negated to CS negated 10 10 5 5 ns 9a DS negated to CS negated 10 10 5 5 ns 10 RAW high to AS asserted read 15 10 5 5 ns 10a R W high to DS asserted read 15 10 5 5 ns 10b RAW low to DS asserted write 35 30 25 25 ns AS negated to R W low read or 11 AS negated to R W high write 10 19 9 3 us DS negated to R W low read or Ma DS negated to R W high write 10 19 2 3 ns 12 DS width asserted write 40 38 30 23 ns 13 DS width negated 40 38 30 23 ns 13a DS negated to AS asserted 30 30 25 18 ns 14 CS DS asserted to data out valid read 80 45 45 30 ns 15 DS negated to data out invalid read 0 0 0 0 ns 16 DS negated to data out high impedance 50 35 35 30 s read 17 Data in invalid to DS asserted write 15 10 5 5 ns 18 DS negated to data in invalid write 15 10 5 5 ns 19 START fus to DSACKO and DSACK1 50 35 25 20 de asserted 19a peasy asserted to DSACK1 asserted 45 15 40 10 40 10 5 Re skew 20 DSACKO or DSACK1 asserted to data out 50 43 32 17 s valid 21 START Pog to DSACKO and DSACK1 50 30 40 30 ag negated AMEL n 2119A HIREL 04 02 AMEL Table 7 AC Electrical Characteristics Read and Write Cycles Continued Voc 5 0 Vog 10 GND 0 Vog Te 55 C 125 C or Tc 40 C 85 C see Figure 7 Figure 8 Figure 9 16 67 MHz 20 MHz 25 MHz 33 33 MHz N Param
7. brief description of the input and output signals for the TS68882 floating point co processor The signals are functionally organized into groups as shown in Figure 3 Figure 3 TS68882 Input output Signals Note AQ A4 AS TS 68882 FLOATING POINT RIW COPROCESSOR DS Cs DSACKO DSACK1 The terms assertion and negation are used extensively This is done to avoid confusion when describing active low and active high signals The term assert or assertion is used to indicate that a signal is active or true independent of whether that level is repre sented by a high or low voltage The term negate or negation is used to indicate that a signal is inactive or false AMEL s Signal Summary Table 1 Signal Summary AMEL Table 1 provides a summary of all the TS68882 signals described in this section Signal Name Mnemonic Input Output Active State Three State Address Bus AO A4 Input High Data Bus DO D31 Input Output High Yes Size SIZE Input Low Address Strobe AS Input Low Chip Select cs Input Low Read Write RAW Input High Low Data Strobe DS Input Low Data Transfer and Size Acknowledge DSACKO DSACK1 Output Low Yes Reset RESET Input Low Clock CLK Input Sense Device SENSE Input Output Low No Power Input Vee Input Ground GND Input Detailed Specifications Scope This drawing describes the specific requirements for the microprocessor 68882 16 67 20
8. closely as possible non concurrent operation between the TS68020 TS68030 and the TS68882 The TS68882 is s non DMA type co processor which uses a subset of the general pur pose co processor interface supported by the TS68020 TS68030 Features of the interface implemented in the TS68882 are as follows e The main processor s and TS68882 communicate via standard TS68000 bus cycles e The main processor s and TS68882 communications are not dependent upon the instruction sets or internal details of the individual devices i e instruction pipes or caches addressing modes e The main processor s and TS68882 may operate at different clock speeds e TS68882 instructions utilize all addressing modes provided by the main processor all effective addresses are calculated by the main processor at the request of the co processor e All data transfers are performed by the main processor at the request of the TS68882 thus memory management bus errors address errors and bus arbitration function as if the TS68882 instructions are executed by the main processor e Overlapped concurrent instruction execution enhances throughput while maintaining the programmer s model of sequential instruction execution e Co processor detection of exceptions which require a trap to be taken are serviced by the main processor at the request of the TS68882 thus exception processing functions as if the TS68882 instructions were executed by the main processor e Su
9. due to the special values in IEEE floating point arithmetic When a conditional instruction is executed the TS68882 performs the necessary condition checking and tells the MPU whether the condition is true or false the MPU then takes the appropriate action Since the TS68882 and TS68020 TS68030 are closely coupled the floating point branch operations executed by the pair are very fast The TS68882 conditional operations are FBcc Branch FDBcc Decrement and Branch FScc Set Byte According to Condition ETRAPcc Trap on Condition with an Optional Parameter where cc is one of the 32 floating point conditional test specifiers as shown in Table 9 Table 9 Floating point Conditional Test Specifiers Mnemonic Definition Note The following conditional tests do not set the BSUN bit in the status register exception byte under any circumstances F False EQ Equal OGT Ordered Greater Than OGE Ordered Greater Than or Equal OLT Ordered Less Than OLE Ordered Less Than or Equal OGL Ordered Greater or Less Than OR Ordered UN Unordered UEQ Unordered or Equal UGT Unordered or Greater Than UGE Unordered or Greater or Equal ULT Unordered or Less Than ULE Unordered or Less or Equal NE Not Equal 2119A HIREL 04 02 AMEL 29 AMEL Table 9 Floating point Conditional Test Specifiers Continued Mnemonic T Definition True Note The following condi
10. operated CIR Once the MPU fulfills the co processor request s it is free to fetch and execute subsequent instructions AMEL n Co processor Interface AMEL A key concern in a co processor interface that allows concurrent instruction execution is synchronization during main processor and co processor communication If a subse quent instruction is written to the TS68882 before the CCU has passed the operands for the previous instructions to the ECU the response instructs the TS68020 TS68030 to wait Thus the choice of concurrent or nonconcurrent instruction execution is deter mined on an instruction by instruction basis by the co processor The only difference between a co processor bus transfer and any other bus transfer is that the TS68020 TS68030 issues a function code to indicate the CPU address space during the cycle the function codes are generated by the TS68000 Family processors to identify eight separate address spaces Thus the memory mapped co processor inter face registers do not infringe upon instruction or data address spaces The TS68020 TS68030 places a co processor ID field from the co processor instruction onto three of the upper address lines during co processor accesses This ID along with the CPU address space function code is decoded to select one of eight co processors in the system Since the co processor interface protocol is based solely on bus transfers the protocol is easily emulated by software when
11. or TS 68030 D24 D31 D16 D23 D8 D15 DO D7 DSACKO e DSACK1 MAIN PROCESSOR CLOCK Figure 20 8 bit Data Bus Co processor Connection FCO FC2 A20 A31 A16 A19 A13 A15 AS A12 O ise Q 8 YN H 6 e N Q 8 wn D24 D31 D16 D23 D8 D15 DO D7 DSACKO DSACKT o gt oo TS 68882 RW D24 D31 D16 D23 D8 D15 DO D7 DSACKO DSACK1 COPROCESSOR CLOCK D24 D31 D16 D23 DSACKO DSACKT MAIN PROCESSOR COPROCESSOR CLOCK CLOCK 2119A HIREL 04 02 2119A HIREL 04 02 Figure 21 16 bit Data Bus Peripheral Processor Connection FCO FC2 A20 A23 OR A31 A16 A19 A13 A15 AS A12 A1 A4 o 2 En AS e UDS LDS RM RW YN H D24 D31 D16 D23 D8 D15 D8 D15 D0 D7 DO D7 DSACKO DSACK1 MAIN PROCESSOR COPROCESSOR CLOCK CLOCK Figure 22 8 bit Data Bus Peripheral Processor Connection FCO FC2 CHIP SELECT A16 A19 DECODE SYSTEM IR DEPENDENT A5 A12 gt GND gt A1 A4 AO 8 AS 8 n DS 2 DSACKO DSACK1 MAIN PROCESSOR COPROCESSOR CLOCK CLOCK AMEL TS68882 37 8 bit Data Bus Peripheral Processor Connection Preparation For Delivery Certificate of Compliance Handling AMEL Figure 22 illustrates the connection of a TS68882 to a TS68008 as a peripheral proces sor over an 8 bit data bus The TS68882 is configured to operate over an 8 bit data bus
12. standard warranty which is detailed in Atmel s Terms and Conditions located on the Company s web site The Company assumes no responsibility for any errors which may appear in this document reserves the right to change devices or specifications detailed herein at any time without notice and does not make any commitment to update the information contained herein No licenses to patents or other intellectual property of Atmel are granted by the Company in connection with the sale of Atmel products expressly or by implication Atmel s products are not authorized for use as critical components in life support devices or systems ATMEL is the registered trademarks of Atmel Other terms and product names may be the trademarks of others er Printed on recvcled paper 2119A HIREL 04 02 OM Copyright O Each Manufacturing Company All Datasheets cannot be modified without permission This datasheet has been download from www AllDataSheet com 100 Free DataSheet Search Site Free Download No Register Fast Search System www AllDataSheet com
13. the waveforms shown in Figure 6 In order to test the parameters guaranteed inputs must be driven to the voltage levels specified in Figure 6 Outputs are specified with minimum and or maximum limits as appropriate and are measured as shown Inputs are specified with minimum and an appropriate maximum setup and hold times and are measured as shown Finally the measurement for signal to signal specifications are also shown Note that the testing levels used to verify conformance to the AC specifications does not affect the guaranteed DC operation of the device specified in the DC electrical characteristics AMEL 5 2119A HIREL 04 02 AMEL Figure 6 Drive Levels and Test Points for AC Specifications DRIVE TO 2 4 V CLK 20 V 20 V 0 8 V 0 8 V DRIVE d am TO0 5V B VALID 20V 20V VALID OUTPUTS CLK OUTPUTn 08V KUN 08 V OUTPUT n 1 lt A B a VALD 20V 20V VALID OUTPUTS 2 CLK OUTPUT n 08 V KR Saar Oe ae DRIVE ee TO24V 4 20V VALD 20V j Y ie di DRIVE X08 INPUT 08 vl TO0 5V DRIVE 20 V VALD 20V TO 2 4 V idad 08 V INPUT 08V DA E TO0 5V ALL SIGNALS 5 Legend A Maximum output delav specification B Minimum output hold time C Minimum input setup time specification D Minimum input hold time specification E Signal valid to signal valid specification maximum or minimum F Signal valid to signal invalid specification maximum or minimum Notes 1 This output timing is applicable
14. to the reference terminal see Symbol Parameter Min Max Unit Voc Supply Voltage 4 5 5 5 V Tease Operating Temperature 55 125 C Vin Input High Voltage 2 0 Vee Vi Input Low Voltage GND 0 3 0 8 In Input Leakage Current at 5 5V CLK RESET RAW AO A4 CS DS AS SIZE 10 HA Its HI Z Off state Input Current at 2 4V 0 4V DSACKO DSACK1 DO D31 20 HA Vou Output High Voltage IOH 400 uA DSACKO DSACK1 DO D31 2 4 Vor Output Low Voltage IOL 5 3 mA DSACKO DSACK1 DO D31 0 5 Vv lor Output Low Current VOL GND SENSE 500 HA Pp Power Dissipation 0 75 W Cin Capacitance Vn 0 Ta 25 C f 1 MHz 9 20 pF CL Output Load Capacitance 130 pF Notes 1 Test load see Figure 5 2 Capacitance is periodically sampled rather than 100 tested 2119A HIREL 04 02 AMEL AMEL Thermal Characteristics Table 4 Package Symbol Parameter Value Rating SES OJA Thermal Resistance Ceramic Junction To Ambient 33 C W Oc Thermal Resistance Ceramic Junction To Case 4 C W Gare On Thermal Resistance Ceramic Junction To Ambient 33 C W Oc Thermal Resistance Ceramic Junction To Case 3 C W Power The average chip junction temperature T in C can be obtained from Considerations T Ta Pp Oja 1 Ta Ambient Temperature C On Package Thermal Resistance Junction to Ambient C W Pp Pint Pro Pint lcc X Vee Watts
15. 55 125 20 TS68882MFB C25 MIL STD 883 CQFP 68 55 125 25 TS68882DESC01XA DESC PGA 68 55 125 16 67 5962 8946301XA TS68882DESC02XA DESC PGA 68 55 125 20 5962 8946301XA TS68882DESCO3XA DESC PGA 68 55 125 25 5962 8946301XA TS68882DESCO4XA DESC PGA 68 55 125 33 5962 8946301XA TS68882DESCO1YA DESC CQFP 68 55 125 16 67 5962 8946301XA TS68882DESCO2YA DESC CQFP 68 55 125 20 5962 8946301XA TS68882DESCO3YA DESC CQFP 68 55 125 25 5962 8946301XA TS68882DESCO4YA DESC CQFP 68 55 125 33 5962 8946304YA Standard Product Commercial Atmel Temperature Range Frequency Part Number Norms Package Te c MHZ Drawing Number TS68882VR16 ATMEL Grenoble Standard PGA 68 40 85 16 67 Internal TS68882V R20 ATMEL Grenoble Standard PGA 68 40 85 20 Internal TS68882VR25 ATMEL Grenoble Standard PGA 68 40 85 25 Internal TS68882VR33 ATMEL Grenoble Standard PGA 68 40 85 33 Internal TS68882MR16 ATMEL Grenoble Standard PGA 68 55 125 16 67 Internal TS68882MR20 ATMEL Grenoble Standard PGA 68 55 125 20 Internal TS68882MR25 ATMEL Grenoble Standard PGA 68 55 125 25 Internal TS68882MR33 ATMEL Grenoble Standard PGA 68 55 125 33 Internal TS68882VF 16 ATMEL Grenoble Standard CQFP 68 40 85 16 67 Internal TS68882VF20 ATMEL Grenoble Standard CQFP 68 40 85 20 Internal TS68882VF25 ATMEL Grenoble Standard CQFP 68 40 85 25 Internal TS68882VF33 ATMEL Grenoble Standard CQFP 68 40 85 33 Internal TS68882MF16 ATMEL Grenoble S
16. 80 bit floating point data registers FPO FP7 are located in the ECU In addi tion to these registers the ECU contains a high speed 67 bit arithmetic unit used for both mantissa and exponent calculations a barrel shifter that can shift from 1 bit to 67 bits in one machine cycle and ROM constants for use by the internal algorithms or user programs The MCU contains the clock generator a two level microcoded sequencer that controls the ECU the microcode ROM and self test circuitry The built in self test capabilities of the TS68882 enhance reliability and ease manufacturing requirements however these diagnostic functions are not available to the user 2 TSOSS NN 2119A HIREL 04 02 a SG8882 Figure 1 TS68882 Simplified Block pS O AA A AO pat ARA f 91907 ANNOY HVId4 8 HSd4 HOdA HI GNVH3dO LL ANNO FR yp E eea ma nan l 91907 NOISHJANOO a LWWHO4 X a S man 1 m A X O e 3 U Z 5 p o 5 HJONANDIS i i 9 3 9 3 DOTVIA SNOILYOINNWWOO l n D O l gt Qn gt gt I m gt 5 2 r gt 23 i q D 3 gt Sdt M ik P i a D 1 2 La HID 103738 431SI934 5 m 2 3i m si Bi i D a 9 HID SS34GGV NOLLONHLSNI 1 m m 1 i a 5 1 1 1 A A ee eee YIO NOLLIONOD ONVNWNOO SOV SNIVIS Vld 3SNOdS38 A HALSID3H 300930 NOLLONHLSNI CONTROL CS AS DS R W SIZE DSACK 1 0 RESET 910 JSNOdS3U SVI
17. 81 Atmel Operations Memory Atmel Corporate 2325 Orchard Parkway San Jose CA 95131 TEL 1 408 441 0311 FAX 1 408 436 4314 Microcontrollers Atmel Corporate 2325 Orchard Parkway San Jose CA 95131 TEL 1 408 441 0311 FAX 1 408 436 4314 Atmel Nantes La Chantrerie BP 70602 44306 Nantes Cedex 3 France TEL 33 2 40 18 18 18 FAX 33 2 40 18 19 60 ASIC ASSP Smart Cards Atmel Rousset Zone Industrielle 13106 Rousset Cedex France TEL 33 4 42 53 60 00 FAX 33 4 42 53 60 01 Atmel Colorado Springs 1150 East Cheyenne Mtn Blvd Colorado Springs CO 80906 TEL 1 719 576 3300 FAX 1 719 540 1759 Atmel Smart Card ICs Scottish Enterprise Technology Park Maxwell Building East Kilbride G75 OQR Scotland TEL 44 1355 803 000 FAX 44 1355 242 743 RF Automotive Atmel Heilbronn Theresienstrasse 2 Postfach 3535 74025 Heilbronn Germany TEL 49 71 31 67 0 FAX 49 71 31 67 2340 Atmel Colorado Springs 1150 East Cheyenne Mtn Blvd Colorado Springs CO 80906 TEL 1 719 576 3300 FAX 1 719 540 1759 Biometrics Imaging Hi Rel MPU High Speed Converters RF Datacom Atmel Grenoble Avenue de Rochepleine BP 123 38521 Saint Egreve Cedex France TEL 33 4 76 58 30 00 FAX 33 4 76 58 34 80 e mail literature atmel com Web Site http www atmel com O Atmel Corporation 2002 Atmel Corporation makes no warranty for the use of its products other than those expressly contained in the Company s
18. 82 is operated as a co processor or a peripheral processor all inter processor transfers of instruction information operand data status information and requests for service occur as standard TS68000 bus cycles The TS68882 will operate over an 8 16 or 32 bit system data bus Depending upon the system data bus configuration both the AO and SIZE pins are configured specifically for the applicable bus configuration Refer to ADDRESS BUS AO through A4 and SIZE SIZE for further details This active low input signal is used in conjunction with the AO pin to configure the TS68882 for operation over an 8 16 or 32 bit system data bus When the TS68882 is configured to operate over a 16 or 32 bit system data bus both the SIZE and AO pins are strapped high and or low as listed in Table 11 This active low input signal indicates that there is a valid address on the address bus and both the chip select CS and read write R W signal lines are valid This active low input signal enables the main processor access to the TS68882 co pro cessor interface registers When operating the TS68882 as a peripheral processor the chip select decode is system dependent i e like the chip select on any peripheral The CS signal must be valid either asserted or negated when AS is asserted Refer to CHIP SELECT TIMING for further discussion of timing restrictions for this signal This input signal indicates the direction of a bus transaction
19. ACOS FETOXM1 FGETEXP FGETMAN FINT FINTRZ FLOG10 FLOG2 FLOGN FLOGNP FNEG FSIN FSINCOS FSINH FSQRT FTAN FTANH FTENTOX FTST FTWOTOX Dyadic Operations AMEL Absolute Value Arc Cosine e to the x Power 1 Get Exponent Get Mantissa Integer Part Integer Part Truncated Log Base 10 Log Base 2 Log Base e Log Base e of x 1 Negate Sine Simultaneous Sine and Cosine Hyperbolic Sine Square Root Tangent Hyperbolic Tangent 10 to the x Power test 2 to the x Power Dyadic operations have two input operands The first input operand comes from a float ing point data register memory or MPU data register The second input operand comes from a floating point data register The destination is the same floating point data regis ter used for the second input For example the syntax for add is FADD fmt FADD X ea FPnor FPm FPn The TS68882 dyadic operations available are as follows FADD Add FCMP Compare FDIV Divide FMOD Modulo Remainder FMUL Multiply FREM IEEE Remainder FSCALE Scale Exponent 28 TS68882 memme 2119A HIREL 04 02 a SG8882 Branch Set and Trap on Condition FADD Add FSGLDIV Single Precision Divide FSGLMUL Single Precision Multiply FSUB Subtract The floating point branch set and trap on condition instructions implemented by the TS68882 are similar to the equivalent integer instructions of the TS68000 Family pro cessors except that more conditions exist
20. Chip Internal Power Po Power Dissipation on Input and Output Pins User Determined For most applications Pig lt Pinr and can be neglected An Approximate relationship between Pp and T if Pyo is neglected is Pp K Ty 273 2 Solving equations 1 and 2 for K gives K Pp Ta 273 Oja Pp 3 where K is constant pertaining to the particular part K can be determined from the equa tion 3 by measuring PD at equilibrium for a known T Using this value of K the values of Pp and T can be obtained by solving equations 1 and 2 iteratively for any value of Ta The total thermal resistance of a package 0 ja can be separated into two components B c and Oca representing the barrier to heat flow from the semiconductor junction to the package case surface 6 jc and from the case to the outside ambient Oca These terms are related by the equation Oja Oc Oca 4 ja is device related and cannot be influenced by the user However Oc is user depen dent and can be minimized by such thermal management techniques as heat sinks ambient air cooling and thermal convection Thus good thermal management on the part of the user can significantly reduce Os so that 8 approximately equals 8 c Substi tution of Bjo for Oja in equation 1 will result in a lower semiconductor junction temperature 2119A HIREL 04 02 a SG8882 Mechanical and Environmental Marking Quality Conformance Inspection DESC MIL STD 883
21. Es Features e Eight General purpose Floating point Data Registers Each Supporting a Full 80 bit Extended Precision Real Data Format a 64 bit Mantissa Plus a Sign Bit and a 15 bit Signed Exponent e A 67 bit Arithmetic Unit to Allow Very Fast Calculations with Intermediate are Precision Greater than the Extended Precision Format A 67 bit Barrel Shifter for High speed Shifting Operations for Normalizing etc Special purpose Hardware for High speed Conversion Between Single Double and Extended Formats and the Internal Extended Format e An Independent State Machine to Control Main Processor Communication for Pipelined Instruction Processing Forty six Instructions Including 35 Arithmetic Operations CMOS e Full Conformation to the IEEE 754 Standard Including All Requirements and En hanced Suggestions e Support of Functions Not Defined by the IEEE Standard Including a Full Set of H H Trigonometric and Transcendental Functions Floati ng pol nt Seven Data Type Types Byte Word and Long Integers Single Double and Extended Precision Real Numbers and Packed Binary Coded Decimal String Real Numbers Co processor Twenty two Constants Available In The On chip ROM Including 7 e and Powers of 10 Virtual Memory Machine Operations Efficient Mechanisms for Procedure Calls Context Switches and Interrupt Handling TS68882 Fully Concurrent Instruction Execution with the Main Processor Fully Concurrent Instruction Execution o
22. MHz and 25 MHz in compliance with MIL STD 883 class B Applicable Documents MIL STD 883 1 MIL STD 883 Test Methods And Procedures For Electronics 2 MIL PRF 38535 Appendix A General Specifications For Microcircuits 3 Desc Drawing 5962 89436xxx Requirements General The microcircuits are in accordance with the applicable document and as specified herein Design and Construction Terminal Connections Depending on the package the terminal connections shall be as shown in Figure 2 and Figure 2b Lead Material and Finish Lead material and finish shall be any option of MIL STD 1835 6 TSOSS NN a SG8882 Package The macrocircuits are packaged in hermetically sealed ceramic packages which are conform to case outlines of MIL STD 1835 when defined e 68 PIN SQ PGA UP PAE Outline e 68 PIN Ceramic Quad Flat Pack CQFP The precise case outlines are described on Figure 23 and Figure 24 Electrical Characteristics Table 2 Absolute Maximum Ratings Symbol Parameter Test Conditions Min Max Unit Vee Supply Voltage 0 3 7 0 V Vi Input Voltage 0 3 7 0 V Pomax Max Power Dissipation vas 1 Bi a 0 73 w M Suffix 55 125 C Tcase Operating Temperature VET AD a Tera Storage Temperature 55 150 C Ti Fans Lead Temperature Max 5 sec Soldering 270 C Recommended Condition of Use Table 1 Table 3 DC Electrical Characteristics Unless otherwise stated all voltages are referenced
23. Note Though the TS68882 is instruction set compatible with the TS68881 the idle and busy state frames are both 32 bytes larger on the TS68882 than on the TS68881 A unique format word is generated by the TS68882 so that system software can detect this difference The TS68882 supports the following data formats e Byte Integer B e Word Integer W e Long Word Integer L e Single Precision Real S Double Precision Real D Extended Precision Real X e Packed Decimal String Real P The capital letters contained in parenthesis denote suffixes added to instructions in the assembly language source to specify the data format to be used AMEL 2 Integer Data Formats Floating point Data Formats AMEL The three Integer data formats byte word and long word are the standard data for mats supported in the TS68000 Family architecture Whenever an integer is used in a floating point operation the integer is automatically converted by the TS68882 to an extended precision floating point number before being used For example to add an integer constant of five to the number contained in floating point data register 3 FP3 the following instruction can be used FADD W 5 FP3 The ability to effectively use integers in floating point operations saves user memory since an integer representation of a number if representable is usually smaller than the equivalent floating point representation The floating point data for
24. OTIENT SIGN OF QUOTIENT 2119A HIREL 04 02 a SG8882 Figure 15 Accrued Exception Byte 7 6 5 4 3 2 1 0 IOP OVFL UNFL DZ INEX 0 INEXACT DIVIDE BY ZERO UNDERFLOW OVERFLOW INVALID OPERATION Figure 16 Typical Co processor Configuration ADDRESS DECODE TS 68020 or TS 68030 PROCESSOR Bus Interface Unit 2119A HIREL 04 02 ADDRESS BUS FUNCTION CODES TL TU TUK BUS EXTENSION DATA BUS All communications between the TS68020 TS68030 and the TS68882 occur via stan dard TS68000 Family bus transfers The TS68882 is designed to operate on 8 16 or 32 bit data buses The TS68882 contains a number of co processor interface registers CIRs which are addresses in the same manner as memory by the main processor The TS68000 Family co processor interface is implemented via a protocol of reading and writing to these reg isters by the main processor The TS68020 and TS68030 implements this general purpose co processor interface protocol in hardware and microcode When the TS68020 TS68030 detects a typical TS68882 instruction the MPU writes the instruction to the memory mapped command CIR and reads the response CIR In this response the BIU encodes requests for any additional action required of the MPU on behalf of the TS68882 For example the response may request that the MPU fetch an operand from the evaluated effective address and transfer the operand to the
25. ameter Min Max Unit Vin Input High Voltage 2 0 Voc V Vi Input Low Voltage GND 0 3 0 8 V lin Input Leakage Current at 5 5V CLK RESET RAW AO A4 CS DS AS SIZE 10 yA hrs HI Z off state Input Current at 2 4V 0 4V DSACKO DSACK1 DO D31 20 HA Vou Output High Voltage lop 400 pA DSACKO DSACK1 DO D31 2 4 VoL Output Low Voltage lo 5 3 mA DSACKO DSACK1 DO D31 0 5 V lor Output Low Current Vo GND SENSE 500 yA 2119A HIREL 04 02 AMEL AMEL Table 5 Static Characteristics Voc 5 0 Voo 10 GND 0 Vo Te 55 125 C or 40 85 C Symbol Parameter Min Max Unit loc Maximum Supply Current Vog 5 5V CLK fmax part in Reset 136 mA Ci Capacitance Vi 0 Ta 25 C f 1MHz 20 pF CL Output Load Capacitance 130 pF Notes 1 Test load see Figure 5 2 Capacitance is periodically sampled rather than 100 tested Dynamic Switching The limits and values given in this section apply over the full case temperature range Characteristics 55 C to 125 C and Voo in the range 4 5V to 5 5V See AC Electrical Specification Def initions on page 13 The numbers N refer to the timing diagrams See Figure 4 Figure 6 Figure 7 Figure 8 and Figure 9 Table 6 AC Electrical Characteristics Clock Input Voc 5 0 Vog 10 GND 0 Vog Te 55 C to 125 C see Figure 4 16 67 MHz 20 MHz 25 MHz 33 33 MHz N
26. an scendental operations and by all appropriate TS68000 Family addressing modes For example all of the following are legal instructions FADD B 3 FPO FADD W D2 FP3 FADD L BIGINT FP7 FADD S 4 3 14159 FP5 FADD D SP FP6 FADD X TEMP PTR A7 FP3 FADD P 1 23E25 FPO On chip calculations are performed to extended precision format and the eight floating point data registers always contain extended precision values All data used in an oper ation is converted to extended precision by the TS68882 before the specific operation is performed and all results are in extended precision This ensures accuracy without sac rificing performance Refer to Figure 17 for a summary of the memory formats for the seven data formats sup ported by the TS68882 AMEL 2 AMEL Figure 17 TS68882 Data Format Summary 7 0 8 BITS 15 0 16 BITS 31 0 32 BITS 30 2 0 8 BIT 23 BIT EXP FRACTION JAWAT OF FRACTION 62 51 0 11 BIT 52 BIT EXP FRACTION E SIGN OF FRACTION 94 80 63 0 15 BIT 64 BIT EXPONENT ZERO MANTISSA L SIGN OF MANTISSA L IMPLICIT BINARY POINT 91 80 67 0 3 DIGIT bo LAT DIGIT Exp ZERO Dr MANTISSA ES IMPLICIT DECIMAL POINT 2 BITS USED ONLY FOR INFINITY OR NANS ZERO OTHERWISE SIGN OF EXPONENT SIGN OF MANTISSA Unless a binary to decimal conversion overflow occurs Instruction Set Moves
27. cal condition but is shown as an active signal for clarity The logical equation for this signal is START CS AS R W DS Additional Information Additional information shall not be for any inspection purposes Capacitance Not for Inspection Purposes Parameter Test Conditions A l 7 Vin 0 Tang 25 C E i nput Capacitance 20 p m f 1 MHz AMEL 7 2119A HIREL 04 02 Functional Description The Co processor Concept AMEL The TS68882 functions as a co processor in systems where the TS68020 or TS68030 is the main processor via the TS68000 co processor interface It functions as a peripheral processor in systems where the main processor is the TS68000 TS68010 The TS68882 utilizes the TS68000 Family co processor interface to provide extension of the TS68020 TS68030 registers and instruction set in a manner which is transparent to the programmer The programmer perceives the MPU FPCP execution model as if both devices are implemented on one chip A fundamental goal of the TS68000 Family co processor interface is to provide the pro grammer with an execution model based upon sequential instruction execution by the TS68020 TS68030 and the TS68882 For optimum performance however the co pro cessor interface allows concurrent operations in the TS68882 with respect to the TS68020 TS68030 whenever possible In order to simplify the programmer s model the co processor interface is designed to emulate as
28. d 300930 NOILONYLSNI HIJ 3AVS HIJ 3HO1S34 HIJ TOHLNOO HOX31dILINW oa Vd 193138 0d MOVLS Dd TOHLNOO MOVSO ONV 193135 H3181934 JOV4HALNI HOSS30OHAOD Sy31S 9038 YOLVYANAD 9019 1831 373S NI Lng ADDRESS A0 A4 DATA D0 D32 AMEL 2119A HIREL 04 02 AMEL Pin Assignments Figure 2 PGA Terminal Designation D27 D26 0 0 0 0 CS DSACKO D31 D28 D25 GND O AO Vee NO lo glo BIO BO O N m le 4 A2 O A4 O GN O 030 5 O 20 5 ju 50 O O z O 30 D15 D00 B8 B7 Internal logic E2 E9 A2 B2 B3 B4 note DSACK1 DSACKO H C3 E10 K3 Separate Extra A1 B1 J2 A10 D2 F2 H9 Note SENSE pin may be used as an additional GND pin Reserved for future ATMEL Grenoble use 4 TS68882 memme 2119A HIREL 04 02 a SG8882 Functional Signal Descriptions 2119A HIREL 04 02 Figure 2b CQFP Terminal Designation LU fta i aaa ao 260 658588388568 gt 60 UCC As f 0000000000 X Voc I ETA D9 CLKIN TL CT 010 GND CI CI Dit RESET ET 012 NC TI Cos 013 Veo EE ET pu Veo TI CE 015 SIZE T TOP CL Vcc GND TE VIEW CE Vcc DS oo CASE Co GND AS TI DT 016 M CIT Cr D17 A3 TO TA pis A2 CI I pig AM Cr U 020 AO TI I IT 021 Vece TT ETA GND NAH A TATA TATATATATATATATAT AT 2 0 PU RRRSERREREESE LS 8 18 This section contains a
29. ddressing modes and to gener ate execution time exception traps Thus from the programmer s view the CPU and co processor appear to be integrated onto a single chip While the execution of the majority of TS68882 instructions may be overlapped with the execution of TS68020 TS68030 instructions concurrency is completely transparent to the programmer The TS68020 TS68030 single step and program flow trace modes are fully supported by the TS68882 and the TS68000 Family co processorco processor interface While the TS68000 Family co processor interface permits co processors to be bus mas ters the TS68882 is never a bus master The TS68882 requests that the TS68020 TS68030 fetch all operands and store all results In this manner the TS68020 TS68030 32 bit data bus provides high speed transfer of floating point oper ands and results while simplifying the design of the TS68882 22 TS68882 memme 2119A HIREL 04 02 a SG8882 Operand Data Formats 2119A HIREL 04 02 Since the co processor interface is based solely upon bus cycles and the TS68882 is never a bus master the TS68882 can be placed on either the logical or physical side of the system memory management unit This provides a great deal of flexibility in the sys tem design The virtual machine architecture of the TS68000 Family is supported by the co proces sor interface and the TS68882 through the FSAVE and FRESTORE instructions If the TS68020 TS68030 detects a page fa
30. e integer counterparts on the TS68000 Family processors Any set of the floating point registers FPO through FP7 can be moved to or from memory with one instruction These registers are always moved as 96 bit extended data with no conversion hence no possibility of conversion errors Some move multiple examples are as follows FMOVEM ea FPO FP3 FP7 FMOVEM FP2 FP4 FP6 ea Move multiples are useful during context switches and interrupts to save or restore the state of a program These moves are also useful at the start and end of a procedure to save and restore the calling routine s register set In order to reduce procedure call over head the list of registers to be saved or restored can be contained in a data register This allows run time optimization by allowing a called routine to save as few registers as possible Note that no rounding or overflow underflow checking is performed by these operations Monadic operations have one operand This operand may be in a floating point data register memory or in an MPU data register The result is always stored in a floating point data register For example the syntax for square root is FSQRT fmt ea FPN or FSQRT X FPm FPn or FSQRT X FPn The TS68882 monadic operations available are as follows FABS Absolute Value FACOS Arc Cosine FASIN Arc Sine FATAN Arc Tangent FATANH Hyperbolic Arc Tangent FCOS Cosine FCOSH Hyperbolic Cosine FETOX e to the x Power AMEL a FABS F
31. erface the MPU performs the addressing mode calculations requested in the instruction In this case the instruction is encoded specifically for the TS68020 TS68030 and the execu tion of the TS68882 is not dependent on that encoding but only on the value of the command word written to the TS68882 by the main processor 30 15868882 mmm 2119A HIREL 04 02 a SG8882 Address Bus A0 through A4 2119A HIREL 04 02 This interface is quite flexible and allows any addressing mode to be used with floating point instructions For the TS68000 Family these addressing modes include immediate postincrement predecrement data or address register direct and the indexed indirect addressing modes of the TS68020 TS68030 Some addressing modes are restricted for some instructions in keeping with the TS68000 Family architectural definitions i e PC relative addressing is not allowed for a destination operand The orthogonal instruction set of the TS68882 along with the flexible branches and addressing modes allows a programmer writing assembly language code or a compiler writer generating object or source code for the MPU TS68882 device pair to think of the TS68882 as though it is part of the MPU There are no special restrictions imposed by the co processor interface and floating point arithmetic is coded exactly like integer arithmetic These active high address line inputs are used by the main processor to select the co processor
32. eter Min Max Min Max Min Max Min Max Unit 22 START false to AO and DSACK1 70 55 55 40 high impedance 23 O to clock high synchronous 0 0 0 0 be read 24 elegy to data out valid synchronous 105 80 60 45 He read 25 START true to data out valid synchronous 0 105 80 60 45 ns read 96 1 5 2 5 1 5 2 5 1 5 2 5 1 5 2 5 Clks 26 Clock low to DSACKO and En 75 55 45 30 is asserted synchronous read 27 START true to DSACKO and DSACK1 75 55 45 30 ns asserted synchronous read 208 1 5 2 5 1 5 2 5 1 5 2 5 1 5 2 5 Clks Notes 1 Timing measurements are referenced to and from a low voltage of 0 8V and a high voltage of 2 0V unless otherwise noted The voltage swing through this range should start outside and pass through the range such that the rise or fall will be linear between 0 8V and 2 0V 2 These specifications only apply if the TS68882 has completed all internal operations initiated by the termination of the previ ous bus cycle when DS was negated 3 Synchronous read cycles occur only when the save or response CIR locations are read 4 This specification only applies to systems in which back to back accesses read write or write write of the operand CIR can occur When the TS68882 is used as a co processor to the TS68020 68030 this can occur when the addressing mode is immediate 5 If the SIZE pin is not strapped to either Vog or GND it must have the same setup times as do addresses 6 If the SIZE pin is not strapped to either Vog
33. f Multiple Floating point Instructions Use with any Host Processor on an 8 16 or 32 bit Data Bus Available in 16 67 20 25 and 33 MHz for T from 55 C to 125 C Vec 5V 10 Description The TS68882 enhanced floating point co processor is a full implementation of the IEEE Standard for Binary Floating Point Arithmetic 754 for use with the THOMSON TS68000 Family of microprocessors It is a pin and software compatible upgrade of the TS68881 with optimized MPU interface that provides over 1 5 times the perfor mance of the TS68881 It is implemented using VLSI technology to give systems designers the highest possible functionality in a physically small device Intended primarily for use as a co processor to the TS68020 68030 32 bit micropro cessor units MPUs the TS68882 provides a logical extension to the main MPU integer data processing capabilities It does this by providing a very high performance floating point arithmetic unit and a set of floating point data registers that are utilized in a manner that is analogous to the use of the integer data registers The TS68882 instruction set is a natural extension of all earlier members of the TS68000 Family and supports all of the addressing modes of the host MPU Due to the flexible bus inter face of the TS68000 Family the TS68882 can be used with any of the MPU devices of the TS68000 Family and it may also be used as a peripheral to non TS68000 processors Screening Quality R su
34. ffix F suffix This product could be manufactured PGA 68 CQFP 68 l l Ceramic Pin Grid Arrav Ceramic Quad Flat Pack in full compliance with either Pa e MIL STD 883 Class B e DESC 5962 89436 taa a e or According to ATMEL Wi Grenoble Standards Rev 2119A HIREL 04 02 Introduction AMEL The TS68882 is a high performance floating point device designed to interface with the TS68020 or TS68030 as a co processor This device fully supports the TS68000 virtual machine architecture and is implemented in HCMOS Atmel s low power small geome try process This process allows CMOS and HMOS high density NMOS gates to be combined on the same device CMOS structures are used where speed and low power is required and HMOS structures are used where minimum silicon area is desired The HCMOS technology enables the TS68882 to be very fast while consuming less power than comparable HMOS and still have a reasonably small die size With some performance degradation the TS68882 can also be used as a peripheral processor in systems where the TS68020 or TS68030 is not the main processor i e TS68000 TS68010 The configuration of the TS68882 as a peripheral processor or co processor may be completely transparent to user software i e the same object code may be executed in either configuration The architecture of the TS68882 appears to the user as a logical extension of the TS68000 Family architecture Coupling of the co processor i
35. he AO pin is connected to GND The sixteen least significant data pins DO D15 must be connected to the sixteen most significant data pins D16 D31 when the TS68882 is configured to operate over an 16 bit data bus i e connect DO to D16 D1 to D17 and D15 to D31 The DSACK1 pin of the TS68882 is connected to the DTACK pin of the main processor and the DSACKO pin is not used 34 TSOSS NN 2119A HIREL 04 02 a SG8882 When connected as a peripheral processor the TS68882 chip select CS decode is system dependent If the TS68000 is used as the main processor the TS68882 CS must be decoded in the supervisor or user data spaces However if the TS68010 is used as the main processor the MOVES instruction may be used to emulate any CPU space access that the TS68020 co processorTS68030 generates for co processor com munications Thus the CS decode logic for such systems may be the same as in a TS68020 TS68030 systems such that the TS68882 will not use any part of the data address spaces Figure 18 32 bit Data Bus co processor Connection DECODE cs A Vee RW TS 68020 or TS 68030 UI n D24 D31 D16 D23 D8 D15 DO D7 DSACKO DSACK1 MAIN PROCESSOR COPROCESSOR CLOCK CLOCK AMEL 5 2119A HIREL 04 02 AMEL Figure 19 16 bit Data Bus co processor Connection FCO FC2 CHIP SELECT DECODE A20 A31 A16 A19 A13 A15 A5 A12 A1 A4 AO AS DS RAW TS 68020
36. interface register locations located in the CPU address space These lines control the register selection as listed in Table 10 When the TS68882 is configured to operate over an 8 bit data bus the AO pin is used as an address signal for byte accesses of the co processor interface registers When the TS68882 is configured to operate over a 16 or 32 bit system data bus both the AO and SIZE pins are strapped high and or low as listed in Table 11 Table 10 Co processor Interface Register Selection A4 A0 Offset Width Type Register 0000x S00 16 Read Response 0001x 02 16 Write Control 0010x S04 16 Read Save 0011x S06 16 R W Restore 0100x S08 16 Reserved 0101x SOA 16 Write Command 0110x SOC 16 Reserved 0111x SOE 16 Write Condition 100xx 10 32 R W Operand 1010x 14 16 Read Register select 1011x 16 16 Reserved 110xx 18 32 Read Instruction Address 111xx S1C 32 R W Operand Address Table 11 System Data Bus Size Configuration AO Size Data bus Low 8 bit Low High 16 bit High High 32 bit AMEL si Data Bus DO through D31 Size SIZE Address Strobe AS Chip Select CS Read Write R W Data Strobe DS Data Transfer and Size Acknowledge DSACKO DSACK1 AMEL This 32 bit bi directional three state bus serves as the general purpose data path between the TS68020 TS68030 and the TS68882 Regardless of whether the TS688
37. ions Table 12 indicates that all accesses over a 32 bit bus where A4 equals zero are to 16 bit registers The TS68882 implements all 16 bit co processor interface registers on data lines D16 D13 to eliminate the need for on chip multiplexers however the TS68020 TS68030 expects 16 bit registers that are located in a 32 bit port at odd word addresses A1 1 to be implemented on data lines DO D15 For accesses to these reg isters when configured for 32 bit bus operation the TS68882 generates DSACK signals as listed in Table 12 to inform the TS68020 TS68030 of valid data on D16 D31 instead of DO D15 An external holding resistor is required to maintain both DSACKO and DSACK1 high between bus cycles In order to reduce the signal rise time the DSACKO and DSACK1 lines are actively pulled up negated by the TS68882 following the rising edge of AS or DS and both DSACK lines are then three stated placed in the high impedance state to avoid interference with the next bus cycle Data Bus A4 DSACK1 DSACK2 Comments 32 bit 1 L L Valid data on D31 DO 32 bit 0 L H Valid data on D31 D16 16 bit x L H Valid data on D31 D16 or D15 DO 8 bit x H L Valid data on D31 D24 D23 D16 D15 D8 D7 DO All x H H Insert Wait States in Current Bus Cycle Reset RESET This active low input signal causes the TS68882 to initialize the floating point data regis ters to non signaling not a numbers NANs and clears the fl
38. mats single precision 32 bits and double precision 64 bits are as defined by the IEEE standard These are the main floating point formats and should be used for most calculations involving real numbers Table 8 lists the exponent and mantissa size for single double and extended precision The exponent is biased and the mantissa is in sign and magnitude form Since single and double precision require normalized numbers the most significant bit of the mantissa is implied as one and is not included thus giving one extra bit of precision Table 8 Exponent and Mantissa Sizes Data Format Single Exponent Bits 8 Mantissa Bits 23 1 Bias 127 Double 11 52 1 1023 Extended 15 64 16383 The extended precision data format is also in conformance with the IEEE standard but the standard does not specify this format to the bit level as it does for single and double precision The memory format on the TS68882 consists of 96 bits three long words Only 80 bits are actually used the other 16 bits are for future expandability and for long word alignment of floating point data structures Extended format has a 15 bit exponent a 64 bit mantissa and a 1 bit mantissa sign Extended precision numbers are intended for use as temporary variables intermediate values or in places where extra precision is needed For example a compiler might select extended precision arithmetic for evaluation
39. nterface allows the TS68020 TS68030 programmer to view the TS68882 registers as though the registers are resident in the TS68020 TS68030 Thus a TS68020 or TS68030 TS68882 device pair appears to be one processor that supports seven floating point and integer data types and has eight integer data registers eight address registers and eight floating point data registers As shown in Figure 1 the TS68882 is internally divided into four processing elements the Bus Interface Unit BIU the Conversion Control Unit CCU the Execution Control Unit ECU and the Microcode Control Unit MCU The BIU communicates with the main processor the CCU controls the main processor communications dialog and per forms some data conversions and the ECU and MCU execute most floating point calculations The BIU contains the co processor interface registers and the 32 bit control and instruction address registers In addition to these registers the register select and DSACK timing control logic is contained in the BIU Finally the status flags used to mon itor the status of communications with the main processor are contained in the BIU The CCU contains special purpose hardware that performs conversions between the single double and extended precision memory data formula and the internal data for mat used by the ECU It also contains a state machine that controls communications with the main processor during co processor interface dialogs The eight
40. o this pin location external hardware may sense the presence of the 15688882 in a system AMEL ss Power Vcc and GND No Connect NC Interfacing Methods 32 bit Data Bus Co processor Connection 16 bit Data Bus Co processor Connection 8 bit Data Bus Co processor Connection 16 bit Data Peripheral Processor Connection AMEL These pins provide the supply voltage and system reference level for the internal cir cuitry of the TS68882 Care should be taken to reduce the noise level on these pins with appropriate capacitance decoupling One pin of the TS68882 package is designated as a no connect NC This pin position is reserved for future use and should not be used for signal routing or connected to Vec or GND TS68882 TS68020 or TS68030 interfacing The following paragraphs describe how to connect the TS68882 to a TS68020 or TS68030 for co processor operation via an 8 16 or 32 bit data bus Figure 18 illustrates the co processor interface connection of a TS68882 to a TS68020 TS68030 via a 32 bit data bus The TS68882 is configured to operate over a 32 bit data bus when both the AO and SIZE pins are connected to Vcc Figure 19 illustrates the co processor interface connection of a TS68882 to a TS68020 TS68030 via a 16 bit data bus The TS68882 is configured to operate over a 16 bit data bus when the SIZE pin is connected to Voo and the AO pin is connected to GND The sixteen least significant data pins DO D15
41. oating point control status and instruction address registers When performing a power up reset external circuitry should keep the RESET line asserted to a minimum of four clock cycles after Vog is within tolerance This assures correct initialization of the TS68882 when power is applied For compatibility with all TS68000 Family devices 100 milliseconds should be used as the minimum When performing a reset of the TS68882 after V has been within tolerance for more than the initial power up time the RESET line must have an asserted pulse width which is greater than two clock cycles For compatibility with all TS68000 Family devices 10 clock cycles should be used as the minimum Clock CLK The TS68882 clock input is a TTL compatible signal that is internally buffered for devel Sense Device SENSE 2119A HIREL 04 02 opment of the internal clock signals The clock input should be a constant frequency square wave with no stretching or shaping techniques required The clock should not be gated off at any time and must conform to minimum and maximum period and pulse width times This pin may be used optionally as an additional GND pin or as an indicator to external hardware that the TS68882 is present in the system This signal is internally connected to the GND of the die but it is not necessary to connect it to the external ground for cor rect device operation If a pullup resistor which should be larger than 10 kQ is connected t
42. of the right side of an equation with mixed sized data and then convert the answer to the data type on the left side of the equation It is anticipated that extended precision data will not be stored in large arrays due to the amount of memory required by each number 24 TS68882 memme 2119A HIREL 04 02 a SG8882 Packed Decimal String Real Data Format Data Format Summary 2119A HIREL 04 02 The packed decimal string data format allows packed BCD strings to be input to and output from the TS68882 The strings consist of a 3 digit base 10 exponent and a 17 digit base 10 mantissa Both the exponent and mantissa have a separate sign bit All digits are packed BCD such that an entire string fits in 96 bits three long words As is the case with all data formats when packed BCD strings are input to the TS68882 the strings are automatically converted to extended precision real values This allows packed BCD numbers to be used as inputs to any operation For example FADD P 6 023E 24 FP5 BCD numbers can be output from the TS68882 in a format readily used for printing by a program generated by a high level language compiler For example FMOVE P FP3 BUFFER 5 instructs the TS68882 to convert the floating point data register 3 FP3 contents into a packed BCD string with five digits to the right of the decimal point FORTRAN F format All data formats described above are supported orthogonally by all arithmetic and tr
43. or GND it must have the same hold times as do addresses 7 This number is reduced to 5 nanoseconds if DSACKO and DSACK1 have equal loads 8 START is not an external signal rather it is the logical condition that indicates the start of an access The logical equation for this condition is START CS AS RW DS _ E o 9 If a subsequent access is not a FPCP access CS must be negated before the assertion of AS and or DS on the non FPCP access These specifications replace the old specifications 8 and 8A the old specifications implied that in all cases transi tions in CS must not occur simultaneously with transitions of AS or DS This is not a requirement of the TS68882 2119A HIREL 04 02 a SG8882 Test Conditions Specific to the Device Test Load The applicable loading network shall be as defined in column Test conditions of Table 2 referring to the loading network number as shown in Figure 5 Figure 5 Test Loads 5V R TEST POINT OR EQUIVALENT CL 130 pF includes all parasitics R 7409 for DSACKO DSACK1 DO D31 RL 6 0 k for DSACKO DSACKI DO D31 MMD7000 OR EQUIVALENT AC Electrical Specification The AC specifications presented consist of output delays input setup and hold times Definitions and signal skew times All signals are specified relative to an appropriate edge of the clock input and possibly relative to one or more other signals The measurement of the AC specifications is defined by
44. pport of virtual memory virtual machine systems is provided via the FSAVE and FRESTORE instructions Up to eight co processors may reside in a system simultaneously multiple co processors of the same type are also allowed e Systems may use software emulation of the TS68882 without reassembling or relinking user software 18 TS68882 mmm 2119A HIREL 04 02 a SG8882 The TS68882 programming model is shown in Figure 10 through 15 and consists of the following e Eight 80 bit floating point data registers FPO FP7 These registers are analogous to the integer data registers DO D7 and are completely general purpose i e any instruction may use any register e A 32 bit control register that contains enable bits for each class of exceptions trap and mode bits to set the user selectable rounding and precision modes e A 32 bit status register that contains floating point condition codes quotient bits and exception status information e A 32 bit instruction address register that contains the main processor memory address of the last floating point instruction that was executed This address is used in exception handling to locate the instruction that caused the exception The connection between the TS68020 TS68030 and the TS68882 is a simple extension of the TS68000 bus interface The TS68882 is connected as a co processor to the TS68020 TS68030 and the selection of the TS68882 is based upon a chip select CS which is decoded f
45. read write by the main pro cessor A logic high 1 indicates a read from the TS68882 and a logic low 0 indicates a write to the TS68882 The R W signal must be valid when AS is asserted This active low input signal indicates that there is valid data on the data bus during a write bus cycle These active low three state output signals indicate the completion of a bus cycle to the main processor The TS68882 asserts both the DSACKO and DSACK1 signals upon assertion of CS If the bus cycle is a main processor read the TS68882 asserts DSACKO and DSACK1 signals to indicate that the information on the data bus is valid Both DSACK signals may be asserted in advance of the valid data being placed on the bus If the bus cycle is a main processor write to the TS68882 DSACKO and DSACK1 are used to acknowl edge acceptance of the data by the TS68882 The TS68882 also uses DSACKO and DSACK1 signals to dynamically indicate to the TS68020 TS68030 the port size system data bus width on a cycle by cycle basis Depending upon which of the two DSACK pins are asserted in a given bus cycle the TS68020 TS68030 assumes data has been transferred to from an 8 16 or 32 bit wide data port Table 12 lists the DSACK assertions that are used by the TS68882 for the various bus cycles over the various bus cycles over the various system data bus configurations 32 15868882 memme 2119A HIREL 04 02 a SG8882 Table 12 DSACK Assert
46. rom the TS68020 TS68030 function codes and address bus Figure 16 illustrates the TS68882 TS68020 or TS68030 configuration Figure 10 TS68882 Programming Model 79 T H l H 1 1 1 i 1 L i T 2119A HIREL 04 02 FPO FP1 FP2 l FP3 l l FPA FP5 l FP6 FP7 31 23 15 7 0 A Exception Mode g Enable Control FROM Condition Exception Accrued Code Quotient Status Exception EPSR EPIAR AMEL FLOATING POINT DATA REGISTERS CONTROL REGISTER STATUS REGISTER INSTRUCTION ADDRESS REGISTER 19 Figure 11 Exception Status Enable Byte 15 14 13 12 11 10 9 8 BSUN SNAN OPERR OVFL UNFL DZ INEX2 INEX1 INEXACT DECIMAL INPUT INEXACT OPERATION DIVIDE BY ZERO UNDERFLOW OVERFLOW OPERAND ERROR SIGNALLING NOT A NUMBER BRANCH SET ON UNORDERED Figure 12 Mode Control Byte 7 6 5 4 3 2 1 0 PREC RND 0 ROUNDING MODE 00 TO NEAREST 01 TOWARD ZERO 10 TOWARD MINUS INFINITY 11 TOWARD PLUS INFINITY ROUNDING PRECISION 00 extended 01 SINGLE 10 DOUBLE 11 UNDEFINED RESERVED Figure 13 Condition Code Byte 31 30 29 28 27 26 25 24 0 N Z l MAN NOT A NUMBER OR UNORDERED INIFINITY ZERO NEGATIVE Figure 14 Quotient Byte 23 22 21 20 19 18 17 16 s QUOTIENT SEVEN LEAST SIGNIFICANT BITS OF QU
47. tandard CQFP 68 55 125 16 67 Internal 2119A HIREL 04 02 AMEL 41 AMEL Standard Product Note 42 Type y Temperature range Tc M 55 125 C V 40 85 C Package R Pin grid array 68 F CQFP 68 Commercial Atmel Temperature Range Frequency Part Number Norms Package Te c MHZ Drawing Number TS68882MF20 ATMEL Grenoble Standard CQFP 68 55 125 20 Internal TS68882MF25 ATMEL Grenoble Standard CQFP 68 55 125 25 Internal TS68882MF33 ATMEL Grenoble Standard CQFP 68 55 125 33 Internal TS68882 M R 1 B C 20 Speed MHz Screening Standard B C MIL STD 883 Class B Hirel lead finish 1 Hot solder dip 883C Gold For availability of the different versions contact your Atmel sales office TSOSS NN 2119A HIREL 04 02 AMEL T Atmel Headquarters Corporate Headquarters 2325 Orchard Parkway San Jose CA 95131 TEL 1 408 441 0311 FAX 1 408 487 2600 Europe Atmel Sarl Route des Arsenaux 41 Case Postale 80 CH 1705 Fribourg Switzerland TEL 41 26 426 5555 FAX 41 26 426 5500 Asia Atmel Asia Ltd Room 1219 Chinachem Golden Plaza 77 Mody Road Tsimhatsui East Kowloon Hong Kong TEL 852 2721 9778 FAX 852 2722 1369 Japan Atmel Japan K K 9F Tonetsu Shinkawa Bldg 1 24 8 Shinkawa Chuo ku Tokyo 104 0033 Japan TEL 81 3 3523 3551 FAX 81 3 3523 75
48. the TS68882 is used as a peripheral with any pro cessor capable of memory mapped I O over on TS68000 style bus When used as a peripheral processor with the 8 bit TS68008 or the 16 bit TS68000 or TS68010 all TS68882 instructions are trapped by the main processor to an exception handler at exe cution time Thus the software emulation of the processor interface protocol can be totally transparent to the user The system can be quickly upgraded by replacing the main processor with a TS68020 TS68030 without changes to the user software Since the bus is asynchronous the TS68882 need not run at the same clock speed as the main processor Total system performance may therefore be customized For exam ple a system requiring very fast floating point arithmetic with relatively slow integer arithmetic can be designed with an inexpensive main processor and a fast TS68882 The TS68000 Family co processor interface is an integral part of the TS68882 and TS68020 TS68030 designs with the interface tasks shared between the two The inter face is fully compatible with all present and future TS68000 Family products Tasks are partitioned such that the TS68020 TS68030 does not have to decode co processor instructions and the TS68882 does not have to duplicate main processor functions such as effective address evaluation This partitioning provides an orthogonal extension of the instruction set by permitting TS68882 instructions to utilize all TS68020 TS68030 a
49. tional tests set the BSUN bit in the status register exception byte if the NAN condition code bit is set when a conditional instruction is executed SF Signaling False SEQ Signaling Equal GT Greater Than GE Greater Than or Equal LT Less Than LE Less Than or Equal GL Greater or Less Than GLE Greater Less or Equal NGLE Not Greater Less or Equal NGL Not Greater or Less NLE Not Less or Equal NLT Not Less Than NGE Not Greater or Equal NGT Not Greater Than SNE Signaling Not Equal ST Signaling True Miscellaneous Instructions Addressing Modes Miscellaneous instructions include moves to and from the status control and instruction address registers and a no operation function that can be used to flush exceptions Also included are the virtual memory machine FSAVE and FRESTORE instructions that save and restore the internal state of the TS68882 FMOVE ea FPcr Move to Control Register s FMOVE FPcr ea Move from Control Register s FNOP No Operation FSAVE ea Virtual Machine State Save FRESTORE ea Virtual Machine State Restore The TS68882 does not perform address calculations This satisfies the criterion that a TS68000 Family co processor must not depend on certain features or capabilities that may or may not be implemented by a given main processor Thus when the TS68882 instructs the TS68020 TS68030 to transfer an operand via the co processor int
50. to all parameters specified relative to the rising edge of the clock 2 This output timing is applicable to all parameters specified relative to the falling edge of the clock 3 This input timing is applicable to all parameters specified relative to the rising edge of the clock 4 This input timing is applicable to all parameters specified relative to the falling edge of the clock 5 This timing is applicable to all parameters specified relative to the assertion negation of another signal 14 TSOSS memme TS68882 Figure 7 Asynchronous Read Cycle Timing Diagram START DSACK1 DSACKO DO D31 Note START is actually a logical condition but is shown as an active signal for clarity The logical equation for this signal is START CS AS R W DS AMEL is 2119A HIREL 04 02 AMEL Figure 8 Asynchronous Write Cycle Timing Diagram O l i RM i Od O 04 D a E 1 Ta FS _ DS _ oka IT 6 gt START ki i 22 19 O DSACKI 7 o DSACKO Note START is actually a logical condition but is shown as an active signal for clarity The logical equation for this signal is START CS AS RAW DS 16 15868882 mmm TS68882 Figure 9 Synchronous Read Cycle Timing Diagram SO S1 S2 Sw Sw Sw Sw S3 S4 S5 CLK A 10 04 Ma START 2 GD DSACK1 DSACKO DO D31 Note START is actually a logi
51. ult and or task time out it can force the TS68882 to stop whatever operation is in process at any time even in the middle of the execution of an instruction and save the TS68882 internal state in memory The size of the saved internal state of the TS68882 is dependent upon what the CCU and ECU are doing at the time that the FSAVE is executed If the TS68882 is in the reset state when the FSAVE instruction is received only one word of state is transferred to memory which may be examined by the operating system to determine that the co processor programmer s model is empty If the co processor is idle when the save instruction is received only a few words of internal state are transferred to memory If the TS68882 is in the middle of performing a calculation it may be necessary to save the entire internal state of the machine Instructions that can complete execution in less time than it would take to save the larger state in mid instruction are allowed to complete execution and then save the dle state Thus the size of the saved internal state is kept to a minimum The ability to utilize sev eral internal state sizes greatly reduces the average context switching time The FRESTORE instruction permits reloading of an internal state that was saved earlier and continue any operation that was previously suspended Restoring of the reset inter nal state functions just like a hardware reset to the TS68882 in that defaults are re established
52. when the SIZE pin is connected to GND The eight least significant data pins D0 D7 must be connected to the twenty four most significant data pins D8 D31 when the TS68882 is configured to operate over an 8 bit data bus i e connect DO to D8 D16 and D24 D1 to D9 D17 and D25 and D7 to D 15 D 23 and D31 The DSACKO pin of the TS68882 is connected to the DTACK pin of the TS68008 and the DSACK1 pin is not used When connected as a peripheral processor the TS68882 chip select CS decode is system dependent and the CS must be decoded in the supervisor or user data spaces ATMEL Grenoble offers a certificate of compliance with each shipment of parts affirm ing the products are in compliance with MIL STD 883 and guaranteeing the parameters are tested at extreme temperatures for the entire temperature range Devices must be handled with certain precautions to avoid damage due to accumulation of static charge Input protection devices have been designed in the chip to minimize the effect of this static buildup However the following handling practices are recommended a Device should be handled on benches with conductive and grounded surface b Ground test equipment tools and operator d Store devices in conductive foam or carriers e Avoid use of plastic rubber or silk f Maintain relative humidity above 50 if practical c Do not handle devices by the leads 38 TS68882 memme 2119A HIREL 04 02

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