ATMEL TS80C31X2 handbook
Contents
1. IDL Be n Description Number Mnemonic Serial port Mode bit 1 Set to select double baud rate in mode 1 2 or 3 Serial port Mode bit 0 Clear to select SMO bit in SCON register Set to to select FE bit in SCON register Reserved The value read from this bit is indeterminate Do not set this bit Power Off Flag Clear to recognize next reset type Set by hardware when VCC rises from 0 to its nominal voltage Can also be set by software General purpose Flag 3 GFI Cleared by user for general purpose usage Set by user for general purpose usage General purpose Flag 2 GFO Cleared by user for general purpose usage Set by user for general purpose usage Power Down mode bit 1 PD Cleared by hardware when reset occurs Set to enter power down mode Idle mode bit 0 IDL Clear by hardware when interrupt or reset occurs Set to enter idle mode Reset Value 00X1 00006 Not bit addressable Power off flag reset value will be 1 only after a power on cold reset A warm reset doesn t affect the value of this bit Rev A Mar 19 1999 17 Preliminary TS80C31X2 6 4 Interrupt System The TS80C31X2 has a total of 5 interrupt vectors two external interrupts INTO and INT1 two timer interrupts timers 0 and 1 and the serial port interrupt These interrupts are shown in Figure 7 High priority interrupt 2 TFO Interrupt INTI polling sequence decreasing2. Priority Level 2 PXIH 0 0 Lowest 0 1 1 0 1 1 Highest Timer 0 overflow interrupt Priority High bit PTOH PTO Priority Level 1 PTOH 0 0 Lowest 0 1 1 0 1 1 Highest External interrupt 0 Priority High bit Priority Level 0 0 0 Lowest 0 1 1 0 1 1 Highest Reset Value 0000b Not bit addressable Rev A Mar 19 1999 21 Preliminary TS80C31X2 6 5 Idle mode An instruction that sets PCON O causes that to be the last instruction executed before going into the Idle mode In the Idle mode the internal clock signal is gated off to the CPU but not to the interrupt Timer and Serial Port functions The CPU status is preserved in its entirely the Stack Pointer Program Counter Program Status Word Accumulator and all other registers maintain their data during Idle The port pins hold the logical states they had at the time Idle was activated ALE and PSEN hold at logic high levels There are two ways to terminate the Idle Activation of any enabled interrupt will cause to be cleared by hardware terminating the Idle mode The interrupt will be serviced and following RETI the next instruction to be executed will be the one following the instruction that put the device into idle The flag bits GFO and can be used to give and indication if an interrupt occured during normal operation or during an Idle For example an instruction that activates Idle can also set one or both f
3. NIC No Internal Connection 4 Rev A Mar 19 1999 Preliminary TS80C31X2 Table 2 Pin Description for 40 44 pin packages PIN NUMBER MNEMONIC TYPE NAME AND FUNCTION DIL LCC VQFP 1 4 Vss 20 22 16 I Ground OV reference Vss1 1 39 I Optional Ground Contact the Sales Office for ground connection Vec 40 44 38 I Power Supply This is the power supply voltage for normal idle and power down operation 0 7 39 32 43 36 37 30 IO Port 0 Port 0 is an open drain bidirectional I O port Port 0 pins that have 1s written to them float and can be used as high impedance inputs Port 0 is also the multiplexed low order address and data bus during access to external program and data memory In this application it uses strong internal pull up when emitting Is P1 0 P1 7 1 8 2 9 40 44 IO Port 1 Port 1 is an 8 bit bidirectional I O port with internal pull ups Port 1 1 3 pins that have 18 written to them are pulled high by the internal pull ups and can be used as inputs As inputs Port 1 pins that are externally pulled low will source current because of the internal pull ups P2 0 P2 7 21 28 24 31 18 25 IO Port 2 Port 2 is an 8 bit bidirectional I O port with internal pull ups Port 2 pins that have 1s written to them are pulled high by the internal pull ups and can be used as inputs As inputs Port 2 pins that are externally pulled low will source current because of the internal pull ups Po
4. TS80C31X2 LIABY TEMIC TS80C31X2 8 bit CMOS Microcontroller 0 60 MHz 1 Description TEMIC TS80C31X2 is high performance CMOS and ROMless versions of the 80C51 CMOS single chip 8 bit microcontroller The TS80C31X2 retains all features of the TEMIC TSC80C31 with 128 bytes of internal RAM a 5 source 4 priority level interrupt system an on chip oscilator and two timer counters In addition the TS80C31X2 has a dual data pointer a more versatile serial channel that facilitates multiprocessor communication EUART and a X2 speed improvement mechanism 2 Features e 80C31 Compatible 8031 pin and instruction compatible e Four 8 bit I O ports Two 16 bit timer counters e 128 bytes scratchpad RAM High Speed Architecture e 40 MHz 5V 30MHz 3V X2 Speed Improvement capability 6 clocks machine cycle 30 MHz 5V 20 MHz 3V Equivalent to 60 MHz 5V 40 MHz 3V Dual Data Pointer Asynchronous port reset Rev A Mar 19 1999 The fully static design of the TS80C31X2 allows to reduce system power consumption by bringing the clock frequency down to any value even DC without loss of data The TS80C31X2 has 2 software selectable modes of reduced activity for further reduction in power consumption In the idle mode the CPU is frozen while the timers the serial port and the interrupt system are still operating In the power down mode the RAM is saved and al
5. STD mode 2 Set to select 6 clock periods per machine cycle X2 mode Fosc Fx tar Reset Value XXXX Not bit addressable 8 Rev A Mar 19 1999 Preliminary 4 14 TS80C31X2 6 2 Dual Data Pointer Register Ddptr The additional data pointer can be used to speed up code execution and reduce code size in a number of ways The dual DPTR structure is a way by which the chip will specify the address of an external data memory location There are two 16 bit DPTR registers that address the external memory and a single bit called DPS 1 510 See Table 5 that allows the program code to switch between them Refer to Figure 3 External Data Memory AUXRI A2H DPH 83H DPL 82H Figure 3 Use of Dual Pointer Rev Mar 19 1999 Preliminary TS80C31X2 Table 4 AUXRI Auxiliary Register 1 7 6 5 4 3 2 1 0 poer Bit Bit Description ipti Number Mnemonic 7 Reserved The value read from this bit is indeterminate Do not set this bit 6 Reserved The value read from this bit is indeterminate Do not set this bit Reserved The value read from this bit is indeterminate Do not set this bit Reserved The value read from this bit is indeterminate Do not set this bit Reserved The value read from this bit is indeterminate Do not set this bit Reserved The value read from this bi
6. 1001b Given 1111 OXX1b Slave C SADDR 1111 00105 SADEN 1111 1101b Given 1111 00X1b The SADEN byte is selected so that each slave may be addressed separately For slave A bit O the LSB is a don t care bit for slaves B and C bit O is a 1 To communicate with slave A only the master must send an address where bit 0 is clear e g 1111 00000 For slave A bit 1 is a 1 for slaves B and C bit 1 is a don t care bit To communicate with slaves B and C but not slave A the master must send an address with bits O and 1 both set e g 1111 00110 To communicate with slaves A B and C the master must send an address with bit O set bit 1 clear and bit 2 clear e g 1111 00015 6 3 4 Broadcast Address A broadcast address is formed from the logical OR of the SADDR and SADEN registers with zeros defined as don t care bits e g SADDR 0101 01105 SADEN 1111 11005 Broadcast SADDR SADEN 1111 111Xb The use of don t care bits provides flexibility in defining the broadcast address however in most applications a broadcast address is FFh The following is an example of using broadcast addresses Slave A SADDR 1111 0001b SADEN 1111 1010b Broadcast 1111 1 11 Slave B SADDR 1111 0011b SADEN 111110015 Broadcast 1111 1 11 Slave SADDR 1111 0010b SADEN 111111015 Broadcast 1111 11116 For slaves and bit 2 is a don t bit for slave bit 2 is set To communicate
7. from high to low priority 1 p RI TI Low priority Individual Enable interrupt Global Disable Figure 7 Interrupt Control System Each of the interrupt sources can be individually enabled or disabled by setting or clearing a bit in the Interrupt Enable register See Table 8 This register also contains a global disable bit which must be cleared to disable all interrupts at once Each interrupt source can also be individually programmed to one out of four priority levels by setting or clearing a bit in the Interrupt Priority register See Table 9 and in the Interrupt Priority High register See Table 10 shows the bit values and priority levels associated with each combination 18 Rev A Mar 19 1999 Preliminary TS80C31X2 Table 7 Priority Level Bit Values IPH x IP x Interrupt Level Priority 0 0 0 Lowest 3 Highest A low priority interrupt can be interrupted by a high priority interrupt but not by another low priority interrupt A high priority interrupt can t be interrupted by any other interrupt source If two interrupt requests of different priority levels are received simultaneously the request of higher priority level is serviced If interrupt requests of the same priority level are received simultaneously an internal polling sequence determines which request is serviced Thus within each priority level there is a second priority structure determined by the
8. with all of the slaves the master must send an address FFh To communicate with slaves A and B but not slave C the master can send and address FBh 14 Rev A Mar 19 1999 Preliminary TS80C31X2 6 3 5 Reset Addresses On reset the SADDR and SADEN registers are initialized to OOh i e the given and broadcast addresses are XXXXb don t care bits This ensures that the serial port will reply to any address and so that it is backwards compatible with the 80C51 microcontrollers that do not support automatic address recognition SADEN Slave Address Mask Register B9h 7 6 5 4 3 2 1 0 Reset Value 0000 0000b Not bit addressable SADDR Slave Address Register A9h 7 6 5 4 3 2 1 0 Reset Value 0000 0000b Not bit addressable Rev A Mar 19 1999 15 Preliminary TEMIC TS80C31X2 Table 5 SCON Register SCON Serial Control Register 98h 7 6 5 4 3 2 1 0 FE SMO SMI SM2 REN TB8 RB8 TI RI Bit Bit Description ipti Number Mnemonic Framing Error bit SMODO0 1 7 FE Clear to reset the error state not cleared by a valid stop bit Set by hardware when an invalid stop bit is detected 5 must be set to enable access to the FE bit Serial port Mode bit 0 SMO Refer to 5 1 for serial port mode selection 5 must be cleared to enable access to the SMO bit Serial port Mode bit 1 SM1 SMO Mode Description Baud Rate 6
9. 00 EFh ACC EOh 0000 0000 D8h DFh PSW DOh 000 0000 D7h C8h CFh C7h IP SADEN B8h 0000 0000 0000 BER P3 IPH Boh 111 111 0000 SADDR A8h oxxo 0000 0000 0000 AFh 2 AUXRI 0 111 111 SCON SBUF 98h 0000 0000 XXXX XXXX 9Fh PI 90h 97h 88h TCON TMOD TLO THO THI CKCON 8Fh 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 XXXX 80h PO SP DPL DPH PCON 87h 111 111 0000 0111 0000 0000 0000 0000 00X1 0000 0 8 1 9 2 3 B AIC 5 6 E 7 reserved Rev A Mar 19 1999 Preliminary TS80C31X2 5 Pin Configuration 1 0 P1 1 P1 2 P1 3 P1 4 P1 5 P1 6 P1 7 RST s i i d d P3 0 RxD 0 5 5 P3 1 TxD P0 6 AD6 P3 2 INTO RST P0 7 AD7 P3 3 INTI E A EA P3 4 TO PLCC44 P3 5 T1 33 ALE P3 2 INTO H PSEN P3 3 INTI fener XTAL2 P2 6 A14 XTALI 3 17 P2 5 A13 VSS 4 25 26 27 28 Bis 29225 SE G n lt Q 2200 5 2255 on O S gt gt K K K K 1 5 4 4 1 6 0 5 5 P1 7 P0 6 AD6 RST P0 7 AD7 P3 0 RxD EA P3 1 TxD VQFP44 ALE P3 2 INTO PSEN P3 3 INTI P2 7 A15 P3 4 TO P2 6 A14 P3 5 T1 2 5 13 2131415 81920212 E a
10. 12 clock cycles per instruction to 6 clock cycles and vice versa At reset the standard speed is activated STD mode Setting this bit activates the X2 feature X2 mode CAUTION In order to prevent any incorrect operation while operating in X2 mode user must be aware that all peripherals using clock frequency as time reference UART timers will have their time reference divided by two For example a free running timer generating an interrupt every 20 ms will then generate an interrupt every 10 ms UART with 4800 baud rate will have 9600 baud rate Rev Mar 19 1999 7 Preliminary TS80C31X2 Table 3 CKCON Register CKCON Clock Control Register 8Fh 7 6 5 4 3 2 1 0 a 2 Bit Bit Description ipti Number Mnemonic 7 Reserved The value read from this bit is indeterminate Do not set this bit 6 Reserved The value read from this bit is indeterminate Do not set this bit Reserved The value read from this bit is indeterminate Do not set this bit Reserved The value read from this bit is indeterminate Do not set this bit Reserved The value read from this bit is indeterminate Do not set this bit Reserved The value read from this bit is indeterminate Do not set this bit Reserved The value read from this bit is indeterminate Do not set this bit CPU and peripheral clock bit 0 x2 Clear to select 12 clock periods per machine cycle
11. 5 0 0 0 Shift Register 1 12 0 1 1 8 bit UART Variable 1 0 2 9 bit UART 1 64 or Fy pay 32 1 1 3 9 bit UART Variable Serial port Mode 2 bit Multiprocessor Communication Enable bit Clear to disable multiprocessor communication feature Set to enable multiprocessor communication feature in mode 2 and 3 and eventually mode 1 This bit should be cleared in mode 0 Reception Enable bit Clear to disable serial reception Set to enable serial reception Transmitter Bit 8 Ninth bit to transmit in modes 2 and 3 Clear to transmit a logic 0 in the 9th bit Set to transmit a logic 1 in the 9th bit Receiver Bit 8 Ninth bit received in modes 2 and 3 Cleared by hardware if 9th bit received is a logic 0 Set by hardware if 9th bit received is a logic 1 In mode 1 if SM2 0 RB8 is the received stop bit In mode 0 is not used Transmit Interrupt flag Clear to acknowledge interrupt Set by hardware at the end of the 8th bit time in mode 0 or at the beginning of the stop bit in the other modes Receive Interrupt flag RI Clear to acknowledge interrupt Set by hardware at the end of the 8th bit time in mode 0 see Figure 5 and Figure 6 in the other modes Reset Value 0000 0000b Bit addressable 16 Rev A Mar 19 1999 Preliminary TS80C31X2 Table 6 PCON Register PCON Power Control Register 87h 7 6 5 4 3 2 1 0 SMOD1 SMOD0 POF GF1
12. 999 Preliminary TEMIC ecemicuamauc vrs 7 4 4 External Data Memory Characteristics Table 19 Symbol Description TS80C31X2 Symbol Parameter TrLRH RD Pulse Width WR Pulse Width RD to Valid Data In Data Hold After RD TRHDZ Data Float After RD TLLDV ALE to Valid Data In TAVDV Address to Valid Data In TLLWL ALE to WR or RD TAVWL Address to WR or RD Tovwx Data Valid to WR Transition Data set up to WR High TwHox Data Hold After WR TRLAZ RD Low to Address Float TwHLH RD or WR High to ALE high Rev Mar 19 1999 Preliminary 33 TS80C31X2 Table 20 AC Parameters for a Fix Clock TEMIC hc n 114 Speed M V L Units see ordering Symbol Min Max Min Max Min Max TRLRH 105 85 200 ns TwiwH 105 90 200 ns Tni Dv 100 60 155 ns 0 0 0 ns 15 13 40 ns 160 100 310 ns TAVDV 165 100 360 ns 40 110 30 65 90 60 ns TAVWL 40 27 100 ns Tovwx 3 0 18 ns TovwH 145 90 280 ns TwHox 10 7 20 ns Trike 0 0 0 ns 5 45 5 29 20 80 ns 34 Preliminary Rev A Mar 19 1999 TS80C31X2 Table 21 AC Parameters for a Variable Clock Standard L Units Clock 100 ns 100 ns 95 ns 0 ns 60 ns 90 ns 90 ns 60 ns 60 ns 100 ns 32 ns 70 ns 30 ns 0 ns 30 ns 30 ns 7 4 5 E
13. Error Block Diagram When this feature is enabled the receiver checks each incoming data frame for a valid stop bit An invalid stop bit may result from noise on the serial lines or from simultaneous transmission by two CPUS If a valid stop bit is not found the Framing Error bit FE in SCON register See Table 5 bit is set 12 Rev A Mar 19 1999 Preliminary TS80C31X2 Software may examine FE bit after each reception to check for data errors Once set only software or a reset can clear FE bit Subsequently received frames with valid stop bits cannot clear FE bit When FE feature is enabled RI rises on stop bit instead of the last data bit See Figure 5 and Figure 6 Sup 428 829 628 Gur 652 529 428 S tart Data byte Stop bit bit RI SMOD0 X FE 221 SMODO0 1 Figure 5 UART Timings in Mode 1 RXD Data byte i Stop bit bit bit RI SMOD0 0 RI SMODO0 1 FE SMODO0 1 Figure 6 UART Timings in Modes 2 and 3 6 3 2 Automatic Address Recognition The automatic address recognition feature is enabled when the multiprocessor communication feature is enabled SM2 bit in SCON register is set Implemented in hardware automatic address recognition enhances the multiprocessor communication feature by allowing the serial port to examine the address of each incoming command frame Only when the serial port recognizes its own address the receiver sets RI bit in SCON register to generate an interru
14. ameter T Oscillator clock period ALE pulse width TAVLL Address Valid to ALE Tr LAX Address Hold After ALE Tr Liv ALE to Valid Instruction In ALE to PSEN PSEN Pulse Width PSEN to Valid Instruction In Tpxix Input Instruction Hold After PSEN Tpxiz Input Instruction FloatAfter PSEN TpxAV PSEN to Address Valid TAVIV Address to Valid Instruction In TpLAZ PSEN Low to Address Float Table 17 AC Parameters for Fix Clock Speed M V L Units see ordering Symbol Min Max Min Max Min Max T 25 17 50 ns 40 25 60 ns TAVLL 10 7 20 ns TLLAX 10 7 20 ns 70 45 125 ns Tir 10 7 20 ns 60 45 105 ns 25 25 60 ns Tpxix 0 0 0 ns Tpxiz 18 12 30 ns Tpxav 18 12 30 ns TAVIV 85 53 145 ns 10 10 10 ns Rev A Mar 19 1999 31 Preliminary TS80C31X2 Table 18 AC Parameters for a Variable Clock Symbol Type Standard X2 Clock M V L Units Clock 40 ns 30 ns 30 ns 75 ns 30 ns 45 ns 90 ns 0 ns 20 ns 20 ns 105 ns 10 ns 7 4 3 External Program Memory Read Cycle 12 PSEN LLA 4 Tpxiz TAVLL 5 P XIX SS lt gt gt ADDRESS PORT2 R SFR P2 ADDRESS 8 15 lt ADDRESS A8 A15 Figure 13 External Program Memory Read Cycle 32 Rev A Mar 19 1
15. er Mnemonic Reserved The value read from this bit is indeterminate Do not set this bit Reserved The value read from this bit is indeterminate Do not set this bit Reserved The value read from this bit is indeterminate Do not set this bit Serial port Priority bit 5 gt Refer to PSH for priority level 3 Timer 1 overflow interrupt Priority bit Refer to PT1H for priority level 2 PXI External interrupt 1 Priority bit Refer to PX1H for priority level 1 PTO Timer 0 overflow interrupt Priority bit Refer to PTOH for priority level 0 External interrupt 0 Priority bit Refer to PXOH for priority level Reset Value 0 0000b Bit addressable 20 Rev A Mar 19 1999 Preliminary TS80C31X2 Table 10 IPH Register IPH Interrupt Priority High Register B7h 7 6 5 4 3 2 1 0 PSH PT1H PX1H Description Number Mnemonic Reserved The value read from this bit is indeterminate Do not set this bit Reserved The value read from this bit is indeterminate Do not set this bit Reserved The value read from this bit is indeterminate Do not set this bit Serial port Priority High bit PSH PS Priority Level 0 0 Lowest 4 PSH 0 1 1 0 1 1 Highest Timer 1 overflow interrupt Priority High bit PT1 Priority Level 3 PTIH 0 0 Lowest 0 1 1 0 1 1 Highest External interrupt 1 Priority High bit
16. ernal bus capacitance discharging into the Port 0 and Port 2 pins when these pins make 1 to 0 transitions during bus operation In the worst cases capacitive loading 100 the noise pulse on the ALE line may exceed 0 45V with maxi Vor peak 0 6V A Schmitt Trigger use is not necessary 5 Typicals are based on a limited number of samples and are not guaranteed The values listed are at room temperature and 5V 6 Under steady state non transient conditions must be externally limited as follows Maximum per port pin 10 mA Maximum Io per 8 bit port Port 0 26 mA Ports 1 2 and 3 15 mA Maximum total Ig for all output pins 71 mA If Ioy exceeds the test condition Vor exceed the related specification Pins are not guaranteed to sink current greater than the listed test conditions 7 Forother values please contact your sales office 28 Rev A Mar 19 1999 Preliminary TS80C31X2 All other pins are disconnected Figure 9 Test Condition Active Mode All other pins are disconnected Figure 10 Test Condition Idle Mode All other pins are disconnected Figure 11 Test Condition Power Down Mode Rev A Mar 19 1999 29 Preliminary TS80C31X2 0 45 0 2 0 1 TCHCL Tecuci 515 Figure 12 Clock Signal Waveform for Tests in Active and Idle Modes 7 4 AC Parameters 7 4 1 Explanation of the AC S
17. ions above those indicated in the operational sections of this specification is not implied Exposure to absolute maximum rating conditions may affect device reliability 2 This value is based on the maximum allowable die temperature and the thermal resistance of the package 26 Rev A Mar 19 1999 Preliminary TEMIC POTITI TS80C31X2 7 2 DC Parameters for Standard Voltage 0 C to 70 C Vss 0 V 5 V 10 F 0 to 40 MHz 40 C to 85 Vss 0 V 5 10 F 0 to 40 MHz Table 14 DC Parameters in Standard Voltage TA TA Symbol Parameter i Max Unit Input Low Voltage Input High Voltage except XTAL1 RST 0 2 0 9 Test Conditions Input High Voltage XTAL1 RST 0 7 Output Low Voltage ports 1 2 3 6 Output Low Voltage port 0 ALE PSEN 6 Output High Voltage ports 1 2 3 Output High Voltage port 0 ALE PSEN RST Pulldown Resistor 100 pA 1 6 mA 3 5 mA 200 pa 23 2 mA 7 0 mA 10 uA 30 uA 60 uA Vec 5 V 10 200 3 2 7 0 mA Vec 5 V 10 Power Supply Current 0 Freq 1 MHz Icc op Icc idle Freq 6 MHz Icc op Icc idle Freq 2 12 MHz Icc op 1 25 Freq MHz 5 mA 13 12 MHz 16 16MHz 5 5 12Mz 7016 MHz Icc idle 0 36 Freq MHz 2 7 mA Rev A Mar 19 1999 Preliminary 27 TS80C31X2 7 3 DC Parameters fo
18. is invoked by driving certain pins of the TS80C31X2 the following sequence must be exercised Pull ALE low while the device is in reset RST high and PSEN is high e Hold ALE low as RST is deactivated While the TS80C31X2 is in ONCE mode an emulator or test CPU can be used to drive the circuit Table 26 shows the status of the port pins during ONCE mode Normal operation is restored when normal reset is applied Table 12 External Pin Status during ONCE Mode ALE PSEN Port 0 Port 1 Port 2 Port 3 XTAL1 2 Weak pull up Weak pull up Float Weak pull up Weak pull up Weak pull up Active 24 Rev A Mar 19 1999 Preliminary TS80C31X2 6 8 Power Off Flag The power off flag allows the user to distinguish between a cold start reset and a warm start reset A cold start reset is the one induced by switch on A warm start reset occurs while is still applied to the device and could be generated for example by an exit from power down The power off flag POF is located in PCON register See Table 13 POF is set by hardware when rises from 0 to its nominal voltage The POF can be set or cleared by software allowing the user to determine the type of reset Table 13 PCON Register PCON Power Control Register 87h 7 6 5 4 3 2 1 0 SMOD1 SMOD0 POF 1 IDL p ie Description Number Mnemonic Serial port Mode bit 1 7 SMODI Set to select double baud rate i
19. l other functions are inoperative e Interrupt Structure with e 5 Interrupt sources e 4 priority level interrupt system Full duplex Enhanced UART e Framing error detection e Automatic address recognition Power Control modes e Idle mode Power down mode Power off Flag Once mode On chip Emulation Power supply 4 5 5 5V 2 7 5 5V Temperature ranges Commercial 0 to 70 C and Industrial 40 to 85 C Packages PDIL40 PLCC44 VQFP44 1 4 PQFP F1 13 9 footprint Preliminary TS80C31X2 c mn 3 Block Diagram XTALI XTAL2 p 98 1 Alternate function of Port 3 Rev A Mar 19 1999 Preliminary TEMIC 6 r 4 SFR Mapping The Special Function Registers SFRs of the TS80C31X2 fall into the following categories C51 core registers DPH PSW SP AUXRI I O port registers PO P1 P2 Timer registers TCON THO TMOD TLO TL1 Serial I O port registers SADDR SADEN SBUF SCON Interrupt system registers IE IP IPH Others CKCON Power and clock control registers PCON TS80C31X2 Table 1 All SFRs with their address and their reset value Bit Non Bit addressable address able 0 8 1 9 2 3 B AIC 5 6 E F8h FFh FOh B F7h 0000 00
20. lag bits When Idle is terminated by an interrupt the interrupt service routine can examine the flag bits The over way of terminating the Idle mode is with a hardware reset Since the clock oscillator is still running the hardware reset needs to be held active for only two machine cycles 24 oscillator periods to complete the reset 6 6 Power Down Mode To save maximum power a power down mode can be invoked by software Refer to Table 6 PCON register In power down mode the oscillator is stopped and the instruction that invoked power down mode is the last instruction executed The internal RAM and SFRs retain their value until the power down mode is terminated Vcc can be lowered to save further power Either a hardware reset or an external interrupt can cause an exit from power down To properly terminate power down the reset or external interrupt should not be executed before is restored to its normal operating level and must be held active long enough for the oscillator to restart and stabilize Only external interrupts INTO and INTI are useful to exit from power down For that interrupt must be enabled and configured as level or edge sensitive interrupt input Holding the pin low restarts the oscillator but bringing the pin high completes the exit as detailed in Figure 8 When both interrupts are enabled the oscillator restarts as soon as one of the two inputs is held low and power down exit will be completed when the first inpu
21. late the DPS bit in the AUXR1 SFR However note that the INC instruction does not directly force the DPS bit to a particular state but simply toggles it In simple routines such as the block move example only the fact that DPS is toggled in the proper sequence matters not its actual value In other words the block move routine works the same whether DPS is 0 or 1 on entry Observe that without the last instruction INC AUXR1 the routine will exit with DPS in the opposite state Rev A Mar 19 1999 Preliminary 11 TS80C31X2 6 3 TS80C31X2 Serial I O Port The serial I O port in the TS80C31X2 is compatible with the serial I O port in the 80C31 It provides both synchronous and asynchronous communication modes It operates as an Universal Asynchronous Receiver and Transmitter UART in three full duplex modes Modes 1 2 and 3 Asynchronous transmission and reception can occur simultaneously and at different baud rates Serial I O port includes the following enhancements Framing error detection Automatic address recognition 6 3 1 Framing Error Detection Framing bit error detection is provided for the three asynchronous modes modes 1 2 and 3 To enable the framing bit error detection feature set SMODO bit in PCON register See Figure 4 SCON 98h Set FE bit if stop bit is 0 framing error SMOD 1 9 SMO to UART mode control SMOD 0 To UART framing error control Figure 4 Framing
22. lays are approximately 50 The other signals are typically 85 ns Propagation delays are incorporated in the AC specifications Rev A Mar 19 1999 39 Preliminary TS80C31X2 8 Ordering Information TS 80C31X2 M B R z T VCC 5V 10 Packages 40 MHz standard mode A PDIL 40 20 MHz X2 mode B PLCC 44 V VCC 5V 10 C FI 13 9 mm footprint 40 MHz standard mode E VQFP 44 1 4mm 30 MHz X2 mode L VCC 2 7 to 5 5 V 30 MHz standard mode 20 MHz X2 mode Conditioning R Tape amp Reel D Dry Pack B Tape amp Reel and Temperature Range Dry Pack C Commercial 0 to 70 C TEMIC Semiconductors I Industrial 40 to 85 C Table 26 Maximum Clock Frequency Code V L Unit Standard Mode oscillator frequency 40 40 30 MHz Standard Mode internal frequency 40 40 30 X2 Mode oscillator frequency X2 Mode internal equivalent frequency 40 Rev A Mar 19 1999 Preliminary
23. n access to external memory In normal operation ALE is emitted at a constant rate of 1 6 1 3 in X2 mode the oscillator frequency and can be used for external timing or clocking Note that one ALE pulse is skipped during each access to external data memory PSEN 29 32 26 Program Store ENable The read strobe to external program memory When executing code from the external program memory PSEN is activated twice each machine cycle except that two PSEN activations are skipped during each access to external data memory PSEN is not activated during fetches from internal program memory EA 31 35 29 External Access Enable EA must be externally held low to enable the device to fetch code from external program memory locations XTALI 19 21 15 I Crystal 1 Input to the inverting oscillator amplifier and input to the internal clock generator circuits XTAL2 18 20 14 Crystal 2 Output from the inverting oscillator amplifier Rev A Mar 19 1999 5 Preliminary TS80C31X2 6 TS80C31X2 Enhanced Features In comparison to the original 80C31 the TS80C31X2 implements some new features which are e The X2 option e The Dual Data Pointer e The 4 level interrupt priority system e The power off flag e The ONCE mode e Enhanced UART 6 1 X2 Feature TS80C31X2 core needs only 6 clock periods per machine cycle This feature called 2 provides the following advantage
24. n mode 1 2 or 3 Serial port Mode bit 0 Clear to select SMO bit in SCON register Set to to select FE bit in SCON register Reserved The value read from this bit is indeterminate Do not set this bit Power Off Flag Clear to recognize next reset type Set by hardware when rises from 0 to its nominal voltage Can also be set by software General purpose Flag Cleared by user for general purpose usage Set by user for general purpose usage General purpose Flag 2 GFO Cleared by user for general purpose usage Set by user for general purpose usage Power Down mode bit 1 PD Cleared by hardware when reset occurs Set to enter power down mode Idle mode bit 0 IDL Clear by hardware when interrupt or reset occurs Set to enter idle mode Reset Value 00X1 0000b Not bit addressable Rev A Mar 19 1999 25 Preliminary TS80C31X2 7 Electrical Characteristics 7 1 Absolute Maximum Ratings Ambiant Temperature Under Bias C commercial I industrial Storage Temperature Voltage on to Vss Voltage on Any Pin to Vss Power Dissipation NOTES TEMIC m hc n sr s 0 C to 70 C 40 C to 85 C 65 C to 150 C 0 5 V 0 7 0 5 V to Vcc 0 5 V 1 wO 1 Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the device This is a stress rating only and functional operation of the device at these or any other condit
25. polling sequence Table 8 IE Register IE Interrupt Enable Register A8h 7 6 5 4 3 2 1 0 EA ES EX1 ETO EX0 Bit Bit Description Number Mnemonic Enable All interrupt bit Clear to disable all interrupts Set to enable all interrupts If EA 1 each interrupt source is individually enabled or disabled by setting or clearing its own interrupt enable bit Reserved The value read from this bit is indeterminate Do not set this bit 5 Reserved 7 The value read from this bit is indeterminate Do not set this bit Serial port Enable bit 4 ES Clear to disable serial port interrupt Set to enable serial port interrupt Timer 1 overflow interrupt Enable bit 3 ET1 Clear to disable timer 1 overflow interrupt Set to enable timer 1 overflow interrupt External interrupt 1 Enable bit 2 EX1 Clear to disable external interrupt 1 Set to enable external interrupt 1 Timer 0 overflow interrupt Enable bit 1 ETO Clear to disable timer 0 overflow interrupt Set to enable timer 0 overflow interrupt External interrupt 0 Enable bit 0 Clear to disable external interrupt 0 Set to enable external interrupt 0 Reset Value 0 0 0000b Bit addressable Table 9 IP Register Rev A Mar 19 1999 19 Preliminary TS80C31X2 IP Interrupt Priority Register B8h 7 6 5 4 3 2 1 0 1 1 5 PT1 1 PTO Bit Bit Description Numb
26. pt This ensures that the CPU is not interrupted by command frames addressed to other devices If desired you may enable the automatic address recognition feature in mode 1 In this configuration the stop bit takes the place of the ninth data bit Bit RI is set only when the received command frame address matches the device s address and is terminated by a valid stop bit To support automatic address recognition a device is identified by a given address and a broadcast address NOTE The multiprocessor communication and automatic address recognition features cannot be enabled in mode 0 i e setting SM2 bit in SCON register in mode 0 has no effect Rev A Mar 19 1999 13 Preliminary TS80C31X2 6 3 3 Given Address Each device has an individual address that is specified in SADDR register the SADEN register is a mask byte that contains don t care bits defined by zeros to form the device s given address The don t care bits provide the flexibility to address one or more slaves at a time The following example illustrates how a given address is formed To address a device by its individual address the SADEN mask byte must be 1111 11116 For example SADDR 0101 0110b SADEN 1111 1100b Given 0101 01 The following is an example of how to use given addresses to address different slaves Slave A SADDR 1111 00015 SADEN 1111 1010b Given 1111 OXOXb Slave B SADDR 1111 0011b SADEN 1111
27. r Low Voltage 0 C to 70 Vss 0 V 2 7 V to 5 5 V 10 0 to 30 MHz TA 40 C to 85 C Vss 0 V 2 7 V to 5 5 V 10 F 0 to 30 MHz Table 15 DC Parameters for Low Voltage Parameter i Max Unit Test Conditions Input Low Voltage Input High Voltage except XTAL1 RST 0 2 0 9 Input High Voltage XTAL1 RST 0 7 0 8 1 6 10 40 nA Vin 0 45 0 45 lt Vin lt Vinz2 0V 1 MHz TA 25 2 0 V to 5 5 VO Power Supply Current 0 Active Mode 16MHz 3 3 VO Idle Mode 16MHz Veco 3 3 NOTES 1 Operating Icc is measured with all output pins disconnected XTALI driven with Terca 5 ns see Figure 12 Viz Vss 0 5 V Vin 0 5V XTAL2 N C EA RST Port 0 would be slightly higher if a crystal oscillator used 2 Idle 1 is measured with all output pins disconnected XTALI driven with Terca Tcuct 5 ns Vss 0 5 V Vcc 0 5 V XTAL2 N C Port 0 Vcc EA RST Vss see Figure 10 3 Power Down is measured with all output pins disconnected EA Vss PORT 0 XTAL2 NC RST see Figure 11 4 Capacitance loading on Ports 0 and 2 may cause spurious noise pulses to be superimposed on the Vors of ALE and Ports 1 and 3 The noise is due to ext
28. rt 2 emits the high order address byte during fetches from external program memory and during accesses to external data memory that use 16 bit addresses MOVX DPTR In this application it uses strong internal pull ups emitting 1s During accesses to external data memory that use 8 bit addresses MOVX Ri port 2 emits the contents of the P2 SFR P3 0 P3 7 10 17 11 5 Port 3 Port 3 is 8 bit bidirectional I O port with internal pull ups Port 3 13 19 7 13 pins that have 18 written to them are pulled high by the internal pull ups and can be used as inputs As inputs Port 3 pins that are externally pulled low will source current because of the internal pull ups Port 3 also serves the special features of the 80C51 family as listed below 10 11 5 I RXD P3 0 Serial input port 11 13 7 O TXD P3 1 Serial output port 12 14 8 I INTO P3 2 External interrupt 0 13 15 9 I INTI P3 3 External interrupt 1 14 16 10 I TO P3 4 Timer 0 external input 15 17 11 I P3 5 Timer 1 external input 16 18 12 WR P3 6 External data memory write strobe 17 19 13 RD 3 7 External data memory read strobe Reset 9 10 4 I Reset A high on this pin for two machine cycles while the oscillator is running resets the device An internal diffused resistor to Vss permits a power on reset using only an external capacitor to ALE 30 33 27 I Address Latch Enable Output pulse for latching the low byte of the address during a
29. s Divide frequency crystals by 2 cheaper crystals while keeping same CPU power Save power consumption while keeping same CPU power oscillator power saving Save power consumption by dividing dynamically operating frequency by 2 in operating and idle modes Increase CPU power by 2 while keeping same crystal frequency In order to keep the original C51 compatibility a divider by 2 is inserted between the signal and the main clock input of the core phase generator This divider may be disabled by software 6 1 1 Description The clock for the whole circuit and peripheral is first divided by two before being used by the CPU core and peripherals This allows any cyclic ratio to be accepted on XTALI input In X2 mode as this divider is bypassed the signals on XTAL1 must have a cyclic ratio between 40 to 60 Figure 1 shows the clock generation block diagram X2 bit is validated on XTAL 1 2 rising edge to avoid glitches when switching from X2 to STD mode Figure 2 shows the mode switching waveforms XTAL1 2 FxTAL state machine 6 clock cycles CPU control Fosc CKCON reg Figure 1 Clock Generation Diagram 6 Rev A Mar 19 1999 Preliminary TS80C31X2 X2 bit I TU mim I I STD Mode gt lt X2 Mode gt lt STD Mode Figure 2 Mode Switching Waveforms The X2 bit in the CKCON register See Table 3 allows to switch from
30. t is indeterminate Do not set this bit Reserved The value read from this bit is indeterminate Do not set this bit Data Pointer Selection 0 DPS Clear to select DPTRO Set to select DPTRI Reset Value XXXX Not bit addressable Application Software can take advantage of the additional data pointers to both increase speed and reduce code size for example block operations copy compare search are well served by using one data pointer as source pointer and the other one as a destination pointer 10 Rev A Mar 19 1999 Preliminary TEMIC 4 14 ASSEMBLY LANGUAGE Block move using dual data pointers Destroys DPTRO DPTRI A PSW note DPS exits opposite of entry state unless an extra INC AUXRI is added 00A2 AUXRI EQU 0A2H 0000 909000MOV DPTR ZSOURCE 0003 05A2 INC AUXRI 0005 904000 MOV DPTR DEST 0008 LOOP 0008 0542 INC AUXRI 0004 MOVX 000BA3 INC DPTR 000C 05A2 INC AUXRI 000E FO MOVX DPTR A DPTR 0010 70 6 JNZ LOOP 0012 05A2 INC AUXRI address of SOURCE switch data pointers address of DEST switch data pointers get a byte from SOURCE increment SOURCE address switch data pointers write the byte to DEST increment DEST address check for 0 terminator optional restore DPS TS80C31X2 INC is a short 2 bytes and fast 12 clocks way to manipu
31. t will be released In this case the higher priority interrupt service routine is executed Once the interrupt is serviced the next instruction to be executed after RETI will be the one following the instruction that put TS80C31X2 into power down mode I I Active phase ______le Power down phase gt lt Oscillator restart phase 4 Active phase Figure 8 Power Down Exit Waveform Exit from power down by reset redefines all the SFRs exit from power down by external interrupt does no affect the SFRs Exit from power down by either reset or external interrupt does not affect the internal RAM content NOTE If idle mode is activated with power down mode IDL and PD bits set the exit sequence is unchanged when execution is vectored to interrupt PD and IDL bits are cleared and idle mode is not entered 22 Rev A Mar 19 1999 Preliminary TEMIC Table 11 The state of ports during idle and power down modes TS80C31X2 Mode Program ALE PSEN PORTO 2 Idle External 1 1 Floating Port Data Address Port Data Power Down External 0 0 Floating Port Data Port Data Port Data Rev A Mar 19 1999 Preliminary 23 TS80C31X2 6 7 ONCE Mode ON Chip Emulation The ONCE mode facilitates testing and debugging of systems using TS80C31X2 without removing the circuit from the board The ONCE mode
32. to XTAL2 divided by two INTERNAL STATE4 STATES STATE6 STATE STATE2 STATE3 STATE4 STATES CLOCK ev vo pi pn vi 22 pi re n pi xa J UOU UO ALE THESE SIGNALS ARE NOT ACTIVATED DURING THE EXTERNAL PROGRAM MEMORY FETCH EXECUTION OF A MOVX INSTRUCTION PSEN PO DATA PCL OUT DATA PCL OUT DATA PCL OUT SAMPLED SAMPLED SAMPLED FLOAT zl Me o s 7 A WDIWESADDRESTRANSHONS READ CYCLE RD PCL OUT IF PROGRAM MEMORY IS EXTERNAL PO DPL OR Rt OUT Y le l P2 INDICATES DPH OR P2 SFR TO PCH TRANSITION WRITE CYCLE WR PCL OUT EVEN IF PROGRAM MEMORY IS INTERNAL PO DPL OR Rt OUT Jar OUT PCL OUT IF PROGRAM MEMORY IS EXTERNAL 2 INDICATES DPH OR P2 SFR TO PCH TRANSITION PORT OPERATION OLD DATA NEW DATA PO PINS SAMPLED PO PINS SAMPLED MOV DEST MOV DEST PORT P1 P2 P3 P2 P3 PINS SAMPLED P1 P2 PINS SAMPLED INCLUDES INTO INT1 TO T1 SERIAL PORT SHIFT CLOCK RXD SAMPLED RXD SAMPLED TXD MODE 0 Figure 20 Clock Waveforms This diagram indicates when signals are clocked internally The time it takes the signals to propagate to the pins however ranges from 25 to 125 ns This propagation delay is dependent on variables such as temperature and pin loading Propagation also varies from output to output and component Typically though T 25 C fully loaded RD and WR propagation de
33. veforms al gt ee ALE CLOCK OUTPUT DATA WRITE to SBUF INPUT DATA CLEAR RI Figure 16 Shift Register Timing Waveforms Rev A Mar 19 1999 37 Preliminary TS80C31X2 7 4 9 External Clock Drive Characteristics XTAL1 Table 25 AC Parameters Parameter Min Max Units Oscillator Period 25 ns High Time 5 ns Low Time 5 ns Rise Time 5 ns Fall Time 5 ns Cyclic ratio in X2 mode 40 60 7 4 10 External Clock Drive Waveforms Figure 17 External Clock Drive Waveforms 7 4 11 AC Testing Input Output Waveforms 0 5 0 2 0 9 INPUT OUTPUT 2 02Vcc 0 1 Figure 18 AC Testing Input Output Waveforms AC inputs during testing are driven at Vcc 0 5 for a logic 1 and 0 45V for a logic 0 Timing measurement are made at min for a logic 1 and max for a logic 0 7 4 12 Float Waveforms FLOAT 01 Vo 0 1 V 0 1 V Figure 19 Float Waveforms 38 Rev A Mar 19 1999 Preliminary TS80C31X2 For timing purposes as port pin is no longer floating when a 100 mV change from load voltage occurs and begins to float when 100 mV change from the loaded Voy Voy level occurs gt 20mA 7 4 13 Clock Waveforms Valid in normal clock mode X2 mode XTAL2 signal must be changed
34. xternal Data Memory Write Cycle WR PORT 0 Tayw gt Figure 14 External Data Memory Write Cycle Rev A Mar 19 1999 35 Preliminary TEMIC TS80C31X2 ncc d 7 4 6 External Data Memory Read Cycle Tij py 99 PSEN 4 T 94 TR rF PORT 0 PORT 2 SAA NIN A0 A7 ADDRESS A8 A15 OR SFR P2 ADDRESS OR SFR P2 Figure 15 External Data Memory Read Cycle 7 4 7 Serial Port Timing Shift Register Mode Table 22 Symbol Description TXLXL Symbol Parameter Serial port clock cycle time Output data set up to clock rising edge Output data hold after clock rising edge Input data hold after clock rising edge Clock rising edge to input data valid Table 23 AC Parameters for a Fix Clock 36 Speed M V L Units see ordering Symbol Min Max Min Max Min Max 300 200 600 ns 200 117 367 ns 20 13 50 ns 0 0 0 ns 200 117 367 ns Rev A Mar 19 1999 Preliminary TS80C31X2 Table 24 AC Parameters for a Variable Clock Standard X2 Clock L Units Clock ns 133 ns 50 ns 0 ns 10 5 50 50 133 ns 7 4 8 Shift Register Timing Wa
35. ymbols Each timing symbol has 5 characters The first character is always a T stands for time The other characters depending on their positions stand for the name of a signal or the logical status of that signal The following is a list of all the characters and what they stand for Example TAvy Time for Address Valid to ALE Low Time for ALE Low to PSEN Low 0 to 70 Vss 0 V 5 V 10 M and V ranges 40 C to 85 C Vss 0 V 5 V 1096 M and V ranges 0 to 70 C Vss 0 V 2 7 V lt lt 5 5 V L range 40 C to 85 C Vss 0 V 2 7 V lt lt 5 5 V L range Load Capacitance for port 0 ALE and PSEN 100 pF Load Capacitance for all other outputs 80 pF Table 16 Table 19 and Table 22 give the description of each AC symbols Table 17 Table 20 and Table 23 give for each range the AC parameter Table 18 Table 21 and Table 24 give the frequency derating formula of the AC parameter To calculate each AC symbols take the x value corresponding to the speed grade you need M V or L and replace this value in the formula Example in X2 mode for V part at 25 MHz x 22 T 40ns 2 x 2 x 40 22 5805 30 Rev A Mar 19 1999 Preliminary TS80C31X2 7 4 2 External Program Memory Characteristics Table 16 Symbol Description Symbol Par
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