Home

ANALOG DEVICES AD9601 handbook

1. e anro 3 5 Lis 8 5 an AND MOA q MON amp oza KR ARA 613 el A ALVIS IL ON anro ano res 199 TOULNOD LOA LAGLNO 5 NN L LNdNMVX ans 1691697 WH3QY3H gooa 5 F JOY1NOO_LIOA an AMANIVLX D M Kg 996 AND a wi ooa r NN Ta ist YEISAID 956 CHAD NS je NO nf s AV ba SLINOUID ZOONS WNOLLdO 00 o log a oy oa AN k h Son 188 O r ezo vio oas ha DOE vc aa 5g AN F MN digs dE a ws Sa OND vue sa DE oy fe er AN ana 3 E 3000N3 VHO OS Hoa savano oy E vo 1aso aza er AN z 1 no Phua D ze NO o ji ET AN r w zL Log zvano oy 00 00 279 6 og BEVOND oy e 1 684 ey E SINHO 0S org Savano q E D I ana Ge ITA oravano 0 ft 1 7 TVOIHLINNAS ONIAYOT OLLISYHYd ANY LNOAVI IVN OL 240 Ki za O9ON9 25 Lee z9 4 Lag ONO co fee ar V VT En KEES oi AVN TT Sp ag vasano oo se F asa AN 9 E ea NN 5 or EN 7 Zoo saoano AA SC er NN S 5 aan w 1 B 819 PA 2 er NN y a KE e lag OMD Goat vr NN no ya 1 Kel hea 8000N9 solat 850 et c 3did AAV 8 e 1 SQ Aer S ON E AO 919 or Sr E T Bad dan A T NI o GOONS ZAdid AAV SR su h 93 ano If OL SLOINNOO SHO 05 g Lid ano a aniv qe mo dS9 L096AV Niv 3 Yng 2 dos z asa 5 AND vn Se Sen E3did AAV 64 RG a sa NA Se F 1769169 IWHJ
2. ano an9 82 82 I 3 d 13 e 3 BI ery ano AM AN On osu os 82 82 d D I E a SZ A A ae G 25 1swaws Lino a SONAS i OND A a MOA e NN INN auno 9 2 D om d Std 23 3 ono 6 6 mo BAN ER 1swaws A ES anro Isu 5o Sia 00 22 5 OND VN VW 419A Mo 089 gz 82 N ano ano a 48 anro OND e VN VW EA 32 82 AD eo 8 3 NID 119 1d0 91560V OND NM VW MIDA zs ano VN VW OA 83 83 S 8 AS ano VWM VW MIDA 82 82 SUE el L 1013 Z NIL 8 938 ltd os AND anne P z OND VMV non S A dNYA AM H 2 LNOL ZL LENIL S 2 d ang mes 2160 eeu 198 91607 SLG6AV ger JE Hede sl DIA UND NIA fe 28LNOL ZANIL H o 25 AND Nau y bj D o Eos Y TT 935 Idd SE a7 aa ea LNOdNNY WW NOA male Ist g e 00 00 ou ver Zoo or IZ a eey Se le dou Sr 2 AND LNOdINY T AA AN dOA z LMI LLOV or vi zz se 5 32 Jono dad NOE 0 KENT H NS AND ar DON WA op fan F Di rey 22 38 1SINENS 2 dNA Eld er fh Isi E se eel dien t Ww H P A a an9 ANI H e H IND Shu pa WI INL WO 120 anr 1 dwy euonelado dNYA OND MOL MOL Figure 47 AD9601 Evaluation Board Schematic Page 3 Rev 0 Page 27 of 32 AD9601 R24 1K VSPIEXT SCLK_DTP 8170 00120 CSB_DUT gt VHI OAS ao 8 ra ES 2 A gt VHO Laso S 2 O es O VHO TAS a dp WHO MIS Figure 48 AD960
3. unused 1010 unused 1011 unused 1100 unused Format determined by output mode OF ain_config 0 0 0 0 0 Analog CML 0 0x00 input enable disable 1 on 1 on 0 off 0 off default default 14 output mode 0 0 Interleave Output 0 Output Data format select 0x00 output enable invert 00 offset binary mode 0 1 on default 1 enable 0 off 01 twos enabled default default complement 0 1 10 Gray code disabled disable default 16 output_phase Output 0 0 0 0x03 clock polarity 12 inverted 0 normal default 17 flex_output_delay Output Output clock delay 0x00 delay 00000 0 1 ns enable 00001 0 2 ns 0 00010 0 3 ns enable Ya 1 11101 3 0ns disable 11110 3 1 ns 11111 3 2 ns 18 flex_vref Input voltage range setting 0x00 10000 0 98 V 10001 1 00 V 10010 1 02 V 10011 1 04 V 11111 1 23 V 00000 1 25 V 00001 1 27 V 01110 1 48 V 01111 1 50 V Rev 0 Page 24 of 32 AD9601 EVALUATION BOARD
4. 8 bit chip ID Bits 7 0 Read AD9601 0x36 only Default is unique chip ID different for each device This is a read only register 02 chip_grade 0 0 0 Speed grade 01 200 MSPS only 10 250 MSPS X X X Read Child ID used to differentiate graded devices Transfer Register FF device_update 0 0 0 0 0 0 SW 0x00 Synchronously transfer transfers data from the master shift register to the slave ADC Functions 08 modes 0 0 PDWN 0 0 full default 1 standby Internal power down mode 0x00 Determines 000 normal power up default various generic 001 full power down modes of chip 010 standby operation 011 normal power up Note external PDWN pin overrides this setting Rev 0 Page 23 of 32 AD9601 Default Addr Bit 7 Bit O Value Default Notes Hex Parameter Name MSB Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 LSB Hex Comments 09 clock 0 0 0 0 0 0 0 Duty cycle 0x01 stabilizer 0 disabled 1 enabled default OD test_io Reset Reset Output test mode 0x00 When set the PN23 gen PN9 gen 0000 off default test data is 1 on 1 on 0001 midscale short placed on the 0 off 0 off 0010 FS short output pins in default default 0011 FS short place of normal 0100 checker board output data 0101 PN 23 sequence 0110 PN9 0111 one zero word toggle 1000 unused 1001
5. Data to DCO Skew tskew Full 0 0 3 0 55 0 0 3 0 55 ns Latency Full 6 6 Cycles Output Interleaved Mode Data Propagation Delay tra tros 25 C 3 5 3 5 ns DCO Propagation Delay tcepa tcros 25 C 3 0 3 0 ns Data to DCO Skew tskewa tskews Full 0 0 5 1 1 0 0 5 1 1 ns Latency Full 6 6 Cycles Standby Recovery 25 C 250 250 ns Power Down Recovery 50 50 us Aperture Delay ta 25 C 0 1 0 1 ns Aperture Uncertainty Jitter tu 25 C 0 2 0 2 ps rms 1 See Figure 2 See Figure 3 Rev 0 Page 6 of 32 AD9601 TIMING DIAGRAMS N 2 N 1 terk fesk r 07100 042 Figure 2 Single Port Mode N 1 N 2 terk fek 07100 043 Figure 3 Interleaved Mode Rev 0 Page 7 of 32 AD9601 ABSOLUTE MAXIMUM RATINGS Table 5 Parameter Rating ELECTRICAL AVDD to AGND 0 3 V to 2 0 V DRVDD to DRGND 0 3 V to 2 0 V AGND to DRGND 0 3 V to 0 3 V AVDD to DRVDD 2 0 V to 2 0 V Dx0 Through Dx9 to DRGND DCO DCO to DRGND OVRA OVRB to DGND CLK to AGND CLK to AGND VIN to AGND VIN to AGND SDIO DCS to DGND PDWN to AGND CSB to AGND SCLK DFS to AGND ENVIRONMENTAL Storage Temperature Range Operating Temperature Range Lead Temperature Soldering 10 sec Junction Temperature 0 3 V to DRVDD 0 3 V 0 3 V to DRVDD 0 3 V 0 3 V to DRVDD 0 3 V 0 3 V to 3 6 V 0 3 V to 3 6 V 0 3 V to AVDD 0 2 V 0 3 V to AVDD 0 2 V 0 3 V to DRV
6. Port Mode Duty Cycle Stabilizer Select External Pin Mode 26 SCLK DFS Serial Port Interface Clock Serial Port Mode Data Format Select Pin External Pin Mode 27 CSB Serial Port Chip Select Active Low 29 PWDN Chip Power Down 49 DCO Data Clock Output Complement 50 DCO Data Clock Output True 53 DAO LSB Output Port A Output Bit 0 LSB 54 DA1 Output Port A Output Bit 1 55 DA2 Output Port A Output Bit 2 56 DA3 Output Port A Output Bit 3 1 DA4 Output Port A Output Bit 4 2 DA5 Output Port A Output Bit 5 3 DA6 Output Port A Output Bit 6 Rev 0 Page 9 of 32 AD9601 Pin No Mnemonic Description 4 DA7 Output Port A Output Bit 7 5 DA8 Output Port A Output Bit 8 6 DA9 MSB Output Port A Output Bit 9 MSB 10 11 51 52 NIC Not internally connected 9 OVRA Output Port A Overrange Output Bit 12 DBO LSB Output Port B Output Bit O LSB 13 DB1 Output Port B Output Bit 1 14 DB2 Output Port B Output Bit 2 15 DB3 Output Port B Output Bit 3 16 DB4 Output Port B Output Bit 4 17 DB5 Output Port B Output Bit 5 18 DB6 Output Port B Output Bit 6 19 DB7 Output Port B Output Bit 7 20 DB8 Output Port B Output Bit 8 21 DB9 MSB Output Port B Output Bit 9 MSB 22 OVRB Output Port B Overrange Output Bit 1 AGND and DRGND should be tied to a common quiet ground plane Rev 0 Page 10 of 32 AD9601 EQUIVALENT CIRCUITS AVDD AVDD 26kQ 1kQ CSB Figure 8 Equ
7. in millimeters AD9601 112805 0 ORDERING GUIDE Model Temperature Range Package Description Package Option AD9601BCPZ 200 40 C to 85 C 56 Lead Lead Frame Chip Scale Package LFCSP_VQ CP 56 2 AD9601BCPZ 250 40 C to 85 C 56 Lead Lead Frame Chip Scale Package LFCSP_VQ CP 56 2 AD9601 250EBZ CMOS Evaluation Board with AD9601BCPZ 250 1 Z RoHS Compliant Part Rev 0 Page 31 of 32 AD9601 NOTES 2007 Analog Devices Inc All rights reserved Trademarks and ANALOG registered trademarks are the property of their respective owners D07100 0 11 07 0 DEVICES www analog com Rev 0 Page 32 of 32
8. to avoid performance degradation or loss of functionality Rev 0 Page 8 of 32 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS DA4 DAS DAG DA7 DAB MSB DA9 DRVDD LSB DBO DB1 DB2 53 DAO LSB 56 DA3 55 DA2 54 DA1 43 AVDD O w PIN 1 INDICATOR AD9601 TOP VIEW Not to Scale Do Joo P GAMM 12 13 PIN 0 EXPOSED PADDLE AGND 14 DB3 15 DB4 16 DB5 17 DB6 18 DB7 19 DB8 20 MSB DB9 21 OVRB 22 DRGND 23 DRVDD 24 SDIO DCS 25 SCLKIDFS 26 Figure 4 Pin Configuration Table 7 Single Data Rate Mode Pin Function Descriptions CSB 27 RESET 28 AVDD AVDD CML AVDD AVDD AVDD VIN VIN AVDD AVDD AVDD RBIAS AVDD PWDN 07100 002 AD9601 Pin No Mnemonic Description 30 32 33 34 37 38 39 AVDD 1 8 V Analog Supply 41 42 43 46 7 24 47 DRVDD 1 8 V Digital Output Supply 0 AGND Analog Ground 8 23 48 DRGND Digital Output Ground 35 VIN Analog Input True 36 VIN Analog Input Complement 40 CML Common Mode Output Pin Enabled through the SPI this pin provides a reference for the optimized internal bias voltage for VIN VIN 44 CLK Clock Input True 45 CLK Clock Input Complement 31 RBIAS Set Pin for Chip Bias Current Place 1 10 kQ resistor terminated to ground Nominally 0 5 V 28 RESET CMOS Compatible Chip Reset Active Low 25 SDIO DCS Serial Port Interface SPI Data Input Output Serial
9. 0 For the specifications provided in Table 2 the fs 2 spur effect is not a factor as the device is specified in single port output mode Rev 0 Page 19 of 32 AD9601 LAYOUT CONSIDERATIONS POWER AND GROUND RECOMMENDATIONS When connecting power to the AD9601 it is recommended that two separate supplies be used one for analog AVDD 1 8 V nominal and one for digital DRVDD 1 8 V nominal If only a single 1 8 V supply is available it is routed to AVDD first then tapped off and isolated with a ferrite bead or filter choke with decoupling capacitors proceeding connection to DRVDD The user can employ several different decoupling capacitors to cover both high and low frequencies These should be located close to the point of entry at the PC board level and close to the parts with minimal trace length A single PC board ground plane is sufficient when using the AD9601 With proper decoupling and smart partitioning of analog digital and clock sections of the PC board optimum performance is easily achieved Exposed Paddle Thermal Heat Slug Recommendations It is required that the exposed paddle on the underside of the ADC be connected to analog ground AGND to achieve the best electrical and thermal performance of the AD9601 An exposed continuous copper plane on the PCB should mate to the AD9601 exposed paddle Pin 0 The copper plane should have several vias to achieve the lowest possible resistive thermal path for heat dissipa
10. 000TRF 1 R2 603 Resistor 499 Q 0603 1 10 W 1 NIC Components NRCO6F4990TRF Rev 0 Page 28 of 32 AD9601 Reference Qty Designator Package Description Vendor Part Number 2 R5 R6 402 Resistor 36 O 0402 1 16 W 1 Panasonic ERJ 2GEJ360X 2 R7 R16 402 Resistor 15 Q 0402 1 16 W 5 Panasonic ERJ 2RKF15ROX 6 R10 R11 R13 402 Resistor 1 kQ 0402 1 16 W 1 NIC Components NRCO4F1001TRF R24 R25 R27 4 R12 R18 R19 402 Resistor 10 kQ 0402 1 16 W 5 NIC Components NRCO4J103TRF R26 7 R15 C16 C18 402 Resistor 0 Q 0402 1 16 W 5 NIC Components NRCO4ZOTRF C19 C20 R89 R90 4 RN1 RN2 RN3 0402x8 Resistor array SMT 0402 0 Q 1 4 W 5 Panasonic EXB2HVO50JV RN4 RESNEXB 2HV 3 L1 L8 L9 603 Resistor 0 Q 0603 1 10 W 5 NIC Components NRCO6ZOTRF 1 P9 P10 805 Resistor 0 Q 0805 1 8 W 1 NIC Components NRC10ZOTRF SW3 EVQ Switch light touch SMD Panasonic P12937SCT ND Q2F03W 1 T1 2020 Ferrite bead 5 A 50 V 190 Q 100 MHz Murata DLW5BSN191SQ2L 2 T2 T3 CD542 Transformer 0 5 W 30 mA Mini Circuits ADT1 1WT 1 U3 6 SC70 IC buffer inverter UHS dual SC70 6 Fairchild NC7WZ16P6X 1 U5 6 SC70 IC buffer inverter UHS dual OD out SC70 6 Fairchild NC7WZ07P6X 1 U7 DO 214AA Diode 50 V 2 A Micro Commercial S2A TPMSTR ND 1 U8 DO 214AB Diode 30 V 3 A SMC Micro Commercial SK33 TPMSCT ND 1 U11 SOT 223 Voltage regulator 3 3 V 1 5 A Analog Devices ADP3339AKCZ 3 3 2 U9 U12 SOT 223 Voltage re
11. 1 Evaluation Board Schematic Page 4 Table 13 Bill of Materials Reference Qty Designator Package Description Vendor Part Number 1 PCB PCB AD9230 customer evaluation board Rev G Moog AD9230revG 7 C1 C3 C4 C5 603 Capacitor 1 uF 0603 X5R ceramic 6 3 V 10 Panasonic ECJ 1VB0J105K C6 C7 C10 6 C8 C9 C11 6032 28 Capacitor 10 uF tantalum 16 V 10 Kemet T491C106KO16AS C12 C14 C55 C17 402 Capacitor 2 0 pF 50 V ceramic 0402 SMD Murata GRM1555C1H2R0GZ01D 7 C27 C32 C33 402 Capacitor 0 33 UF ceramic X5R 10 V 10 Murata GRM155R61A334KE15D C62 C63 C64 C71 6 C28 C29 C30 402 Capacitor 120 pF ceramic COG 25 V 5 Murata GRM1555C1H121JA01J C31 C65 C70 10 C21 C22 C23 402 Capacitor 0 1 uF ceramic X5R 10 V 10 Murata GRM155R71C104KA88D C24 C25 C26 C34 C35 C36 C39 1 CR4 603 LED green SMT 0603 SS TYPE Panasonic LNJ314G8TRA 1 CR2 Mini 3P Diode 30 V 20 mA Agilent HSMS2812 1 F1 1210 Fuse 6 0 V 2 2 A trip current resettable fuse Tyco Raychem NANOSMDC110F 2 15 E1 E2 E3 E4 Connector header 0 1 Samtec TSW 150 08 G S E5 E7 E8 E9 E10 E12 E13 E14 E31 E32 E33 2 J2 J3 SMA end Connector SMA PCB coax end launch Johnson Johnson 142 0701 851 launch 142 10 L2 L3 L4 L5 1206 Ferrite bead BLM 3 A 50 Q 100 MHz Murata BLM31PG500SN1L L7 L12 L13 L14 L15 R88 1 P8 Power jack male 2 1 mm power jack dc CUI Inc CP 102A ND 1 R1 201 Resistor 100 Q 0201 1 20 W 1 NIC Components NRCO2F1
12. 100 009 Figure 34 Differential Transformer Coupled Configuration As an alternative to using a transformer coupled input at frequencies in the second Nyquist zone the AD8352 differential driver can be used see Figure 35 Vee o ANALOG INPUT O VIN AD9601 K VIN CML ANALOG INPUT Q 00 RI 0 1pF y Figure 35 Differential Input Configuration Using the AD8352 07100 010 Rev 0 Page 16 of 32 CLOCK INPUT CONSIDERATIONS For optimum performance the AD9601 sample clock inputs CLK and CLK should be clocked with a differential signal This signal is typically ac coupled into the CLK pin and the CLK pin via a transformer or capacitors These pins are biased internally and require no additional bias Figure 36 shows one preferred method for clocking the AD9601 The low jitter clock source is converted from single ended to differential using an RF transformer The back to back Schottky diodes across the secondary transformer limit clock excursions into the AD9601 to approximately 0 8 V p p differential This helps prevent the large voltage swings of the clock from feeding through to other portions of the AD9601 and preserves the fast rise and fall times of the signal which are critical to low jitter performance MINI CIRCUITS ADTI AWT 1 12 0 1uF WI CLOCK XFMR INPUT 500 1000 TT 0 1uF SCHOTTKY DIODES 3 HSM2812 E Figure 36 Transformer Coupled Differential Clock If a low jitter cl
13. 200MSPS 170 3MHz 1 0dBFS 80 SFDR dBFS SNR 59 35dB ENOB 9 7 BITS SFDR 83dBe 70 5 _ 60 S a SNR dBFS u x 50 g 2 2 2 40 z z SFDR dBc lt 30 20 SNR dB 10 y 0 1g 8 90 80 70 6 50 40 30 2 10 oi FREQUENCY MHz E AMPLITUDE dBFS 5 Figure 13 AD9601 200 64k Point Single Tone FFT 200 MSPS 170 3 MHz Figure 16 AD9601 200 SNR SFDR vs Input Amplitude 170 3 MHz Rev 0 Page 12 of 32 INL LSB CURRENT mA DNL LSB o 400 350 Figure 17 AD9601 200 INL 200 MSPS 384 512 640 OUTPUT CODE 768 896 1024 TOTAL POWER mW lavop MA Ipvop MA 5 25 45 65 SAMPLE RATE MSPS 85 105 125 145 165 185 205 225 245 Figure 18 AD9601 200 Power Supply Current vs Sample Rate 1 0 o 128 Figure 19 AD9601 200 DNL 200 MSPS 256 384 512 640 OUTPUT CODE 768 896 1024 07100 026 SNR SFDR dB SFDR 25 C AD9601 5 C SFDR 40 C 0 50 100 150 200 NR 25 C T SNR 40 C 300 350 400 450 500 ANALOG INPUT FREQUENCY MHz 07100 029 Figure 20 SNR SFDR vs Analog Input Frequency Interleaved Mode vs 07100 027 AMPLITUDE dBFS Temperature 250MSPS 10 3MHz 1 0dBFS SNR 59 4dB ENOB 9 7 BITS SFDR 84dBc FREQUENCY MHz 07100 030 Figure 21 AD9601 250 64k Point Single Tone F
14. 402 Resistor 5 Q NIC Components NRCO4J5R1TRF 0 R58 R59 402 Resistor 100 Q NIC Components NRCO4F1000TRF 0 R60 R61 402 Resistor 240 A NIC Components NRC04J241TRF 0 R8 R9 R17 402 Resistor 0 Q NIC Components NRCO4ZOTRF R36 R40 R41 R44 R46 R47 R87 R50 R51 R52 R53 R55 R56 R57 R62 R63 R64 R65 R66 R67 R68 R69 R70 R71 R72 R73 R74 R75 R76 R77 R78 R79 R80 R81 R82 R83 R84 0 P1 P2 P16 P17 805 Resistor 00 NIC Components NRC10ZOTRF 0 SW1 EVQ Switch light touch SMD Panasonic P12937SCT ND Q2F03W 0 T4 Transformer RF 0 4 MHz to 800 MHz SMD case Mini Circuits ADT1 1WT style CD542 0 T5 T6 sm 22 Balun M A Com MABA007159 0000 0 U2 SOIC 8 PIC12F629 Microchip Tech PIC12F629 1 SN 0 U6 Crystal Cvhd_956 crystal CVHD_956 0 U10 SOT 223 Regulator ADP3339AKCZ 5 0 0 Z1 16CSP4X4 AD8352 0 U1 16CSP8X8 AD9515 0 P6 8 pin power connector post Wieland Z5 530 0825 0 0 P6 8 pin power connector top Wieland 25 602 2853 0 Rev 0 Page 30 of 32 OUTLINE DIMENSIONS 0 3 oo INDICATOR TOP VIEW 0 3 0 60 MAX lt 0 2 0 1 43 42 PIN 1 INDICATOR EXPOSED PAD BOTTOM VIEW HARAM gt k 0 50 BSC 0 80 MAX 0 65 TYP 0 30 MIN Sen 0 02 NOM COPLANARITY 0 20 REF 0 08 COMPLIANT TO JEDEC STANDARDS MO 220 VLLD 2 Figure 49 56 Lead Lead Frame Chip Scale Package LFCSP_VQ 8 mm x 8 mm Body Very Thin Quad CP 56 2 Dimensions shown
15. A or Port B The user cannot control the polarity of the output data clock relative to the input sample clock In this mode it is recom mended to use the rising edge of DCO to capture the data from Port A and the rising edge of DCO to capture the data from Port B In both cases the setup and hold time depends on the input sample clock period and both are approximately 2 fs tsxew fs 2 Spurious Because the AD9601 output data rate is at one half the sampling frequency in interleaved output mode there is significant fs 2 energy in the outputs of the part and there is significant energy in the ADC output spectrum at fs 2 Care must be taken to be certain that this fs 2 energy does not couple into either the clock circuit or the analog inputs of the AD9601 When fs 2 energy is coupled in this fashion it appears as a spurious tone reflected around fs 4 3fs 4 5fs 4 and so on For example in a 125 MSPS sampling application with a 90 MHz single tone analog input this energy generates a tone at 97 5 MHz 3 x 125 MSPS 4 90 MHz 3 x 125 MSPS 4 Depending on the relationship of the IF frequency to the center of the Nyquist zone this spurious tone may or may not be in the user s band of interest Some residual fs 2 energy is present in the AD9601 and the level of this spur is typically below the level of the harmonics at clock rates Figure 20 shows a plot of the fs 2 spur level vs the analog input frequency for the AD9601 25
16. ANALOG DEVICES 10 Bit 200 MSPS 250 MSPS 1 8 V Analog to Digital Converter AD9601 FEATURES SNR 59 4 dBFS fin up to 70 MHz 250 MSPS ENOB of 9 7 fin up to 70 MHz 250 MSPS 1 0 dBFS SFDR 81 dBc fin up to 70 MHz 250 MSPS 1 0 dBFS Excellent linearity DNL 0 2 LSB typical INL 0 2 LSB typical CMOS outputs Single data port at up to 250 MHz Demultiplexed dual port at up to 2 x 125 MHz 700 MHz full power analog bandwidth On chip reference no external decoupling required Integrated input buffer and track and hold Low power dissipation 274 mW 200 MSPS 322 mW 250 MSPS Programmable input voltage range 1 0V to 1 5 V 1 25 V nominal 1 8 V analog and digital supply operation Selectable output data format offset binary twos complement Gray code Clock duty cycle stabilizer Integrated data capture clock GENERAL DESCRIPTION The AD9601 is a 10 bit monolithic sampling analog to digital converter optimized for high performance low power and ease of use The product operates at up to a 250 MSPS conversion rate and is optimized for outstanding dynamic performance in wideband carrier and broadband systems All necessary func tions including a track and hold T H and voltage reference are included on the chip to provide a complete signal conversion solution The ADC requires a 1 8 V analog voltage supply and a differen tial clock for full performance operation The digital outputs are CMOS compatible and suppo
17. AVIH aza AN 5 Walle CON a090 uf g w 094 za NN SAdid GGAV ae 1NOdNY 610 zi E a Y vu afz avano 64 Sviau 935 Idd ano za J asa er y ag ALNOL y ye BN Hi ZVCN es AN g a g A38 any e ano wo Ea WI 4 Di 22 Nad 963 VE ONG YA TT SES H ka 4 er AN z 5 5 E aaen 3 fash M AND LMI LLOV indu aea psa YA 9L AN 1 Z0 ON3 RR Si 4 asa og OM sa suondo away 1 ENH aza ra SVR za KLB E mana DOTVNV asa feg Havana ca EMS 4 atia Heg Sevano La 86d NN 5 Geer 018 ow 6a r NN 7 an9 zal le ano CY Whig OH VOND y gold AN 3 Edo og gt n ra ana 1 E s IdSA za zo org S IdSA ol 4 Die TE po aua y AN 7 m8 Eon 1 org ela goa rg 000m9 vo E oq Ha ven E sr y yaana aza sa so za a400 er AN z 8 8 wa rn oa NAY 38 i agg fra 9999N9 75 ga g g 6d FOND Id DON asa Shaq 0909 go lE gq WHO 05 p Old OND za OG ano er y Padang 1 INU _ 91d OND d OND gold z sa 89 Tes 010 4 lea LINT eso Lid E an9 td ND awoa ora 8090N9 919 JE HOO aso ozea sd G an Je ISA GOONS ee zr OL SLOINNOO Ld AND Figure 45 AD9601 Evaluation Board Schematic Page 1 Rev 0 Page 25 of 32 AD9601 AVDD Figure 46 AD9601 Evaluation Board Schematic Page 2 Rev 0 Page 26 of 32 2d001 940 001L0 anro ao A ezo 999 anro Ee e B A8 259 o anro ren
18. All data is composed of 8 bit words The first bit of each individual byte of serial data indicates whether this is a read or write command This allows the serial data input output SDIO pin to change direction from an input to an output Data can be sent in MSB or in LSB first mode MSB first is default on power up and can be changed by changing the configuration register For more information about this feature and others see Interfacing to High Speed ADCs via SPI at www analog com Rev 0 Page 20 of 32 HARDWARE INTERFACE The pins described in Table 8 comprise the physical interface between the users programming device and the serial port of the AD9601 All serial pins are inputs which is an open drain output and should be tied to an external pull up or pull down resistor suggested value of 10 kQ This interface is flexible enough to be controlled by either PROMS or PIC microcontrollers as well This provides the user with an alternate method to program the ADC other than a SPI controller If the user chooses not to use the SPI interface some pins serve a dual function and are associated with a specific function when strapped externally to AVDD or ground during device power on The Configuration Without the SPI section describes the strappable functions supported on the AD9601 tos ty e tek CSB SCLK DON T CARE SDIO DON T CARE AD9601 CONFIGURATION WITHOUT THE SPI In applications that do no
19. DD 0 3 V 0 3 V to 3 6 V 0 3 V to 3 6 V 0 3 V to 3 6 V 65 C to 125 C 40 C to 85 C 300 C 150 C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device This is a stress rating only functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied Exposure to absolute maximum rating conditions for extended periods may affect device reliability THERMAL RESISTANCE The exposed paddle must be soldered to the ground plane for the LFCSP package Soldering the exposed paddle to the customer board increases the reliability of the solder joints maximizing the thermal capability of the package Table 6 Package Type Osa Osc Unit 56 Lead LFCSP CP 56 2 30 4 2 9 C W Typical Ou and 0jc are specified for a 4 layer board in still air Airflow increases heat dissipation effectively reducing Oja In addition metal in direct contact with the package leads from metal traces and through holes ground and power planes reduces the Du ESD CAUTION ESD electrostatic discharge sensitive device Charged devices and circuit boards can discharge without detection Although this product features patented or proprietary protection circuitry damage may occur on devices subjected to high energy ESD Asa Therefore proper ESD precautions should be taken
20. DRIVER ADC AD9601 500 RESISTOR IS OPTIONAL Figure 40 Single Ended 3 3 V CMOS Sample Clock 07100 015 Clock Duty Cycle Considerations Typical high speed ADCs use both clock edges to generate a variety of internal timing signals As a result these ADCs may be sensitive to the clock duty cycle Commonly a 5 tolerance is required on the clock duty cycle to maintain dynamic per formance characteristics The AD9601 contains a duty cycle stabilizer DCS that retimes the nonsampling edge providing an internal clock signal with a nominal 50 duty cycle This allows a wide range of clock input duty cycles without affecting the performance of the AD9601 When the DCS is on noise and distortion performance are nearly flat for a wide range of duty cycles However some applications may require the DCS function to be off If so keep in mind that the dynamic range performance can be affected when operated in this mode See the AD9601 Configuration Using the SPI section for more details on using this feature The duty cycle stabilizer uses a delay locked loop DLL to create the nonsampling edge As a result any changes to the sampling frequency require approximately eight clock cycles to allow the DLL to acquire and lock to the new rate Rev 0 Page 17 of 32 AD9601 Clock Jitter Considerations High speed high resolution ADCs are sensitive to the quality of the clock input The degradation in SNR for a full scale input signa
21. E al a a 2 ES 859 a gt a nH a gt lt gt a lt Ge TT AA D su sx SE wo kel N anro 1 Se 5 5 5 as w w w w amp 3 El El El E 190 lt 6 E3 d d 5 D E E E u Q a Q Q td r anro SE 0 6 Ge gt a EI 4 a 5 z Bl lzl el eLo ES a z o o o HA 3 dd i E EE sE o E E is 25 Y anro au Ts I S zt 52 H 2 090 ja S 6 N amp 2 3 H to t o 5 x an 5 o gt u g3 oO anro SR vzo anro szo g 5 ano ISA anro 8 x 4 4 os 5 VSPIEXTX ARE 929 5 kino VSPIEKTK g t LIX3IdSA g He 8 318833 Qu 2 gro os 8 25 3 ge S a E h E x Q Q g bi a z TUF gt o tc z a a u Q o 2 z 3 o OND GND amp k 884 e a ie ISA ge S pino bte LxaaaHa 314433 eer y ed x Er a ES wie VIN 5 A a F ge g B Zal BN A 3 2 ci 2 AUF LAGAHA 2 3118833 TUF a Zz 2 0 Q 9 z n N o AND GND E a k AVDDX A e a S 4 10 HNO E LA LO 3118833 amp NJ VIN dp sr za Z 8 c10 O 2 23 c7 G TUF L a E k 6 AUF a H D Q O Jo a L Ze am 2 LL ano GND x 4 VAMPX SE e 110 LINO LANYA O u y z 5 s gt 3118833 z2 e NG VIN D oF a ER 2 jo E w ER C6 a5 a g tur Ed a 8 el 2 ale 2 a tol E o 2v0 00120 AD9601 OND e VW VW a TOA q ES ANI VV VNV 9A F AND ANRO 08 62 92 Ya IG Oz AA MIDA s 913 o 82 LZ ONA OND VW VN a TOA
22. FT 250 MSPS 10 3 MHz 07100 028 AMPLITUDE dBFS 250MSPS 70 3MHz 1 0dBFS 20 F SNR 59 4dB ENOB 9 7 BITS SFDR 81dBc 80 100 120 FREQUENCY MHz Dh dl ck L 100 120 07100 031 Figure 22 AD9601 250 64k Point Single Tone FFT 250 MSPS 70 3 MHz Rev 0 Page 13 of 32 AD9601 250MSPS 170 3MHz 1 0dBFS 90 SFDR dBFS SNR 59 1dB ENOB 9 60 BITS 80 SFDR 73dBc SNR dBFS AMPLITUDE dBFS SNR SFDR dB a o SFDR dBc SNR dB 0 20 40 60 80 100 120 90 80 70 60 50 40 30 20 10 0 FREQUENCY MHz AMPLITUDE dBFS Figure 23 AD9601 250 64k Point Single Tone FFT 250 MSPS 170 3 MHz Figure 26 AD9601 250 SNR SFDR vs Input Amplitude 250 MSPS 170 3 MHz 07100 032 07100 035 70k 1 0 INL LSB o NUMBER OF HITS 0 128 256 384 512 640 768 896 1024 OUTPUT CODE Figure 27 AD9601 250 DNL 250 MSPS 07100 033 07100 036 400 SFDR 85 C 350 300 TOTAL POWER mW T 250 2 NEN E 2 SFDR 40 C Z 200 N D g g lavop mA 5 2 150 SNR 25 C 100 SNR 40 C 50 Ipvpp MA 0 0 50 100 150 200 250 300 350 400 450 500 5 25 45 65 85 105 125 145 165 185 205 225 245 ANALOG INPUT FREQUENCY MHz SAMPLE RATE MSPS Figure 25 AD9601 250 Single Tone SNR SFDR vs Input Frequency
23. ched capacitor DAC and interstage residue amplifier MDAC The residue amplifier magnifies the difference between the reconstructed DAC output and the flash input for the next stage in the pipeline One bit of redundancy is used in each stage to facilitate digital correction of flash errors The last stage simply consists of a flash ADC The input stage contains a differential SHA that can be ac or dc coupled The output staging block aligns the data carries out the error correction and passes the data to the output buffers The output buffers are powered from a separate supply allowing adjustment of the output voltage swing During power down the output buffers go into a high impedance state ANALOG INPUT AND VOLTAGE REFERENCE The analog input to the AD9601 is a differential buffer For best dynamic performance the source impedances driving VIN and VIN should be matched such that common mode settling errors are symmetrical The analog input is optimized to provide superior wideband performance and requires that the analog inputs be driven differentially A wideband transformer such as Mini Circuits ADT1 1WT can provide the differential analog inputs for applications that require a single ended to differential conversion Both analog inputs are self biased by an on chip resistor divider to a nominal 1 4 V An internal differential voltage reference creates positive and negative reference voltages that define the 1 25 V p p fixe
24. d span of the ADC core This internal voltage reference can be adjusted by means of SPI control See the AD9601 Configuration Using the SPI section for more details Differential Input Configurations Optimum performance is achieved while driving the AD9601 in a differential input configuration For baseband applications the AD8138 differential driver provides excellent performance and a flexible interface to the ADC The output common mode voltage of the AD8138 is easily set to AVDD 2 0 5 V and the driver can be configured in a Sallen Key filter topology to provide band limiting of the input signal 07100 008 Figure 33 Differential Input Configuration Using the AD8138 At input frequencies in the second Nyquist zone and above the performance of most amplifiers may not be adequate to achieve the true performance of the AD9601 This is especially true in IF undersampling applications where frequencies in the 70 MHz to 100 MHz range are being sampled For these applications differential transformer coupling is the recommended input configuration The signal characteristics must be considered when selecting a transformer Most RF transformers saturate at frequencies below a few millihertz and excessive signal power can also cause core saturation which leads to distortion In any configuration the value of the shunt capacitor C is dependent on the input frequency and may need to be reduced or removed 1 25V p p AD9601 07
25. digital power dissipation does not vary much because it is determined primarily by the DRVDD supply and bias current of the LVDS output drivers By asserting PDWN Pin 29 high the AD9601 is placed in standby mode or full power down mode as determined by the contents of Serial Port Register 08 Reasserting the PDWN pin low returns the AD9601 into its normal operational mode An additional standby mode is supported by means of varying the clock input When the clock rate falls below 20 MHz the AD9601 assumes a standby state In this case the biasing network and internal reference remain on but digital circuitry is powered down Upon reactivating the clock the AD9601 resumes normal operation after allowing for the pipeline latency DIGITAL OUTPUTS Digital Outputs and Timing The off chip drivers on the AD9601 are CMOS compatible output levels The outputs are biased from a separate supply DRVDD allowing isolation from the analog supply and easy interface to external logic The outputs are CMOS devices that swing from ground to DRVDD with no dc load It is recom mended to minimize the capacitive load the ADC drives by keeping the output traces short lt 1 inch for a total Croan lt 5 pF When operating in CMOS mode it is also recommended to place low value 20 Q series damping resistors on the data lines to reduce switching transient effects on performance The format of the output data is offset binary by default An exam
26. el Input Voltage Vi Full 0 0 8 0 0 8 V Input Resistance Differential Full 16 20 24 16 20 24 kQ Input Capacitance Full 4 4 pF LOGIC INPUTS Logic 1 Voltage Full 0 8 x VDD 0 8 x VDD V Logic 0 Voltage Full 0 2 x AVDD 0 2 x AVDD V Logic 1 Input Current SDIO Full 0 0 uA Logic 0 Input Current SDIO Full 60 60 uA Logic 1 Input Current Full 55 50 HA SCLK PDWN CSB RESET Logic 0 Input Current Full 0 0 yA SCLK PDWN CSB RESET Input Capacitance 25 C 4 4 pF LOGIC OUTPUTS High Level Output Voltage Full DRVDD 0 05 DRVDD 0 05 V Low Level Output Voltage Full GND 0 05 GND 0 05 V Output Coding Twos complement Gray code or offset binary default 1 See the AN 835 Application Note Understanding High Speed ADC Testing and Evaluation for a complete set of definitions and how these tests were completed Rev 0 Page 5 of 32 AD9601 SWITCHING SPECIFICATIONS AVDD 1 8 V DRVDD 1 8 V Tum 40 C Tmax 85 C fn 1 0 dBFS full scale 1 25 V DCS enabled unless otherwise noted Table 4 AD9601 200 AD9601 250 Parameter Conditions Temp Min Typ Max Min Typ Max Unit Maximum Conversion Rate Full 200 250 MSPS Minimum Conversion Rate Full 40 40 MSPS CLK Pulse Width High tcy Full 2 15 24 1 8 2 0 ns CLK Pulse Width Low ta Full 2 15 24 1 8 2 0 ns Output Single Data Port Mode Data Propagation Delay tro 25 C 3 7 3 7 ns DCO Propagation Delay tceo 25 C 3 4 3 4 ns
27. fm and Figure 28 AD9601 Power Supply Current vs Sample Rate Temperature with 1 25 V p p Full Scale 250 MSPS 07100 034 07100 037 Rev 0 Page 14 of 32 DNL LSB SNR SFDR dB 1 0 0 8 0 6 0 4 0 2 0 0 2 0 4 0 6 0 8 1 0 0 128 256 384 512 640 768 896 OUTPUT CODE Figure 29 AD9601 250 DNL 250 MSPS 07100 038 07100 039 SAMPLE RATE MSPS Figure 30 SNR SFDR vs Sample Rate AD9626 250 170 3 MHz 1 dBFS OFFSET mV Rev 0 Page 15 of 32 AD9601 AD9601 210 A 40 60 80 100 120 TEMPERATURE C Figure 31 Gain vs Temperature AD9601 210 2 0 40 30 20 10 0 10 20 30 40 50 60 70 80 90 TEMPERATURE C Figure 32 Offset vs Temperature 07100 040 07100 041 AD9601 THEORY OF OPERATION The AD9601 architecture consists of a front end sample and hold amplifier SHA followed by a pipelined switched capacitor ADC The quantized outputs from each stage are combined into a final 10 bit result in the digital correction logic The pipelined architecture permits the first stage to operate on a new input sample while the remaining stages operate on preceding samples Sampling occurs on the rising edge of the clock Each stage of the pipeline excluding the last consists of a low resolution flash ADC connected to a swit
28. gulator 1 8V 1 5A Analog Devices ADP3339AKCZ 1 8 1 U4 LFCSP56 AD9230 12 bit 170 MSPS 210 MSPS 250 MSPS Analog Devices AD9230BCPZ xxx 1 8 V ADC LFCSP 56 2 P7 P11 HM Zd PCB Connector 2 Pr 10 column high speed HM Zd Tyco 6469169 1 PCB mounted Do not install the following 0 C2 C54 TAJD Capacitor tantalum SMT 6032 10 uF 16 V 10 Kemet T491C106KO16AS 0 C15 C37 C38 402 Capacitor 0 1 uF ceramic 10 Murata GRM155R71C104KA88D C40 C41 C61 C42 C43 C44 C45 C46 C47 C48 C49 C50 C51 C52 C53 C39 C56 C57 C58 C59 C74 C75 C60 C66 C67 C68 C69 C72 0 CRI Led ss LED green USS type 0603 Panasonic LNJ314G8TRA 0 CR3 Diode Schottky diode Agilent HSMS2812 0 805 Tyco Raychem NANOSMDC110F 2 0 E6 E15 E16 Connector header 0 1 Samtec TSW 150 08 G S E17 E18 E19 E20 0 Ji 10 pin TSW 110 08 G D Samtec TSW 110 08 G D header 0 J4 SMA Connector PCB coax SMA end launch Johnson 142 0701 851 Johnson 142 0 L6 1206 Inductor 10 nH Murata BLM31P500S 0 P12 P13 P14 SMA Amphenol RF ARFX1231 ND P15 Rev 0 Page 29 of 32 AD9601 Reference Qty Designator Package Description Vendor Part Number 0 R3 R14 R33 402 Resistor 49 9 Q Susumu RRO510R 49R9 D R34 R35 R48 R49 0 R42 R43 R54 402 Resistor 10 kQ NIC Components NRC04J103TRF R85 R86 0 R28 R29 R30 402 Resistor 5 kQ NIC Components NRCO4F4991TRF R31 R32 0 R37 R38 402 Resistor 25 A NIC Components NRCO4F24R9TRF 0 R39 R45
29. igital Qutputs iii ia 18 Timing Single Port Mode ENEE 19 Timing Interleaved MOde o oocoocoocooococooooo 19 Layout Considerations ENEE 20 Power and Ground Recommendations o ooooooo 20 CM iii anakanak 20 UE 20 AD9601 Configuration Using the SPI unne 20 Hardware Interact 21 Configuration Without the SPI o o coocoocoocoocoooo 21 Memory Map iii tii dentes 23 Reading the Memory Map Table 23 Reserved Locations mannenstem 23 KE NA Na ui aa iaa 23 RE 23 Eval ation Board anssen kal kal la a et 25 Outline Dimensions ENEE 31 Ordering Guide arn erneer eenen 31 Rev 0 Page 2 of 32 SPECIFICATIONS DC SPECIFICATIONS AD9601 AVDD 1 8 V DRVDD 1 8 V Tuin 40 C Tmax 85 C fin 1 0 dBES full scale 1 25 V single port output mode DCS enabled unless otherwise noted Table 1 AD9601 200 AD9601 250 Parameter Temp Min Typ Max Min Typ Max Unit RESOLUTION 10 10 Bits ACCURACY No Missing Codes Full Guaranteed Guaranteed Offset Error 25 C 4 0 4 0 mV Full 12 12 12 12 mV Gain Error 25 C 14 14 Yo FS Full 2 1 4 5 2 1 4 5 FS Differential Nonlinearity DNL 25 C 0 2 0 2 LSB Full 0 5 0 5 0 5 0 5 LSB Integral Nonlinearity INL 25 C 0 2 0 2 LSB Full 0 5 0 5 0 5 40 5 LSB TEMPERATURE DRIFT Offset Error Full 8 8 UNC Gain Error Full 0 021 0 021 C ANALOG INPUTS VIN VIN Differential Input Voltage Range Full 0 98 1 25 1 5 0 98 1 25 1 5 V
30. ivalent CSB Input Circuit 07100 003 07100 006 DRVDD 3 DRGND 2 Figure 6 Analog Inputs Vem 1 4 V Figure 9 CMOS Outputs Dx OVRA OVRB DCO DCO 1kO DRVDD SCLK DFS Ean D 1kO SDIO DCS Figure 7 Eguivalent SCLK DFS RESET PDWN Input Circuit Figure 10 Equivalent SDIO DCS Input Circuit Rev 0 Page 11 of 32 AD9601 TYPICAL PERFORMANCE CHARACTERISTICS AVDD 1 8 V DRVDD 1 8 V rated sample rate DCS enabled Ta 25 C 1 25 V p p differential input AIN 1 dBFS unless otherwise noted 70k 200MSPS 10 3MHz 1 0dBFS SNR 59 48dB 60k ENOB 9 58 BITS SFDR 83 79dBc AMPLITUDE dBFS NUMBER OF HITS 07100 020 07100 023 BIN Figure 11 AD9601 200 64k Point Single Tone FFT 200 MSPS 10 3 MHz Figure 14 AD9601 200 Grounded Input Histogram 200 MSPS 90 200MSPS SFDR 85 C 70 3MHz 1 0dBFS L SNR 59 3dB 85 SFDR 40 C ENOB 9 7 BITS SFDR 78dBc 80 SFDR 25 C 75 70 SNR SFDR dB 65 AMPLITUDE dBFS SNR 25 C 60 SNR 40 C 55 SNR 85 C 50 0 50 100 150 200 250 300 350 400 450 500 ANALOG INPUT FREQUENCY MHz Figure 12 AD9601 200 64k Point Single Tone FFT 200 MSPS 70 3 MHz Figure 15 AD9601 200 Single Tone SNR SFDR vs Input Frequency fix and Temperature with 1 25 V p p Full Scale 200 MSPS 07100 021 07100 024 90
31. l at a given input frequency fa due only to aperture jitter tj can be calculated by SNR Degradation 20 x logio 1 2 x n x fa x tr In this equation the rms aperture jitter represents the root mean square of all jitter sources including the clock input analog input signal and ADC aperture jitter specifications IF undersampling applications are particularly sensitive to jitter see Figure 41 The clock input should be treated as an analog signal in cases where aperture jitter may affect the dynamic range of the AD9601 Power supplies for clock drivers should be separated from the ADC output driver supplies to avoid modulating the clock signal with digital noise Low jitter crystal controlled oscillators make the best clock sources If the clock is generated from another type of source by gating dividing or other methods it should be retimed by the original clock at the last step Refer to the AN 501 Application Note and the AN 756 Application Note for more in depth information about jitter performance as it relates to ADCs visit www analog com 130 RMS CLOCK JITTER REQUIREMENT 120 110 100 90 80 SNR dB 70 60 50 40 30 1 10 100 1000 ANALOG INPUT FREQUENCY MHz 07100 016 Figure 41 Ideal SNR vs Input Frequency and Jitter for 0 dBFS Input Signal POWER DISSIPATION AND POWER DOWN MODE As shown in Figure 28 the power dissipated by the AD9601 is proportional to its sample rate The
32. lity in system design Use of a single 1 8 V supply simplifies system power supply design 4 Serial Port Control Standard serial port interface supports various product functions such as data formatting power down gain adjust and output test pattern generation 5 Pin Compatible Family 12 bit pin compatible family offered as the AD9626 One Technology Way P O Box 9106 Norwood MA 02062 9106 U S A Tel 781 329 4700 www analog com Fax 781 461 3113 2007 Analog Devices Inc All rights reserved AD9601 TABLE OF CONTENTS Features ee 1 Ap a A A Na na 1 Functional Block Diagram eenen enn eeneeneenenneenn 1 General Description miii 1 Product Highlights aan 1 REVISION History Se neten 2 petite EE 3 Re 3 AC Specifications ia 4 Digital Specifications o ooocoocoococoocoooooooooo 5 Switching Specifications ENEE 6 Timing Diagrams EEN 7 Absolute Maximum RatingS oo cooccococoocoooooc 8 Thermal Resistance oo oooooooccocoocoocooocooooooooo 8 ESD Cationic iia 8 Pin Configurations and Function Descriptions 9 Equivalent Circuiitsc 2 csssessessnosssctioensssesnsetivshoondsestonsdevstnoctsoriosaasoes 11 Typical Performance Characteristics o oooooooocooo 12 Theory Of Operation dad 16 Analog Input and Voltage Reference ooooo cooooocoooooo 16 REVISION HISTORY 11 07 Revision 0 Initial Version Clock Input Considerations ENEE 17 Power Dissipation and Power Down Mode 18 D
33. ltage and Output Data Rev 0 Page 18 of 32 AD9601 TIMING SINGLE PORT MODE In single port mode the CMOS output data is available from Data Port A DAO to DA9 The outputs for Port B DBO to DB9 are unused and are high impedance in this mode The Port A outputs and the differential output data clock DCO DCO switch nearly simultaneously during the rising edge of DCO In this mode it is recommended to use the rising edge of DCO to capture the data from Port A The setup and hold time depends on the input sample clock period and is approximately 1 fcrx tsxew TIMING INTERLEAVED MODE In interleaved mode the output data of the AD9601 is de multiplexed onto two data port buses Port A DAO to DA9 and Port B DBO to DB9 The output data and differential data capture clock switch at one half the rate of the sample clock input CLK CLK increasing the setup and hold time for the external data capture circuit relative to single port mode see Figure 3 interleaved mode timing diagram The two ports switch on alternating sample clock cycles with the data for Port A being valid during the rising edge of DCO and the data for Port B being valid during the rising edge of DCO The pipeline latency for both ports is six sample clock cycles Due to the random nature of the 2 circuit that generates the timing for the output stage in interleaved mode the first data sample during power up can be assigned to either Data Port
34. mented in the Memory Map section There are three pins that define the serial port interface or SPI to this particular ADC They are the SPI SCLK DFS SPI SDIO DCS and CSB pins The SCLK DFS serial clock is used to synchronize the read and write data presented the ADC The SDIO DCS serial data input output is a dual purpose pin that allows data to be sent and read from the internal ADC memory map registers The CSB is an active low control that enables or disables the read and write cycles see Table 8 Table 8 Serial Port Pins Mnemonic Function SCLK SCLK Serial Clock is the serial shift clock in SCLK is used to synchronize serial interface reads and writes SDIO SDIO Serial Data Input Output is a dual purpose pin The typical role for this pin is an input and output depending on the instruction being sent and the relative position in the timing frame CSB CSB Chip Select Bar is an active low control that gates the read and write cycles RESET Master Device Reset When asserted device assumes default settings Active low The falling edge of the CSB in conjunction with the rising edge of the SCLK determines the start of the framing An example of the serial timing and its definitions can be found in Figure 44 and Table 10 During an instruction phase a 16 bit instruction is transmitted Data then follows the instruction phase and is determined by the WO and W1 bits which is 1 or more bytes of data
35. ock is available another option is to ac couple a differential PECL signal to the sample clock input pins as shown in Figure 37 The AD9510 AD9511 AD9512 AD9513 AD9514 AD9515 family of clock drivers offers excellent jitter performance AD9510 AD9511 AD9512 AD9513 AD9514 AD9515 CLOCK a INPUT CLK PECL DRIVER _ 0 1uF CLOCK 6 INPUT 500 500 2400 2400 500 RESISTORS ARE OPTIONAL Figure 37 Differential PECL Sample Clock 07100 012 AD9510 AD9511 AD9512 AD9513 0 1uF AD9514 AD9515 0 1pF CLOCK INPUT En 0 1uF CLOCK INPUT 500 500 500 RESISTORS ARE OPTIONAL Figure 38 Differential LVDS Sample Clock 07100 013 AD9601 In some applications it is acceptable to drive the sample clock inputs with a single ended CMOS signal In such applications CLK should be directly driven from a CMOS gate and the CLK pin should be bypassed to ground with a 0 1 uF capacitor in parallel with a 39 kO resistor see Figure 39 Although the CLK4 input circuit supply is AVDD 1 8 V this input is designed to withstand input voltages up to 3 3 V making the selection of the drive logic voltage very flexible AD9510 AD9511 AD9512 AD9513 AD9514 AD9515 0 1uF OPTIONAL 1 ooo 0 1uF 500 CMOS DRIVER 07100 014 500 RESISTOR IS OPTIONAL Figure 39 Single Ended 1 8 V CMOS Sample Clock AD9510 AD9511 AD9512 AD9513 AD9514 AD9515 0 1uF OPTIONAL 500 1000 CMOS
36. p p Input Common Mode Voltage Full 14 1 4 V Input Resistance Differential Full 4 3 4 3 kQ Input Capacitance 25 C 2 2 pF POWER SUPPLY AVDD Full 1 7 1 8 1 9 1 7 1 8 1 9 V DRVDD Full 1 7 1 8 1 9 1 7 1 8 1 9 V Supply Currents lavoo Full 133 142 157 167 mA Ibrvoo Single Port Mode Full 19 20 22 24 mA lorvoo Interleaved Mode Full 16 18 mA Power Dissipation Full mW Single Port Mode Full 274 291 322 344 mW Interleaved Mode Full 268 315 mW Power Down Mode Supply Currents lavoD Full 40 40 uA lorvoD Full 170 170 22 yA Standby Mode Supply Currents lavoo Full 19 19 mA lorvoD Full 170 170 22 yA 1 See the AN 835 Application Note Understanding High Speed ADC Testing and Evaluation for a complete set of definitions and how these tests were completed The input range is programmable through the SPI and the range specified reflects the nominal values of each setting See the Memory Map section 3 lavoo and lorvoo are measured with a 1 dBFS 10 3 MHz sine input at rated sample rate 4 Single data rate mode this is the default mode of the AD9601 gt Interleaved mode user programmable feature See the Memory Map section Rev 0 Page 3 of 32 AD9601 AC SPECIFICATIONS AVDD 1 8 V DRVDD 1 8 V Tuin 40 C Tmax 85 C fin 1 0 dBES full scale 1 25 V DCS enabled unless otherwise noted Table 2 AD9601 200 AD9601 250 Parameter Temp Min Typ Max Min Typ Max Unit SNR fin 10 MH
37. ple of the output coding format can be found in Table 11 If it is desired to change the output data format to twos comple ment see the AD9601 Configuration Using the SPI section An output clock signal is provided to assist in capturing data from the AD9601 The DCO DCO signal is used to clock the output data and is equal to the sampling clock CLK rate in single port mode and one half the clock rate in interleaved output mode See the timing diagrams shown in Figure 2 and Figure 3 for more information Out of Range An out of range condition exists when the analog input voltage is beyond the input range of the ADC OVRA OVRB is a digital output that is updated along with the data output corresponding to the particular sampled input voltage Thus OVRA OVRB has the same pipeline latency as the digital data OVRA OVRB is low when the analog input voltage is within the analog input range and high when the analog input voltage exceeds the input range as shown in Figure 42 OVRA OVRB remains high until the analog input returns to within the input range and another conversion is completed By logically AND ing OVRA OVRB with the MSB and its complement overrange high or under range low conditions can be detected OVRA OVRB DATA OUTPUTS FFS LSB 1111 1111 1111 OVRA 1111 1111 1111 OVRB 1111 1111 1110 FS 1 2 LSB 0000 0000 0001 0000 0000 0000 0000 0000 0000 FS 3 FS 1 2 LSB FS 1 2LSB 5 Figure 42 OVRA OVRB Relation to Input Vo
38. rising edge not shown in Figure 44 Table 11 Output Data Format Gray Code Mode Offset Binary Output Mode Twos Complement Mode SPI Accessible Input V Condition V D11 to DO D11 to DO D11 to DO OR VIN VIN lt 0 62 0000 0000 0000 0000 0000 0000 0000 0000 0000 1 VIN VIN 0 62 0000 0000 0000 0000 0000 0000 0000 0000 0000 0 VIN VIN 0 0000 0000 0000 0000 0000 0000 0000 0000 0000 0 VIN VIN 0 62 111111111111 1111 1111 1111 0000 0000 0000 0 VIN VIN gt 0 62 0 5 LSB 111111111111 1111 1111 1111 0000 0000 0000 1 Rev 0 Page 22 of 32 MEMORY MAP READING THE MEMORY MAP TABLE Each row in the memory map table has eight address locations The memory map is roughly divided into three sections chip configuration register map Address 0x00 to Address 0x02 transfer register map Address OxFF and program register map Address 0x08 to Address 0x2A The Addr Hex column of the memory map indicates the register address in hexadecimal and the Default Value Hex column shows the default hexadecimal value that is already written into the register The Bit 7 MSB column is the start of the default hexadecimal value given For example Hexadecimal Address 0x09 clock has a hexadecimal default value of 0x01 This means Bit 7 0 Bit 6 0 Bit 5 0 Bit 4 0 Bit 3 0 Bit 2 0 Bit 1 0 and Bit 0 1 or 0000 0001 in binary The default value enables the duty cycle s
39. rt either twos complement offset binary format or Gray code A data clock output is available for proper output data timing Fabricated on an advanced CMOS process the AD9601 is available in a 56 lead LFCSP specified over the industrial temperature range 40 C to 85 C Rev 0 Information furnished by Analog Devices is believed to be accurate and reliable However no responsibility is assumed by Analog Devices for its use nor for any infringements of patents or other rights of third parties that may result from its use Specifications subject to change without notice No license is granted by implication or otherwise under any patent or patent rights of Analog Devices Trademarks and registered trademarks are the property of their respective owners APPLICATIONS Wireless and wired broadband communications Cable reverse path Communications test equipment Radar and satellite subsystems Power amplifier linearization FUNCTIONAL BLOCK DIAGRAM RBIAS PWDN AGND AVDD 1 8V REFERENCE DRVDD DRGND TRACK AND HOLD Dx9 TO Dx0 CLOCK OVRA MANAGEMENT OVRB DCO DCO 07100 001 RESET SCLK SDIO CSB Figure 1 PRODUCT HIGHLIGHTS 1 High Performance Maintains 59 4 dBFS SNR 250 MSPS with a 70 MHz input 2 Low Power Consumes only 322 mW 250 MSPS 3 Ease of Use CMOS output data and output clock signal allow interface to current FPGA technology The on chip reference and sample and hold provide flexibi
40. t interface to the SPI control registers the SPI SDIO DCS and SPI SCLK DFS pins can alternately serve as standalone CMOS compatible control pins When the device is powered up it is assumed that the user intends to use the pins as static control lines for the duty cycle stabilizer In this mode the SPI CSB chip select should be connected to ground which disables the serial port interface Table 9 Mode Selection External Mnemonic Voltage Configuration SPI SDIO DCS AVDD Duty cycle stabilizer enabled AGND Duty cycle stabilizer disabled SPI SCLK DFS AVDD Twos complement enabled AGND Offset binary enabled ty gee DON T CARE DON T CARE 07100 019 Figure 44 Serial Port Interface Timing Diagram Rev 0 Page 21 of 32 AD9601 Table 10 Serial Timing Definitions Parameter Timing minimum ns Description tos 5 Setup time between the data and the rising edge of SCLK ton 2 Hold time between the data and the rising edge of SCLK tak 40 Period of the clock ts 5 Setup time between CSB and SCLK tH 2 Hold time between CSB and SCLK thi 16 Minimum period that SCLK should be in a logic high state Do 16 Minimum period that SCLK should be in a logic low state ten sdio 1 Minimum time for the SDIO pin to switch from an input to an output relative to the SCLK falling edge not shown in Figure 44 tdis sdio 5 Minimum time for the SDIO pin to switch from an output to an input relative to the SCLK
41. tabilizer Overwriting this default so that Bit 0 0 disables the duty cycle stabilizer For more information on this and other functions consult the Interfacing to High Speed ADCs via SPI user manual at www analog com Table 12 Memory Map Register AD9601 RESERVED LOCATIONS Undefined memory locations should not be written to other than their default values suggested in this data sheet Addresses that have values marked as 0 should be considered reserved and have a 0 written into their registers during power up DEFAULT VALUES Coming out of reset critical registers are preloaded with default values These values are indicated in Table 12 Other registers do not have default values and retain the previous value when exiting reset LOGIC LEVELS An explanation of various registers follows Bit is set is synonymous with bit is set to Logic 1 or writing Logic 1 for the bit Similarly clear a bit is synonymous with bit is set to Logic 0 or writing Logic 0 for the bit Addr Bit 7 Hex Parameter Name MSB Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 LSB Hex Default Bit O Value Default Notes Comments Chip Configuration Registers 00 chip port config 0 LSB Softreset 1 first Soft reset LSBfirst O 0x18 The nibbles should be mirrored by the user so that LSB or MSB first mode registers correctly regardless of shift mode 01 chip_id
42. tion to flow through the bottom of the PCB These vias should be solder filled or plugged To maximize the coverage and adhesion between the ADC and PCB partition the continuous plane by overlaying a silkscreen on the PCB into several uniform sections This provides several tie points between the two during the reflow process Using one continuous plane with no partitions guarantees only one tie point between the ADC and PCB See Figure 43 for a PCB layout example For detailed information on packaging and the PCB layout of chip scale packages see Application Note AN 772 A Design and Manufacturing Guide for the Lead Frame Chip Scale Package SILKSCREEN PARTITION PIN 1 INDICATOR 07100 018 Figure 43 Typical PCB Layout CML The CML pin should be decoupled to ground with a 0 1 uF capacitor as shown in Figure 45 RBIAS The AD9601 requires the user to place a 10 kQ resistor between the RBIAS pin and ground This resistor sets the master current reference of the ADC core and should have at least a 1 tolerance AD9601 CONFIGURATION USING THE SPI The AD9601 SPI allows the user to configure the converter for specific functions or operations through a structured register space inside the ADC This gives the user added flexibility to customize device operation depending on the application Addresses are accessed programmed or read back serially in one byte words Each byte can be further divided down into fields which are docu
43. z 25 C 59 5 59 4 dB Full 58 5 57 8 dB fin 70 MHz 25 C 59 3 59 4 dB SINAD fin 10 MHz 25 C 59 5 59 4 dB Full 58 5 57 7 dB fin 70 MHz 25 C 59 3 59 4 dB EFFECTIVE NUMBER OF BITS ENOB fin 10 MHz 25 C 9 6 9 7 Bits fin 70 MHz 25 C 9 6 9 7 Bits WORST HARMONIC SECOND OR THIRD fin 10 MHz 25 C 84 84 dBc Full 77 72 dBc fin 70 MHz 25 C 78 81 dBc WORST OTHER SFDR EXCLUDING SECOND AND THIRD fin 10 MHz 25 C 88 86 dBc Full 80 75 dBc fin 70 MHz 25 C 87 85 dBc TWO TONE IMD 170 2 MHz 171 3 MHz 7 dBFS 25 C 81 81 dBFS ANALOG INPUT BANDWIDTH 25 C 700 700 MHz 1 All ac specifications tested by driving CLK and CLK differentially See the AN 835 Application Note Understanding High Speed ADC Testing and Evaluation for a complete set of definitions and how these tests were completed Rev 0 Page 4 of 32 DIGITAL SPECIFICATIONS AD9601 AVDD 1 8 V DRVDD 1 8 V Tum 40 C Tmax 85 C fn 1 0 dBFS full scale 1 25 V DCS enabled unless otherwise noted Table 3 AD9601 200 AD9601 250 Parameter Temp Min Typ Max Min Typ Max Unit CLOCK INPUTS Logic Compliance Full CMOS LVDS LVPECL CMOS LVDS LVPECL Internal Common Mode Bias Full 1 2 1 2 V Differential Input Voltage Full 0 2 6 0 2 6 Vp p Input Voltage Range Full AVDD 0 3 AVDD 1 6 AVDD 0 3 AVDD 1 6 V Input Common Mode Range Full 1 1 AVDD 1 1 AVDD V High Level Input Voltage Vin Full 1 2 3 6 1 2 3 6 V Low Lev

ANALOG DEVICES AD9601 handbook

Contents

Download Pdf Manuals

Related Search

Related Contents