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TEXAS INSTRUMENTS ADS1255 ADS1256 handbook

1. 3 84 Frequency MHz Figure 16 Frequency Response Out to 7 68MHz for Data Rate 30kSPS foara 2 5SPS Lt em 7 68MHz 3 84 Frequency MHz Figure 17 Frequency Response Out to 7 68MHz for Data Rate 2 5SPS SETTLING TIME The ADS1255 6 features a digital filter optimized for fast settling The settling time time required for a step change on the analog inputs to propagate through the filter for the different data rates is shown in Table 13 The following sections highlight the single cycle settling ability of the filter and show various ways to control the conversion process 20 d TEXAS INSTRUMENTS www ti com Table 13 Settling Time vs Data Rate DATA RATE SETTLING TIME t18 SPS ms 30 000 0 21 15 000 0 25 7500 0 31 3750 0 44 2000 0 68 1000 1 18 500 2 18 100 10 18 60 16 84 50 20 18 30 33 51 25 40 18 15 66 84 10 100 18 5 200 18 2 5 400 18 NOTE CLKIN 7 68MHz Settling Time Using Synchronization The SYNC PDWN pin allows direct control of conversion timing Simply issue a Sync command or strobe the SYNC PDWN pin after changing the analog inputs see the Synchronization section for more information The conversion begins when SYNC PDWN is taken high stopping the current conversion and restarting the digital filter As soon as SYNC PDWN goes low
2. gh IL kl sts Sek nce ek Ya SEE E a ek IN Standby Standby Status Performing One Shot Conversion Li tig DRDY BIN STANDBY DOUT gt RDATA STANDBY Settled Data Figure 20 One Shot Conversions Using the STANDBY Command Vin AINp AN New Vu On Mix of Old and New Fully Settled Old Vy Data La Vy Data New Vu Data DRDY DN ig Prom 1 Settled Data Figure 21 Step Change on Vum while Continuously Converting for Data Rates lt 3750SPS 22 d TEXAS INSTRUMENTS www ti com DATA FORMAT The ADS1255 6 output 24 bits of data in Binary Two s Complement format The LSB has a weight of 2VreF PGA 223 1 A positive full scale input produces an output code of 7FFFFFh and the negative full scale input produces an output code of 800000h The output clips at these codes for signals exceeding full scale Table 16 summarizes the ideal output codes for different input signals Table 16 Ideal Output Code vs Input Signal INPUT SIGNAL Vin AINp AINN IDEAL OUTPUT CODE 1 2VREF e 7FFFFFh PGA _ Wiener 000001h PGA 223 1 0 000000h EYRE 2 FFFFFFh PGA 223 1 lt ERT ee 800000h PGA 223 4 1 Excludes effects of noise INL offset and gain errors GENERAL PURPOSE DIGITAL I O DO D3 The ADS1256 has 4 pins dedicated for digital I O and the ADS1255 has 2 digi
3. DATA RATE ZEFF SPS MQ 30 000 10 15 000 10 7 500 10 3 750 10 2 000 10 1 000 20 500 40 100 40 60 40 lt 50 80 NOTE CLKIN 7 68MHz With the buffer enabled the voltage on the analog inputs with respect to ground listed in the Electrical Characteristics as Absolute Input Voltage must remain between AGND and AVDD 2 0V Exceeding this range reduces performance in particular the linearity of the ADS1255 6 This same voltage range AGND to AVDD 2 0V applies to the reference inputs when performing a self gain calibration with the buffer enabled 15 ADS1255 ADS1256 SBAS288D JUNE 2003 REVISED AUGUST 2004 PROGRAMMABLE GAIN AMPLIFIER PGA The ADS1255 6 is a very high resolution converter To further complement its performance the low noise PGA provides even more resolution when measuring smaller input signals For the best resolution set the PGA to the highest possible setting This will depend on the largest input signal to be measured The ADS1255 6 full scale input voltage equals 2Vper PGA Table 8 shows the full scale input voltage for the different PGA settings for Vrer 2 5V For example if the largest signal to be measured is 1 0V the optimum PGA setting would be 4 which gives a full scale input voltage of 1 25V Higher PGAs cannot be used since they cannot handle a 1 0V input signal Table 8 Full Scale Input Voltage vs PGA Setting 1 5V 2 2 5V 4 1 2
4. Sensor detect current sources System Performance SDCS 1 0 01 0 5 SDCS 1 0 10 SDCS 1 0 11 10 Resolution 24 Bit No missing codes All data rates and PGA settings 24 Bit Data rate fp ATA fCLKIN 7 68MHz 2 5 30 000 Spa E Differential input PGA 1 0 0003 0 0010 FSR 3 integral noniinearity Differential input PGA 64 0 0007 FSR Offset error After calibration On the level of the noise PGA 1 100 nV C SEH PGA 64 4 nV C After calibration PGA 1 Buffer on 0 005 Pa After calibration PGA 64 Buffer on 0 03 E PGA 1 0 8 Dm Gain arit PGA 64 0 8 ppm C Common mode rejection fom 60Hz fpata 30kSPS 95 110 dB Noise See Noise Performance Tables AVDD power supply rejection 5 A in AVDD 60 70 dB DVDD power supply rejection 10 Ain DVDD 100 dB Voltage Reference Inputs Reference input voltage VREF VREF VREFP VREFN 05 2 5 2 6 V l Buffer off AGND 0 1 VREFP 0 5 V Negative reference input VREFN Buffer on AGND VREFP L05 V Buffer off VREFN 0 5 AVDD 0 1 V Positive reference input VREFP Buffer on 6 VREEN 05 AVDD 2 0 V Voltage reference impedance fCLKIN 7 68MHz 18 5 kQ Digital Input Output DIN SCLK XTAL1 CLKIN fh SYNC PDWN CS RESET 0 8 DVDD 5 25 y DO CLKOUT D1 D2 D3 0 8 DVDD DVDD V VIL DGN
5. VREFN AINCOM AINO SYNC PDWN XTAL1 CLKIN O AVDD VREFP AIN1 RESET DVDD d TEXAS INSTRUMENTS www ti com the digital pins can help by controlling the trace impedance When not using the RESET or SYNC PDWN inputs tie directly to the ADS1255 6 DVDD pin Pay special attention to the reference and analog inputs These are the most critical circuits On the voltage reference inputs bypass with low equivalent series resistance ESR capacitors Make these capacitors as large as possible to maximize the filtering on the reference With the outstanding performance of the ADS1255 6 it is easy for the voltage reference to limit overall performance if not carefully selected When using a stand alone reference make sure it is very low noise and very low drift Ratiometric measurements where the input signal and reference track each other are somewhat less sensitive but verify the reference signal is clean Often times only a simple RC filter as shown in Figure 25 is needed on the inputs This circuit limits the high frequency noise near the modulator frequency see the Frequency Response section Avoid low grade dielectrics for the capacitors to minimize temperature variations and leakage Keep the input traces as short as possible and place the components close to the input pins When using the ADS1256 make sure to filter all the input channels b
6. T S 2 Buffer Off 3 PGA 64 Buffe O O D D xe 2 oO oO E E lt E 50 30 10 10 30 50 70 90 110 1 2 4 8 16 32 64 Temperature C PGA Setting 10 d TEXAS INSTRUMENTS www ti com OVERVIEW The ADS1255 and ADS1256 are very low noise A D converters The ADS1255 supports one differential or two single ended inputs and has two general purpose digital I Os The ADS1256 supports four differential or eight single ended inputs and has four general purpose digital I Os Otherwise the two units are identical and are referred to together in this data sheet as the ADS1255 6 Figure 5 shows a block diagram of the ADS1256 The input multiplexer selects which input pins are connected to the A D converter Selectable current sources within the input multiplexer can check for open or short circuit conditions on the external sensor A selectable onboard input buffer greatly reduces the input circuitry loading by providing up to 80MQ of impedance A low noise PGA provides a gain of 1 2 4 8 16 32 or 64 The ADS1255 6 converter is comprised of a 4th order delta sigma modulator followed by a programmable digital filter ADS1255 ADS1256 SBAS288D JUNE 2003 REVISED AUGUST 2004 The modulator measures the amplified differential input signal Vin AINp AINy against the differential reference Veer VREFP VREFN The differential reference is scaled internally by a factor of two so that the full scale input rang
7. JUNE 2003 REVISED AUGUST 2004 REGISTER MAP The operation of the ADS1255 6 is controlled through a set of registers Collectively the registers contain all the information needed to configure the part such as data rate multiplexer settings PGA setting calibration etc and are listed in Table 23 Table 23 Register Map ADDRESS REGISTER ie BIT 7 BIT 6 BIT5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 00h ID3 ID2 ID1 ID STATUS x1H 0 ORDER ACAL BUFEN DRDY Oth MUX 01H PSEL3 PSEL2 PSEL1 PSELO NSEL3 NSEL2 NSEL1 NSELO 02h ADCON 20H 0 CLK1 CLKO SDCS1 SDCSO PGA2 PGA1 PGAO 03h DRATE FOH DR7 DR6 DR5 DR4 DR3 DR2 DR1 DRO 04h 10 E0H DIRS DIR2 DIR1 DIRO DIO3 DIO2 DIO1 DIOO Dh OFCO XXH OFC07 OFC06 OFC05 OFC04 OFC03 OFC02 OFC01 OFC00 06h OFC1 XXH OFC15 OFC14 OFC13 OFC12 OFC11 OFC10 OFC09 OFC08 07h OFC2 XXH OFC23 OFC22 OFC21 OFC20 OFC19 OFC18 OFC17 OFC16 08h FSCO XXH FSC07 FSC06 FSC05 FSC04 FSC03 FSC02 FSC01 FSC00 09h FSC1 XXH FSC15 FSC14 FSC13 FSC12 FSC11 FSC10 FSC09 FSC08 OAh FSC2 XXH FSC23 FSC22 FSC21 FSC20 FSC19 FSC18 FSC17 FSC16 STATUS STATUS REGISTER ADDRESS 00h Reset Value xth BIT7 BIT 6 BIT5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 D mD mD D ORDER ACAL BUFEN DRDY Bits 7 4 ID3 ID2 ID1 IDO Factory Programmed Identification Bits Read Only Bit3 ORDER Data Output Bit Order 0 Most Significant Bit First default 1 Least Significant Bit First Input data is always shifted in most significant byte and bit
8. SCLK bel ett T be Figure 2 SCLK Reset Timing TIMING CHARACTERISTICS FOR FIGURE 2 ai S 15 SCLK reset pattern second high pulse 5 750 TCLKIN SCLK reset pattern third high pulse 1050 1250 seim 1 tcLKIN master clock period 1 fCLKIN tis gt La RESET SYNC PDWN Figure 3 RESET and SYNC PDWN Timing TIMING CHARACTERISTICS FOR FIGURE 3 SYMBOL DESCRIPTION MN MAX UNT RESET SYNC PDWN pulse width sc em 1 tcLKIN master clock period 1 f LKIN gt tiz La DRDY Figure 4 DRDY Update Timing TIMING CHARACTERISTICS FOR FIGURE 4 SYMBOL DESCRIPTION MN MAX UNT Conversion data invalid while being updated DRDY shown with no data retrieval 16 TCLKIN 1 tcLKIN master clock period 1 fCLKIN N ADS1255 i ADS1256 K Texas INSTRUMENTS www ti com SBAS288D JUNE 2003 REVISED AUGUST 2004 TYPICAL CHARACTERISTICS Ta 25 C AVDD 5V DVDD 1 8V foLKIN 7 68MHz PGA 1 and VREF 2 5V unless otherwise noted OFFSET DRIFT HISTOGRAM OFFSET DRIFT HISTOGRAM 90 Units from 3 Production Lots 90 Units from 3 Production Lots Percent of Population Percent of Population LI CO OO st OO oO st OO st oO OO Ost oO Oe ECH SAY SE EEN Offset Drift nV C Offset Drift nV C GAIN ERROR HISTOGRAM GAIN ERROR HISTOGRAM 90 Units from 3 Production Lots 90 Units from 3 Production Lots Percent
9. rms with Buffer On 100 23 4 23 0 22 5 22 0 21 4 20 8 19 8 500 22 3 21 9 21 5 20 9 20 3 19 6 18 7 1000 21 7 21 3 20 8 20 2 19 8 19 2 18 3 2000 21 2 20 9 20 4 19 7 19 3 18 8 17 9 3750 20 8 20 5 20 0 19 4 19 0 18 4 17 4 7500 20 4 20 1 19 6 19 0 18 5 17 9 17 0 15 000 20 1 19 7 19 3 18 7 18 2 17 7 16 7 30 000 19 8 19 5 19 1 185 18 0 17 4 16 5 Table 3 Noise Free Resolution bits with Buffer On 100 20 9 20 7 20 2 19 6 19 1 18 5 17 4 500 20 1 19 6 19 1 186 18 0 17 3 16 3 1000 19 0 18 6 18 1 17 5 17 2 16 5 15 6 2000 18 5 18 1 17 8 17 0 16 6 16 1 15 3 3750 18 1 17 8 17 3 16 6 16 2 15 7 14 7 7500 17 7 17 3 16 9 16 2 15 8 15 3 14 4 15 000 17 3 17 0 16 5 15 9 15 5 14 9 13 9 30 000 17 1 16 7 164 15 9 15 4 14 6 13 8 ADS1255 i MO Texas ADS1256 www ti com SBAS288D JUNE 2003 REVISED AUGUST 2004 Table A Input Referred Noise uV rms Table 6 Noise Free Resolution bits with Buffer Off with Buffer Off 100 0 815 0 530 0 360 0 233 0 169 0 123 0 122 100 21 1 20 5 20 3 19 9 19 5 19 0 17 9 500 1 957 1 148 0 772 0 531 0 375 0 276 0 259 500 20 0 19 7 19 3 18
10. the DRDY output goes high and remains high during the conversion After the settling time tg DRDY goes low indicating that data is available The ADS1255 6 settles in a single cycle there is no need to ignore or discard data after synchronization Figure 18 shows the data retrieval sequence following synchronization AINp AINy SYNC PDWN RDATAN Settled Data Figure 18 Data Retrieval After Synchronization DOUT cl d TEXAS INSTRUMENTS www ti com Settling Time Using the Input Multiplexer The most efficient way to cycle through the inputs is to change the multiplexer setting using a WREG command to the multiplexer register MUX immediately after DRDY goes low Then after changing the multiplexer restart the conversion process by issuing the SYNC and WAKEUP commands and retrieve the data with the RDATA command Changing the multiplexer before reading the data allows the ADS1256 to start measuring the new input channel sooner Figure 19 demonstrates efficient input cycling There is no need to ignore or discard data while cycling through the channels of the input multiplexer because the ADS1256 fully settles before DRDY goes low indicating data is ready Step 1 When DRDY goes low indicating that data is ready for retrieval update the multiplexer register MUX using the WREG command For example setting MUX to 23h gives AINp AIN2 AINy AINS Step 2 Restart the conv
11. 9 18 3 17 8 16 9 1000 2 803 1 797 1 191 0 940 0 518 0 392 0 365 1000 19 0 18 7 18 4 17 7 17 5 16 9 15 9 2000 4 025 2 444 1 615 1 310 0 700 0 526 0 461 2000 18 5 18 3 17 9 17 4 17 0 16 4 15 6 3750 5 413 3 250 2 061 1 578 0 914 0 693 0 625 3750 18 1 17 8 17 5 17 0 16 7 16 1 15 2 7500 7 017 4 143 2 722 1 998 1 241 0 914 0 857 7500 17 7 17 6 17 0 16 6 16 2 15 7 14 8 15 000 8 862 5 432 3 378 2 411 1 569 1 149 1 051 15 000 17 4 17 1 168 16 3 15 9 15 3 14 4 30 000 10 341 6 137 3 873 2 775 1 805 1 313 1 211 30 000 17 1 17 0 166 16 0 15 6 15 0 14 4 Table 5 Effective Number of Bits ENOB rms with Buffer Off 100 23 5 23 2 22 7 22 4 21 8 21 3 20 3 500 22 3 22 1 21 6 21 2 20 7 20 1 19 2 1000 21 8 21 4 21 0 20 3 20 2 19 6 18 7 2000 21 2 21 0 20 6 19 9 19 8 19 2 18 4 3750 20 8 20 6 20 2 19 6 19 4 188 17 9 7500 20 4 20 2 19 8 19 3 18 9 18 4 17 5 15 000 20 1 19 8 19 5 19 0 18 6 18 1 17 2 30 000 19 9 19 6 19 3 188 184 17 9 17 0 13 ADS1255 ADS1256 SBAS288D JUNE 2003 REVISED AUGUST 2004 INPUT MULTIPLEXER Figure 6 shows a simplified diagram of the input multiplexer This flexible block allows any analog input pin to be connected to either of
12. When using ADS1255 6 for single ended measurements it is important to note that common input AINCOM does not need to be tied to ground For example AINCOM can be tied to a midpoint reference such as 2 5V or even AVDD Sensor Detect Current Source Sensor Detect Current Source AINCOM O y AVDD AGND Input Multiplexer Figure 6 Simplified Diagram of the Input Multiplexer 14 d TEXAS INSTRUMENTS www ti com OPEN SHORT SENSOR DETECTION The sensor detect current sources SDCS provide a means to verify the integrity of the external sensor connected to the ADS1255 6 When enabled the SDCS supply a current Ispc of approximately 0 5uA 2A or 10uA to the sensor through the input multiplexer The SDCS bits in the ADCON register enable the SDCS and set the value of Ispc When the SDCS are enabled the ADS1255 6 automatically turns on the analog input buffer regardless of the BUFEN bit setting This is done to prevent the input circuitry from loading the SDCS AINp must stay below 3V to be within the absolute input range of the buffer To ensure this condition is met a 3V clamp will start sinking current from AINp to AGND if AINp exceeds 3V Note that this clamp is activated only when the SDCS are enabled Figure 7 shows a simplified diagram of ADS1255 6 input structure with the external sensor modeled as
13. of Population Percent of Population EES ouMnuowWnononownow Uess iess CO OO oO ot E oO oO LO Tt Oon ON es e EA e E E E E E E CO Ce CO CH ooo0oo0oooo EES Kee Ve ee e dee Tet dee ge TT Gain Error GAIN DRIFT HISTOGRAM GAIN DRIFT HISTOGRAM 90 Units from 3 Production Lots 90 Units from 3 Production Lots E xe Re 5 5 Sc Q Q o o a As e e be be KS E o o O O 2 8 o o a a Da AO T LOG N kee ac AC O Nro oa O Dm AO T OO N ee ac AC ONO O CO OO OO OO OO OO OO ee ee e e e ON o o 0 0 oO EN 0 0 N e gn rr rr e a age DN Gain Drift ppm C Gain Drift ppm C d TEXAS INSTRUMENTS www ti com TYPICAL CHARACTERISTICS continued ADS1255 ADS1256 SBAS288D JUNE 2003 REVISED AUGUST 2004 Ta 25 C AVDD 5V DVDD 1 8V foLKIN 7 68MHz PGA 1 and VREF 2 5V unless otherwise noted Percent of Population Percent of Population Percent of Population NOISE HISTOGRAM PGA 1 Data Rate 2 5SPS Buffer Off 256 Readings 5 4 3 2 1 0 1 2 3 4 5 Output Code LSB NOISE HISTOGRAM PGA 1 Data Rate 1kSPS Buffer Off 4096 Readings IN ie rrr Output Code LSB NOISE HISTOGRAM PGA 1 Data Rate 30kSPS Buffer Off 4096 Readings DOTNODHOTFTNONTODWDONTOWS errre e e GI E NN SET EE oo0oo0oo TWOOnN OD Output Code LSB 100 Percent of Population Percent of
14. of registers read will be one plus the second byte of the command If the count exceeds the remaining registers the addresses will wrap back to the beginning 1st Command Byte 0001 rrrrwhere rrrris the address of the first register to read 2nd Command Byte 0000 nnnn where nnnn is the number of bytes to read 1 See the Timing Characteristics for the required delay between the end of the RREG command and the beginning of shifting data on DOUT tg 0001 0001 X 0000 0001 1stCommand 2nd Command Byte Byte Figure 33 RREG Command Example Read Two Registers Starting from Register 01h multiplexer WREG Write to Register Description Write to the registers starting with the register specified as part of the command The number of registers that will be written is one plus the value of the second byte in the command 1st Command Byte 0101 rrrrwhere rrrris the address to the first register to be written 2nd Command Byte 0000 nnnn where nnnn is the number of bytes to be written 1 Data Byte s data to be written to the registers DIN 0101 0011 X 0000 0001 IO Data 1st Command 2nd Command Data Data Byte Byte Byte Byte Figure 34 WREG Command Example Write Two Registers Starting from 03h DRATE SELFCAL Self Offset and Gain Calibration Description Performs a self offset and self gain calibration The Offset Calibration Register OFC and Full Scale Calibration Register FSC are updated after this operation DRDY goe
15. the converter differential inputs That is any pin can be selected as the positive input AINp likewise any pin can be selected as the negative input AINN The pin selection is controlled by the multiplexer register The ADS1256 offers nine analog inputs which can be configured as four independent differential inputs eight single ended inputs or a combination of differential and single ended inputs The ADS1255 offers three analog inputs which can be configured as one differential input or two single ended inputs When using the ADS1255 and programming the input make sure to select only the available inputs when programming the input multiplexer register In general there are no restrictions on input pin selection d TEXAS INSTRUMENTS www ti com However for optimum analog performance the following recommendations are made 1 For differential measurements use AINO through AIN7 preferably adjacent inputs For example use AINO and AIN1 Do not use AINCOM 2 For single ended measurements use AINCOM as common input and AINO through AIN7 as single ended inputs 3 Leave any unused analog inputs floating This minimizes the input leakage current ESD diodes protect the analog inputs To keep these diodes from turning on make sure the voltages on the input pins do not go below AGND by more than 100mV and likewise do not exceed AVDD by more than 100mV 100mV lt AINO 7 and AINCOM lt AVDD 100mV
16. 0 0 ADSI 0 0 ADS1255 frore Tones Instruments oD ADS1256 SBAS288D JUNE 2003 REVISED AUGUST 2004 Very Low Noise 24 Bit Analog to Digital Converter FEATURES DESCRIPTION e 24 Bits No Missing Codes The ADS1255 and ADS1256 are extremely low noise All Data Rates and PGA Settings 24 bit analog to digital A D converters They provide complete high resolution measurement solutions for the Up to 23 Bits Noise Free Resolution most demanding applications 0 0010 Nonlinearity max The converter is comprised of a 4th order delta sigma Data Output Rates to 30kSPS AZ modulator followed by a programmable digital filter A Fast Channel Cycling flexible input multiplexer handles differential or 18 6 Bits Noise Free 21 3 Effective Bits single ended signals and includes circuitry to verify the at 1 45kHz integrity of the external sensor connected to the inputs i The selectable input buffer greatly increases the input s One Shot Conversions with Single Cycle impedance and the low noise programmable gain Settling amplifier PGA provides gains from 1 to 64 in binary steps Flexible Input Multiplexer with Sensor Detect The programmable filter allows the user to optimize Four Differential Inputs ADS1256 only between a resolution of up to 23 bits noise free and a data Eight Single Ended Inputs ADS1256 only rate of up to 30k samples per second SPS The Chopper Stabilized Input Buffer conve
17. 0SPS 30SPS 15SPS 10SPS 5SPS or 2 5SPS will further improve the common mode rejection of this frequency 6 The reference input range with Buffer on is restricted only if self calibration or gain self calibration is to be used If using system calibration or writing calibration values directly to the registers the entire Buffer off range can be used d TEXAS INSTRUMENTS www ti com AVDD D1 AGND DO CLKOUT VREFN SCLK VREFP DIN AINCOM DOUT AINO DRDY AIN1 ts SYNC PDWN XTAL1 CLKIN RESET XTAL2 DVDD DGND ADS1255 ADS1256 SBAS288D JUNE 2003 REVISED AUGUST 2004 PIN ASSIGNMENTS SSOP PACKAGE AVDD D3 TOP VIEW AGND D2 VREFN D1 VREFP DO CLKOUT AINCOM SCLK AINO DIN AIN1 DOUT PS ADS1256 AIN3 cs AIN4 XTAL1 CLKIN AIN5 XTAL2 AING DGND AIN7 DVDD SYNC PDWN RESET Terminal Functions TERMINAL NO ANALOG DIGITAL NAME ADS1255 ADS1256 INPUT OUTPUT DESCRIPTION AIN2 Analog input Analog input 2 Analog input Analog input 3 AIN4 10 Analog input Analog input 4 AIN5 11 Analog input Analog input 5 AING Analog input Analog input 6 XTALI CEKIN Digital 3 Crystal oscillator connection Digital Digital input 2 Crystal oscillator connection external clock input Se input 1 2 active low Chip select SCH Schmitt Trigger digital input 5V tolerant digital input Digital 10 4 Digital Det E 2 3 Leave disconnected if external clock input is applied to XTA
18. 13 8ms 2 5 1227 2ms NOTE For fCLKIN 7 68MHz 25 ADS1255 ADS1256 SBAS288D JUNE 2003 REVISED AUGUST 2004 System Calibration System calibration corrects both internal and external offset and gain errors using the SYSOCAL and SYSGCAL commands During system calibration the appropriate calibration signals must be applied by the user to the inputs SYSOCAL performs a system offset calibration The user must supply a zero input differential signal The ADS1255 6 then computes a value that will nullify the offset in the system Table 22 shows the time required for system offset calibration for the different data rate settings Note this timing is the same for the self offset calibration System offset calibration updates the OFC register SYSGCAL performs a system gain calibration The user must supply a full scale input signal to the ADS1255 6 The ADS1255 6 then computes a value to nullify the gain error in the system System gain calibration can correct inputs that are 80 of the full scale input voltage and larger Make sure not to exceed the full scale input voltage when using system gain calibration Table 22 shows the time required for system gain calibration for the different data rate settings System gain calibration updates the FSC register Table 22 System Gain Calibration Timing Tee SYSTEM GAIN CALIBRATION TIME 30 000 417us 15 000 484us 7500 617us 3750 884
19. 256 only 0100 AIN4 ADS1256 only 0101 AIN5 ADS1256 only 0110 AIN6 ADS1256 only 0111 AIN7 ADS1256 only 1xxx AINCOM when NSEL3 1 NSEL2 NSEL1 NSELO are don t care NOTE When using an ADS1255 make sure to only select the available inputs ADCON A D Control Register Address 02h Reset Value 20h BIT7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 i a CLK1 CLKO SDCS1 SDCSO PGA2 PGAt PGAO Bit7 Reserved always 0 Read Only Bits 6 5 CLK1 CLKO DO CLKOUT Clock Out Rate Setting 00 Clock Out OFF 01 Clock Out Frequency Jet em default 10 Clock Out Frequency fo kl 11 Clock Out Frequency fo Kin 4 When not using CLKOUT it is recommended that it be turned off These bits can only be reset using the RESET pin Bits 4 2 SDCS1 SCDSO Sensor Detect Current Sources 00 Sensor Detect OFF default 01 Sensor Detect Current 0 5uA 10 Sensor Detect Current 2uA 11 Sensor Detect Current 10uA The Sensor Detect Current Sources can be activated to verify the integrity of an external sensor supplying a signal to the ADS1255 6 A shorted sensor produces a very small signal while an open circuit sensor produces a very large signal Bits 2 0 PGA2 PGA1 PGAO Programmable Gain Amplifier Setting 000 1 default 31 ADS1255 ii ADS1256 We Texas s www ti com SBAS288D JUNE 2003 REVISED AUGUST 2004 DRATE A D Data Rate Address 03h Reset Value FOh BIT7 BIT 6 BIT5 BIT 4 BIT
20. 3 BIT 2 BIT 1 BIT O DR7 Dpp DR5 DR4 DR3 DR2 DR1 The 16 valid Data Rate settings are shown below Make sure to select a valid setting as the invalid settings may produce unpredictable results Bits 7 0 DR 7 0 Data Rate Setting 11110000 30 000SPS default 11100000 15 000SPS 11010000 7 500SPS 11000000 3 750SPS 10110000 2 000SPS 10100001 1 000SPS 10010010 500SPS 10000010 100SPS 01110010 60SPS 01100011 50SPS 01010011 30SPS 01000011 25SPS 00110011 15SPS 00100011 10SPS 00010011 5SPS 00000011 2 5SPS 1 for fCLKIN 7 68MHz Data rates scale linearly with fCLKIN I O GPIO Control Register Address 044 Reset Value EOh BIT7 BIT 6 BIT5 BIT 4 BIT3 BIT 2 BIT 1 BITO DIR3 DIR2 DIR1 DRO DIO3 DIO2 DIO1 Don The states of these bits control the operation of the general purpose digital I O pins The ADS1256 has 4 I O pins D3 D2 D1 and DO CLKOUT The ADS1255 has two digital I O pins D1 and DO CLKOUT When using an ADS1255 the register bits DIR3 DIR2 DIO3 and DIO2 can be read from and written to but have no effect Bit7 DIR3 Digital I O Direction for Digital I O Pin D3 used on ADS1256 only 0 D3 is an output 1 D3 is an input default Bit6 DIR2 Digital I O Direction for Digital I O Pin D2 used on ADS1256 only 0 D2 is an output 1 D2 is an input default Bit5 DIR1 Digital I O Direction for Digital I O Pin D1 0 D1 is an output 1 D1 is an input default DI A DIRO Di
21. 4 Hi A VV i Nn WAN 10 15 20 25 30 35 40 45 50 55 60 Frequency Hz Figure 15 Frequency Response for Data Rate 2 5SPS Table 12 First Notch Frequency and 3dB Filter Bandwidth DATA RATE FIRST NOTCH 3dB BANDWIDTH SPS Hz Hz 30 000 30 000 6106 15 000 15 000 4807 7500 7500 3003 3750 3750 1615 2000 2000 878 1000 1000 441 500 500 221 100 100 44 2 60 1 60 26 5 50 2 50 22 1 30 1 30 13 3 25 2 25 11 1 150 15 6 63 10 3 10 4 42 5 3 5 2 21 NOTE fCLKIN 7 68MHz 1 Notch at 60Hz 2 Notch at 50Hz 3 Notch at 50Hz and 60Hz The digital filter low pass characteristic repeats at multiples of the modulator rate of fo_Kin 4 Figure 16 and Figure 17 show the responses plotted out to 7 68MHz at the data rate extremes of 30KSPS and 2 5SPS Notice how the responses near DC 1 92MHz 3 84MHz 19 ADS1255 ADS1256 SBAS288D JUNE 2003 REVISED AUGUST 2004 5 76MHz 7 68MHz are the same The digital filter will attenuate high frequency noise on the ADS1255 6 inputs up to the frequency where the response repeats If significant noise on the inputs is present above this frequency make sure to remove with external filtering Fortunately this can be done on the ADS1255 6 with a simple RC filter as shown in the Applications Section see Figure 25 f 30kSPS DATA LG Gem 7 68MHz
22. 5V 8 0 625V 16 312 5mV 32 156 25mV 64 78 125mV The PGA is controlled by the ADCON register Recalibrating the A D converter after changing the PGA setting is recommended The time required for self calibration is dependent on the PGA setting See the Calibration section for more details The analog current and input impedance when the buffer is disabled vary as a function of PGA setting MODULATOR INPUT CIRCUITRY The ADS1255 6 modulator measures the input signal using internal capacitors that are continuously charged and discharged Figure 9 shows a simplified schematic of the ADS1255 6 input circuitry with the input buffer disabled Figure 10 shows the on off timings of the switches of Figure 9 S1 switches close during the input sampling phase With S1 closed Ca charges to AINp Cao charges to AINy and Cg charges to AINp AINn For the discharge phase S1 opens first and then S2 closes Ca and Cas discharge to approximately AVDD 2 and Ce discharges to OV This two phase sample discharge cycle 16 da TEXAS INSTRUMENTS www ti com repeats with a period of tsampce This time is a function of the PGA setting as shown in Table 9 along with the values of the capacitor Ca Cao Ca and Cpg AVDD 2 oO O AVDD 2 Figure 9 Simplified Input Structure with Buffer Off T sample Figure 10 S1 and S2 Switch Timing for Figure 9 Table 9 d Sampling Time tSAMPLE and Ca and Cp vs P
23. ANDBY Command Sequence WAKEUP Complete Synchronization or Exit Standby Mode Description Used in conjunction with the SYNC and STANDBY commands Two values all zeros or all ones are available for this command RESET Reset Registers to Default Values Description Returns all registers except the CLKO and CLK1 bits in the ADCON register to their default values This command will also stop the Read Continuous mode in this case issue the RESET command after DRDY goes low 37 MECHANICAL DATA MSSO002E JANUARY 1995 REVISED DECEMBER 2001 DB R PDSO G PLASTIC SMALL OUTLINE 28 PINS SHOWN Ze Gage Plane 4 0 A Seating Plane 2 00 MAX 0 05 MIN Be DAD PINS 4040065 E 12 01 NOTES A All linear dimensions are in millimeters This drawing is subject to change without notice Body dimensions do not include mold flash or protrusion not to exceed 0 15 Falls within JEDEC MO 150 gow d TEXAS INSTRUMENTS POST OFFICE BOX 655303 DALLAS TEXAS 75265 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries Tl reserve the right to make corrections modifications enhancements improve
24. D 0 2 DVDD V VOH IOH 5MA 0 8 DVDD V VOL IOL 5mA 0 2 DVDD V Input hysteresis 0 5 V Input leakage 0 lt VDIGITAL INPUT lt DVDD 10 uA External crystal between XTAL1 and 2 7 68 10 MHz Master clock rate XTAL2 External oscillator driving CLKIN 0 1 7 68 10 MHz ADS1255 ii ADS1256 We Texas s www ti com SBAS288D JUNE 2003 REVISED AUGUST 2004 ELECTRICAL CHARACTERISTICS continued All specifications at 40 C to 85 C AVDD 5V DVDD 1 8V fCLKIN 7 68MHz PGA 1 and VREF 2 5V unless otherwise noted PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Power Supply AVDD 4 75 5 25 V DVDD 1 8 3 6 V Power down mode 2 uA Standby mode 20 uA Normal mode PGA 1 Buffer off 7 10 mA AVDD ren Normal mode PGA 64 Buffer off 16 22 mA Normal mode PGA 1 Buffer on 13 19 mA Normal mode PGA 64 Buffer on 36 50 mA Power down mode 2 uA Standby mode CLKOUT off 95 uA DVDD current DVDD 3 3V Ge CLKOUT off 0 9 2 mA Normal mode PGA 1 Buffer off Power dissipation DVDD 3 3V SS e Standby mode DVDD 3 3V 0 4 mW Temperature Range Specified A0 85 C Operating 40 105 C Storage DO 150 C 1 See text for more information on input impedance 2 SPS samples per second 3 FSR full scale range 4VREF PGA 4 fom is the frequency of the common mode input signal 5 Placing a notch of the digital filter at 60Hz setting fpATA 6
25. GA 1 fCLKIN 4 521ns 2 T 2 2 fCLKIN 4 521ns 4 2pF 4 9pF 4 fCLKIN 4 521ns 8 3pF 9 7pF 8 fCLKIN 4 521ns 17pF 19pF 16 fCLKIN 4 521ns 33pF 39pF 32 fCLKIN 2 260ns 33pF 39pF 64 fCLKIN 2 260ns 33pF 39pF 1 TSAMPLE for fCLKIN 7 68MHz d TEXAS INSTRUMENTS www ti com The charging of the input capacitors draws a transient current from the sensor driving the ADS1255 6 inputs The average value of this current can be used to calculate an effective impedance Zerr where Zerr Vin lavERAGE Figure 11 shows the input circuitry with the capacitors and switches of Figure 9 replaced by their effective impedances These impedances scale inversely with the CLKIN frequency For example if fo_Kin is reduced by a factor of two the impedances will double They also change with the PGA setting Table 10 lists the effective impedances with the buffer off for fe_Kin 7 68MHz AVDD 2 oO d Zelt Tsampce Ca AINp Zeffs T sampLe Cs Multiplexer AINy Zeff T sampLe Ca O AVDD 2 Figure 11 Analog Input Effective Impedances with Buffer Off Table 10 Analog Input Impedances with Buffer Off PGA ZeffA Zeffg SETTING kQ kQ 1 260 220 2 130 110 4 65 55 8 33 28 16 16 14 32 8 7 64 8 7 NOTE fCLKIN 7 68MHz VOLTAGE REFERENCE INPUTS VREFP VREFN The voltage reference for the ADS1255 6 A D converter is the differential voltage between
26. L1 CLKIN 4 Schmitt Trigger digital input when the digital I O is configured as an input ADS1255 ii ADS1256 We Texas s www ti com SBAS288D JUNE 2003 REVISED AUGUST 2004 PARAMETER MEASUREMENT INFORMATION gt L Le La t gt ty ts Figure 1 Serial Interface Timing TIMING CHARACTERISTICS FOR FIGURE 1 SYMBOL DESCRIPTION MIN MAX UNIT t SCLK period 4 TCLKIN perio 10 tpata 2 r 200 ns 2H SCLK pulse width high fom tol SCLK pulse width low 200 ns Valid DIN to SCLK falling edge setup time Valid DIN to SCLK falling edge hold time t Delay from last SCLK edge for DIN to first SCLK rising edge for DOUT RDATA RDATAC 50 P 6 RREG Commands CLKIN t 50 n SCLK rising edge to valid new DOUT propagation delay 4 s SCLK rising edge to DOUT invalid hold time 0 n Last SCLK falling edge to DOUT high impedance 1 NOTE DOUT goes high impedance immediately when CS goes high CLKIN CS low after final SCLK falling edge 0 Im rising edge of next command RDATAC STANDBY SELFOCAL SY SOCAL SELFGCAL Wait for DRDY to go low SYSGCAL SELFCAL cs i RREG WREG RDATA t Final SCLK falling edge of command to first SCLK REARS RESET SYNC 1 tCLKIN master clock period UCL KN 2 para output data period 1 fpaTa 3 CS can be tied low 4 DOUT load 20pF 100k to DGND ADS1255 i MB Texas ADS1256 www ti com SBAS288D JUNE 2003 REVISED AUGUST 2004
27. OF foLkin 4 using CLK1 and CLKO in the ADCON register Note that enabling the output clock and driving an external load will increase the digital power dissipation Standby mode does not affect the clock output status That is if Standby is enabled the clock output will continue to run during Standby mode If the clock output function is not needed it should be disabled by writing to the ADCON register after power up or reset CLOCK GENERATION The master clock source for the ADS1255 6 can be provided using an external crystal or clock generator When the clock is generated using a crystal external capacitors must be provided to ensure start up and a stable clock frequency as shown in Figure 22 Table 17 lists two recommended crystals Long leads should be minimized with the crystal placed close to the ADS1255 6 pins For information on ceramic resonators see application note SBAA104 Using Ceramic Resonators with the ADS1255 6 available for download at www ti com CH XTAL1 CLKIN 1 Figure 22 Crystal Connection Table 17 Recommended Crystals PART NUMBER Citizen 7 68MHz CIA 53383 ECS 8 0MHz ECS 80 5 4 When using a crystal neither the XTAL1 CLKIN nor XTAL2 pins can be used to drive any other logic If other devices need a clock source the DO CLKOUT pin is available for this function When using an external clock generator supply the clock signal to XTAL1 CLKIN and leave XTAL2 floating Make sure th
28. Population Percent of Population PGA 64 Data Rate NOISE HISTOGRAM Buffer Off 256 Readings 2 5SPS PGA 64 Data Rate 1kSPS NOMHDTNONTDDONTODMSO SC 7 orr IN WW kee Output Code LSB NOISE HISTOGRAM Buffer Off 4096 Readings PGA 64 Data Rate NOISE HISTOGRAM Buffer Off 30kSPS 4096 Readings Output Code LSB ADS1255 ii ADS1256 We Texas s www ti com SBAS288D JUNE 2003 REVISED AUGUST 2004 TYPICAL CHARACTERISTICS continued Ta 25 C AVDD 5V DVDD 1 8V foLKIN 7 68MHz PGA 1 and VREF 2 5V unless otherwise noted EFFECTIVE NUMBER OF BITS EFFECTIVE NUMBER OF BITS vs INPUT VOLTAGE vs TEMPERATURE 23 Data Rate 1kSPS Data Rate 1kSPS 22 eee a e a a Rate 30k 5 ta Rate 30kS Z PAAA Z 20 19 18 0 05 10 15 20 25 30 35 40 45 50 50 30 10 10 30 50 70 90 110 Input Voltage Vn V Temperature C INTEGRAL NONLINEARITY vs INPUT SIGNAL INTEGRAL NONLINEARITY vs PGA T Buffer o Ww Ki 5 5 gt z Z Buffer On 1 2 4 8 16 32 64 Input Voltage Vn V PGA Setting ANALOG SUPPLY CURRENT vs TEMPERATURE ANALOG SUPPLY CURRENT vs PGA PGA 64 Buffer On T T E E
29. T pins into and out of the ADS1255 6 Even though the input has hysteresis it is recommended to keep SCLK as clean as possible to prevent glitches from accidentally shifting the data If SCLK is held low for 32 DRDY periods the serial interface will reset and the next SCLK pulse will start a new communication cycle This timeout feature can be used to recover communication when a serial interface transmis sion is interrupted A special pattern on SCLK will reset the chip see the RESET section for more details on this procedure DATA INPUT DIN AND DATA OUTPUT DOUT The data input pin DIN is used along with SCLK to send data to the ADS1255 6 The data output pin DOUT along with SCLK is used to read data from the ADS1255 6 Data on DIN is shifted into the part on the falling edge of SCLK while data is shifted out on DOUT on the rising edge of SCLK DOUT is high impedance when not in use to allow DIN and DOUT to be connected together and be driven by a bi directional bus Note the RDATAC command must not be issued while DIN and DOUT are connected together d TEXAS INSTRUMENTS www ti com DATA READY DRDY The DRDY output is used as a status signal to indicate when conversion data is ready to be read DRDY goes low when new conversion data is available It is reset high when all 24 bits have been read back using Read Data RDATA or Read Data Continuous RDATAC command It also goes high when the new conversion data is be
30. VREFP and VREFN Vrer VREFP VREFN The reference inputs use a structure similar to that of the analog inputs with the circuitry on the reference inputs of Figure 12 The load presented by the switched capacitor can be modeled with an effective impedance Zepp of 18 5kQ2 for fcLk in 7 68MHz The temperature coefficient of the effective impedance of the voltage reference inputs is approximately 35ppm C ADS1255 ADS1256 SBAS288D JUNE 2003 REVISED AUGUST 2004 VREFP VREFN Self Gain Calibration 1 forku 7 68MHz Figure 12 Simplified Reference Input Circuitry ESD diodes protect the reference inputs To keep these diodes from turning on make sure the voltages on the reference pins do not go below AGND by more than 100mV and likewise do not exceed AVDD by 100mV 100mV lt VREFP or VREFN lt AVDD 100mV During self gain calibration all the switches in the input multiplexer are opened VREFN is internally connected to AINy and VREFP is connected to AINp The input buffer may be disabled or enabled during calibration When the buffer is disabled the reference pins will be driving the circuitry shown in Figure 9 during self gain calibration resulting in increased loading To prevent this additional loading from introducing gain errors make sure the circuitry driving the reference pins has adequate drive capability When the buffer is enabled the loading on the reference pi
31. andby mode to begin a one shot conversion Following the settling time t48 DRDY will go low indicating that the conversion is complete and data can be read using the RDATA command The ADs1255 6 settles in a single cycle there is no need to ignore or discard data Following the data read cycle issue another STANDBY command to reduce power consumption When ready for the next measurement repeat the cycle starting with another WAKEUP command Settling Time while Continuously Converting After a synchronization input multiplexer change or wakeup from Standby mode the ADS1255 6 will continuously convert the analog input The conversions coincide with the falling edge of DRDY While continuously converting it is often more convenient to consider settling times in terms of DRDY periods as shown in Table 15 The DRDY period equals the inverse of the data rate If there is a step change on the input signal while continuously converting performing a synchronization operation to start a new conversion is recommended Otherwise the next data will represent a combination of ADS1255 6 d TEXAS INSTRUMENTS www ti com the previous and current input signal and should therefore be discarded Figure 21 shows an example of readback in this situation Table 15 Data Settling Delay vs Data Rate DATA RATE SETTLING TIME SPS DRDY Periods 30 000 15 000 oa 7500 3750 2000 1000 500 100
32. ddress 08h Reset value depends on calibration results BIT7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 FSC07 FSC06 FSC05 FSC04 FSC03 FSC02 FSCO1 FSC00 FSC1 Full scale Calibration Byte 1 Address 09h Reset value depends on calibration results BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 FSC15 FSC14 FSC13 FSC12 FSC11 FSC10 FSC09 FSC08 FSC2 Full scale Calibration Byte 2 most significant byte Address 0Ah Reset value depends on calibration results BIT 7 BIT 6 BIT5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 FSC23 FSC22 FSC21 FSC20 FSC19 FSC18 FSC17 FSC16 33 ADS1255 ADS1256 We Texas s www ti com SBAS288D JUNE 2003 REVISED AUGUST 2004 COMMAND DEFINITIONS The commands summarized in Table 24 control the operation of the ADS1255 6 All of the commands are stand alone except for the register reads and writes RREG WREG which require a second command byte plus data Additional command and data bytes may be shifted in without delay after the first command byte The ORDER bit in the STATUS register sets the order of the bits within the output data CS must stay low during the entire command sequence Table 24 Command Definitions COMMAND DESCRIPTION 1ST COMMAND BYTE 2ND COMMAND BYTE WAKEUP Completes SYNC and Exits Standby Mode 0000 0000 00h RDATA Read Data 0000 0001 Oth RDATAC Read Data Continuously 0000 0011 03h SDATAC Stop Read Data Continuously 0000 1111 OFh RREG Read fr
33. e averager 1st order sinc filter with the number of averages set by the DRATE register The data rate is a function of the number of averages Num_Ave and is given by Equation 1 Joan 1 Data Rata KE Num Ave 1 Modulator Rate fCLKIN 4 Analog d Modulato Programmable Averager Num_Ave set by DRATE Digital Filter Figure 13 Block Diagram of the Analog Modulator and Digital Filter 18 d TEXAS INSTRUMENTS www ti com Table 11 shows the averaging and corresponding data rate for each of the 16 valid DRATE register settings when foLKIN 7 68MHz Note that the data rate scales directly with the CLKIN frequency For example reducing fcLKIN from 7 68MHz to 3 84MHz reduces the data rate for DR 7 0 11110000 from 30 000SPS to 15 000SPS Table 11 Number of Averages and Data Rate for Each Valid DRATE Register Setting NUMBER OF AVERAGES FOR 1 PRATE PROGRAMMABLE FILTER DATA RATE DR 7 0 Niri Ate SPS 11110000 1 averager bypassed 30 000 11100000 2 15 000 11010000 4 7500 11000000 8 3750 10110000 15 2000 10100001 30 1000 10010010 60 500 10000010 300 100 01110010 500 60 01100011 600 50 01010011 1000 30 01000011 1200 25 00110011 2000 15 00100011 3000 10 00010011 6000 5 00000011 12 000 2 5 1 for fe ei 7 68MHz da TEXAS INSTRUMENTS www ti com FREQUENCY RESPONSE The low pass digital filter sets the overall frequency respons
34. e external clock generator supplies a clean clock waveform Overshoot and glitches on the clock will degrade overall performance MANUFACTURER FREQUENCY 23 ADS1255 ADS1256 SBAS288D JUNE 2003 REVISED AUGUST 2004 CALIBRATION Offset and gain errors can be minimized using the ADS1255 6 onboard calibration circuitry Figure 23 shows the calibration block diagram Offset errors are corrected with the Offset Calibration OFC register and likewise full scale errors are corrected with the Full Scale Calibration FSC register Each of these registers is 24 bits and can be read from or written to VREFP VREFN Analog Digital Modulator Filter CC C9 Output OFC FSC Register Register Figure 23 Calibration Block Diagram The output of the ADS1255 6 after calibration is shown in Equation 3 d TEXAS INSTRUMENTS www ti com PGA Vy 2V REF Output lk p where o and D vary with data rate settings shown in Table 18 along with the ideal values assumes perfect analog performance for OFC and FSC OFC is a Binary Two s Complement number that can range from 8 388 608 to 8 388 607 while FSC is unipolar ranging from 0 to 16 777 215 The ADS1255 6 supports both self calibration and system calibration for any PGA setting using a set of five commands SELFOCAL SELFGCAL SELFCAL SYSOCAL and SYSGCAL Calibration can be done at any time though in many applications the ADS1255 6 drift perfor
35. e for the ADS1255 6 The filter response is the product of the responses of the fixed and programmable filter sections and is given by Equation 2 H A H ll enee fl 5 2567 f H 256x Num_Ave f sin i sin TCLKIN 2 Joen 64 sin fe Num Ave sin 22 The digital filter attenuates noise on the modulator output including noise from within the ADS1255 6 and external noise present on the ADS1255 6 input signal Adjusting the filtering by changing the number of averages used in the programmable filter changes the filter bandwidth With a higher number of averages bandwidth is reduced and more noise is attenuated The low pass filter has notches or zeros at the data output rate and multiples thereof At these frequencies the filter has zero gain This feature can be useful when trying to eliminate a particular interference signal For example to eliminate 60Hz and the harmonics pickup set the data rate equal to 2 5SPS 5SPS 10SPS 15SPS 30SPS or 60SPS To help illustrate the filter characteristics Figure 14 and Figure 15 show the responses at the data rate extremes of 30kSPS and 2 5SPS respectively Table 12 summarizes the first notch frequency and 3dB bandwidth for the different data rate settings foara 30kSPS 45 60 7 Frequency kHz Figure 14 Frequency Response for Data Rate 30kSPS ADS1255 ADS1256 SBAS288D JUNE 2003 REVISED AUGUST 200
36. e is 2Vpepf for PGA 1 The digital filter receives the modulator signal and provides a low noise digital output The data rate of the filter is programmable from 2 5SPS to 30kKSPS and allows tradeoffs between resolution and speed Communication is done over an SPl compatible serial interface with a set of simple commands providing control of the ADS1255 6 Onboard registers store the various settings for the input multiplexer sensor detect current sources input buffer enable PGA setting data rate etc Either an external crystal or clock oscillator can be used to provide the clock source General purpose digital I Os provide static read write control of up to four pins One of the pins can also be used to supply a programmable clock output VREFP VREFN Input Multiplexer and Sensor Detect Converter Clock E XTAL1 CLKIN Generator XTAL2 Programmable Modulator Digital Filter RESET Control Doo SYNC PDWN General Purpose Digital UO za O O O O D3 D2 D1 DO CLKOUT ADS1256 Figure 5 Block Diagram 11 ADS1255 ADS1256 SBAS288D JUNE 2003 REVISED AUGUST 2004 d TEXAS INSTRUMENTS www ti com NOISE PERFORMANCE The ADS1255 6 offer outstanding noise performance that can be optimized by adjusting the data rate or PGA setting As the averaging is increased by reducing the data rate the noise drops correspondingly The PGA reduces the
37. eing used ADS1255 D1 DO CLKOUT SCLK DIN cs XTAL2 7 68MHz A DGND Figure 25 ADS1255 Basic Connections 28 d TEXAS INSTRUMENTS www ti com DIGITAL INTERFACE CONNECTIONS The ADS1255 6 5V tolerant GPL QSPI and MICROWIRE compatible interface easily connects to a wide variety of microcontrollers Figure 26 shows the basic connection to Te MSP430 family of low power microcontrollers Figure 27 shows the connection to microcontrollers with an SPI interface like le MSC12xx family or the 68HC11 family Note that the MSC12xx includes a high resolution A D converter the ADS1255 6 can be used to add additional channels of measurement or provide higher speed conversions Finally Figure 28 shows how to connect the ADS1255 6 to an 8xC51 UART in serial mode 0 in a 2 wire configuration Avoid using the continuous read mode RDATAC when DIN and DOUT are connected together ADS1255 MSP430 ADS1256 1 CS may be tied low Figure 26 Connection to MSP430 Microcontroller ADS1255 ADS1256 SBAS288D JUNE 2003 REVISED AUGUST 2004 ADS1255 MSC1 2xx or ADS1256 68HC11 1 GS may be tied low Figure 27 Connection to Microcontrollers with an SPI Interface ADS1255 ADS1256 P3 0 RXD P3 1xTXD Figure 28 Connection to 8xC51 Microcontroller UART with a 2 Wire Interface 29 ADS1255 ii ADS1256 We Texas s www ti com SBAS288D
38. ersion process by issuing a SYNC command immediately followed by a WAKEUP command Make sure to follow timing specification tj between commands Step 3 Read the data from the previous conversion using the RDATA command Step 4 When DRDY goes low again repeat the cycle by first updating the multiplexer register then reading the previous data ADS1255 ADS1256 SBAS288D JUNE 2003 REVISED AUGUST 2004 Table 14 gives the effective overall throughput 1 t19 when cycling the input multiplexer The values for throughput 1 t19 assume the multiplexer was changed with a 3 byte WREG command and fscLK fcLKIN 4 Table 14 Multiplexer Cycling Throughput DATA RATE CYCLING THROUGHPUT 1 t19 SPS Hz 30 000 4374 15 000 3817 7500 3043 3750 2165 2000 1438 1000 837 500 456 100 98 60 59 50 50 30 30 25 25 15 15 10 10 5 5 Data from MUX 01h MUX Oth 23h Register AINp AINO AINy AINy AINp AIN2 AINy AIN3 WREG 45h to MUX reg SYNC WAKEUP RDATA Data from AINp AIN4 AINy AINS Figure 19 Cycling the ADS1256 Input Multiplexer 21 ADS1255 ADS1256 SBAS288D JUNE 2003 REVISED AUGUST 2004 Seitling Time Using One Shot Mode A dramatic reduction in power consumption can be achieved in the ADS1255 6 by performing one shot conversions using the STANDBY command the sequence for this is shown in Figure 20 Issue the WAKEUP command from St
39. espective owners PRODUCTION DATA information is current as of publication date Products i conform to specifications per the terms of Texas Instruments standard warranty TEXAS Production processing does not necessarily include testing of all parameters IN STRUMENTS www ti com Copyright 2003 2004 Texas Instruments Incorporated ADS1255 An ADS1256 INSTRUMENTS www ti com SBAS288D JUNE 2003 REVISED AUGUST 2004 ORDERING INFORMATION PACKAGE PACKAGE TRANSPORT MEDIA SR m ADS1255IDBT Tape and Reel 250 ADS1295 SEH BEE ADS1255IDBR Tape and Reel 1000 b D ADS1256IDBT Tape and Reel 250 ADS1296 SE EE ADS1256IDBR Tape and Reel 1000 For the most current package and ordering information refer to our web site at www ti com A This integrated circuit can be damaged by ESD Texas ABSOLUTE MAXIMUM RATINGS p 4 A Instruments recommends that all integrated circuits be over operating free air temperature range unless otherwise noted 1 Ata handled with appropriate precautions Failure to observe Po ADS1255 ADS1256 UNIT proper handling and installation procedures can cause damage AVDD to AGND 0 3 to 6 v ESD damage can range from subtle performance degradation to DVDD to DGND 0 3 to 3 6 V complete device failure Precision integrated circuits may be more AGND to DGND 0 3 to 40 3 y susceptible to damage because very small parametric changes could cause the device not to meet its p
40. f during self gain calibration Otherwise use system gain calibration or write the gain coefficients directly to the FSC register Table 20 shows the time required for self gain calibration for the different data rate and PGA settings Self gain calibration updates the FSC register ADS1255 ADS1256 SBAS288D JUNE 2003 REVISED AUGUST 2004 Table 20 Self Gain Calibration Timing DATA RATE PGA SETTING SPS A 3750 884 2000 1 4ms 1000 2 4ms 500 4 5ms 100 21 0ms 60 34 1ms 50 41 7ms 30 67 8ms 25 83 0ms 15 135 3ms 10 207 0ms 5 413 7ms 2 5 827 0ms NOTE For fCLKIN 7 68MHZz SELFCAL performs first a self offset and then a self gain calibration The analog inputs are disconnected from the from the signal source during self calibration When using the input buffer with self calibration make sure to observe the common mode range of the reference inputs as described above Table 21 shows the time required for self calibration for the different data rate settings Self calibration updates both the OFC and FSC registers Table 21 Self Calibration Timing SPS 30 000 596us 596us 692us 696us 892us 15 000 696us 696us 696us 762us 896us 7500 896us 896us 896us 896us 1029us 3750 1 3ms 2000 2 0ms 1000 3 6ms 500 6 6ms 100 31 2ms 60 50 9ms 50 61 8ms 30 101 3ms 25 123 2ms 15 202 1ms 10 307 2ms 5 6
41. ffset calibration The analog inputs AINp and AINy are disconnected from the signal source and connected to AVDD 2 See Table 19 for the time required for self offset calibration for the different data rate settings As with most of the ADS1255 6 timings the calibration time scales directly with Tv Self offset calibration updates the OFC register Table 19 Self Offset and System Offset Calibration Timing DATA RATE SELF OFFSET CALIBRATION AND SPS SYSTEM OFFSET CALIBRATION TIME 30 000 387s 15 000 453s 7500 587us 3750 853s 2000 1 3ms 1000 2 3ms 500 4 3ms 100 20 3ms 60 33 7ms 50 40 3ms 30 67 0ms 25 80 3ms 15 133 7ms 10 200 3ms 5 400 3ms 2 5 800 3ms NOTE For fCLKIN 7 68MHz SELFGCAL performs a self gain calibration The analog inputs AINp and AINy are disconnected from the signal source and AINp is connected internally to VREFP while AINwn is connected to VREFN Self gain calibration can be used with any PGA setting and the ADS1255 6 has excellent gain calibration even for the higher PGA settings as shown in the Typical Characteristics section Using the buffer will limit the common mode range of the reference inputs during self gain calibration since they will be connected to the buffer inputs and must be within the specified analog input range When the voltage on VREFP or VREFN exceeds the buffer analog input range AVDD 2 0V the buffer must be turned of
42. first Output data is always shifted out most significant byte first The ORDER bit only controls the bit order of the output data within the byte Bit2 ACAL Auto Calibration 0 Auto Calibration Disabled default 1 Auto Calibration Enabled When Auto Calibration is enabled self calibration begins at the completion of the WREG command that changes the PGA bits 0 2 of ADCON register DR bits 7 0 in the DRATE register or BUFEN bit 1 in the STATUS register values Bit 1 BUFEN Analog Input Buffer Enable 0 Buffer Disabled default 1 Buffer Enabled BitO DRDY Data Ready Read Only This bit duplicates the state of the DRDY pin 30 ADS1255 i MO Texas ADS1256 www ti com SBAS288D JUNE 2003 REVISED AUGUST 2004 MUX Input Multiplexer Control Register Address 01h Reset Value 01h BIT 7 BIT 6 BIT5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 Bits 7 4 PSEL3 PSEL2 PSEL1 PSELO Positive Input Channel AINp Select 0000 AINO default 0001 AIN1 0010 AIN2 ADS1256 only 0011 AIN3 ADS1256 only 0100 AIN4 ADS1256 only 0101 AIN5 ADS1256 only 0110 AIN6 ADS1256 only 0111 AIN7 ADS1256 only 1xxx AINCOM when PSEL3 1 PSEL2 PSEL1 PSELO are don t care NOTE When using an ADS1255 make sure to only select the available inputs Bits 3 0 NSEL3 NSEL2 NSEL1 NSELO Negative Input Channel AINj Select 0000 AINO 0001 AIN1 default 0010 AIN2 ADS1256 only 0011 AIN3 ADS1
43. for 20 DRDY periods the ADS1255 6 will enter Power Down mode To synchronize using the SYNC command first shift in all eight bits of the SYNC command This stops the operation of the ADS1255 6 When ready to synchronize issue the WAKEUP command Synchronization occurs on the first rising edge of the master clock after the first SCLK used to shift in the WAKEUP command After a synchronization operation either with the SYNC PDWN pin or the SYNC command DRDY stays high until valid data is ready ADS1255 ADS1256 SBAS288D JUNE 2003 REVISED AUGUST 2004 STANDBY MODE The standby mode shuts down all of the analog circuitry and most of the digital features The oscillator continues to run to allow for fast wakeup If enabled clock output DO CLKOUT will also continue to run during during Standby mode To enter Standby mode issue the STANDBY command To exit Standby mode issue the WAKEUP command DRDY will stay high after exiting Standby mode until valid data is ready Standby mode can be used to perform one shot conversions see Settling Time Using One Shot Mode section for more details POWER DOWN MODE Holding the SYNC PDWN pin low for 20 DRDY cycles activates the Power Down mode During Power Down mode all circuitry is disabled including the oscillator and the clock output To exit Power Down mode take the SYNC PDWN pin high Upon exiting from Power Down mode the ADS1255 6 crystal o
44. gital I O Direction for Digital I O Pin DO CLKOUT 0 DO CLKOUT is an output default 1 DO CLKOUT is an input Bits 3 0 DIO 3 0 Status of Digital I O Pins D3 D2 D1 DO CLKOUT Reading these bits will show the state of the corresponding digital I O pin whether if the pin is configured as an input or output by DIR3 DIRO When the digital I O pin is configured as an output by the DIR bit writing to the corresponding DIO bit will set the output state When the digital I O pin is configured as an input by the DIR bit writing to the corresponding DIO bit will have no effect When DO CLKOUT is configured as an output and CLKOUT is enabled using CLK1 CLKO bits in the ADCON register writing to DIOO will have no effect ADS1255 i MO Texas ADS1256 www ti com SBAS288D JUNE 2003 REVISED AUGUST 2004 OFCO Offset Calibration Byte 0 least significant byte Address 05h Reset value depends on calibration results BIT7 BIT 6 BIT5 BIT 4 BIT3 BIT 2 BIT 1 BITO OFCO6 OFCOS OFCOS OFC00 OFC1 Offset Calibration Byte 1 Address 06h Reset value depends on calibration results BIT 7 BIT6 BIT5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 OFC15 OFC14 OFC13 OFC12 OFC11 OFC10 OFCO9 OFC08 OFC2 Offset Calibration Byte 2 most significant byte Address 07h Reset value depends on calibration results BIT7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 OFC23 OFC22 OFC21 OFC20 OFC19 OFC18 OFC17 OFC16 FSCO Full scale Calibration Byte 0 least significant byte A
45. hout the need to issue subsequent read commands After all 24 bits have been read DRDY goes high It is not necessary to read back all 24 bits but DRDY will then not return high until new data is being updated This mode may be terminated by the Stop Read Data Continuous command STOPC Because DIN is constantly being monitored during the Read Data Continuous mode for the STOPC or RESET command do not use this mode if DIN and DOUT are connected together See the Timing Characteristics for the required delay between the end of the RDATAC command and the beginning of shifting data on DOUT tg DRDY DIN 0000 0011 _ Figure 30 RDATAC Command Sequence On the following DRDY shift out data by applying SCLKs The Read Data Continuous mode terminates if inout_data equals the STOPC or RESET command in any of the three bytes on DIN DRDY Figure 31 DIN and DOUT Command Sequence During Read Continuous Mode STOPC Stop Read Data Continuous Description Ends the continuous data output mode see RDATAC The command must be issued after DRDY goes low and completed before DRDY goes high DRDY DIN 000 1111 Figure 32 STOPC Command Sequence 35 ADS1255 ii ADS1256 We Texas s www ti com SBAS288D JUNE 2003 REVISED AUGUST 2004 RREG Read from Registers Description Output the data from up to 11 registers starting with the register address specified as part of the command The number
46. ing updated Do not retrieve during this update period as the data is invalid If data is not retrieved DRDY will only be high during the update time as shown in Figure 24 Data Updating a was se JC IL Thy Figure 24 DRDY with No Data Retreival After changing the PGA data rate buffer status writing to the OFC or FSC registers and enabling or disabling the sensor detect circuitry perform a synchronization operation to force DRDY high It will stay high until valid data is ready If auto calibration is enabled by setting the ACAL bit in the ADCON register DRDY will go low after the self calibration is complete and new data is valid Exiting from Reset Synchronization Standby or Power Down mode will also force DRDY high DRDY will go low as soon as valid data is ready SYNCHRONIZATION Synchronization of the ADS1255 6 is available to coordinate the A D conversion with an external event and also to speed settling after an instantaneous change on the analog inputs see Conversion Time using Synchronization section Synchronization can be achieved either using the SYNC PDWN pin or with the SYNC command To use the SYNC PDWN pin take it low and then high making sure to meet timing specification t46 Synchronization occurs on the first rising edge of the master clock after SYNC PDWN is taken high No communication is possible on the serial interface while SYNC PDWN is low If the SYNC PDWN pin is held low
47. input referred noise when measuring lower level signals Table 1 through Table 6 summarize the typical noise performance with the inputs shorted externally In all six tables the following conditions apply T 25 C AVDD 5V DVDD 1 8V Vper 2 5V and fcLKIN 7 68MHz Table 1 to Table 3 reflect the device input buffer enabled Table 1 shows the rms value of the input referred noise in volts Table 2 shows the effective number of bits of resolution ENOB using the noise data from Table 1 ENOB is defined as In FSR RMS Noise ENOB DEI where FSR is the full scale range Table 3 shows the noise free bits of resolution It is calculated with the same formula as ENOB except the peak to peak noise value is used instead of rms noise Table 4 through Table 6 show the same noise data but with the input buffer disabled Table 1 Input Referred Noise uV rms with Buffer On 500 1 946 1 250 0 630 0 648 0 497 0 390 0 367 1000 2 931 1 891 1 325 1 070 0 689 0 512 0 486 2000 4 173 2 589 1 827 1 492 0 943 0 692 0 654 3750 5 394 3 460 2 376 1 865 1 224 0 912 0 906 7500 7 249 4 593 3 149 2 436 1 691 1 234 1 187 S ol CO oO 2 D Q gt wo Gi CO So IW IV oO oO Sat l CH CH Sat D 100 E 15 000 9 074 5 921 3 961 2 984 2 125 1 517 1 515 30 000 12 Table 2 Effective Number of Bits ENOB
48. mance is low enough that a single calibration is all that is needed DRDY goes high when calibration begins and remains so until settled data is ready afterwards There is no need to discard data after a calibration It is strongly recommended to issue a self calibration command after power up when the reference has stabilized After a reset the ADS1255 6 performs self calibration Calibration must be performed whenever the data rate changes and should be performed when the buffer configuration or PGA changes Table 18 Calibration Values for Different Data Rate Settings a ooo oo o oe e 30 000 4000004 0000004 44AC08H 15 000 4000004 0000004 44ACO08H 7500 4000004 1 8639 0000004 44AC08H 3750 4000004 1 8639 0000004 44AC08H 2000 3C0000H 1 7474 0000004 494008 1000 3C0000 4 1 7474 0000004 494008 500 3C0000 4 1 7474 0000004 494008 100 4B0000q 2 1843 0000004 3A99A0H 60 3E8000H 1 8202 0000004 4651F3H 50 4B0000H 2 1843 0000004 3A99A0H 30 3E8000H 1 8202 0000004 4651F3H 25 4B0000H 2 1843 0000004 3A99A0H 15 3E8000H 1 8202 0000004 4651F3H 10 5DC000H 2 7304 0000004 2EE14CH 5 5DC000H 2 7304 0000004 2EE14CH 2 5 5DC000H 2 7304 0000004 2EE14Cy 24 d TEXAS INSTRUMENTS www ti com Self Calibration Self calibration corrects internal offset and gain errors During self calibration the appropriate calibration signals are applied internally to the analog inputs SELFOCAL performs a self o
49. ments and other changes to its products and services at any time and to discontinue any product or service without notice Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete All products are sold subject to Tl s terms and conditions of sale supplied at the time of order acknowledgment Tl warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with Tl s standard warranty Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty Except where mandated by government requirements testing of all parameters of each product is not necessarily performed TI assumes no liability for applications assistance or customer product design Customers are responsible for their products and applications using TI components To minimize the risks associated with customer products and applications customers should provide adequate design and operating safeguards TI does not warrant or represent that any license either express or implied is granted under any TI patent right copyright mask work right or other TI intellectual property right relating to any combination machine or process in which TI products or services are used Information published by TI regarding third party products or services does not constitute a license from TI to use such products or ser
50. nal commands after issuing this command until DRDY goes low indicating that the calibration is complete SYSGCAL System Gain Calibration Description Performs a system gain calibration The Full Scale Calibration Register FSC is updated after this operation DRDY goes high at the beginning of the calibration It goes low after the calibration completes and settled data is ready Do not send additional commands after issuing this command until DRDY goes low indicating that the calibration is complete SYNC Synchronize the A D Conversion Description This command synchronizes the A D conversion To use first shift in the command Then shift in the WAKEUP command Synchronization occurs on the first CLKIN rising edge after the first SCLK used to shift in the WAKEUP command 1111 1100 0000 0000 SYNC WAKEUP Synchronization Occurs Here Figure 35 SYNC Command Sequence STANDBY Standby Mode One Shot Mode Description This command puts the ADS1255 6 into a low power Standby mode After issuing the STANDBY command make sure there is no more activity on SCLK while CS is low as this will interrupt Standby mode If CS is high SCLK activity is allowed during Standby mode To exit Standby mode issue the WAKEUP command This command can also be used to perform single conversions see One Shot Mode section 1111 1101 0000 0000 STANDBY WAKEUP SCLK Normal Mode Standby Mode Normal Mode Figure 36 ST
51. ns will be much less but the buffer will limit the allowable voltage range on VREFP and VREFN during self or self gain calibration as the reference pins must remain within the specified input range of the buffer in order to establish proper gain calibration A high quality reference voltage is essential for achieving the best performance from the ADS1255 6 Noise and drift on the reference degrade overall system performance It is especially critical that special care be given to the circuitry generating the reference voltages and their layout when operating in the low noise settings that is with low data rates to prevent the voltage reference from limiting performance 17 ADS1255 ADS1256 SBAS288D JUNE 2003 REVISED AUGUST 2004 DIGITAL FILTER The programmable low pass digital filter receives the modulator output and produces a high resolution digital output By adjusting the amount of filtering tradeoffs can be made between resolution and data rate filter more for higher resolution filter less for higher data rate The filter is comprised of two sections a fixed filter followed by a programmable filter Figure 13 shows the block diagram of the analog modulator and digital filter Data is supplied to the filter from the analog modulator at a rate of foLKin 4 The fixed filter is a 5th order sinc filter with a decimation value of 64 that outputs data at a rate of foL_Kin 256 The second stage of the filter is a programmabl
52. om REG rrr 0001 mr ah 0000 nnnn WREG Write to REG rrr 0101 mr 5xh 0000 nnnn SELFCAL Offset and Gain Self Calibration 1111 0000 FOh SELFOCAL Offset Self Calibration 1111 0001 Fih SELFGCAL Gain Self Calibration 1111 0010 F2h SYSOCAL System Offset Calibration 1111 0011 F3h SYSGCAL System Gain Calibration 1111 0100 F4h SYNC Synchronize the A D Conversion 1111 1100 FCh STANDBY Begin Standby Mode 1111 1101 FDh RESET Reset to Power Up Values 1111 1110 FEh WAKEUP Completes SYNC and Exits Standby Mode 1111 1111 FFh NOTE n number of registers to be read written 1 For example to read write three registers set nnnn 2 0010 r Starting register address for read write commands RDATA Read Data Description Issue this command after DRDY goes low to read a single conversion result After all 24 bits have been shifted out on DOUT DRDY goes high It is not necessary to read back all 24 bits but DRDY will then not return high until new data is being updated See the Timing Characteristics for the required delay between the end of the RDATA command and the beginning of shifting data on DOUT tg Figure 29 RDATA Command Sequence 34 ADS1255 Ai MO Texas ADS1256 www ti com SBAS288D JUNE 2003 REVISED AUGUST 2004 RDATAC Read Data Continuous Description Issue command after DRDY goes low to enter the Read Data Continuous mode This mode enables the continuous output of new data on each DRDY wit
53. resistance Rsens between two input pins When the SDCS are enabled they source Ispc to the input pin connected to AINp and sink Igpc from the input pin connected to AINw The two 25Q series resistors Rmux model the ADS1255 6 internal resistances The signal measured with the SDCS enabled equals the total IR drop Ispc x 2Rmux Rgens Note that when the sensor is a direct short that is Rgeng 0 there will still be a small signal measured by the ADS1255 6 when the SDCS are enabled Ispc x 2Rmuux Sensor Detect Current Source gt o o5 Si 7 Q RE E hfe 82 Kal Sensor Detect Current Source NOTE Arrows indicate switch positions when the SDCS are enabled Figure 7 Sensor Detect Circuitry ADS1255 ADS1256 SBAS288D JUNE 2003 REVISED AUGUST 2004 ANALOG INPUT BUFFER To dramatically increase the input impedance presented by the ADS1255 6 the low drift chopper stabilized buffer can be enabled via the BUFEN bit in the STATUS register The input impedance with the buffer enabled can be modeled by a resistor as shown in Figure 8 Table 7 lists the values of Zerr for the different data rate settings The input impedance scales inversely with the frequency of CLKIN For example if fcLk n is reduced by half to 3 84MHZ Zefe for a data rate of 50SPS will double from 80MQ to 160MQ Figure 8 Effective Impedance with Buffer On Table 7 Input Impedance with Buffer On
54. rters offer fast channel cycling for measuring i multiplexed inputs and can also perform one shot Low Noise PGA 27nV Input Referred Noise conversions that settle in just a single cycle S Self and System Calibration for All PGA Communication is handled over an SPl compatible serial Settings interface that can operate with a 2 wire connection 5V Tolerant SPI Compatible Serial Interface Onboard calibration supports both self and system Analog Supply 5V correction of offset and gain errors for all the PGA settings e Digital S lv 1 8V to 3 6V Bidirectional digital I Os and a programmable clock output ER K driver are provided for general use The ADS1255 is Power Dissipation packaged in an SSOP 20 and the ADS1256 in an As Low as 38mW in Normal Mode SSOP 28 0 4mW in Standby Mode VREFP VREFN DVDD APPLICATIONS e Weigh Scal AINO XTAL1 CLKIN Verte AIN1 XTAL2 SG Scientific Instrumentation vw Industrial Process Control A AIN3 PRESEI Medical Equipment le Se T SYNG RDWN Test and Measurement t i en O DRDY T SCLK 1 AIN7 General Serial E r a n Purpose Interface DIN Digital UO DOUT D3 D2 D1 DO CLKOUT ADS1256 Only Please be aware that an important notice concerning availability standard warranty and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet All trademarks are the property of their r
55. s high at the beginning of the calibration It goes low after the calibration completes and settled data is ready Do not send additional commands after issuing this command until DRDY goes low indicating that the calibration is complete SELFOCAL Self Offset Calibration Description Performs a self offset calibration The Offset Calibration Register OFC is updated after this operation DRDY goes high at the beginning of the calibration It goes low after the calibration completes and settled data is ready Do not send additional commands after issuing this command until DRDY goes low indicating that the calibration is complete SELFGCAL Self Gain Calibration Description Performs a self gain calibration The Full Scale Calibration Register FSC is updated with new values after this operation DRDY goes high at the beginning of the calibration It goes low after the calibration completes and settled data is ready Do not send additional commands after issuing this command until DRDY goes low indicating that the calibration is complete 36 ADS1255 j YO Texas ADS1256 www ti com SBAS288D JUNE 2003 REVISED AUGUST 2004 SYSOCAL System Offset Calibration Description Performs a system offset calibration The Offset Calibration Register OFC is updated after this operation DRDY goes high at the beginning of the calibration It goes low after the calibration completes and settled data is ready Do not send additio
56. scillator typically requires 30ms to wake up If using an external clock source 8192 CLKIN cycles are needed before conversions begin RESET There are three methods to reset the ADS1255 6 the RESET input pin RESET command and a special SCLK reset pattern When using the RESET pin take it low to force a reset Make sure to follow the minimum pulse width timing specifications before taking the RESET pin back high The RESET command takes effect after all eight bits have been shifted into DIN Afterwards the reset releases automatically The ADS1255 6 can also be reset with a special pattern on SCLK see Figure 2 Reset occurs on the falling edge of the last SCLK edge in the pattern After performing the operation the reset releases automatically On reset the configuration registers are initialized to their default state except for the CLKO and CLK1 bits in the ADCON register that control the DO CLKOUT pin These bits are only initialized to the default state when RESET is performed using the RESET pin After releasing from RESET self calibration is performed regardless of the reset method or the state of the ACAL bit before RESET POWER UP All of the configuration registers are initialized to their default state at power up A self calibration is then performed automatically For the best performance it is strongly recommended to perform an_ additional self calibration by issuing the SELFCAL command after the po
57. tal I O pins All of the digital I O pins are individually configurable as either inputs or outputs through the IO register The DIR bits of the IO register define whether each pin is an input or output and the DIO bits control the status of the pins Reading back the DIO register shows the state of the digital I O pins whether they are configured as inputs or outputs by the DIR bits When digital I O pins are configured as inputs the DIO register is used to read the state of these pins When configured as outputs DIO sets the output value On the ADS1255 the digital I O pins D2 and D3 do not exist and the settings of the IO register bits that control operation of D2 and D3 have no effect on that device During Standby and Power Down modes the GPIO remain active If configured as outputs they continue to drive the pins If configured as inputs they must be driven not left floating to prevent excess power dissipation The digital I O pins are set as inputs after power up or a reset except for DO CLKOUT which is enabled as a clock output If the digital I O pins are not used either leave them as inputs tied to ground or configure them as outputs This prevents excess power dissipation ADS1255 ADS1256 SBAS288D JUNE 2003 REVISED AUGUST 2004 CLOCK OUTPUT D0 CLKOUT The clock output pin can be used to clock another device such as a microcontroller This clock can be configured to operate at frequencies of fcLKIN foLkin 2
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59. ublished specifications 100 Momentary mA nput Current 10 Continuous mA Analog inputs to AGND 0 3 to AVDD 0 3 V DIN SCLK CS RESET SS SYNC PDWN 0 3 to 6 V Digital XTAL1 CLKIN to DGND inputs Vroctkour D1 D2 D3 to DGND 0 3 to DVDD 0 3 V Maximum Junction Temperature 150 C Operating Temperature Range 40 to 105 C Storage Temperature Range 60 to 150 C Lead Temperature soldering 10s 300 C 1 Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device Exposure to absolute maximum conditions for extended periods may degrade device reliability These are stress ratings only and functional operation of the device at these or any other conditions beyond those specified is not implied d TEXAS INSTRUMENTS www ti com ADS1255 ADS1256 SBAS288D JUNE 2003 REVISED AUGUST 2004 ELECTRICAL CHARACTERISTICS All specifications at 40 C to 85 C AVDD 5V DVDD 1 8V fCLKIN 7 68MHz PGA 1 and VREF 2 5V unless otherwise noted PARAMETER Analog Inputs TEST CONDITIONS MIN TYP MAX UNIT Full scale input voltage AINp AINN 2VREF PGA Absolute input voltage AINO 7 AINCOM to AGND Buffer off Buffer on AGND 0 1 AVDD 0 1 AGND AVDD 2 0 Programmable gain amplifier 1 64 Differential input impedance Buffer off PGA 1 2 4 8 16 150 PGA Buffer off PGA 32 64 4 7 Buffer on fpaTa lt 50Hz 7 80
60. us 2000 1 4ms 1000 2 4ms 500 4 4ms 100 20 4ms 60 33 7ms 50 40 4ms 30 67 0ms 25 80 4ms 15 133 7ms 10 200 4ms 5 400 4ms 2 5 800 4ms NOTE For fCLKIN 7 68MHz Auto Calibration Auto calibration can be enabled ACAL bit in ADCON register to have the ADS1255 6 automatically initiate a self calibration at the completion of a write command WREG that changes the data rate PGA setting or Buffer status 26 d TEXAS INSTRUMENTS www ti com SERIAL INTERFACE The SPl compatible serial interface consists of four signals CS SCLK DIN and DOUT and allows a controller to communicate with the ADS1255 6 The programmable functions are controlled using a set of on chip registers Data is written to and read from these registers via the serial interface The DRDY output line is used as a status signal to indicate when a conversion has been completed DRDY goes low when new data is available The Timing Specification shows the timing diagram for interfacing to the ADS1255 6 CHIP SELECT CS The chip select CS input allows individual selection of a ADS1255 6 device when multiple devices share the serial bus CS must remain low for the duration of the serial communication When CS is taken high the serial interface is reset and DOUT enters a high impedance state CS may be permanently tied low SERIAL CLOCK SCLK The serial clock SCLK features a Schmitt triggered input and is used to clock data on the DIN and DOU
61. vices or a warranty or endorsement thereof Use of such information may require a license from a third party under the patents or other intellectual property of the third party or a license from TI under the patents or other intellectual property of TI Reproduction of information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties conditions limitations and notices Reproduction of this information with alteration is an unfair and deceptive business practice TI is not responsible or liable for such altered documentation Resale of TI products or services with statements different from or beyond the parameters stated by TI for that product or service voids all express and any implied warranties for the associated TI product or service and is an unfair and deceptive business practice TI is not responsible or liable for any such statements Following are URLs where you can obtain information on other Texas Instruments products and application solutions Products Applications Amplifiers amplifier ti com Audio www ti com audio Data Converters dataconverter ti com Automotive www ti com automotive DSP dsp ti com Broadband www ti com broadband Interface interface ti com Digital Control www ti com digitalcontrol Logic logic ti com Military www ti com military Power Mgmt power ti com Optical Networking www ti com opticalnetwork Microcontrollers microcontroller
62. wer supplies and voltage reference have had time to settle to their final values 27 ADS1255 ADS1256 SBAS288D JUNE 2003 REVISED AUGUST 2004 APPLICATIONS INFORMATION GENERAL RECOMMENDATIONS The ADS1255 and ADS1256 are very high resolution A D converters Getting the optimal performance from them requires careful attention to their support circuitry and printed circuit board PCB design Figure 25 shows the basic connections for the ADS1255 It is recommended to use a single ground plane for both the analog and digital supplies This ground plane should be shared with the bypass capacitors and analog conditioning circuits However avoid using this ground plane for noisy digital components such as microprocessors If a split ground plane is used with the ADS1255 6 make sure the analog and digital planes are tied together There should not be a voltage difference between the ADS1255 6 analog and digital ground pins AGND and DGND As with any precision circuit use good supply bypassing techniques A smaller value ceramic capacitor in parallel with a larger value tantalum or a larger value low voltage ceramic capacitor works well Place the capacitors in particular the ceramic ones close to the supply pins Run the digital logic off as low of voltage as possible This helps reduce coupling back to the analog inputs Avoid ringing on the digital inputs Small resistors 100Q in series with AGND

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