TEXAS INSTRUMENTS CDC318A handbook
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1. High Speed Low Skew 1 to 18 Clock Buffer for Synchronous DRAM SDRAM Clock Buffering Applications Output Skew tsk o gt Less Than 250 ps Pulse Skew tsk p Less Than 500 ps Supports up to Four Unbuffered SDRAM Dual Inline Memory Modules DIMMs 12C Serial Interface Provides Individual Enable Conirol for Each Output Operates at 3 3 V Distributed Vcc and Ground Pins Reduce Switching Noise 100 MHz Operation ESD Protection Exceeds 2000 V Per MIL STD 883 Method 3015 Packaged in 48 Pin Shrink Small Outline DL Package description The CDC318A is a high performance clock buffer designed to distribute high speed clocks in PC applications This device distributes one input A to 18 outputs Y with minimum skew for clock distribution The CDC318A operates from a 3 3 V power supply It is characterized for operation from 0 C to 70 C This device has been designed with consideration for optimized EMI performance Depending on the application layout damping resistors in series to the clock outputs like proposed in the PC100 specification may not be needed in most cases CDC318A 1 LINE TO 18 LINE CLOCK DRIVER WITH I2C CONTROL INTERFACE SCAS614 SEPTEMBER 1998 DL PACKAGE TOP VIEW SDATA 24 25 SCLOCK NC No internal connection The device provides a standard mode 100K bits s 12C serial interface for device control The implementation is as a slave receiver The devi2. DALLAS TEXAS 75265 CDC318A 1 LINE TO 18 LINE CLOCK DRIVER WITH I2C CONTROL INTERFACE SCAS614 SEPTEMBER 1998 absolute maximum ratings over operating free air temperature range unless otherwise noted t Supply voltage range VOC sisrscicersi orii ierti stii e eee EN GETEN ANER EEA 0 5 V to 4 6 V Input voltage range V see Note 1 0 ete ene 0 5 V to 4 6 V Input voltage range Vi SCLOCK SDATA see Note 1 1 eee eee ee 0 5 V to 6 5 V Output voltage range Vo SDATA see Note 1 eee eee 0 5 V t0 6 5 V Voltage range applied to any output in the high or power off state VO 0 5 V to Vcc 0 5 V Current into any output in the low state except SDATA lQ 1 eee eet eens 48 mA Current into SDATA in the low state IQ nnn teens 12mA Input clamp current lik Vj lt 0 SCLOCK 0 0 ccc idnosiai urinii ruit kisika iah 50 mA Output clamp current lox VQ lt 0 SDATA 6 ett tenet eens 50 mA Package thermal impedance Oj see Notes 2 and 3 0 ccc eee 84 C W Storage temperature range Tstg 1 1 e eee eee eee ee eee 65 C to 150 C Lead temperature 1 6 mm 1 16 inch from case for 10 seconds 0000 eee ee eee aes 260 C T Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated und
3. gt tsu SDATA Ke Repeat Start etree Condition Stop Condition Repeat Start ener Condition VOLTAGE WAVEFORMS BYTE DESCRIPTION 2 O Command dummy value ignored 3 Byte count dummy value ignored 4 Peame SSC Ps Poemen OOS 6 Pe databytes SSS NOTES A The repeat start condition is not supported B Allinput pulses are supplied by generators having the following characteristics PRR lt 100 kHz Zo 50 Q tr 2 10 ns tf 2 10 ns Figure 3 Propagation Delay Times tp and t ki TEXAS INSTRUMENTS 10 POST OFFICE BOX 655303 DALLAS TEXAS 75265 CDC318A 1 LINE TO 18 LINE CLOCK DRIVER WITH I2C CONTROL INTERFACE SCAS614 SEPTEMBER 1998 MECHANICAL INFORMATION DL R PDSO G PLASTIC SMALL OUTLINE PACKAGE 48 PIN SHOWN 0 025 0 635 0 012 0 305 0 008 0 203 0 005 0 13 Mi 0 006 0 15 NOM 299 7 59 7 39 A 0 420 10 67 0 395 10 03 l Gage Plane 0 040 1 02 0 020 0 51 Seating Plane 0 004 0 10 0 110 2 79 MAX 0 008 0 20 MIN PINS 4040048 C 03 97 NOTES A All linear dimensions are in inches millimeters This drawing is subject to change without notice Body dimensions do not include mold flash or protrusion not to exceed 0 006 0 15 Falls within JEDEC MO 118 GOB ki TEXAS INSTRUMENTS POST OFFICE BOX 655303 DALLAS
4. 5303 DALLAS TEXAS 75265 1 CDC318A 1 LINE TO 18 LINE CLOCK DRIVER WITH I2C CONTROL INTERFACE SCAS614 SEPTEMBER 1998 FUNCTION TABLE OUTPUTS 1Y0 1Y3 2Y0 2Y3 3Y0 3Y3 4Y0 4Y3 5Y0 5Y1 Hi Z Hi Z Hi Z Hi Z Hi Z L L L L HT H Ht Ht T The function table assumes that all outputs are enabled via the appropriate 12C configuration register bit If the output is disabled via the appropriate configuration bit then the output is driven to a low state regardless of the state of the A input logic diagram positive logic 38 OE 24 SDATA 2c Register Space 4 5 8 9 SCLOCK _ _e _ 1Y0 1Y3 13 14 17 18 2Y0 2Y3 11 A 31 32 35 36 3Y0 3Y3 40 41 44 45 4Y0 4Y3 21 28 5Y0 5Y1 ki TEXAS INSTRUMENTS 2 POST OFFICE BOX 655303 DALLAS TEXAS 75265 CDC318A 1 LINE TO 18 LINE CLOCK DRIVER WITH I2C CONTROL INTERFACE SCAS614 SEPTEMBER 1998 Terminal Functions TERMINAL 1 0 DESCRIPTION NAME NO o ases o onomea O wo ieie o SSVSORAMbye 1dockoupuis o o ooo wove arasso o 83 SDRAM bye 2 deck outs O moe waaa o SSVSDRAM bye Sdock ouput SSCS Pad a SCSCS S SSCSC C Output enable When asserted OE puts all outputs in a high impedance state A nominal 140 kQ pullup resistor is internally integrated SCLOCK 25 12C serial clock input A nominal 140 kQ pullup resistor is internally integrated Bidirectional 12C serial da
5. TERFACE SCAS614 SEPTEMBER 1998 electrical characteristics over recommended operating free air temperature range unless otherwise noted PARAMETER Ps TEST CONDITIONS MIN TYP MAX UNIT i Vcc V Min to Max IOH 1 mA High level output voltage Y outputs 4 Vcc 3 135 V IOH 36 mA 2 Y outputs Voo 8135V lov 24mA Low level output voltage SDATA Voc 3 135 V SDATA Voo 8195 __Yo VooMAX 54 Voc 3 135 V Vo 2V 126 Y outputs Voc 3 3 V Vo 1 65 V Voc 3 465 V Vo 3 135 V Voc 3 135 V Vo 1V Low level output current Y outputs Voc 3 3 V Vo 1 65 V Voc 3 465 V Vo 0 4V High level input current OE sid Voc 3 465 V A High level output current afd Y ajn ojlo A ol l lt o oo N Lyi ofja DS gl A ojlo oo o gt ke 3 3 else bys fe 3 ye Oo SCLOCK SDATA OE OE Low level input current OE sid Voc 3 465 V High impedance state output current SOLOGK SDATA Vcc 3 135 V to 3 465 V Alcc Change in supply current One input at Vcc 0 6 V All other inputs at Vcc or GND alo gt O E gt 3 gt al O o 7a ne z ki TEXAS INSTRUMENTS 6 POST OFFICE BOX 655303 DALLAS TEXAS 75265 CDC318A 1 LINE TO 18 LINE CLOCK DRIVER WITH I2C CONTROL INTERFACE SCAS614 SEPTEMBER 1998 switching characteristics over recommended operating conditions Low to high level propagation delay time SDATA Vc
6. TEXAS 75265 11 IMPORTANT NOTICE Texas Instruments and its subsidiaries Tl reserve the right to make changes to their products or to discontinue any product or service without notice and advise customers to obtain the latest version of relevant information to verify before placing orders that information being relied on is current and complete All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement including those pertaining to warranty patent infringement and limitation of liability Tl warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with Tl s standard warranty Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty Specific testing of all parameters of each device is not necessarily performed except those mandated by government requirements CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH PERSONAL INJURY OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE CRITICAL APPLICATIONS TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED AUTHORIZED OR WARRANTED TO BE SUITABLE FOR USE IN LIFE SUPPORT DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER S RISK In order to minimize risks associated with the customer s applications adequate des
7. an tPHL18 Output skew tsk q iS calculated as the greater of gt g 4 tPLH18 The difference between the fastest and slowest of tpLHn n 1 18 The difference between the fastest and slowest of tpHLn n 1 18 Pulse skew tsk p is calculated as the greater of tPLHn tPHLnl Nn 1 18 Process skew tgk pr is calculated as the greater of Thedifference between the fastest and slowest of tpLHn n 1 1 The difference between the fastest and slowest oftpHLn n 1 1 Figure 2 Waveforms for Calculation of tsx 9 tsk p gt tsk pr ki TEXAS INSTRUMENTS POST OFFICE BOX 655303 DALLAS TEXAS 75265 SCAS614 SEPTEMBER 1998 across multiple devices under identical operating conditions across multiple devices under identical operating conditions CDC318A 1 LINE TO 18 LINE CLOCK DRIVER WITH I2C CONTROL INTERFACE SCAS614 SEPTEMBER 1998 PARAMETER MEASUREMENT INFORMATION Vo 3 3V RL 1kQ Cy 10 pF or CL 400 pF T e _ GND TEST CIRCUIT A 4 to 6 Bytes for Complete Device Programming Start Bit 0 Stop Condition LSB a T Condition S R W P tsu START Ke SCLOCK 0 7Vcc 0 3 Vcc wey ee t gt E tPHL M iBUS _ gt t tpPLH I SDATA 0 7 Vcc 0 3 Vcc t t SDATA gt gt tr SDATA gt Ke th SDATA tsusToP gt KR th START
8. c 3 3 V 40 165 V SCLOCK valid See Figure 3 Voc 3 3 V 0 165 V Low to high level propagation delay time SDATAT Y See Figure 3 Y High to low level propagation delay time SDATA Vcc 3 3 V 0 165 V SCLOCKL valid See Figure 3 2 Voc 3 3 V tPHL High to low level propagation delay time SDATAT See Figure 3 fe feme o Rise time see Note 5 and SDATA Figure 3 a T D tpzH teiz NOTE 5 This parameter has a lower limit than BUS specification This allows use of series resistors for current spike protection k TEXAS INSTRUMENTS POST OFFICE BOX 655303 DALLAS TEXAS 75265 7 CDC318A 1 LINE TO 18 LINE CLOCK DRIVER WITH 12C CONTROL INTERFACE SCAS614 SEPTEMBER 1998 PARAMETER MEASUREMENT INFORMATION 6V 500 2 S17 Open TEST s1 From Output t R Open Under Test GND PLH PHL p tPLZ tPZL 6V CL 30 pF 500 Q tpHZ tPZH GND see Note A a tw gt LOAD CIRCUIT FOR tod AND tsk 3V Input 1 5V 1 5V From Output O ov Under Test CL 30pF see Note A ms Output LOAD CIRCUIT FOR tr AND tf Enable high level enabling tPZL 3V E Te matt e a PLH E tPHL Si at6V VoL 0 3 VoL 24v zav VOH iin tPZH gt Mii Output OO KH a wy vai Output VOH Waveform 2 ee En t t S1 at GND 1 5V VoH 0 3 V Mii i see Note B OV VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS NOTES A Cy includes probe and jig
9. capacitance B Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control C Allinput pulses are supplied by generators having the following characteristics PRR lt 10 MHz Zo 50 Q tr lt 2 5 ns tps 2 5 ns D The outputs are measured one at a time with one transition per measurement Figure 1 Load Circuit and Voltage Waveforms ki TEXAS INSTRUMENTS 8 POST OFFICE BOX 655303 DALLAS TEXAS 75265 NOTES A CDC318A 1 LINE TO 18 LINE CLOCK DRIVER WITH I2C CONTROL INTERFACE PARAMETER MEASUREMENT INFORMATION a NOZ cn 1Y0 tPpHLi gt gt 4 tPLH1 MW TL Na tpHL2 gt tpLH2 we TW HI N tPHL3 gt f gt I tPLH3 wa NN tpHL4 gt gt 4 tPLH4 w TN ASN tPH5 f gt tPLH5 mw TNA N a tPHe gt f gt i tPLH6 x KL SN tPH7 gt gt 4 tPLH7 na C a O tpHis f gt tPLH8 3Y0 tpHig gt t gt tpLug 3Y1 tPHLIO P tPLH10 3Y2 tpHL11 gt ft gt tPLH11 3Y3 tpHLi2 gt gt k tpLH12 w NOI A N tpHLi3 P gt PLH13 4Y1 tPpHL14 gt gt PLH14 w NOIA VY tPHLis gt F gt tPLH15 4Y3 tpHLi6 gt gt tpLHi6 5Y0 tpHLi7 ff gt tPLHi7 5Y1 i ae i KRA s
10. ce address is specified in the 12C device address table Both of the 12C inputs SDATA and SCLOCK are 5 V tolerant and provide integrated pullup resistors typically 140 kQ Three 8 bit 12C registers provide individual enable control for each of the outputs All outputs default to enabled at powerup Each output can be placed in a disabled mode with a low level output when a low level control bit is written to the control register The registers are write only and must be accessed in sequential order i e random access of the registers is not supported The CDC318A provides 3 state outputs for testing and debugging purposes The outputs can be placed in a high impedance state via the output enable OE input When OE is high all outputs are in the operational state When OE is low the outputs are placed in a high impedance state OE provides an integrated pullup resistor Please be aware that an important notice concerning availability standard warranty and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet Intel is a trademark of Intel Corporation Products conform to specifications per the terms of Texas Instruments Copyright 1998 Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date standard warranty Production processing does not necessarily include testing of all parameters be EXAS POST OFFICE BOX 65
11. er recommended operating conditions is not implied Exposure to absolute maximum rated conditions for extended periods may affect device reliability NOTES 1 The input and output negative voltage ratings may be exceeded if the input and output clamp current ratings are observed 2 The package thermal impedance is calculated in accordance with EIA JEDEC Std JESD51 except for through hole packages which use a trace length of zero The absolute maximum power dissipation allowed at Ta 55 C in still air is 1 2 W 3 Thermal impedance Qj can be considerably lower if the device is soldered on the PCB board with a copper layer underneath the package A simulation on a PCB board 3 in x 3 in with two internal copper planes 1 oz cu 0 036 mm thick and 0 071 mm cu 202 in area underneath the package resulted in J 60 C W This would allow 1 2 W total power dissipation at TA 70 C recommended operating conditions see Note 4 A OE High level input voltage SDATA SCLOCK see Note 3 A OE Low level input voltage SDATA SCLOCK see Note 3 IOH High level output current Y outputs IOL Low level output current Y outputs 3 SDATA SCLOCK ri Input resistance to Vcc see Note 3 4 NOTE 4 The CMOS level inputs fall within these limits Vjy min 0 7 x Vcc and Vi max 0 3 x Vcc vy TEXAS INSTRUMENTS POST OFFICE BOX 655303 DALLAS TEXAS 75265 5 CDC318A 1 LINE TO 18 LINE CLOCK DRIVER WITH I2C CONTROL IN
12. ign and operating safeguards must be provided by the customer to minimize inherent or procedural hazards Tl assumes no liability for applications assistance or customer product design TI does not warrant or represent that any license either express or implied is granted under any patent right copyright mask work right or other intellectual property right of TI covering or relating to any combination machine or process in which such semiconductor products or services might be or are used Tl s publication of information regarding any third party s products or services does not constitute Tl s approval warranty or endorsement thereof Copyright 1998 Texas Instruments Incorporated
13. ta input output A nominal 140 kQ pullup resistor is internally integrated 6 10 15 19 22 26 ane 27 30 34 39 43 ou 1 2 47 48 oo No internal connection Reserved for future use 3 7 12 16 20 23 3a NiooWer i 29 33 37 42 46 POWer SURRY 12C DEVICE ADDRESS m ae as m m onw H H L H L L H Pr eemo e e z enable ton zee To re nai ing J T When the value of the bit is high the output is enabled When the value of the bit is low the output is forced to a low state The default value of all bits is high wy TEXAS INSTRUMENTS POST OFFICE BOX 655303 DALLAS TEXAS 75265 3 CDC318A 1 LINE TO 18 LINE CLOCK DRIVER WITH I2C CONTROL INTERFACE SCAS614 SEPTEMBER 1998 12C BYTE 1 BIT DEFINITIONT e rroen __ E a 4 ayoenabie onay __ 3 _ avaenabie pings o Ce avzenabie nas _ _ t 1 avr enatie pingey __ o voro T When the value of the bit is high the output is enabled When the value of the bit is low the output is forced to a low state The default value of all bits is high 12C BYTE 2 BIT DEFINITIONT 6 svoenabieton2n __ Reserves o 4 _Resenes __ Reserves o Reserves Oo o E Resened id o reena id T When the value of the bit is high the output is enabled When the value of the bit is low the output is forced to a low state The default value of all bits is high ki TEXAS INSTRUMENTS POST OFFICE BOX 655303
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TEXAS INSTRUMENTS CDC318A handbook