FAIRCHILD FDS8876 Manual
Contents
1. Ves GATE TO SOURCE VOLTAGE V DESCENDING ORDER Ip 12 5A Ip 1A 10 15 20 25 30 Qg GATE CHARGE nC Figure 13 Gate Charge Waveforms for Constant Gate Currents 3000 Ciss c Coss Cps 4000 ul o z Crss o amp lt o o Vos OV f 1MHz 100 L Irn 0 1 1 10 30 Vps DRAIN TO SOURCE VOLTAGE V Figure 12 Capacitance vs Drain to Source Voltage 200 100 448 100 5 UN 4 N E 10 MS NIN 2 nN 1ms o 4 msaas 1795 z E 5 LIMITED BY rs 44525 ems lt a SINGLE PULSE 54 1 8 0 1 Ty MAX RATED Roya 125 CIW SEs 25 De 0 01 0 01 0 1 1 10 100 Vps DRAIN to SOURCE VOLTAGE V Figure 14 Forward Bias Safe Operating Area 2007 Fairchild Semiconductor Corporation FDS8876 Rev www fairchildsemi com 133SOlN 4U9U91 9UUEU N 9 88SQ04 Test Circuits and Waveforms VARY tp TO OBTAIN REQUIRED las ov Figure 15 Unclamped Energy Test2. 5222 22 22 FAIRCHILD aaa SEMICONDUCTOR FDS8876 April 2007 N Channel PowerTrench MOSFET 30V 12 5A 8 2mO Features L DS on 8 2mQ Ves 10V lp 12 5 DS on 10 2mQ Ves 4 5V Ip 11 4A W High performance trench technology for extremely low lt W Low gate charge High power and current handling capability Hs m RoHS Compliant Branding Dash 2007 Fairchild Semiconductor Corporation FDS8876 Rev B General Description This N Channel MOSFET has been designed specifically to improve the overall efficiency of DC DC converters using either synchronous or conventional switching PWM controllers It has been optimized for low gate charge low 5 and fast switching speed Applications W DC DC converters www fairchildsemi com LAASOW 4 U9U91 9uUEU N 9 88S04 LAASOW 4 U9U91 9UuUEU N 9 88S04 MOSFET Maximum Ratings T 25 C unless otherwise noted Symbol Parameter Ratings Units Vpss Drain to Source Voltage 30 V Ves Gate to Source Voltage 20 V Drain Current Continuous TA 25 Veg 10V Roya 50 C W 12 5 A D Continuous TA 25 C Veg 4 5V Roja 50 C W 11 4 A Pulsed 91 A Eas Single Pulse Avalanche Energy Note 1 105 mJ P Power dissipation 2 5 Derate above 25 C 2
3. n18 1 tc1 8 3e 4 tc2 8e 7 res rdrain n50 n16 2 6e 3 tc1 8 0e 3 tc2 1 0e 6 res rgate n9 n20 2 3 res rsic1 n5 n51 1e 6 tc1 1e 4 tc2 1e 6 res rsic2 n5 n50 1e3 res rsource n8 n7 3 8e 3 1 3 2 6 res rvthres n22 n8 1 tc1 2 0e 3 tc2 6e 6 res rvtemp n18 n19 1 tc1 1 8e 3 tc2 2e 7 Sw vcsp s1a n12 n13 n8 model s1amod Sw vcsp s1b n13 n12 n13 n8 model s1bmod Sw vcsp s2a n6 n15 n14 n13 model s2amod Sw vcsp s2b n13 n15 n14 n13 model s2bmod v vbat n22 n19 dc 1 equations i n51 gt n50 iscl v n51 n50 v n5 n51 1e 9 abs v n5 n51 abs v n5 n51 1e6 170 5 2007 Fairchild Semiconductor Corporation 10 www fairchildsemi com FDS8876 Rev B 133SOlN 4U9U91 9UUEU N 9 88SQ4 SPICE Thermal Model REV January 2005 FDS8876 Copper Area 1 0 in CTHERM1 8 2 0e 3 CTHERM2 8 7 5 0e 3 RTHERM1 CTHERM3 7 6 1 0e 2 CTHERMA 6 5 4 0e 2 CTHERMS 5 4 9 0e 2 CTHERM6 4 3 2e 1 CTHERM7 321 CTHERMB 2 TL 3 RTHERM TH 8 1 1 RTHERM2 8 7 5e 1 RTHERMS 7 6 1 RTHERM4 6 5 5 5 548 RTHERM6 4 3 12 RTHERM7 3 2 18 RTHERMS 2 TL 25 SABER Thermal Model RTHERM4 SABER thermal model FDS8876 Copper Area 1 0 in template thermal model th tl thermal c th tl RTHERM3 5 ctherm ctherm1 th 8 2 0 3 ctherm ctherm2 8 7 5 0e 3 ctherm ctherm3 7 6 1 0 2 ctherm ctherm4 6 5 4 0e 2 ctherm ctherm5 5 4 9 0e 2
4. 0 mW C Ty TsrG Operating and Storage Temperature 55 to 150 Thermal Characteristics Roc Thermal Resistance Junction to Case Note 2 25 C W Roja Thermal Resistance Junction to Ambient Note 2a 50 C W RoJA Thermal Resistance Junction to Ambient Note 2b 125 C W Package Marking and Ordering Information Device Marking Reel Size Tape Width Quantity FDS8876 FDS8876 330mm 12mm 2500 units Electrical Characteristics 25 unless otherwise noted Symbol Parameter Test Conditions Min Typ Max Units Off Characteristics Bypss Drain to Source Breakdown Voltage Ip 250 Veg OV 30 V Vps 24V a 1 Ipss Zero Gate Voltage Drain Current Ves 0V Ty 150 C 250 less Gate to Source Leakage Current Ves 20V 100 nA On Characteristics Vos TH Gate to Source Threshold Voltage Ves Vps Ip 250A 1 2 2 5 V Ip 12 5A Veg 10V 6 8 8 2 DS on Drain to Source On Resistance Ip Ge a 8 3 10 2 mo Ip 12 5A Veg 10V 109 141 Ty 150 C Dynamic Characteristics Ciss Input Capacitance 1650 pF Coss Output Capacitance icd Ves 0V 330 pF CRss Reverse Transfer Capacitance 180 pF Gate Resistance Ves 0 5V f 1MHz 0 6 2 3 4 0 Qg toT Total Gate Charge at 10V Ves OV to 10V 28 36 nC Qa Total Gate Charge at 5V Vas OV to 5V more 15 20 nC QgTH Threshold Gate Charge Ves OV to 1V s 1 1 5 2 0 nC Gate to Source Gate Charge 1 4 3 nC Qgs2 Gate Charg
5. 150 is 1e 30 tox 1 m model mweakmod type _n vto 1 62 kp 0 02 is 1e 30 tox 1 rs 0 1 Sw vcsp model s1amod 1 5 0 1 4 3 5 LDRAIN Sw vcsp model s1bmod ron 1e 5 roff 0 1 von 3 5 voff 4 DPLCAP 5 DRAIN Sw vcsp model s2amod ron 1e 5 roff 0 1 von 1 5 voff 1 0 10 zu 02 Sw vcsp model s2bmod ron 1e 5 roff 0 1 von 1 0 voff 1 5 RLDRAIN c ca n12 n8 10 3e 10 RSLCT c cb n15 n14 10 3e 10 2 n6 8 1 6e 9 ISCL dp dbody n7 n5 model dbodymod 50 DBREAK dp dbreak n5 n11 model dbreakmod RDRAIN dp dplcap n10 n5 model dplcapmod ESG 11 EVTHRES a 18 DBODY spe ebreak n11 n7 n17 n18 33 7 T 9 MWEAK spe eds n14 n8 n5 n8 1 GATE RGATE 6 EA spe egs n13 n8 n6 n8 1 19 Su 14 EBREAK 20 spe esg n6 n10 n6 n8 1 RLGATE MSTRO spe evthres n6 n21 n19 n8 1 LSOURCE spe evtemp n20 n18 n22 1 CIN 8 7 3 Ma SOURCE T RSOURCE i it nB n17 1 RLSOURCE S1A 9 9 92A l gate n1 n9 5 29e 9 ea a 15 RBREAK n2 n5 1 0e 9 13 17 18 5 n3 n7 0 18 9 S1B o gt S2B RVTEMP 13 res rigate n1 n9 52 9 CA GB 14 IT 4 19 s res rldrain n2 n5 10 res rlsource n3 n7 1 8 EGS EDS 2 8 m mmed n16 n6 n8 n8 model mmedmod 1 w 1u 22 m mstrong n16 n6 n8 n8 model mstrongmod 1 w 1u RVTHRES m mweak n16 n21 n8 n8 model mweakmod I2 1u w 1u n17
6. 18 33 7 Eds 14858 1 Egs 13868 1 Esg 6 1068 1 Evthres 6 21 198 1 Evtemp 20 6 18 22 1 It 8 17 1 Lgate 1 9 5 29e 9 Ldrain 2 5 1 0e 9 Lsource 3 7 0 18e 10 RLgate 1 9 52 9 RLdrain 2 5 10 RLsource 3 7 1 8 Mmed 16 6 8 8 MnedMOD Mstro 16 6 8 8 MstroMOD Mweak 16 21 8 8 MweakMOD Rbreak 17 18 RbreakMOD 1 Rdrain 50 16 RdrainMOD 2 6e 3 Rgate 9 20 2 3 RSLC1 5 51 RSLCMOD 1e 6 RSLC2 5 50 1e3 Rvthres 22 8 RvthresMOD 1 Rvtemp 18 19 RvtempMOD 1 51 6 12 13 8 STAMOD S1b 13 12 13 8 STBMOD S2a 6 15 14 13 S2AMOD S2b 13 15 14 13 S2BMOD Vbat 22 19 DC 1 MODEL S1AMOD VSWITCH MODEL S1BMOD VSWITCH MODEL S2AMOD VSWITCH MODEL S2BMOD VSWITCH aon ENDS Wheatley Rsource 8 7 RsourceMOD 3 8e 3 PSPICE Electrical Model rev January 2005 LGATE GATE DVS RLGATE DPLCAP 5 10 RSLC1 51 RSLC2 ESLC 50 ein RDRAIN gt EVTHRES 4 5 S1A S2A 1210 75 74 15 8 13 S1B o S2B CA 13 14 ESLC 51 50 VALUE V 5 51 ABS V 5 51 PWR V 5 51 1e 6 170 5 MODEL RbreakMOD RES TC1 8 3e 4 TC2 8e 7 MODEL RdrainMOD RES 1 8 0 3 2 1 0 6 MODEL RSLCMOD RES TC1 1e 4 2 1 6 MODEL RsourceMOD RES TC1 1e 3 TC2 3e 6 MODEL RvthresMOD RES TC1 2 0e 3 2 6 MODEL RvtempMOD RES TC1 1 8e 3 2 2 7 RON 1e 5 ROFF 0 1 VON 4 VOFF 3 5 RON 1e 5 ROFF 0 1 VON 3 5 VOFF 4 RON 1e 5 ROFF 0 1 VON 1 5 VOFF 1 0 RON 1e 5 ROFF 0 1 VON 1 0 V
7. CURRENT A POWER DISSIPATION MULTIPLIER 25 50 75 100 AMBIENT TEMPERATURE C 125 Figure 1 Normalized Power Dissipation vs Ambient Temperature 150 25 Figure 2 Maximum Continuous Drain Current vs 50 150 75 AMBIENT TEMPERATURE C 100 125 Ambient Temperature 2 1 DUTY CYCLE DESCENDING ORDER D 0 5 5 Lae 02 5 0 1 c 2 Ja 01 0 05 0 02 9 2 0 01 5 d 5 amp 0 01 2 z SINGLE PULSE 125 C W 0 001 Rosa 0 0005 10 10 10 10 10 10 10 10 t RECTANGULAR PULSE DURATION s Figure 3 Normalized Maximum Transient Thermal Impedance m JT 65 SINGLE PULSE Roya 1259 w T 25 C 9 100
8. Circuit la REF Figure 17 Gate Charge Test Circuit Vos Figure 19 Switching Time Test Circuit f lg REF 0 0o 4 Ves QgtH Figure 18 Gate Charge Waveforms torr ta orr 5076 PULSE WIDTH 391 Figure 20 Switching Time Waveforms 2007 Fairchild Semiconductor Corporation FDS8876 Rev B www fairchildsemi com LAASOW 4U9U91 9uUEU N 9 88S04 Thermal Resistance vs Mounting Pad Area The maximum rated junction temperature and the thermal resistance of the heat dissipating path determines the maximum allowable device power dissipation Ppy in an application Therefore the application s ambient temperature T4 C and thermal resistance Raja C W must be reviewed to ensure that is never exceeded Equation 1 mathematically represents the relationship and Serves as the basis for establishing the rating of the part _ Cau TA EQ 1 RoJA Pom In using surface mount devices such as the SO8 package the environment in which it is applied will have a significant influence on the part s current and maximum power dissipation ratings Precise determination of Ppp is complex and influenced by many factors 1 Mounting pad area onto which the device is attached and whether there is copper on one side or both sides of the board 2 The number of copper layers and the thickness of the board Th
9. He z ui N 3 2 10 x lt 1 0 5 10 10 10 10 10 10 10 10 t PULSE WIDTH s Figure 4 Single Pulse Maximum Power Dissipation 2007 Fairchild Semiconductor Corporation 4 www fairchildsemi com FDS8876 Rev B LAASOW 4U9U91 9uUEU N 9 885 0 J las 1 3 RATED L R In las R 1 3 Vpss Vpp RATED BVp ss 1 STARTING T 25 STARTING T 1509 100 C C tav L tav E 2 2 2 2 o o 5 lt amp a lt 1 0 01 0 1 tay NOTE Refer to Fairchild App 1 10 100 E IN AVALANCHE ms ication Notes AN7514 and AN7515 Figure 5 Unclamped Inductive Switching Capability 50 Ves 10V Ves 5V _ 40 lt Ves 3 5V E z t 30 72 a Ves 3V 2 5 20 4 10 Ta 25 C PULSE DURATION 80us DUTY CYCLE 0 5 MAX 0 1 0 0 2 0 4 0 6 Vps DRAIN SOURCE VOLTAGE V Figure 7 Saturation Characteristics PULSE DURATION 80us u DUTY CYCLE 0 5 MAX 4 D 1 4 2 2 1 2 z 25 on u 2 1 0 lt E o 08 z Ves 10V Ip 12 5A 0 6 80 40 0 40 80 120 160 Ty JU
10. NCTION TEMPERATURE C Figure 9 Normalized Drain to Source On Resistance vs Junction Temperature 0 8 50 40 30 20 Ip DRAIN CURRENT A 10 roson DRAIN TO SOURCE ON RESISTANCE mW Typical Characteristics 25 unless otherwise noted 3 5 PULSE DURATION 80us DUTY CYCLE 0 5 MAX Vpp 15V 25 C 2 0 2 5 3 0 Ves GATE TO SOURCE VOLTAGE V Figure 6 Transfer Characteristics 50 PULSE DURATION 80us DUTY CYCLE 0 5 MAX 40 30 20 10 4 6 8 10 Ves GATE TO SOURCE VOLTAGE V Figure 8 Drain to Source On Resistance vs Gate NORMALIZED GATE THRESHOLD VOLTAGE Voltage and Drain Current Ves Vos lp 2504A 0 8 0 6 40 0 40 80 120 Ty JUNCTION TEMPERATURE C 160 200 Figure 10 Normalized Gate Threshold Voltage vs Junction Temperature 2007 Fairchild Semiconductor Corporation FDS8876 Rev B www fairchildsemi com LAASOW 5 9UUEU N 9Z288SC4 1 10 Typical Characteristics 25 unless otherwise noted 1 05 Ip 2504A 1 00 0 95 NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE 0 90 80 10 40 0 40 80 120 160 Ty JUNCTION TEMPERATURE C Figure 11 Normalized Drain to Source Breakdown Voltage vs Junction Temperature WAVEFORMS IN
11. OFF 1 5 MODEL DbodyMOD D 15 2 0 12 IKF 10 N 1 01 RS 5 6e 3 TRS1 8e 4 52 2 7 CJO 5 7e 10 M 0 52 TT 7e 11 2 MODEL DbreakMOD D RS 0 2 TRS1 1e 3 TRS2 8 9e 6 MODEL DplcapMOD D CJO 5 3e 10 15 1 30 N 10 0 37 MODEL MmedMOD NMOS VTO 1 9 5 IS 1e 30 N 10 TOX 1 L 1u W 1u RG 2 3 MODEL MstroMOD NMOS VTO 2 42 KP 150 IS 1e 30 N 10 TOX 1 L 1u W 1u MODEL MweakMOD NMOS VTO 1 62 KP 0 02 IS 1e 30 N 10 TOX 1 L 1u W 1u RG 23 RS 0 1 EBREAK 17 MWEAK RSOURCE LDRAIN DRAIN uus RLDRAIN DBREAK 11 DBODY LSOURCE SOURCE S MEER RLSOURCE RBREAK 18 RVTEMP 22 RVTHRES Note For further discussion of the PSPICE model consult A New PSPICE Sub Circuit for the Power MOSFET Featuring Global Temperature Options IEEE Power Electronics Specialist Conference Records 1991 written by William J Hepp and C Frank 2007 Fairchild Semiconductor Corporation FDS8876 Rev B www fairchildsemi com LAASOW 4U9U91 9uUEU N 9Z288SC4 SABER Electrical Model REV January 2005 template FDS8876 n2 n1 n3 electrical n2 n1 n3 var i iscl dp model dbodymod isl 2 0e 12 ikf 10 nl 1 01 rs 5 6e 3 trs 1 8e 4 trs2 2e 7 cjo 5 7e 10 m 0 52 tt 7e 11 xti 2 dp model dbreakmod rs 0 2 trs1 1e 3 trs2 8 9e 6 dp model dplcapmod cjo 5 3e 10 isl 10e 30 nl 10 m 0 37 m model mmedmod type _n vto 1 9 kp 5 is 1e 30 tox 1 m model mstrongmod type _n vto 2 42 kp
12. RTHERM6 ctherm ctherm6 4 3 2e 1 ctherm ctherm7 3 2 1 ctherm ctherm8 2 tl 3 rtherm rtherm1 th 8 1e 1 rtherm rtherm2 8 7 5e 1 RTHERM7 rtherm rtherm3 7 6 1 rtherm rtherm4 6 5 5 rtherm rtherm5 5 4 8 rtherm rtherm6 4 3 12 rtherm rtherm7 3 2 18 RIDUERM rtherm rtherm8 2 tl 25 TABLE 1 THERMAL MODELS th JUNCTION CTHERM1 CTHERM2 CTHERM3 CTHERM4 5 6 CTHERM7 CTHERM8 COMPONANT 0 04 in 0 28 in 0 52 in CTHERM6 1 2e 1 1 5e 1 2 0e 1 CTHERM7 0 5 1 0 1 0 CTHERM8 1 3 2 8 3 0 RTHERM6 26 20 15 RTHERM7 39 24 21 RTHERM8 55 38 7 31 3 29 7 2007 Fairchild Semiconductor Corporation 11 FDS8876 Rev B www fairchildsemi com LAASOW 5 9uUEU N 9Z288SC4 FAIRCHILD ees SEMICONDUCTOR TRADEMARKS The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is not intended to be an exhaustive list of all such trademarks ACEx i Lo Across the board Around the world ImpliedDisconnect ActiveArray IntelliMAX Bottomless ISOPLANAR Build it Now MICROCOUPLER CoolFET MicroPak CROSSVOLT MICROWIRE CTL Motion SPM Current Transfer Logic MSX DOME MSXPro E CMOS ocx EcoSPARK OCXPro EnSigna OPTOLOGIC FACT Quiet Series OPTOPLANAR FACT PACMAN FAS
13. T PDP SPM FASTr POP FPS Power220 FRFET Power2479 GlobalOptoisolator PowerEdge GTO PowerSaver HiSeC DISCLAIMER Power SPM TinyBoost PowerTrench TinyBuck Programmable Active Droop TinyLogic QFET TINYOPTO QST TinyPower QT Optoelectronics TinyWire Quiet Series TruTranslation RapidConfigure uSerDes RapidConnect UHC ScalarPump UniFET SMART START VOX SPM Wire STEALTH SuperFET SuperSOT 3 SuperSOT 6 SuperSOT 8 SyncFET TCM The Power Franchise FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY FUNCTION OR DESIGN FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS NOR THE RIGHTS OF OTHERS THESE SPECIFICATIONS DO NOT EXPAND THE TERMS OF FAIRCHILD S WORLDWIDE TERMS AND CONDITIONS SPECIFICALLY THE WARRANTY THEREIN WHICH COVERS THESE PRODUCTS LIFE SUPPORT POLICY FAIRCHILD S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION As used herein 1 Life support devices or systems are devices or systems which a are intended for surgical implant into the body or b support or sust
14. ain life and c whose failure to perform when properly used in accordance with instructions for use provided in the labeling can be reasonably expected to result in a significant injury of the user PRODUCT STATUS DEFINITIONS Definition of Terms 2 A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system or to affect its safety or effectiveness Datasheet Identification Product Status Definition Advance Information Formative or In Design This datasheet contains the design specifications for product development Specifications may change in any manner without notice Preliminary First Production No Identification Needed Full Production This datasheet contains preliminary data supplementary data will be published at a later date Fairchild Semiconductor reserves the right to make changes at any time without notice to improve esign This datasheet contains final specifications Fairchild Semiconductor reserves the right to make changes at any time without notice to improve design Obsolete Not In Production This datasheet contains specifications product that has been discontinued by Fairchild Semiconductor The datasheet is printed for reference information only Rev 126 02007 Fairchild Semiconductor Corporation 12 www fairchildsemi com FDS8876 R
15. e Threshold to Plateau 2 8 nC Gate to Drain Miller Charge 5 0 nC 2007 Fairchild Semiconductor Corporation 2 FDS8876 Rev B www fairchildsemi com Switching Characteristics Vos 10V 1 Starting Ty 25 C L 1mH las 14 5A Vpp 30V Veg 10V 2 Roya is the sum of the junction to case and case to ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of the drain pins is guaranteed by design while is determined by the user s board design a 50 C W when mounted on a tin pad of 2 oz copper b 125 C W when mounted on a minimum pad ton Turn On Time 63 ns Turn On Delay Time 8 ns tr Rise Time Vpp 15V Ip 12 5A 34 ns ta oFF Turn Off Delay Time Ves 10V Reg 100 53 ns ty Fall Time 19 ns torr Turn Off Time 108 ns Drain Source Diode Characteristics na Isp 12 5A 1 25 V Vsp Source to Drain Diode Voltage Isp 2 1A 1 0 V m Reverse Recovery Time Isp 12 5A 15 9 100A us 29 ns QRR Reverse Recovered Charge Isp 12 5A dlgp dt 100A us 15 nC Notes 2007 Fairchild Semiconductor Corporation FDS8876 Rev www fairchildsemi com LAASOW 4U9U91 9UUEU N 9 88SQ4 Typical Characteristics 25 unless otherwise noted 16 1 2 1 0 12 Ip DRAIN
16. e use of external heat sinks The use of thermal vias Air flow and board orientation A For non steady state applications the pulse width the duty cycle and the transient thermal response of the part the board and the environment they are in Fairchild provides thermal information to assist the design er s preliminary application evaluation Figure 21 defines the Roya for the device as a function of the top copper compo nent side area This is for a horizontally positioned FR 4 board with 1oz copper after 1000 seconds of steady state power with no air flow This graph provides the necessary in formation for calculation of the steady state junction temper ature or power dissipation Pulse applications can be evaluated using the Fairchild device Spice thermal model or the normalized maximum transient thermal impedance curve Thermal resistances corresponding to other copper areas can be obtained from Figure 21 or by calculation using Equation 2 The area in square inches is the top copper area including the gate and source pads 26 R REESE orsi RN 0 28 Area 64 EQ 2 0JA The transient thermal impedance ZoJA is also effected by varied top copper board area Figure 22 shows the effect of copper pad area on single pulse transient thermal imped ance Each trace represents copper pad area in square inches corresponding to the descending list in the graph Spice and SABER thermal models are p
17. ev B LAASOW 4U92U94 19MOog 9UUEU N 9788SQ4
18. rovided for each of the listed pad areas Copper pad area has no perceivable effect on transient thermal impedance for pulse widths less than 100ms For pulse widths less than 100ms the transient thermal impedance is determined by the die and package Therefore CTHERM1 through 5 and RTHERM1 through RTHERM5 remain constant for each of the thermal models A listing of the model component values is available in Table 1 200 Roua 64 26 0 23 Area 150 Roja C W 100 50 0 001 0 01 0 1 1 10 AREA TOP COPPER AREA in Figure 21 Thermal Resistance vs Mounting manually utilizing Pad Area 150 _ COPPER BOARD AREA DESCENDING ORDER 0 04 in _ 120 0 28 in 48 0 52 in 59 0 76 90 100in uo 2 amp iu 60 Nz 30 0 101 10 101 10 103 t RECTANGULAR PULSE DURATION s Figure 22 Thermal Impedance vs Mounting Pad Area 2007 Fairchild Semiconductor Corporation FDS8876 Rev B www fairchildsemi com 133SOlN 4U9U91 9UuUEU N 9788SQ4 SUBCKT FDS8876 213 Ca 12 8 10 3 10 Cb 15 14 10 3e 10 Cin 6 8 1 6e 9 Dbody 7 5 DbodyMOD Dbreak 5 11 DbreakMOD Dplcap 10 5 DplcapMOD Ebreak 11 7 17
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FAIRCHILD FDS8876 Manual