PHILIPS PCK351 handbook
Contents
1. tpty tpH_ propagation delay A to Yn C 50 pF see Figures 5 and 8 3 1 3 6 4 1 ns tpzH tpz_ propagation delay OE to Yn C 50 pF see Figures 6 and 8 1 8 3 8 5 5 ns tpyz tp_z propagation delay OE to Yn C 50 pF see Figures 6 and 8 1 8 4 0 5 9 ns tsk o output to output skew Ato Yn Cu 50 pF see Figures 7 and 8 0 3 0 5 ns tsk p pulse skew A to Yn C 50 pF see Figures 7 and 8 0 2 0 8 ns tsk pr part to part skew A to Yn C 50 pF see Figures 7 and 8 1 ns tr rise time A to Yn C 50 pF see Figures 5 and 8 ns ti fall time A to Yn C 50 pF see Figures 5 and 8 ns Vcc 3 3 to 3 6 V Tamb 0 C to 70 C tpty tpH_ propagation delay A to Yn C 50 pF see Figures 5 and 8 ns tpzp t ez propagation delay OE to Y C 50 pF see Figures 6 and 8 1 3 5 9 ns tpyz tp_z propagation delay OE to Y C 50 pF see Figures 6 and 8 1 7 6 3 ns tsk o output to output skew Ato Yn Cu 50 pF see Figures 7 and 8 0 5 ns tsk p pulse skew A to Yn C 50 pF see Figures 7 and 8 0 8 ns tsk pr part to part skew A to Yn C 50 pF see Figures 7 and 8 1 ns tr rise time A to Yn C 50 pF see Figures 5 and 8 1 5 ns ti fall time A to Yn C 50 pF see Figures 5 and 8 1 5 ns Table 9 Switching characteristics Temperature and Vcc coefficients over recommended operating free air temperature and Vcc range note 1 AtpLH T temperature co2. 00000uee 4 6 1 Function table 200200000 ee 4 6 2 Logic symbol 0 00 e eee eee eee 4 6 3 Logic diagram 0 eee eee 5 7 Limiting valueS 2 0 0c eee eee eee 6 8 Recommended operating conditions 6 9 Static characteristics 0 000000 7 10 Dynamic characteristics 8 10 1 AC waveforms 0002 cee ee eeee 9 11 Package outline 00e cece eee 12 12 Soldering wise cee cee s ew eee ie ee 14 12 1 Introduction to soldering surface mount packages ected horr oorsien uoe ra Gees 14 12 2 Reflow soldering nanana nuanua 14 12 3 Wave soldering n nanunua aeea 14 12 4 Manual soldering asasena aaan 15 12 5 Package related soldering information 15 13 Revision history 0 000 cence ences 15 14 Data sheet statuS 00 0 e ee eee 16 15 Definitions scr gentacunedews cones gems 16 16 Disclaimers 220622 60 es eis eee ee ioniza 16 Koninklijke Philips Electronics N V 2002 Printed in the U S A All rights are reserved Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner The information presented in this document does not form part of any quotation or contract is believed to be accurate and reliable and may be changed without notice No liability will be accepted by the publisher for any consequence of its use Publication thereof does not convey nor imply any license under patent
3. DIMENSIONS mm are the original dimensions A UNIT ax At A2 As 1 80 2 0 1 65 Note 1 Plastic or metal protrusions of 0 20 mm maximum per side are not included OUTLINE REFERENCES EUROPEAN VERSION JEDEC EIAJ PROJECTION SOT340 1 MO 150 Ey as aa ISSUE DATE Fig 10 SSOP24 package outline SOT340 1 9397 750 09791 Koninklijke Philips Electronics N V 2002 All rights reserved Product data Rev 01 14 May 2002 13 of 17 Philips Semiconductors PCK351 12 Soldering 9397 750 09791 12 1 12 2 12 3 1 10 clock distribution device with 3 State outputs Introduction to soldering surface mount packages This text gives a very brief insight to a complex technology A more in depth account of soldering ICs can be found in our Data Handbook IC26 Integrated Circuit Packages document order number 9398 652 90011 There is no soldering method that is ideal for all surface mount IC packages Wave soldering can still be used for certain surface mount ICs but it is not suitable for fine pitch SMDs In these situations reflow soldering is recommended Reflow soldering Reflow soldering requires solder paste a suspension of fine solder particles flux and binding agent to be applied to the printed circuit board by screen printing stencilling or pressure syringe dispensing before package p
4. or other industrial or intellectual property rights Date of release 14 May 2002 Document order number 9397 750 09791 1 10 clock distribution device with 3 State outputs PHILIPS Lot make things bette
5. 2002 All rights reserved Product data Rev 01 14 May 2002 3 of 17 Philips Semiconductors PCK351 1 10 clock distribution device with 3 State outputs 6 Functional description 6 1 Function table Table 4 Function table L H Z H H Z L L L H L H 1 H HIGH voltage level L LOW voltage level Z high impedance OFF state 6 2 Logic symbol V V V V V V V V V y 002aaa283 Fig 3 Logic symbol 9397 750 09791 Koninklijke Philips Electronics N V 2002 All rights reserved Product data Rev 01 14 May 2002 4 of 17 Philips Semiconductors PCK351 9397 750 09791 1 10 clock distribution device with 3 State outputs 6 3 Logic diagram Fig 4 Logic diagram 002aaa282 Koninklijke Philips Electronics N V 2002 All rights reserved Product data Rev 01 14 May 2002 5 of 17 Philips Semiconductors PCK351 1 10 clock distribution device with 3 State outputs 7 Limiting values Table 5 Limiting values In accordance with the Absolute Maximum Rating System IEC 60134 1 21 Vec supply voltage range 0 5 4 6 V VI input voltage range B 0 5 7 0 V Vo output voltage range BI 0 5 3 6 V lik input clamp current Vi lt 0V 18 mA lox output clamp current Vi lt O0V 50 mA lo output sink current 64 mA lcc lanp Vec or GND current E 75 mA Tstg storage temperature 65 150 C Pp m
6. such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application Right to make changes Philips Semiconductors reserves the right to make changes without notice in the products including circuits standard cells and or software described or contained herein in order to improve design and or performance Philips Semiconductors assumes no responsibility or liability for the use of any of these products conveys no licence or title under any patent copyright or mask work right to these products and makes no representations or warranties that these products are free from patent copyright or mask work right infringement unless otherwise specified For additional information please visit http www semiconductors philips com For sales office addresses send e mail to sales addresses www semiconductors philips com 9397 750 09791 Fax 31 40 27 24825 Koninklijke Philips Electronics N V 2002 All rights reserved Product data Rev 01 14 May 2002 16 of 17 Philips Semiconductors PCK351 Contents 1 Description lt cerro awe eae ede 1 2 FOaAtures iscsi ccc ee eee siaaa gis 1 3 Quick reference data 0eeeeeeue 2 4 Ordering information 0 00e000 2 5 Pinning information 2 00 0 e eens 3 5 1 PINNING segr cewek Gh ee POR ees 3 5 2 Pin description 0 00 c eee eee 3 6 Functional description
7. 1 Description 2 Features PCK351 1 10 clock distribution device with 3 State outputs Rev 01 14 May 2002 Product data The PCK351 is a high performance 3 3 V LVTTL clock distribution device The PCK351 enables a single clock input to be distributed to ten outputs with minimum output skew and pulse skew The use of distributed Vcc and GND pins in the PCK351 ensures reduced switching noise The PCK351 is characterized for operation over the supply range 3 0 V to 3 6 V and over the industrial temperature range 40 to 85 C 1 10 LVTTL clock distribution Low output to output skew Low output pulse skew Over voltage tolerant inputs and outputs LVTTL compatible inputs and outputs Distributed Vcc and ground pins reduce switching noise Balanced High drive outputs 32 mA lop 32 MA lot Reduced power dissipation due to the state of the art QUBiC LP process Supply range of 3 0 V to 3 6 V Package options include plastic small outline D and shrink small outline DB packages Industrial temperature range 40 to 85 C PCK351 is identical to and replaces PTN3151 PHILIPS Philips Semiconductors PCK351 1 10 clock distribution device with 3 State outputs 3 Quick reference data Table 1 Quick reference data GND 0 V Tamp 25 C t t lt 3 0 ns tpHL tPLH propagation delay A to Yn C 50 pF Vec 3 3 V 3 1 3 6 4 1 ns Ci input capacitance Vi Vcc or GND 4 pF Co output capacitanc
8. K351 1 10 clock distribution device with 3 State outputs 9 Static characteristics Table 7 DC characteristics Over recommended operating conditions voltages are referenced to GND ground 0 V Tamp 25 C Vik input diode voltage Voc 3 0 V l 18 mA 1 2 V Vou HIGH level output voltage Vcc 3 0 V loH 32 mA 2 0 V VoL LOW level output voltage Vcc 3 0 V loL 32 mA 0 5 V lu input leakage current Voc 3 6 V Vi GND or 5 5 V 1 0 uA ILo output leakage current Vec 3 6 V Vo 2 5 V 15 150 mA loz 3 State output OFF state Vcc 3 6 V Vo 3 V mo 10 uA current loc quiescent supply current Vcc 3 6 V Vi Vcc or GND l 0 0 3 mA outputs HIGH Voc 3 6 V Vi Voc or GND Io 0 z 25 mA outputs LOW Voc 3 6V Vi Voc or GND lo 0 s A 0 3 mA outputs disabled Ci input capacitance Vec 3 3 V Vi Vcc or GND 4 pF f 10 MHz Co output capacitance Vec 3 3 V Vo Vec or GND 6 pF f 10 MHz 1 Not more than one output should be tested at a time and the duration of the test should not exceed one second 9397 750 09791 Koninklijke Philips Electronics N V 2002 All rights reserved Product data Rev 01 14 May 2002 7 of 17 Philips Semiconductors PCK351 1 10 clock distribution device with 3 State outputs 10 Dynamic characteristics Table 8 AC characteristics GND 0 V t t lt 3 0 ns Vcc 3 3 V Tamb 25 C
9. a sheet may have changed since this data sheet was published The latest information is available on the Internet at URL http www semiconductors philips com 15 Definitions Short form specification The data in a short form specification is extracted from a full data sheet with the same type number and title For detailed information see the relevant data sheet or data handbook Limiting values definition Limiting values given are in accordance with the Absolute Maximum Rating System IEC 60134 Stress above one or more of the limiting values may cause permanent damage to the device These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied Exposure to limiting values for extended periods may affect device reliability Application information Applications that are described herein for any of these products are for illustrative purposes only Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification Contact information 16 Disclaimers Life support These products are not designed for use in life support appliances devices or systems where malfunction of these products can reasonably be expected to result in personal injury Philips Semiconductors customers using or selling these products for use in
10. aximum power dissipation SO package Tamb 55 C 0 65 W SSOP package Tamb 55 C 1 7 W 1 Stresses beyond those listed may cause permanent damage to the device These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied Exposure to absolute maximum rated conditions for extended periods may affect device reliability 2 The performance capability of a high performance integrated circuit in conjunction with its thermal environment can create junction temperatures which are detrimental to reliability The maximum junction temperature of this integrated circuit should not exceed 150 C 3 The input and output negative voltage ratings may be exceeded if the input and output clamp currents are observed 8 Recommended operating conditions 9397 750 09791 Table 6 Recommended operating conditions See note 1 Vec supply voltage 3 0 3 6 V Vin HIGH level input voltage 2 0 5 5 V VI input voltage 0 0 8 V Tamb ambient temperature see Table 7 DC 40 85 C characteristics and Table 8 AC characteristics per device tr t input rise and fall times Vec 3 3 0 3 V 100 ns V 1 Unused pins input or I O must be held HIGH or LOW Koninklijke Philips Electronics N V 2002 All rights reserved Product data Rev 01 14 May 2002 6 of 17 Philips Semiconductors PC
11. d at a 45 angle to the transport direction of the printed circuit board The footprint must incorporate solder thieves downstream and at the side corners Koninklijke Philips Electronics N V 2002 All rights reserved Product data Rev 01 14 May 2002 14 of 17 Philips Semiconductors PCK351 1 10 clock distribution device with 3 State outputs During placement and before soldering the package must be fixed with a droplet of adhesive The adhesive can be applied by screen printing pin transfer or syringe dispensing The package can be soldered after the adhesive is cured Typical dwell time is 4 seconds at 250 C A mildly activated flux will eliminate the need for removal of corrosive residues in most applications 12 4 Manual soldering Fix the component by first soldering two diagonally opposite end leads Use a low voltage 24 V or less soldering iron applied to the flat part of the lead Contact time must be limited to 10 seconds at up to 300 C When using a dedicated tool all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 C 12 5 Package related soldering information Table 10 Suitability of surface mount IC packages for wave and reflow soldering methods HBCC HBGA HLQFP HSQFP HSOP not suitable suitable HTQFP HTSSOP HVQFN HVSON SMS PLCCI4 SO SOJ suitable suitable LQFP QFP TQFP not recommended 4ls5 suitable SSOP TSSOP VSO not recomme
12. e Vi Vcc or GND 6 pF Cpp power dissipation capacitance C 50 pF f 1 MHz 48 pF 1 Cpp is used to determine the dynamic power dissipation Pp in uW Pp Cpp X Voc x fi Ci x Vec x fo where fi input frequency in MHz fo output frequency in MHz E CL x Voc x fo sum of outputs C output load capacitance in pF Voc supply voltage in Volts 4 Ordering information Table 2 Ordering information PCK351D S024 plastic small outline package 24 leads body width 7 5 mm SOT137 1 PCK351DB SSOP24 plastic shrink small outline package 24 leads body width 5 3 mm SOT340 1 9397 750 09791 Koninklijke Philips Electronics N V 2002 All rights reserved Product data Rev 01 14 May 2002 2 of 17 Philips Semiconductors PCK351 1 10 clock distribution device with 3 State outputs 5 Pinning information 5 1 Pinning GND GND GND Yio Y1 Yio Voc Voc Voc Y2 Yg GND OE a a Y3 A 8 p GND 5 Y4 GND g a O anD 8 GND GND a Y5 Yg Voc Voc Voc Y6 Y7 GND GND GND 002aaa280 002aaa281 Fig 1 S024 pin configuration Fig 2 SSOP24 pin configuration 5 2 Pin description Table 3 Pin description GND 1 7 8 12 13 17 20 24 ground 0 V Yio to Y1 2 4 9 11 14 16 18 19 21 23 outputs Vec 3 10 15 22 supply voltage OE 5 output enable input Active LOW A 6 data input 9397 750 09791 Koninklijke Philips Electronics N V
13. efficient of LOW to HIGH propagation delay A to Yn note 2 65 ps 10 C average value AtpHL T temperature coefficient of HIGH to LOW propagation delay A to Yn note 2 45 ps 10 C average value AtpLH v Vec coefficient of LOW to HIGH propagation delay A to Yn note 3 140 ps 100 mV average value AtpHL v Vec coefficient of HIGH to LOW propagation delay A to Yn note 3 120 ps 100 mV average value 1 These data were extracted from characterization material and are not tested at the factory 2 AtptHcr and Atp are virtually independent of Vcc 3 AtpLHcv and Atphov are virtually independent of temperature 9397 750 09791 Koninklijke Philips Electronics N V 2002 All rights reserved Product data Rev 01 14 May 2002 8 of 17 Philips Semiconductors PCK351 9397 750 09791 1 10 clock distribution device with 3 State outputs 10 1 AC waveforms Yh Output VOL a 0024aa289 Fig 5 The input A to outputs Yn propagation delays and rise and fall times 3V OE input 1 5V ov Voc output LOW to OFF OFF to LOW VoL VoH output HIGH to OFF OFF to HIGH GND outputs outputs outputs disabled disabled disabled 002aaa290 Fig 6 3 State enable and disable times Koninklijke Philips Electronics N V 2002 All rights reserved Product data Rev 01 14 May 2002 9 of 17 Philips Semiconductors PCK351 1 10 clock distribu
14. eserved Product data Rev 01 14 May 2002 11 of 17 PCK351 1 10 clock distribution device with 3 State outputs Philips Semiconductors 11 Package outline S024 plastic small outline package 24 leads body width 7 5 mm SOT137 1 detail X 5 scale DIMENSIONS inch dimensions are derived from the original mm dimensions A3 p 6 He UNIT Ay Ao 15 6 7 6 15 2 7 4 inches i TA ee Note 1 Plastic or metal protrusions of 0 15 mm maximum per side are not included OUTLINE REFERENCES EUROPEAN ISSUE DATE VERSION IEC JEDEC EIAJ PROJECTION SOT137 1 075E05 MS 013 ES 99 12 27 Fig 9 S024 package outline SOT137 1 Koninklijke Philips Electronics N V 2002 All rights reserved 12 of 17 9397 750 09791 Product data Rev 01 14 May 2002 Philips Semiconductors PCK351 1 10 clock distribution device with 3 State outputs SSOP24 plastic shrink small outline package 24 leads body width 5 3 mm SOT340 1 pin 1 index i i T lt lt detail X
15. lacement Several methods exist for reflowing for example convection or convection infrared heating in a conveyor type oven Throughput times preheating soldering and cooling vary between 100 and 200 seconds depending on heating method Typical reflow peak temperatures range from 215 to 250 C The top surface temperature of the packages should preferable be kept below 220 C for thick large packages and below 235 C small thin packages Wave soldering Conventional single wave soldering is not recommended for surface mount devices SMDs or printed circuit boards with a high component density as solder bridging and non wetting can present major problems To overcome these problems the double wave soldering method was specifically developed If wave soldering is used the following conditions must be observed for optimal results e Use a double wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave e For packages with leads on two sides and a pitch e larger than or equal to 1 27 mm the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed circuit board smaller than 1 27 mm the footprint longitudinal axis must be parallel to the transport direction of the printed circuit board The footprint must incorporate solder thieves at the downstream end e For packages with leads on four sides the footprint must be place
16. nded s suitable 1 For more detailed information on the BGA packages refer to the LF BGA Application Note AN01026 order a copy from your Philips Semiconductors sales office 2 All surface mount SMD packages are moisture sensitive Depending upon the moisture content the maximum temperature with respect to time and body size of the package there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them the so called popcorn effect For details refer to the Drypack information in the Data Handbook IC26 Integrated Circuit Packages Section Packing Methods 3 These packages are not suitable for wave soldering On versions with the heatsink on the bottom side the solder cannot penetrate between the printed circuit board and the heatsink On versions with the heatsink on the top side the solder might be deposited on the heatsink surface 4 If wave soldering is considered then the package must be placed at a 45 angle to the solder wave direction The package footprint must incorporate solder thieves downstream and at the side corners 5 Wave soldering is suitable for LQFP QFP and TQFP packages with a pitch e larger than 0 8 mm it is definitely not suitable for packages with a pitch e equal to or smaller than 0 65 mm 6 Wave soldering is suitable for SSOP and TSSOP packages with a pitch e equal to or larger than 0 65 mm it is definitely not suitable for packages with a pi
17. tch e equal to or smaller than 0 5 mm 13 Revision history Table 11 Revision history 01 20020514 Product data initial version Engineering Change Notice 853 2344 28198 9397 750 09791 Koninklijke Philips Electronics N V 2002 All rights reserved Product data Rev 01 14 May 2002 15 of 17 Philips Semiconductors PCK351 14 Data sheet status Objective data 1 10 clock distribution device with 3 State outputs Development This data sheet contains data from the objective specification for product development Philips Semiconductors reserves the right to change the specification in any manner without notice Preliminary data Qualification This data sheet contains data from the preliminary specification Supplementary data will be published at a later date Philips Semiconductors reserves the right to change the specification without notice in order to improve the design and supply the best possible product Product data Production This data sheet contains data from the product specification Philips Semiconductors reserves the right to make changes at any time in order to improve the design manufacturing and supply Changes will be communicated according to the Customer Product Process Change Notification CPCN procedure SNW SQ 650A 1 Please consult the most recently issued data sheet before initiating or completing a design 2 The product status of the device s described in this dat
18. tion device with 3 State outputs A input Y4 output PHL1 a PLH1 me Yo output tPHL2 e PLH2 P Y3 output PHL3 kK tPLH3 lt Y4 output PHL4 gt PLH4 _ Y5 output tPHLS e PLH5 me Y6 output PHL6 gt PLH6 r Y7 output tPHL7 e PLH7 lt _ __ Yg output tPHL8 gt PLH8 ma Yg output PHL9 gt tPLH9 mae Y10 output 002aaa286 PHL10 gt a PLH10 1 Output to output skew is the highest values of positive and negative edge skew tsk o teLHn max PLHn min ANd tsk o PHLn max PHLn min for n 1 to 10 2 Output pulse skew is the highest value of tsk p ItpLHn teHinl for n 1 to 10 3 Part to part skew tsk pr represents the positive and negative edge skew between outputs of several devices operating under identical conditions Fig 7 Calculation of tsx o tsk p ANd tsk pr 9397 750 09791 Koninklijke Philips Electronics N V 2002 All rights reserved Product data Rev 01 14 May 2002 10 of 17 Philips Semiconductors PCK351 9397 750 09791 1 10 clock distribution device with 3 State outputs an open Voc 5009 GND VI Vo PULSE GENERATOR ik 1 CL Rr I 50 pF 5002 7 4 7 A A 002aaa285 Tenia open tpHz tpzH GND Fig 8 Load circuitry for switching times Koninklijke Philips Electronics N V 2002 All rights r
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PHILIPS PCK351 handbook