PHILIPS 74F2373 handbook
Contents
1. Oz 1 2 l Input current at maximum input voltage Vcc MAX V 7 0V D High level input current Vcc MAX V 2 7V O Low level input current Voc MAX V 0 5V 6 Off state output current high level voltage applied Voc MAX Vo 2 7V 5 Off state output current low level voltage applied Voc MAX Vo 0 5V mE Short circuit output current Voc MAX 60 150 Supply ourrent otal Voc MAX OO NOTES 1 For conditions shown as MIN or MAX use the appropriate value specified under recommended operating conditions for the applicable type 2 All typical values are at Vcc 5V Tamb 25 C 3 Not more than one output should be shorted at a time For testing los the use of high speed test apparatus and or sample and hold techniques are preferable in order to minimize internal heating and more accurately reflect operational values Otherwise prolonged shorting of a high output may raise the chip temperature well above normal and thereby cause invalid readings in other parameter tests In any sequence of parameter tests los tests should be performed last 1999 Feb 01 4 Philips Semiconductors Product specification Octal transparent latch with 30Q equivalent output termination 3 State 74F2373 AC ELECTRICAL CHARACTERISTICS Tamb 25 C Tamb 0 C to 70 C SYMBOL PARAMETER TEST Voc 5 0V Vee 5 0V 10 CONDITION PLH Propagation delay tPHZ Output disable time tpLz from high or low level A2. using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application Right to make changes Philips Semiconductors reserves the right to make changes without notice in the products including circuits standard cells and or software described or contained herein in order to improve design and or performance Philips Semiconductors assumes no responsibility or liability for the use of any of these products conveys no license or title under any patent copyright or mask work right to these products and makes no representations or warranties that these products are free from patent copyright or mask work right infringement unless otherwise specified Philips Semiconductors Copyright Philips Electronics North America Corporation 1998 811 East Arques Avenue All rights reserved Printed in U S A P O Box 3409 Sunnyvale California 94088 3409 print code Date of release 10 98 Telephone 800 234 7381 Document order number 9397 750 05201 Lett make things beter ee PHILIPS
3. C SETUP REQUIREMENTS Tamb 0 C to 70 C SYMBOL PARAMETER TEST Vcc 5 0V Vec 5 0V 10 CONDITION C 50pF R 5002 C 50pF R 5000 tsu H Setup time high or low level 0 tsu L Dn to E Waveform 3 5 th H Hold time high or low level 3 0 tn b Waveform 3 3 0 Dn to E tw H E Pulse width high 5 AC WAVEFORMS For all waveforms Vyp 1 5V The shaded areas indicate when the input is permitted to change for predictable output performance SF00261 SF00259 Waveform 3 Data setup time and hold times Waveform 1 Propagation delay for enable to output and enable pulse width B VOH 0 3V SF00260 SF00263 Waveform 2 Propagation delay for data to output Waveform 4 3 State output enable time to high level and output disable time from high level 1999 Feb 01 5 Philips Semiconductors Product specification Octal transparent latch with 30Q equivalent output 74F2373 termination 3 State AC WAVEFORMS Continued For all waveforms Vy 1 5V The shaded areas indicate when the input is permitted to change for predictable output performance VOL 0 3V SF00264 Waveform 5 3 State output enable time to low level and output disable time from low level TEST CIRCUIT AND WAVEFORMS SWITCH POSITION TEST SWITCH 90 tpLz tpz_ closed NEGATIVE Allother open PULSE PULSE GENERATOR POSITIVE PULSE Test circuit for 3 state ou
4. DATA SAHEET 74F2373 Octal transparent latch with 30Q equivalent output termination 3 State Product specification 1999 Feb 01 Supersedes data of 1995 Jun 20 IC15 Data Handbook PHILIPS Philips Semiconductors Philips Semiconductors Product specification Octal transparent latch with 30Q equivalent output termination 3 State 74F2373 FEATURES 8 bit transparent latch 30 Ohm output termination for driving DRAM 3 State outputs glitch free during power up and power down Common 3 State output register Independent register and 3 State buffer operation DESCRIPTION The 74F2373 is an octal transparent latch coupled to eight 3 State output devices The two sections of the device are controlled independently by enable E and output enable OE control gates The 30 Ohm series termination on the outputs reduces over undershoot making them ideal for driving DRAM ORDERING INFORMATION The data on the D inputs is transferred to the latch outputs when the enable E input is high The latch remains transparent to the data input while E is high and stores the data that is present one setup time before the high to low enable transition The 3 State output buffers are designed to drive heavily loaded 3 State buses MOS memories or MOS microprocessors The active low output enable OE controls all eight 3 State buffers independent of the latch operation When OE is low latched or transparent data a
5. change Don t care High impedance off state High to low enable transition 1999 Feb 01 3 Philips Semiconductors Product specification Octal transparent latch with 30Q equivalent output termination 3 State 74F2373 ABSOLUTE MAXIMUM RATINGS Operation beyond the limit set forth in this table may impair the useful life of the device Unless otherwise noted these limits are over the operating free air temperature range SYMBOL PARAMETER RATING UNIT V Supply voltage 0 5 to 7 0 V Input voltage 0 5 to 7 0 Input current 30 to 5 Voltage applied to output in high output state 0 5 to Voc Current applied to output in low output state Tamb Operating free air temperature range 0 to 70 Tstg Storage temperature range RECOMMENDED OPERATING CONDITIONS LIMITS SYMBOL PARAMETER a aan uT pS arawere roe Vin ahrevelinputwotags CP TCT Cd Low level output current 12mA with reduced noise margin DC ELECTRICAL CHARACTERISTICS Over recommended operating free air temperature range unless otherwise noted TEST LIMITS SYMBOL PARAMETER CONDITIONS MIN TYP MAX Vin MIN loH 3MA 5 Vcc 2 7 3 4 Vou High level output voltage Sojer jst e Voc MIN Vi MAX 10 Voc 0 42 0 50 Vin MIN lop 5mA 5 V 42 VoL Low level output voltage us foL om Ee 042 050 Voc MIN Vi MAX 10 Voc 0 67 ViW MIN o tama e forj Input clamp voltage Voc MIN l lik
6. leads body width 7 5 mm SOT163 1 detail X 5 scale DIMENSIONS inch dimensions are derived from the original mm dimensions 0 012 0 096 0 019 0 013 0 004 0 089 i 0 014 0 009 Note 1 Plastic or metal protrusions of 0 15 mm maximum per side are not included OUTLINE REFERENCES EUROPEAN VERSION IEC JEDEC EIAJ PROJECTION SOT163 1 075E04 MS 013AC P ISSUE DATE 1999 Feb 01 8 Philips Semiconductors Product specification Octal transparent latch with 30Q equivalent output 74F2373 termination 3 State NOTES 1999 Feb 01 9 Philips Semiconductors Product specification Octal transparent latch with 30Q equivalent output termination 3 State 74F2373 Data sheet status Data sheet Product Definition 1 status status Objective Development This data sheet contains the design target or goal specifications for product development specification Specification may change in any manner without notice Preliminary Qualification This data sheet contains preliminary data and supplementary data will be published at a later date specification Philips Semiconductors reserves the right to make chages at any time without notice in order to improve design and supply the best possible product Product Production This data sheet contains final specifications Philips Semiconductors rese
7. ppears at the output When OE is high the outputs are in high impedance off state which means they will neither drive nor load the bus TYPICAL TYPICAL SUPPLY PROPAGATION CURRENT DELAY TOTAL ORDERCODE td CODE DESCRIPTION oe RANGE DRAWING NUMBER Vec 5V 10 Tamb 0 C to 70 C 20 pin plastic DIP N74F2373N SOT 146 1 20 pin plastic SOL N74F2373D SOT 163 1 INPUT AND OUTPUT LOADING AND FAN OUT TABLE 74F U L LOAD VALUE Enable input active high 1 0 1 0 20nA 0 6mA Output enable inputs active low 1 0 1 0 20uA 0 6mA o7 750140 SOMAS OMA NOTE One 1 0 FAST unit load is defined as 20A in the high state and 0 6mA in the low state PIN CONFIGURATION SF00250 1999 Feb 01 LOGIC SYMBOL 13 14 17 18 DO Di D2 D3 D4 D5 D6 D7 9 12 15 16 19 Voc Pin 20 GND Pin 10 SF00251 853 2140 20747 Philips Semiconductors Product specification Octal transparent latch with 30Q equivalent output termination 3 State 74F2373 IEC IEEE SYMBOL SF00252 LOGIC DIAGRAM Voc Pin 20 GND Pin 10 SF00256 OPERATING MODE Enable and read register FUNCTION TABLE Latch and read register Disable outputs High voltage level High state must be present one setup time before the high to low enable transition Low voltage level Low state must be present one setup time before the high to low enable transition No
8. rves the right to make specification changes at any time without notice in order to improve design and supply the best possible product 1 Please consult the most recently issued datasheet before initiating or completing a design Definitions Short form specification The data in a short form specification is extracted from a full data sheet with the same type number and title For detailed information see the relevant data sheet or data handbook Limiting values definition Limiting values given are in accordance with the Absolute Maximum Rating System IEC 134 Stress above one or more of the limiting values may cause permanent damage to the device These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied Exposure to limiting values for extended periods may affect device reliability Application information Applications that are described herein for any of these products are for illustrative purposes only Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification Disclaimers Life support These products are not designed for use in life support appliances devices or systems where malfunction of these products can reasonably be expected to result in personal injury Philips Semiconductors customers
9. tputs DEFINITIONS tw Input pulse definition Load resistor see AC electrical characteristics for value INPUT PULSE REQUIREMENTS Load capacitance includes jig and probe capacitance see AC electrical characteristics for value amplitude Vm rep rate tw ttTLH tTHL Termination resistance should be equal to Zour of pulse 3 0V 4MHz 25ns 2 5ns generators i i i SF00265 1999 Feb 01 6 Philips Semiconductors Octal transparent latch with 30Q equivalent output termination 3 State DIP20 plastic dual in line package 20 leads 300 mil lt seating plane scale DIMENSIONS inch dimensions are derived from the original mm dimensions Product specification 74F2373 SOT146 1 A Ay A2 UNIT max min max b b4 c p Et z max 1 73 0 53 4 2 0 51 3 2 130 0 38 26 92 26 54 6 40 6 22 0 254 2 0 0 068 0 021 inches 0 17 0 020 0 13 0 051 0 015 1 060 1 045 0 25 0 24 0 01 0 078 Note 1 Plastic or metal protrusions of 0 25 mm maximum per side are not included OUTLINE REFERENCES VERSION JEDEC EIAJ EUROPEAN PROJECTION ISSUE DATE SOT146 1 C603 EJ 92 44 44 95 05 24 1999 Feb 01 Philips Semiconductors Product specification Octal transparent latch with 30Q equivalent output 74F2373 termination 3 State 020 plastic small outline package 20
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PHILIPS 74F2373 handbook