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freescale MC68HC908AP64A MC68HC908AP32A MC68HC908AP16A MC68HC908AP8A Data Sheet Manual

1. dew aw ee wes 19 Chapter 2 MenmtalV usi odd mac ca Pac WO CAE RU CU Je RU Odd C a 29 Chapter 3 Configuration amp Mask Option Registers CONFIG 8 MOR 49 Chapter 4 Central Processor Unit 55 Chapters Oscillator sus erm pa CER WR 71 Chapter 6 Clock Generator Module 79 Chapter 7 System Integration Module 97 Chapter 8 Monitor ROM 115 Chapter 9 Timer Interface Module 131 Chapter 10 Timebase Module 147 Chapter 11 Serial Communications Interface Module 8 151 Chapter 12 Infrared Serial Communications Interface Module IRSCI 177 Chapter 13 Serial Peripheral Interface Module 205 Chapter 14 Multi Master Interface 225 Chapter 15 Analog to Digital Converter 243 Chapter 16 Input Output VO 255 Chapter 17 External Interrupt IRQ eee kh wee RR nm e n 267 Chapter 18 Keyboard Interrupt Module
2. X1OH VIOH 19 6 v 6 v v v 5 v 6 XI 146 IXI 5 151 visl 151 13589 19599 8 v 9 v v v v 6 5 IXI 5 VLS VIS VIS VIS VIS VIS XHSV VHSV usv d10d H OHH 4 v 8 v v v v 6 XI 146 5 t vaql vaql vaql vaql XHOH VHOH HOH aNg 1354 Lasud 9 2 v 5 S v v v 5 v 6 XI 5 LXI 0 246 t 64 Lid XHLS sog 5 v 6 6 6 XI 1496 IXI 2246 81 vus 951 998 1959 13 v v 5 6 L L v S v 6 5 IXI 2848 XINOO VINOO WOO 514 v 6 v v v 6 v 6 XI 5 2246 HNI ogas 295 295 985 295 295 FAWN 1989 LL3SHH v 6 9 v v 4 6 5 v 9 XI 5 c ecdS
3. ADCH4 ADCH3 ADCH2 ADCH1 ADCHO ADC Channel Input Select 0 0 0 0 0 ADCO PTAO 0 0 0 0 1 ADC1 PTA1 0 0 0 1 0 ADC2 PTA2 0 0 0 1 1 0 0 1 0 0 ADC4 PTA4 0 0 1 0 1 ADC5 5 0 0 1 1 0 ADC6 PTA6 0 0 1 1 1 ADC7 PTA7 0 1 0 0 0 ADC8 l l l l Reserved 1 1 1 0 0 ADC28 1 1 1 0 1 ADC29 see Note 2 1 1 1 1 0 ADC30 Vner see Note 2 1 1 1 1 1 ADC powered off NOTES 1 If any unused channels are selected the resulting ADC conversion will be unknown 2 The voltage levels supplied from internal reference nodes as specified in the table are used to verify the operation of the ADC converter both in production test and for user applications 15 7 2 ADC Clock Control Register The ADC clock control register ADICLK selects the clock frequency for the ADC Address 0058 Read 0 0 ADIV2 ADIV1 ADIVO ADICLK MODE1 MODEO Write R 0 0 0 0 0 1 Reset 0 0 Unimplemented R Reserved Figure 15 4 ADC Clock Control Register ADICLK ADIV 2 0 ADC Clock Prescaler Bits ADIV2 ADIV1 and ADIVO form a 3 bit field which selects the divide ratio used by the ADC to generate the internal ADC clock Table 15 2 shows the available clock configurations The ADC clock should be set to between 500kHz 1 MHz MC68HC908AP A Family Data Sheet Rev 2 250 Freescale Semiconductor 1 0 Registers Table 15 2 ADC Clock Divide Ratio ADIV2 ADIV1 ADI
4. 205 134 Functional wd unici RARE COT beeen ed 206 13 4 1 Master Mode 4535 exc a RO Ge KNEE Ge RS 206 13 4 2 Slave Mode 208 135 208 13 5 1 Clock Phase and Polarity Cones ss X ed RES 208 13 5 2 Transmission Format When CPHA 0 209 13 5 3 Transmission Format When CPHA 1 210 13 5 4 Transmission Initiation 210 13 6 Queuing Transmission Data 44 RES 211 137 EE Rod ROB dol dde Rid oon bate dod 212 13 7 1 TERES T IT 213 13 72 EO 2242 o eben Qum e UT ir e mium Sige Gar do dian 214 19 8 p 215 13 9 Messing 52455455 45 rx ERE n o 216 19 10 Low Power MOGGS s Shea E irom Se eh be ECC ee oS 217 TS DU 217 Pads 217 19 11 Break Interrupts a deb baw rue swt eau dob Doe Gu doe Ue d e a bus ah tar ics 217 218 139 121 Master dde x eon eek 218 13322 MOS Master
5. eee des 218 139 123 9 418 218 155 ea ENS vis 219 134125 Grind 222556255465 Goes erie Ss 220 220 MC68HC908AP A Family Data Sheet Rev 2 Freescale Semiconductor 13 Table of Contents 19391 Rt EC PR RU Rura 220 13 13 2 SPI Status and Control 222 19399 sem bp tare radit n d qun Rote 224 Chapter 14 Multi Master Interface MMIIC 14 1 oasis edd ee de LIRE SE RES ET EET a SEC DE TA E REC ERR 225 Wie o2 4d huh CP P HERE 225 Cc NM c1 MP PME 226 14 4 Multi Master System Configuration 226 145 IC Bus PIO DOO 12 23 4 2425 cde d OR 227 14 5 1 START Signal ceeds RO 227 14 5 2 Slave Address Transmission 227 14 5 3 Data 228 14 5 4 Repeated START SONA EATER RR 228 14 5 5 ae 228 14 5 6 Arbitrati
6. 131 FORI acia d FOU e aoo d det oe ECMO 9 dub bee pened 131 Name Conventions 131 F nctional Descriptio UM 132 TIM Counter Prescaler essed a 134 OS a ed ee S bo ata ae 134 Output eor 134 Unbuffered Output COMPATTE seco 6 134 Output COMPAS dox ERE RO de 135 MC68HC908AP A Family Data Sheet Rev 2 Freescale Semiconductor 9 4 4 Pulse Width Modulation PWM bene ERE 185 9 4 4 1 Unbuffered PWM Signal Generation 136 9 4 4 2 Buffered PWM Signal Generation 137 9 4 4 3 des eats tah aoa ren ence qn a S AGT dh ae at B does 137 9 5 Interrupts RON 138 9 6 Low Power Modes Tec FIER epi oet Ren Mie as 138 9 6 1 Walt Mode Rond 138 9 6 2 ModE obo n eod 138 9 7 TIM D nng Break DUSITUDIS cud i Ern rhe quet i e dS d anui ease 138 9 8 rrr PEE Tre 139 9 9 VO REJSES CUP 139 9 9 1 TIM Status and Control 5
7. Chapter 2 Memory dr e Gees dias d 0 CI Seon UE ids aeu s Monitor au adea o dco RA b Ue cerdo SUCRE So a aod DER o Red p E d P Cd Random Access Memory heated es b Bb aru ater tre FLASH FLASH Page Erase FLASH Mass Erase Operation Reged EP REX E PE Pads FLASH Program a aree PIPERIS dso FLASH 6442406 P toe FLASH Block Protect Register ser uoti ar DE PE Tin r ERN Chapter 3 Configuration amp Mask Option Registers CONFIG amp MOR Iur eei Poe Pr PR ER me CT owas ashes weeds das Configuration Register 1 CONFIGT uias esie es Comiguration Register 2 CONFIG vo cua FER uw eo eae Mask Option Register MOR cues oY eee Chapter 4 Central Processor Unit CPU ires pec Features sse S CV gore
8. 139 9 9 2 TiM Counter 2 214 050 141 9 9 3 TIM Counter Modulo Registers 141 9 9 4 TIM Channel Status and Control Registers 142 9 9 5 TIM Channel Registers icis sess pen EG RR RR RES RII GO GRE 144 Chapter 10 Timebase Module TBM 10 15 peg debere E edad 147 102 FeatuleS s use gx E REA edad ed ach Ee EES RES eee 147 10 9 Functional DescripUOl 147 10 4 Register Description 148 10 5 150 1025 Low Power MOO GS dta poet kente ROUES Ih PIE EC odere 4 pedo don 150 10 6 1 x are REG RE Y Y 4X XE EY EE Y 150 10 6 2 SOP MOJE RT 150 Chapter 11 Serial Communications Interface Module SCI 2522 2 0 ort at oce ated D an D ethane ne ae oe 151 12 PO AUTOS pep EPOR der PRSE d 151 11 3 Conventions 2241244564405 WERE Base aes 152 a Funcional DeScripUOD eee 153 11 4 1 154 11 4 2
9. 103 Monitor Mode Entry Module 1 103 SIM a ee ee ee ee de 103 SIM Counter During Power On 103 SIM Counter During Stop Mode Recovery 103 SIM Counter and Reset States 104 Exception COMOL er 104 MC68HC908AP A Family Data Sheet Rev 2 Freescale Semiconductor 9 Table of Contents 7 5 1 T5131 5 1 2 Loe 7 5 2 1 7 5 2 2 7 5 2 3 7 5 3 7 5 4 7 5 5 7 6 7 6 1 76 8 7 7 1 42 7 7 0 7 7 3 8 1 8 2 8 3 8 3 1 8 3 2 8 3 3 8 3 4 8 3 5 8 4 8 5 8 5 1 8 52 8 5 3 8 5 4 855 9 1 9 2 9 3 9 4 9 4 1 9 4 2 9 4 3 9 4 3 1 9 4 3 2 t 104 Hardware MENUS pud bounds adds 105 so Mu epo PET eh ted 106 Interrupt Status Registers eese e us E Eee a Fossa 106 Status Register Tos ices RP ETE PUARRC RE PEERS ses 107 Interrupt Status Register 2 qu ERE EE 107 interrupt Status Register 107 1 nr 109 Break Imeruple ace sd EE E RE RP AGE EN ERT Ed RI 109 Status Flag Protection in Break 109 SR nere Miei SON SSS d ib die 109
10. Bit 7 6 5 4 3 2 1 Bit 0 Read Bit 7 6 5 4 3 2 1 Bit 0 Write Reset 0 0 0 0 0 0 0 0 Figure 21 5 Break Address Register Low BRKL 21 5 3 SIM Break Status Register The SIM break status register SBSR contains a flag to indicate that a break caused an exit from wait mode The flag is useful in applications requiring a return to wait mode after exiting from a break interrupt Address 00 Bit 7 6 5 4 3 2 1 Bit 0 Read SBSW R R R R R R m R Write Note Reset 0 Note Writing a logic 0 clears SBSW R Reserved Figure 21 6 SIM Break Status Register SBSR SBSW Break Wait Bit This status bit is set when a break interrupt causes an exit from wait mode or stop mode Clear SBSW by writing a logic 0 to it Reset clears SBSW 1 Stop mode or wait mode was exited by break interrupt 0 Stop mode wait mode was not exited by break interrupt SBSW can be read within the break interrupt routine The user can modify the return address on the stack by subtracting 1 from it The following code is an example MC68HC908AP A Family Data Sheet Rev 2 290 Freescale Semiconductor Break Module Registers This code works if the H register has been pushed onto the stack in the break service routine software This code should be executed at the end of the break service routine software HIBYTE EQU 5 LOBYTE EQU 6 not SBSW do RTI
11. Jm 8 ase ars fare pars fers ts TI II 3 4 4d 4d Aa A 4 Figure 13 6 Transmission Format CPHA 1 When CPHA 1 for a slave the first edge of the SPSCK indicates the beginning of the transmission This causes the SPI to leave its idle state and begin driving the MISO pin with the MSB of its data Once the transmission begins no new data is allowed into the shift register from the transmit data register Therefore the SPI data register of the slave must be loaded with transmit data before the first edge of SPSCK Any data written after the first edge is stored in the transmit data register and transferred to the shift register after the current transmission 13 5 4 Transmission Initiation Latency When the SPI is configured as a master SPMSTR 1 writing to the SPDR starts a transmission CPHA has no effect on the delay to the start of the transmission but it does affect the initial state of the SPSCK signal When CPHA 0 the SPSCK signal remains inactive for the first half of the first SPSCK cycle When CPHA 1 the first SPSCK cycle begins with an edge on the SPSCK line from its inactive to its active level The SPI clock rate selected by SPR1 SPRO0O affects the delay from the write to SPDR and the start of the SPI transmission See Figure 13 7 The internal SPI clock in the master is a free running derivative of the internal MCU clock To
12. RC RR CaS de DEFUI TIBUBIBIE sss ts us MC68HC908AP A Family Data Sheet Rev 2 Freescale Semiconductor Table of Contents 4 3 2 4 3 3 4 3 4 4 3 5 4 4 4 5 4 5 1 4 5 2 4 6 4 7 4 8 5 2 1 5 2 2 5 6 6 545 5 7 2 Index COMIC casi dx RES PEE E ENS eade bin diis 56 Stack POIDS ia cadens 57 Programm MUR TTE 57 Condition Cote Nc MC M 58 Arithmetic Logic Unit ALU i oues egutkr tke or stead eek aes APER RR RR RE 59 Low Power Puede tee eed UAR IEEE uS RE Far 59 Wait Mode 59 SIOP Mode 59 CPU During Break Mepis 60 Sel SUMMAY weet eee eee IRE ES RI ID 60 Opcode 60 Chapter 5 Oscillator OSC lui cip TP 71 ee eee ues tes 71 Reference Clock TBM Reference Clock Selection 73 Internal OSOIIAIOE iudi ee ee ee e RO ORC 74 i NET 75 75 Rh 7
13. BRCLR SBSW SBSR RETURN See if wait mode or stop mode was exited by break TST LOBYTE SP RETURNLO is not zero BNE DOLO then just decrement low byte DEC HIBYTE SP Else deal with high byte too DOLO DEC LOBYTE SP Point to WAIT STOP opcode RETURN PULH Restore H register RTI 21 5 4 SIM Break Flag Control Register The SIM break flag control register SBFCR contains a bit that enables software to clear status bits while the MCU is in a break state Address FE03 Bit 7 6 5 4 3 2 1 Bit 0 Read BCFE R R R R R R R Write Reset 0 R Reserved Figure 21 7 SIM Break Flag Control Register SBFCR BCFE Break Clear Flag Enable Bit This read write bit enables software to clear status bits by accessing status registers while the MCU is in a break state To clear status bits during the break state the BCFE bit must be set 1 Status bits clearable during break 0 Status bits not clearable during break MC68HC908AP A Family Data Sheet Rev 2 Freescale Semiconductor 291 Break Module BRK MC68HC908AP A Family Data Sheet Rev 2 292 Freescale Semiconductor Chapter 22 Electrical Specifications 22 1 Introduction This section contains electrical and timing specifications 22 2 Absolute Maximum Ratings Maximum ratings are the extreme limits to which the MCU can be exposed without permanently damaging it NOTE This device is not
14. 260 POG TEIL NO 261 Port Data Register 2255 32 idap 261 Data Direction Register C 262 POT EI sued SAR erba D arene 263 Port D Data Register PTD 242106 uter ERE Y GR Tp de 263 Data Direction Register D 264 Chapter 17 External Interrupt IRQ luni csi PTT crm 267 M 267 Functional DescriptioN is v tersin tp RR 267 and IO PINS 2s b 269 MC68HC908AP A Family Data Sheet Rev 2 Freescale Semiconductor 15 Table of Contents 17 5 17 6 17 6 1 17 6 2 IRO Module During Break Interupls E RR RHET ER EIL DRESS eee ess 270 ipo c r D RR EESTI US TET 270 IRQ1 Status and Control 270 IRQ2 Status and Control 271 Chapter 18 Keyboard Interrupt Module KBI sso oe et 273 PPM 273 VO FING dauid Edd ad dud dcn dose ipaam aeui efi des 273 425256556 aiat pu 274 Keyboard Initialization 4 du dcn qom bees he w
15. bit will be cleared by hardware before the next CRC byte is loaded 14 6 8 MMIIC Frequency Divider Register MMFDR Address 004 Bit 7 6 5 4 3 2 1 Bit 0 Read 0 0 0 0 0 MMBR2 MMBR1 MMBRO Write Reset 0 0 0 0 0 1 0 0 Unimplemented Figure 14 11 MMIIC Frequency Divider Register MMFDR The three bits in the frequency divider register MMFDR selects the divider to divide the bus clock to the desired baud rate for the MMIIC data transfer Table 14 2 shows the divider values for MMBR 2 0 MC68HC908AP A Family Data Sheet Rev 2 236 Freescale Semiconductor Table 14 2 MMIIC Baud Rate Selection Program Algorithm MMIIC Baud Rates for Bus Clocks MMBR2 MMBR1 MMBRO Divider 8MHz 4MHz 2MHz 1MHz 0 0 0 20 400kHz 200kHz 100kHz 50kHz 0 0 1 40 200kHz 100kHz 50kHz 25kHz 0 1 0 80 100kHz 50kHz 25kHz 12 5kHz 0 1 1 160 50kHz 25kHz 12 5kHz 6 25kHz 1 0 0 320 25kHz 12 5kHz 6 25kHz 3 125kHz 1 0 1 640 12 5kHz 6 25kHz 3 125kHz 1 5625kHz 1 1 0 1280 6 25kHz 3 125kHz 1 5625kHz 0 78125kHz 1 1 1 2560 3 125kHz 1 5625kHz 0 78125kHz 0 3906kHz NOTE The frequency of the MMIIC baud rate is only guaranteed for 100kHz to 10kHz The divider is available for the flexibility on bus frequency selection 14 7 Program Algorithm When the MMIIC module detects an arbitration loss in master mode it releases both SDA and SCL lines immediately But if there are
16. is disabled during a break interrupt when is present on the RST MC68HC908AP A Family Data Sheet Rev 2 282 Freescale Semiconductor Chapter 20 Low Voltage Inhibit LVI 20 1 Introduction This section describes the low voltage inhibit LVI module The LVI module monitors the voltage the Vpp and pin and can force a reset when Vpp voltage falls below or Vreg voltage falls below VTRIPF2 NOTE The Vggg pin is the output of the internal voltage regulator and is guaranteed to meet operating specification as long as Vpp is within the MCU operating voltage The LVI feature is intended to provide the safe shutdown of the microcontroller and thus protection of related circuitry prior to any application Vpp voltage collapsing completely to an unsafe level It is not intended that users operate the microcontroller at lower than the specified operating voltage VDD 20 2 Features Features of the LVI module include e Independent voltage monitoring circuits for Vpp and e Independent disable for Vpp and LVI circuits Programmable LVI reset e Programmable stop mode operation Addr Register Name Bit 7 6 5 4 3 2 1 Bit 0 Read LVIOUT 0 0 0 0 LVI Status Register io ou FEOF LVISR Write Reset 0 0 0 0 0 0 0 0 Unimplemented Figure 20 1 LVI Register Summary 20 3 Functional Description Figure 20 2 s
17. 273 Chapter 19 Computer Operating Properly 279 Chapter 20 Low Voltage Inhibit 283 Chapter 21 Break Module 287 Chapter 22 Electrical 293 Chapter 23 Mechanical Specifications 307 Chapter 24 Ordering 311 MC68HC908AP A Family Data Sheet Rev 2 Freescale Semiconductor 5 D List of Chapters MC68HC908AP A Family Data Sheet Rev 2 6 Freescale Semiconductor Table of Contents 1 1 ee 1 3 1 4 15 1 6 kT 24 2 2 23 2 4 2 5 2 5 1 2 5 2 2 5 3 2 5 4 2 5 5 2 5 6 2 5 7 3 1 3 2 3 3 3 4 3 5 4 1 4 2 4 3 4 3 1 Chapter 1 General Description i osos dons a ace aioe dors add on ee en tees eo eas aioe Bath dis ds END OR RE ER ESE EUR PEDANE KO RE RE RS eS MICU wens oes tice anders Bese OI OS eod obi ee ee add Power Supply Bypassing VDD VDDA VSS 55 Regulator Power Supply Configuration VREG
18. SCI TxD SCTxD CGMXCLK SERIAL SCI_R32XCLK COMMUNICATIONS INFRARED INTERFACE MODULE SCI_R16XCLK SUB MODULE BUS CLOCK SCI SCI_RxD SCRxD ht Figure 12 2 IRSCI Block Diagram The SCI module provides serial data transmission and reception with a programmable baud rate clock based on the bus clock or the CGMXCLK The infrared sub module receives two clock sources from the SCI module R16XCLK and SCI_R32XCLK Both reference clocks are used to generate the narrow pulses during data transmission The SCI_R16XCLK and SCI_R32XCLK are internal clocks with frequencies that are 16 and 32 times the baud rate respectively Both R16XCLK and SCI_R32XCLK clocks are used for transmitting data The SCI_R16XCLK clock is used only for receiving data NOTE For proper SCI function transmit or receive the bus clock MUST be programmed to at least 32 times that of the selected baud rate When the infrared sub module is disabled signals on the TxD and RxD pins pass through unchanged to the SCI module 12 4 Infrared Functional Description Figure 12 3 shows the structure of the infrared sub module The infrared sub module provides the capability of transmitting narrow pulses to an infrared LED and receiving narrow pulses and transforming them to serial bits which are sent to the SCI module The infrared sub module receives two clocks from the SCI One of these two clocks is selected as the base clock to generate the
19. 15 15 15 XLS XLS XLS XLS VXL LIVM 419 x410 410 29199 v 6 6 v v 5 v 6 L 5 v 6 XI 5 IXI 2246 HNI L Q XI HH 901 AOW AOW AOW AOW 41454 219599 v 9 v v v v v 6 6 v 6 XI IXI 6 HNI XI 195 IXI 6 usf usf usf usf usf ysg dON AS 161 151 XLSL 151 9H OHH v 9 9 9 v v v 6 6 v 6 XI IXI amp 4 6 c L XI 5 IXI ONI ONI ONI XONI VONI ONI 913589 91 5 2 2 v 6 2 L 6 9 v v 6 v 6 XI 146 5 t L XI 195 7 aav aav aav aav aav aav aav aav 195 HHSd ZN8G 2 ZN8G XZN8G VZN8G ZN8G s4109 v 5 6 5 6 v 6 XI 6 IXI 2248 v ZXI 913589 919599 v 5 6 v v v 5 v 6 XI 6 IXI 2 245 v ZXI
20. Bit 7 6 5 4 3 2 1 Bit 0 Read TOF 0 0 L 4 TOE TSTOP L PS2 51 50 Write 0 TRST Reset 0 0 1 0 0 0 0 0 Unimplemented Figure 9 4 TIM Status and Control Register TSC MC68HC908AP A Family Data Sheet Rev 2 Freescale Semiconductor 139 Timer Interface Module TIM TOF TIM Overflow Flag Bit This read write flag is set when the TIM counter reaches the modulo value programmed in the TIM counter modulo registers Clear TOF by reading the TIM status and control register when TOF is set and then writing a logic 0 to TOF If another TIM overflow occurs before the clearing sequence is complete then writing logic 0 to TOF has no effect Therefore a TOF interrupt request cannot be lost due to inadvertent clearing of TOF Reset clears the TOF bit Writing a logic 1 to TOF has no effect 1 TIM counter has reached modulo value 0 TIM counter has not reached modulo value TOIE TIM Overflow Interrupt Enable Bit This read write bit enables TIM overflow interrupts when the TOF bit becomes set Reset clears the TOIE bit 1 overflow interrupts enabled 0 TIM overflow interrupts disabled TSTOP TIM Stop Bit This read write bit stops the TIM counter Counting resumes when TSTOP is cleared Reset sets the TSTOP bit stopping the TIM counter until software clears the TSTOP bit 1 TIM counter stopped 0 TIM counter active NOTE Do not set the TSTOP bit before entering wait mode
21. INH 1 TXS Transfer H X to SP SP lt H X 1 7 94 2 WAIT Enable Interrupts Wait for Interrupt Clocking nti 0 8F 1 interrupted MC68HC908AP A Family Data Sheet Rev 2 Freescale Semiconductor 67 Central Processor Unit CPU 68 Table 4 1 Instruction Set Summary Operation Accumulator Carry borrow bit Condition code register Direct address of operand Direct address of operand and relative offset of branch instruction Direct to direct addressing mode Direct addressing mode Direct to indexed with post increment addressing mode High and low bytes of offset in indexed 16 bit offset addressing Extended addressing mode Offset byte in indexed 8 bit offset addressing Half carry bit Index register high byte High and low bytes of operand address in extended addressing Interrupt mask Immediate operand byte Immediate source to direct destination addressing mode Immediate addressing mode Inherent addressing mode Indexed no offset addressing mode Indexed no offset post increment addressing mode Indexed with post increment to direct addressing mode Indexed 8 bit offset addressing mode Indexed 8 bit offset post increment addressing mode Indexed 16 bit offset addressing mode Memory location Negative bit Description Effect on CCR Any bit Operand one or two bytes Program counter Program counter high byte Program counter low
22. PRESCALER SELECT INTERNAL BUS CLOCK PRESCALER TSTOP TRST TL INTERRUPT PORT LOGIC TMODH TMODL INTERRUPT LOGIC CHANNEL 0 ELSOB ELSOA PORT LOGIC 16 BIT COMPARATOR INTERRUPT LOGIC T 1 2 CHO TCHOH TCHOL 16 BIT LATCH MS0A CHOIE CHANNEL 1 ELSOB ELSOA CH1MAX 16 BIT COMPARATOR TCH1H TCH1L 16 BIT LATCH T 1 2 CH1 0 CHIIE INTERNAL BUS lt Figure 9 1 TIM Block Diagram Figure 9 2 summarizes the timer registers NOTE References to either timer 1 or timer 2 may be made in the following text by omitting the timer number For example TSC may generically refer to both T1SC and T2SC MC68HC908AP A Family Data Sheet Rev 2 132 Freescale Semiconductor Addr Register Name TIM1 Status and Control Read 0020 Register Write T1SC Reset TIM1 Counter Register Read 0021 High Write Reset TIM1 Counter Register Read 0022 Low Write TICNTL Reset TIM Counter Modulo Read 0023 Register High Write TMODH Reset TIM1 Counter Modulo Read 0024 Register Low Write T1MODL Reset TIM1 Channel 0 Status Read 0025 and Control Register Write 115 Reset TIM1 Channel 0 Read 0026 Register High Write T1CHOH Reset TIM1 Channel 0 Read 0027 Register Low Write T1CHOL Reset TIM1 Channel 1 Stat
23. am Gore 154 11 4 2 1 Character LENO qd 155 11 4 2 2 Gharacter TESPISIEISSIODL wrist a eee ee OSA REPE 155 11 4 2 3 Biedak 155 11 4 2 4 016 156 11 4 2 5 Inversion Of Transmitted 156 11 4 2 6 2 exces cose eter eke Rhee ei Ger ss ew ee 156 11 4 3 gig T rU 156 11 4 3 1 Character ee eee PAS CR Ea i 156 11 4 3 2 Character Reception de Re Rire dde Spr dard e dus Datis mr Pan 156 11 4 3 3 Data C DB 158 MC68HC908AP A Family Data Sheet Rev 2 Freescale Semiconductor 11 A Table of Contents 11 4 3 4 Framing ENOS rM PEUT 160 11 4 3 5 Baud Rate Tolerance 56 A e 160 11 4 3 6 Receiver WakGe bp 161 11 4 3 7 RECEIVER 1 oa e oaa emeret eras aah Gute ae 162 11 4 3 8 weak Pto Sa PP eR hae a 162 TES EoOWsPOWOPMOOS cat ah ae EROR bebes he 46 163 13 5 1 Walt eA RAT ROLE CC ACA RR Ro 163 11 5 2 SIOD NOUO
24. interrupt request e Controls triggering sensitivity of the IRQ1 interrupt pin Address 001 Bit 7 6 5 4 3 2 1 Bit 0 Read 0 0 0 0 IRQ1F 0 IMASK1 MODE1 Write ACK1 Reset 0 0 0 0 0 0 0 0 Unimplemented Figure 17 4 IRQ1 Status and Control Register INTSCR1 IRQ1F IRQ1 Flag This read only status bit is high when the IRQ1 interrupt is pending 1 IRQ1 interrupt pending 0 interrupt not pending ACK1 IRQ1 Interrupt Request Acknowledge Bit Writing a logic 1 to this write only bit clears the IRQ1 latch ACK1 always reads as logic 0 Reset clears ACK1 MC68HC908AP A Family Data Sheet Rev 2 270 Freescale Semiconductor IRQ Registers IMASK1 IRQ1 Interrupt Mask Bit Writing a logic 1 to this read write bit disables IRQ1 interrupt requests Reset clears IMASK1 1 interrupt requests disabled 0 IRQ1 interrupt requests enabled MODE1 IRQ1 Edge Level Select Bit This read write bit controls the triggering sensitivity of the IRQ1 pin Reset clears MODE1 1 IRQ1 interrupt requests on falling edges and low levels 0 1 1 interrupt requests on falling edges only 17 6 2 IRQ2 Status and Control Register The IRQ2 status and control register INTSCR2 controls and monitors operation of IRQ2 The INTSCR2 has the following functions e Enables disables the internal pullup device on IRQ2 pin e Shows the state of the IRQ2 flag e Clears the IRQ2 latch e Masks IRQ2 interr
25. 298 Electrical CharacteriStiCS s si RieEOCRGR 299 CGM Electrical Specificaties ieir LOREM E ds 301 SPI CharacterisltieS 2 2 rure sro mx gere teg nente ert eere baeo i s 302 Memory Characteristics 3m eh be eas 305 MC68HC908AP A Family Data Sheet Rev 2 Freescale Semiconductor 17 Table of Contents 23 1 23 2 23 3 23 4 24 1 24 2 Chapter 23 Mechanical Specifications ice ile fe ea A ee ee eee ee 307 48 Low Profile Quad Flat Pack 1 308 suede ieu irs aus dit Geo quede prac qus a exi Kad Eua od uh dae de 309 42 Pin Shrink Dual In Line Package SDIP 310 Chapter 24 Ordering Information Ignis fu PP 311 MC Onder MADE a pua mice odd oboe 311 MC68HC908AP A Family Data Sheet Rev 2 Freescale Semiconductor Chapter 1 General Description 1 1 Introduction The MC68HC908AP64A is a member of the low cost high performance M68HC08 Family of 8 bit microcontroller units MCUs All MCUs in the family use the enhanced M68HCO68 central processor unit 08 and are available with a variety of modules memory sizes and types and package types Table 1 1 Summ
26. 64 WAI VOAEO 0392 NHH L v 5 9 v v v v 6 5 v 6 XI 5 IXI 5 ans ans ans ans ans ans XSAN VOAN SAN 01959 OLASHA 0 v 9 v v L L v 5 v 6 851 336 4 v L 0 aen XI 145 LXI HNI HNI XI 145 HNI HNI 151 104440 uoneindiuey 1 1 MC68HC908AP A Family Data Sheet Rev 2 69 Freescale Semiconductor Central Processor Unit CPU MC68HC908AP A Family Data Sheet Rev 2 70 Freescale Semiconductor Chapter 5 Oscillator OSC 5 1 Introduction The oscillator module consist of three types of oscillator circuits e Internal oscillator RC oscillator e 1MHz to 8MHz crystal x tal oscillator The reference clock for the CGM and other MCU sub systems is selected by programming the mask option register located at FFCF The reference clock for the timebase module TBM is selected by the two bits OSCCLK1 and OSCCLKO in the CONFIG2 register The internal oscillator runs continuously after a POR or reset and is always available The RC and crystal oscillator cannot run concurrently one is disabled while the other
27. m D m gt SECTION B B VIEW ROTATED 90 EAD EXITS THE PLASTIC BODY AT THE NG PLANE C PER SIDE DIMENSIONS A AND B DO CLUDE MOLD MISMATCH AND ARE DETERMINED DATUM PLANE H N D DOES NOT INCLUDE DAMBAR 0 08 MILLIMETERS INCHES z MIN MAX MAX 9 90 0 10 0 390 0 398 9 90 0 10 0 390 0 398 2 10 2 45 0 083 0 096 0 30 0 45 0 012 0 018 2 00 2 10 0 079 0 083 0 30 0 40 0 012 0 016 0 80 BSC 0 031 BSC 0 25 0 010 0 13 0 23 0 005 0 009 0 65 0 95 0 026 0 037 lt gt 0 13 0 005 0 0 12 95 1345 0 510 0 530 0 40 0 016 1 6 REF 0 063 REF RUSION ALLOWABLE DAMBAR PROTRUSION 0 003 TOTAL IN EXCESS OF THE MENSION AT MAXIMUM MATERIAL CONDITION DAMBAR CANNOT BE LOCATED ON THE LOWER RADIUS OR THE FOOT 309 Mechanical Specifications 23 4 42 Pin Shrink Dual In Line Package SDIP NOTES 1 DIMENSIONING AND TOLERANCING PER ANSI 14 5 1982 2 CONTROLLING DIMENSION INCH 3 DIMENSION L TO CENTER OF LEAD WHEN FORMED PARALLEL 4 DIMENSIONS A AND DO NOT INCLUDE MOLD FLASH MAXIMUM MOLD FLASH 0 25 0 01
28. Bit 7 6 5 4 3 2 1 Bit 0 Read 0 0 0 R _ R TNP1 TNPO IREN Write Reset 0 0 0 0 0 0 0 0 Unimplemented R Reserved Figure 12 20 IRSCI Infrared Control Register IRSCIRCR TNP1 and TNPO Transmitter Narrow Pulse Bits These read write bits select the infrared transmitter narrow pulse width as shown in Table 12 10 Reset clears TNP1 and TNPO Table 12 10 Infrared Narrow Pulse Selection TNP1 and TNPO Prescaler Divisor PD 00 SCI transmits a 3 16 narrow pulse 01 SCI transmits a 1 16 narrow pulse 10 m SCI transmits a 1 32 narrow pulse IREN Infrared Enable Bit This read write bit enables the infrared sub module for encoding and decoding the SCI data stream When this bit is clear the infrared sub module is disabled Reset clears the IREN bit 1 infrared sub module enabled 0 infrared sub module disabled MC68HC908AP A Family Data Sheet Rev 2 Freescale Semiconductor 205 Infrared Serial Communications Interface Module IRSCI MC68HC908AP A Family Data Sheet Rev 2 206 Freescale Semiconductor Chapter 13 Serial Peripheral Interface Module 13 1 Introduction This section describes the serial peripheral interface SPI module which allows full duplex synchronous serial communications with peripheral devices 13 2 Features Features of the SPI module include the following e Full duplex operation e Master and slave modes e Double buffered operat
29. OPERATION OPERATION OPERATION OPERATION Slave address match and Slave address match and Transmit data Last data sent check for data direction get ready to transmit data FLAGS FLAGS FLAGS FLAGS MMTXIF set MMTXIF set set set MMRXAK clear MMRXAK set MMATCH set MMATCH set ACTION MMSRW depends on 8th MMSRW depends on 8th ACTION bit of calling address byte bit of calling address byte Load Data3 to MMDTR Load dummy FF to MMDTR ACTION ACTION 2 Read Slave address OPERATION OPERATION OPERATION Read and decode received command OPERATION Last data is going to be sent Prepare for Slave mode FLAGS Transmit data FLAGS ACTION MMRXIF set FLAGS 1 Load slave address to MMADR clear MMTXIF set d 2 Clear MMTXAK ACTION ACTION ACTION 3 Clear MMAST Load Data1 to MMDTR Load Data2 to MMDTR Load dummy FF to MMDTR 242 Figure 14 20 SMBus Protocol Implementation MC68HC908AP A Family Data Sheet Rev 2 Freescale Semiconductor Chapter 15 Analog to Digital Converter ADC 15 1 Introduction This section describes the analog to digital converter ADC The ADC is a 8 channel 10 bit linear successive approximation ADC 15 2 Features Features of the ADC module include Eight channels with multiplexed input High impedance buffered input Linear successive approximation with monotonicity 10 bit resolution Single or continuous conversion Auto scan conversion on four
30. Reset 0 0 0 0 0 0 0 0 MMIIC CRC Data Register Read MMCRCD7 MMCRCD6 5 MMCRCD4 MMCRCD3 MMCRCD2 MMCRCD1 MMCRCDO MMCRDR write Reset 0 0 0 0 0 0 0 0 MMIIC Frequency Divider Read 0 0 0 0 MMBR2 MMBRi MMBRO Register Write MMFDR Reset 0 0 0 0 0 1 0 0 Read Reserved Write Reset Timebase Control Register ne TBIF TBR2 TBRI TBRO 0 TBIE TBON R TBCR Write TACK Reset 0 0 0 0 0 0 0 0 Read Unimplemented Write Reset Read Unimplemented Write Reset Read Unimplemented Write Reset Read Unimplemented Write Reset Read Unimplemented Write Reset Read COCO ADC Status and Control 7 ADCO ADCH4 ADCH3 ADCH2 ADCHO Register Write ADSCR Reset o 0 0 1 1 1 1 1 Read 0 0 ADICLK e Reset 0 0 0 0 0 0 0 0 Read ADx ADx ADx ADx ADx ADx ADx ADx ADC Data Register High0 5 1 5 1 z 1 z2 1 s T s T T ADRHO Write R R R R R R R R Reset 0 0 0 0 0 0 0 0 U Unaffected X Indeterminate Unimplemented R Reserved Figure 2 2 Control Status and Data Registers Sheet 7 of 9 MC68HC908AP A Family Data Sheet Rev 2 Freescale Semiconductor 37 Memory Addr Register Name Bit 7 6 5 4 3 2 1 Bit 0
31. 12 5 2 3 Break Characters Writing a logic 1 to the send break bit SBK in IRSCC2 loads the transmit shift register with a break character A break character contains all logic Os and has no start stop or parity bit Break character length depends on the M bit IRSCC1 As long as SBK is at logic 1 transmitter logic continuously loads break characters into the transmit shift register After software clears the SBK bit the shift register finishes transmitting the last break character and then transmits at least one logic 1 The automatic logic 1 at the end of a break character guarantees the recognition of the start bit of the next character The SCI recognizes a break character when a start bit is followed by eight or nine logic O data bits and a logic 0 where the stop bit should be Receiving a break character has the following effects on SCI registers Sets the framing error bit FE in IRSCS1 Sets the SCI receiver full bit SCRF in IRSCS1 e Clears the SCI data register IRSCDR e Clears the R8 bit in IRSCC3 Sets the break flag bit in IRSCS2 e May set the overrun OR noise flag NF parity error PE or reception in progress bits 12 5 2 4 Idle Characters An idle character contains all logic 1s and has no start stop or parity bit Idle character length depends on the M bit in IRSCC1 The preamble is a synchronizing idle character that begins every transmission If the TE bit is cleared during a
32. 4 32 4 32 CYCLES CYCLES se sess IDB A6 A6 A6 LLU SUELE LFU LE LI 32 Figure 7 17 Wait Recovery from Internal Reset 7 6 2 Stop Mode In stop mode the SIM counter is reset and the system clocks are disabled An interrupt request from a module can cause an exit from stop mode Stacking for interrupts begins after the selected stop recovery time has elapsed Reset or break also causes an exit from stop mode The SIM disables the clock generator module output CGMOUT in stop mode stopping the CPU and peripherals Stop recovery time is selectable using the SSREC bit in the configuration register 1 CONFIG1 If SSREC is set stop recov