National Semiconductor DAC1006/DAC1007/DAC1008 mP Compatible Double-Buffered D to A Converters handbook
Contents
1. LI cs From ADDRESS DECODER SYSTEM WR SYSTEM ADDRESS BIT 9 LOW FOR BYTE 1 HIGH FOR BYTE 2 Y DATA BUS Hn 18 DM74LS374 MS DAC1006 1007 1008 El BYTE2 Vi 3 ec GND 11 DB7 B AFB le lout OP AMP NOTE DATA HOLD TIME REDUCED TO THAT OF DM74LS374 10 ns FIGURE 20 Isolating Data Bus from DAC Circuitry to Eliminate Digital Noise Coupling MICRO DAC DAC1006 SERIES TL H 5688 26 FIGURE 21 Digitally Controlled Amplifier Attenuator 7 4 Digitally Controlled Amplifier Attenuator An unusual application of the DAC Figure 21 applies the input voltage via the on chip feedback resistor The lower op amp automatically adjusts the VreF n voltage such that lour1 is equal to the input current ViN Rfg The magnitude of this Vagr jn voltage depends on the digital word which is in the DAC register loyy2 then depends upon both the magnitude of Viv and the digital word The second op amp converts louT2 to a voltage Vout which is given by 1023 N VouT VIN CN 7 where 0 Nx 1023 Note that N 0 or a digital code of all zeros is not allowed or this will cause the output amplifier to saturate at either Vmax depending on the sign of Viy To provide a digitally controlled divider the output op amp can be eliminated Ground the Ioyt2 pin of the DAC and Vour is now taken from the lower op amp which also drives the Vngr input of the DAC The expression for Vout is n2. FS ADJ xz VREF vee MICRO DAC RFB 511 4 Vrer lt Vouts VREF 3 FIGURE 12 Full Scale Adjust Current Switching with Bipolar Output Voltage Vcc O V 2 500 Vpc LM336 VREF IOUT O VouT ovog lt Vour lt 2 5Vpc 1 RD 7833 FS ADJ TL H 5688 14 FIGURE 13 Full Scale Adjust Voltage Switching with a Unipolar Output Voltage 12 FS ADJ MICRO DAC 2 56 p FS ADJ R MATCH TO 0 01 R R O VouT 2 5v lt vout lt 2s 81 v TL H 5688 15 FIGURE 14 Voltage Switching with a Bipolar Output Voltage 6 0 DIGITAL CONTROL DESCRIPTION The DAC1006 series of products can be used in a wide variety of operating modes Most of the options are shown in Table 1 Also shown in this table are the section numbers of this data sheet where each of the operating modes is discussed For example if your main interest in interfacing to a uP with an 8 bit data bus you will be directed to Section 6 1 0 The first consideration is will the DAC be interfaced to a uP with an 8 bit or a 16 bit data bus or used in the stand alone mode For the 8 bit data bus a second selection is made on how the 2nd digital data buffer the DAC Latch is updat ed by a transfer from the 1st digital data buffer the Input Latch Three options are provided 1 an automatic transfer when the 2nd data byte is written to the DAC 2 a transfer which i
3. 55 35 1 10 15 SUPPLY VOLTAGE Ve V 5 5 25 45 65 85 105 125 TEMPERATURE C TL H 5688 3 Block and Connection Diagrams DAC1006 1007 1008 20 Pin Parts DAC1006 1007 1008 20 Pin Parts Dual In Line Package MSB Dig 9 VREF ae loutz is vec Dig 6 lout WR Dia Dlg 5 DAC Byte 1 Byte 2 DI MULTIPLYING 3 E le REGISTER D A CONVERTER XFER Dl DI DAC1006 o H F DAC1007 an n E FB Dl DAC1008 Dio LSB LSB Dip D7 RFB Dig VREF MSB Dig louTi st 2nd XFER STROBE GND IQUT2 BYTE BYTE Vcc STROBE STROBE CONTROL LOGIC GND TL H 5688 28 Top View See Ordering Information NN m USE DAC1006 1007 1008 CS wn XFER BYTE w FOR LEFT JUSTIFIED DATA BYTE 2 TL H 5688 5 DAC1006 1007 1008 Simple Hookup for a Quick Look E Swi DAC1006 DAC1007 O Vout DAC1008 6 0 voc lt Vout lt vrer 1023 A TOTAL OF 10 1024 INPUT SWITCHES 4 amp 1K RESISTORS E 15Vpc TL H 5688 7 Notes 1 For Vgge 10 240 Vpc the output voltage steps are approximately 10 mV each 2 SW1 is a normally closed switch While SW1 is closed the DAC register is latched and new data can be loaded into the input latch via the 10 SW2 switches When SW1 is momentarily opened the new data is transferred from the input latch to the DAC register and is latched when SW1 again closes 1 0 DEFINITION OF PACKAGE PINOUTS 1 1 Control Signals All control signals a
4. MSB Dig Dig 0 R 15kQ D eeeee DH Dio LSB 0 FIGURE 2 Current Mode Switching Vcc 15 Vp VREF O MICRO DAC VIRTUAL GROUND UL INTERNAL Rrg IOUT 1 O VouT l0UT1 x RB OP AMP Cc pF Rj ts p S TL H 5688 10 FIGURE 3 Converting lour to Voyt LF356 22 o 3 LF351 24 o 4 LF357 10 2 4k 1 5 shown in Figure 4 where the sign of the reference voltage has been changed to provide a positive output voltage Note that the output current loyy4 now flows through the Rfg pin 5 1 2 Providing a Bipolar Output Voltage with the DAC in the Current Switching Mode The addition of a second op amp to the circuit of Figure 4 can be used to generate a bipolar output voltage from a fixed reference voltage Figure 5 This in effect gives sign significance to the MSB of the digital input word to allow two quadrant multiplication of the reference voltage The polarity of the reference can also be reversed to realize the full four quadrant multiplication The applied digital word is offset binary which includes a code to output zero volts without the need of a large valued resistor common to existing bipolar multiplying DAC circuits Offset binary code can be derived from 2 s complement data most common for signed processor arithmetic by in verting the state of the MSB in either software or hardware After doing this the output then responds in accordance
5. 2 0 0000000000 1000000000 512 0 0 1 1111111111 0111111111 511 1LSB 1LSB 256 1100000000 0100000000 256 Vrer 2 Vnerl 2 512 1000000000 0000000000 0 VREF VReF VI with 1 Leg BEE 512 TL H 5688 11 FIGURE 5 Providing a Bipolar Output Voltage with the DAC in the Current Switching Mode 5 2 Analog Operation in the Voltage Switching Mode Some useful application circuits result if the R 2R ladder is operated in the voltage switching mode There are two very important things to remember when using the DAC in the voltage mode The reference voltage V must always be positive since there are parasitic diodes to ground on the lout1 pin which would turn on if the reference voltage went negative To maintain a degradation of linearity less than 0 005 keep V lt 3 Vpc and Vcc at least 10V more positive than V Figures 6 and 7 show these errors for the voltage switching mode This operation appears unusual since a reference voltage V is applied to the lour4 pin and the voltage output is the Vngr pin This basic idea is shown in Figure 8 This Vout range can be scaled by use of a non inverting gain stage as shown in Figure 9 41 es A LINEARITY x 0 e S 2 amp z 0 us S z o o 12 3 4 5 67 8 REFERENCE VOLTAGE V Vpc Notice that this is unipolar operation since all voltages are positive A bipolar output voltage can be obtained by using a sin
6. Switches operate in the current mode with a small voltage drop across them and can therefore switch currents of ei ther polarity This is the basis for the 4 quadrant multiplying feature of this DAC 5 1 1 Providing a Unipolar Output Voltage with the DAC in the Current Switching Mode A voltage output is provided by making use of an external op amp as a current to voltage converter The idea is to use the internal feedback resistor Reg from the output of the op amp to the inverting input Now when current is entered at this inverting input the feedback action of the op amp keeps that input at ground potential This causes the applied input current to be diverted to the feedback resistor The output voltage of the op amp is forced to a voltage given by Vout louri X Rrg Notice that the sign of the output voltage depends on the direction of current flow through the feedback resistor In current switching mode applications both current output pins Iout1 and lour2 should be operated at 0 Vpc This is accomplished as shown in Figure 3 The capacitor Cc is used to compensate for the output capacitance of the DAC and the input capacitance of the op amp The required feed back resistor Rp is available on the chip one end is inter nally tied to loyr4 and must be used since an external resistor will not provide the needed matching and tempera ture tracking This circuit can therefore be simplified as DIGITAL INPUT CODE
7. affect its safety or effectiveness National Semiconductor National Semiconductor National Semiconductor Corporation 1111 West Bardin Road Arlington TX 76017 Tel 1 800 272 9959 Fax 1 800 737 7018 N National Semiconductor Japan Ltd Tel 81 043 299 2309 Fax 81 043 299 2408 Europe Hong Kong Ltd Fax 49 0 180 530 85 86 13th Floor Straight Block Email cnjwge tevm2 nsc com Ocean Centre 5 Canton Rd Deutsch Tel 49 0 180 530 85 85 Tsimshatsui Kowloon English Tel 49 0 180 532 78 32 Hong Kong Fran ais Tel 49 0 180 532 93 58 Tel 852 2737 1600 Italiano Tel 49 0 180 534 16 80 Fax 852 2736 9960 National does not assume any responsibility for use of any circuitry described no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications
8. amp 2 If Military Aerospace specified devices are required ESD Susceptibility Note 11 800V please contact the National Semiconductor Sales Lead Temp Soldering 10 seconds Office Distributors for availability and specifications Dual In Line Package plastic 260 C Supply Voltage Vcc 17 Vpc Dual In Line Package ceramic 300 C Voltage at Any Digital Input Vcc to GND 3 a Voltage at Veer Input 25V Operating Ratings Note 1 Storage Temperature Range 65 C to 150 C T Range Tmin lt Ta lt TMAX SACR d art numbers wi Said a at eee E Note 3 500 mw LCN and LCWN suffix 0 C to 70 C oltage Applied to loyr4 or louT2 a Note 4 100 mV to Vcc Voltage at Any Digital Input Vcc to GND Electrical Characteristics Tested at Vcc 4 75 Vpc and 15 75 Voc Ta 25 C Vngr 10 000 Vpc unless otherwise noted Vec 12Vpc 5 59 Parameter Conditions bie to 15Vpc 5 Vcec 5Vpc 5 Units Min Typ Max Min Typ Max Resolution 10 10 bits Linearity Error Endpoint adjust only 4 7 Tmin lt TA lt Tmax 6 10V x Vgge lt 10V 5 DAC1006 0 05 0 05 of FSR DAC1007 0 1 0 1 of FSR DAC1008 0 2 0 2 of FSR Differential Endpoint adjust only 4 7 Nonlinearity TMIN TAX TMAX 6 10V x Vgge lt 10V 5 DAC1006 0 1 0 1 of FSR DAC1007 0 2 0 2 of FSR DAC1008 0 4 0 4 of FSR Monotonicity TMIN TAX TMAX 4 6 10V lt Vpers 10V 5 DAC1006 10 10 bits DAC1007 9 9 bits DAC1008 8 8 bits Gain Err
9. to the following expression D Vo VREFXz 5 where Vger can be positive or negative and D is the signed decimal equivalent of the 2 s complement processor data 512x Dx 511 or 1000000000 Dx 0111111111 If the applied digital input is interpreted as the decimal equivalent of a true binary word Vout can be found by D 512 Vo VREF 5 With this configuration only the offset voltage of amplifier 1 need be nulled to preserve linearity of the DAC The offset voltage error of the second op amp has no effect on lineari ty It presents a constant output voltage error and should be nulled only if absolute accuracy is needed Another advan tage of this configuration is that the values of the external resistors required do not have to match the value of the internal DAC resistors they need only to match and temper ature track each other A thin film 4 resistor network available from Beckman Instru ments Inc part no 694 3 R10K D is ideally suited for this application Two of the four available 10 kQ resistor can be paralleled to form R in Figure 5 and the other two can be used separately as the resistors labeled 2R Operation is summarized in the table below 0 lt D lt 1023 512 Applied 2 s Comp 2 s Comp Applied True Binary Vout Decimal Binary Digital Input Decimal VREF VREF 511 0111111111 1111111111 1023 Vnge 1 LSB Vngrl 1 LSB 256 0100000000 1100000000 768 Vrer 2 Vrerl
10. 0 0 092 x 0 030 2 337 x 0762 Ses MAX DP 0 81320 127 RAD PIN NO 1 IDENT 260 30005 o 5 604 20 127 PIN NO T IDENT ce SEED MN n option E MIN 0 090 E OPTION 2 E a 2288 7 620 8 128 0 060 NOM 0 040 OPTION 2 0 130 0 005 11520 7 a 7 ma t im 8 302 0 127 0145 0200 ass 95 5 0 009 0 015 1 90 0 004 WO 0229 9380 uae e Sh aa TYP 0 100 0 010 2d ps 0 125 0 140 0 508 0 060 0 005 2540 20 250 m 0 01820 003 3s 3g MIN 0325 10009 15240127 0 487 0 076 325 9015 1 016 ass a Nana ney 6 Order Number DAC1006LCN DAC1007LCN or DAC1008LCN NS Package Number N20A LIFE SUPPORT POLICY NATIONAL S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION As used herein 1 Life support devices or systems are devices or systems which a are intended for surgical implant into the body or b support or sustain life and whose failure to perform when properly used in accordance with instructions for use provided in the labeling can be reasonably expected to result in a significant injury to the user 2 A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system or to
11. E 6 4 1 Single Buffered b XFER AND LATCH DAC1006 1007 1008 20 Pin Parts DAC REGISTER XFER TO DAC REGISTER CN wi E f Bye 1ye soap pur a f XFH 0 OUTPUT NN INPUT DATA IS LATCH ANALOG LATCHES DATA IN DAC REGISTER A UPDATED 7 A LATCHED OUTPUT INPUT DATA MUST REMAIN VALID LOAD INPUT LATCH UPOATED UNTIL THIS TIME 6 4 2 Double Buffered DAC 1006 1007 1008 20 Pin Parts LOAD INPUT LATCH A wn PA hp LATCH INPUT LATCH XFER 6 3 2 Double Buffered DAC1006 1007 1008 20 Pin Parts INPUT DATA IS LATCHED ANALOG Byte 1 Byte 2 PA d OUTPUT Co LATCH DAC WR N my fe UPDATED REGISTER S XFER 0 T LOAD INPUT LATCH TL H 5688 23 XFER ANALOG OUTPUT DAC REGISTER Byte V BgS2 1 UPDATED n IS LATCHED XFER TL H 5688 22 For a connection diagram of this operating mode use Figure 16 for the Logic and Figure 17 for the Data Input connections 16 7 0 MICROPROCESSOR INTERFACE The logic functions of the DAC1006 family have been ori The circuit will perform an automatic transfer of the 10 bits ented towards an ease of interface with all popular Ps The of output data from the CPU to the DAC register as outlined following sections discuss in detail a few useful interface in Section 6 2 1 Controlling Data Transfer for an 8 Bit Data schemes Bus 7 1 DAC1001 1 2 to INS8080A Interface Since a double byte write is necessary to control the DAC with the INS8080A a possible instruction to achieve this is a PU
12. ING TIME 2 uSEC fy 8 TL H 5688 13 FIGURE 11 Increasing the Output Voltage Swing The output voltage swing can be expanded by adding 2 resistors to Figure 10 as shown in Figure 11 These added resistors are used to attenuate the V voltage The overall gain Ay from the V terminal to the output of the op amp determines the most negative output voltage 4 V when the Vrer voltage at the input of the op amp is zero with the component values shown The complete dy namic range of Vout is provided by the gain from the input of the op amp As the voltage at the Vngr pin ranges from OV to V 1023 1024 the output of the op amp will range from 10 Vpc to 10V 1023 1024 when using a V voltage of 2 500 Vpc The 2 5 Vpc reference voltage can be easily developed by using the LM336 zener which can be biased through the Rfg internal resistor connected to Vcc 5 3 Op Amp Vos Adjust Zero Adjust for Current Switching Mode Proper operation of the ladder requires that all of the 2R legs always go to exactly 0 Vpc ground Therefore offset voltage Vos of the external op amp cannot be tolerated as every millivolt of Vos will introduce 0 01 of added linearity error At first this seems unusually sensitive until it becomes clear the 1 mV is 0 01 of the 10V reference High resolu tion converters of high accuracy require attention to every detail in an application to achieve the available performance which is inherent i
13. O DAC1008 O O General Description The DAC1006 7 8 are advanced CMOS Si Cr 10 9 and 8 bit accurate multiplying DACs which are designed to inter face directly with the 8080 8048 8085 Z 80 and other pop ular microprocessors These DACs appear as a memory lo cation or an I O port to the uP and no interfacing logic is needed These devices combined with an external amplifier and voltage reference can be used as standard D A converters and they are very attractive for multiplying applications such as digitally controlled gain blocks since their linearity error is essentially independent of the voltage reference They become equally attractive in audio signal processing equipment as audio gain controls or as programmable at tenuators which marry high quality audio signal processing to digitally based systems under microprocessor control All of these DACs are double buffered They can load all 10 bits or two 8 bit bytes and the data format is left justified The analog section of these DACs is essentially the same as that of the DAC1020 The DAC1006 series are the 10 bit members of a family of microprocessor compatible DAC s MICRO DACTV s For applications requiring other resolutions the DACO0830 series 8 bits and the DAC1208 and DAC1230 12 bits are avail able alternatives Part aa Pin Description DAC1006 10 For left DAC1007 9 20 justified DAC1008 8 data MICRO DAC and BI FE
14. POP instruction followed by instructions to insure that proper data is in the DAC data register pair be fore it is PUSHED to the DAC should be executed as the POP instruction will arbitrarily alter the contents of a register pair Another double byte write instruction is Store H and L Direct SHLD where the HL register pair would temporarily con tain the DAC data and the two sequential addresses for the DAC are specified by the instruction op code The auto in crementing of the DAC address by the SHLD instruction permits the same simple scheme of using address bit 0 to generate the byte number and transfer strobes 7 2 DAC 1006 to MC6820 1 PIA Interface In Figure 19 the DAC1006 is interfaced to an M6800 system through an MC6820 1 Peripheral Interface Adapter PIA In this case the CS pin of the DAC is grounded since the PIA is already mapped in the 6800 system memory space and no decoding is necessary Furthermore by using both Ports A and B of the PIA the 10 bit data transfer assumed left justified again in two 8 bit bytes is greatly simplified The HIGH byte is loaded into Output Register A ORA of the PIA and the LOW byte is loaded into ORB The 10 bit data transfer to the DAC and the corresponding analog output change occur simultaneously upon CB2 going LOW under program control The 10 bit data word in the DAC register will be latched and hence Vout will be fixed when CB2 is brought back HIGH If both output port
15. SH of a register pair onto a stack in memory The 16 bit register pair word will contain the 10 bits of the eventual DAC input data in the proper sequence to conform to both Figure 18 ilustrates the simplicity of interfacing the DAC1006 to an INS8080A based microprocessor system DATA BUS EE AAA leet tll O VouT Y CONTROL BUS NOTE DOUBLE BYTE STORES CAN BE USED e g THE INSTRUCTION SHLD F001 STORES THE L REG INTO B1 AND THE H REG INTO B2 AND TRANSFERS THE RESULT TO THE DAC REGISTER THE OPERAND OF THE SHLD INSTRUCTION MUST BE AN ODD ADDRESS FOR PROPER TRANSFER TL H 5688 24 FIGURE 18 Interfacing the DAC 1000 to the INS8080A CPU Group 17 the requirements of the DAC with regard to left justified data and the implementation of the PUSH instruction which will output the higher order byte of the register pair i e register B of the BC pair first The DAC will actually appear as a two byte stack in memory to the CPU The auto dec rementing of the stack pointer during a PUSH allows using address bit 0 of the stack pointer as the Byte1 Byte2 and XFER strobes if bit O of the stack pointer address 1 SP 1 is a 1 as presented to the DAC Additional ad dress decoding by the DM8131 will generate a unique DAC chip select CS and synchronize this CS to the two memory write strobes of the PUSH instruction To reset the stack pointer so new data may be output to the same DAC a
16. T are trademarks of National Semiconductor Corp QN vationat Semiconductor DAC 1006 DAC 1007 DAC1008 uP Compatible Double Buffered D to A Converters January 1995 Features m Uses easy to adjust END POINT specs NOT BEST STRAIGHT LINE FIT W Low power consumption W Direct interface to all popular microprocessors W Integrated thin film on CMOS structure m Double buffered single buffered or flow through digital data inputs W Loads two 8 bit bytes or a single 10 bit word W Logic inputs which meet TTL voltage level specs 1 4V logic threshold W Works with 10V reference full 4 quadrant multiplica tion m Operates STAND ALONE without uP if desired W Available in 0 3 standard 20 pin package W Differential non linearity selection available as special order Key Specifications W Output Current Settling Time m Resolution W Linearity 500 ns 10 bits 10 9 and 8 bits guaranteed over temp m Gain Tempco 0 0003 of FS C W Low Power Dissipation 20 mW including ladder m Single Power Supply 5 to 15 Vpc Typical Application c CONTROL BUS ts 4 3 NSEWODO Z 8080 BUS DAC1006 1007 1008 O VOUT NOTE FOR DETAILS OF BUS CONNECTION SEE SECTION 6 0 TL H 5688 1 1995 National Semiconductor Corporation TL H 5688 RRD B30M115 Printed in U S A S49119AUO2 V O1 d paJojjng ejqnog aiqnedwod d 800 2V3 400L9VQ 900L2VG Absolute Maximum Ratings notes 1
17. TLED TO TS LSB Typical Performance Characteristics CHANGE IN ERROR CONTROL SETUP TIME tcs ns Errors vs Supply Voltage ITY ERROR A GAIN ERROR 0 5 10 15 SUPPLY VOLTAGE Vec VDC Control Setup Time tcs Errors vs Temperature 0 100 0 075 0 050 A LINEARITY ER CHANGE IN ERROR e E s 701005 35 15 5 25 45 65 85 105125 AMBIENT TEMPERATURE C Data Setup Time tps B Vint 0V 500 f win 3V 70 sv 2 ui E a 5 u a 2 2 H s 8 0 9 55 35 15 5 25 45 65 85 105 125 55 35 15 5 25 45 65 85 105 125 AMBIENT TEMPERATURE C Ta AMBIENT TEMPERATURE C Digital Threshold vs Supply Voltage 24 2 4 1 34 2 0 1 6 55 00 2 0 TL H 5688 2 Write Width tw VINL OV VINH 3V TO 5V 500 400 300 200 WRI WIDTH tw ns 100 0 55 35 15 5 25 45 65 85 105 125 AMBIENT TEMPERATURE C Data Hold Time tpH VINL OV VINH 3V TO 5V _Vec 10V 300 Fvce 5V CONTROL SETUP TIME tpH ns 0 55 35 15 5 25 45 65 85 105 125 Ta AMBIENT TEMPERATURE C Digital Input Threshold vs Temperature 1 6 Ta 25 zi Ta 28 C 0 8L TAH 125 C DIGITAL THRESHOLD V 12 DIGITAL THRESHOLD V nap 0 4 0 0 5 0 0
18. These parts require the MS or Hi Byte data group to be transferred on the 1st write cycle 6 2 Controlling Data Transfer for an 8 Bit Data Bus Three operating modes are possible for controlling the transfer of data from the Input Latch to the DAC Register where it will update the analog output voltage The simplest is the automatic transfer mode which causes the data transfer to occur at the time of the 2nd write cycle This is recommended when the exact timing of the changes of the DAC analog output are not critical This typically happens where each DAC is operating individually in a system and the analog updating of one DAC is not required to be syn chronized to any other DAC For synchronized DAC updat ing two options are provided uP control via a common XFER strobe or external update timing control via an exter nal strobe The details of these options are now shown DAC1006 1007 1008 20 Pin Parts for Left Justified Data fe B BIT BYTE HI BYTE k LO BYTE pa ER AAA HEFE H HI BYTE LO BYTE TL H 5688 16 FIGURE 15 Fitting a 10 Bit Data Word into 16 Available Bit Locations CURRENT SWITCHES 1 0 OUTPUTS FOLLOW D INPUTS LATCH ENABLE 0 DATA AT D IS LATCHED TL H 5688 17 FIGURE 16 Input Connections and Controls for DAC1006 1007 1008 Left Justified Data 6 2 1 Automatic Transfer This makes use of a double byte double precision write The first byte 8 bits is str
19. ditional 0 01 linearity error Note 5 Guaranteed at Vggp 10 Vpc and Vgge 1 Voc Note 6 Tuin 0 C and Tyax 70 C for LCN and LCWM suffix parts Note 7 The unit FSR stands for Full Scale Range Linearity Error and Power Supply Rejection specs are based on this unit to eliminate dependence on a particular Vgge value and to indicate the true performance of the part The Linearity Error specification of the DAC1006 is 0 05 of FSR MAX This guarantees that after performing a zero and full scale adjustment See Sections 2 5 and 2 6 the plot of the 1024 analog voltage outputs will each be within 0 05 X Vnggr of a straight line which passes through zero and full scale Note 8 This specification implies that all parts are guaranteed to operate with a write pulse or transfer pulse width tw of 320 ns A typical part will operate with ty of only 100 ns The entire write pulse must occur within the valid data interval for the specified tw tps tpH and ts to apply Note 9 Guaranteed by design but not tested Note 10 A 200 nA leakage current with Ry 20K and Vref 10V corresponds to a zero error of 200x 10 9 20 x 103 x 100 10 which is 0 04 of FS Note 11 Human body model 100 pF discharged through a 1 5 kQ resistor Switching Waveforms VIH CS BYTE1 BYTE2 50 50 VIL F Vin WR 50 50 VIL tos 10H DATA BITS VIH 50 50 V IL FR SU lous SET
20. gle op amp as shown in Figure 10 For a digital input code of all zeros the output voltage from the Vngr pin is zero volts The external op amp now has a single input of V and is operating with a gain of 1 to this input The output of the op amp therefore will be at V for a digital input of all zeros As the digital code increases the output voltage at the Vref pin increases Notice that the gain of the op amp to voltages which are applied to the input is 2 and the gain to voltages which are applied to the input resistor R is 1 The output voltage of the op amp depends on both of these inputs and is given by Vout V 71 Vrer 2 A LINEARITY ERROR CHANGE IN ERROR 0 2 4 8 8 10 12 14 16 SUPPLY VOLTAGE Vcc VDC FIGURE 6 FIGURE 7 DIGITAL INPUT CODE MSB Dig Dig Doe DH Dig LSB 0 lt Vout lt 2 5Vpc qu R 15k0 VREF OVpc Vout lt 2 5Vpc 1 f aga FIGURE 9 Amplifying the Voltage Mode Output Single Supply Operation TL H 5688 12 10 VREF E 2 500 VDC LM336 1 2 5Vpc lt VouT lt 2 5Vpc amp gt O VOUT Ea SLEWING AND SETTLING TIME 1 8 SEC FIGURE 10 Providing a Bipolar Output Voltage with a Single Op Amp V 2 500 Vpc VREF MICRO DAC 0 lt Vpac lt 2 5 pc 1041 R4 133K 40Vp lt Vout lt 10Voc 85 O VouT 512 SLEWING AND SETTL
21. ificant byte MS byte or the least significant byte LS byte Table 1 Operating Mode Automatic Transfer pP Control Transfer External Transfer Section Figure No Section Figure No Section Figure No Data Bus 8 Bit Data Bus 6 1 0 Left Justified 6 1 1 6 2 1 16 6 2 2 16 6 2 3 16 Single Buff Double Buff Flow Th h 16 Bit Data Bus 6 3 0 ingle Buffered ouble Buffered ow Throug 6 3 1 17 6 3 2 17 Not Applicable Single Buff Double Buffere Flow Through Stand Alone 6 4 0 ingle Buffered ouble Buffered ow Throug 6 4 1 17 6 4 2 17 NA These data possibilities are shown in Figure 15 Note that the justification of data depends on how the 10 bit data word is located within the 16 bit data source CPU register In either case there is a surplus of 6 bits and these are shown as don t care terms X in this figure All of these DACs load 10 bits on the 1st write cycle A particular set of 2 bits is then overwritten on the 2nd write cycle depending on the justification of the data For all left justified data options the 1st write cycle must contain the MS or Hi Byte data group 6 1 1 For Left Justified Data For applications which require left justified data DAC1006 1008 can be used A simplified logic diagram which shows the external connections to the data bus and the internal functions of both of the data buffer registers Input Latch and DAC Register is shown in Figure 16
22. le Linearity error is a parameter intrinsic to the device and cannot be externally adjusted National s linearity test a and the best straight line test b used by other suppliers are illustrated below The best straight line requires a special zero and FS adjustment for each part which is almost impossible for user to determine The end point test uses a standard zero and FS adjust ment procedure and is a much more stringent test for DAC linearity Power Supply Sensitivity Power supply sensitivity is a measure of the effect of power supply changes on the DAC full scale output which is the worst case b Best Straight Line Y LSB ERROR BAND ACTUAL ANALOG OUTPUT DIGITAL INPUT TL H 5688 8 Settling Time Settling time is the time required from a code transition until the DAC output reaches within 1 LSB of the final output value Full scale settling time requires a zero to full scale or full scale to zero output change Full Scale Error Full scale error is a measure of the output error between an ideal DAC and the actual device output Ideally for the DAC1006 series full scale is Vggp 1 LSB For Vgge 10V and unipolar operation VFULL sca LE 10 0000V 9 8mV 9 9902V Full scale error is adjust able to zero Monotonicity If the output of a DAC increases for increas ing digital input code then the DAC is monotonic A 10 bit DAC with 10 bit monotonicity will produce an increasing a
23. ligible BI FET op amps are strongly recommended for these DACs The distance from the loyr4 pin of the DAC to the inverting input of the op amp should be kept as short as possible to prevent inadvertent noise pickup 5 0 ANALOG APPLICATIONS The analog section of these DACs uses an R 2R ladder which can be operated both in the current switching mode and in the voltage switching mode The major product changes compared with the DAC1020 have been made in the digital functioning of the DAC The analog functioning is reviewed here for completeness For additional analog applications such as multipliers attenua tors digitally controlled amplifiers and low frequency sine wave oscillators refer to the DAC1020 data sheet Some basic circuit ideas are presented in this section in addition to complete applications circuits 5 1 Operation in Current Switching Mode The analog circuitry Figure 2 consists of a silicon chromi um Si Cr thin film R 2R ladder which is deposited on the surface oxide of the monolithic chip As a result there is no parasitic diode connected to the VreF pin as would exist if diffused resistors were used The reference voltage input Vngr can therefore range from 10V to 10V The digital input code to the DAC simply controls the posi tion of the SPDT current switches SWO to SW9 A logical 1 digital input causes the current switch to steer the avail able ladder current to the loyr4 output pin These MOS
24. n alog output when all 10 digital inputs are exercised A 10 bit DAC with 9 bit monotonicity will be monotonic when only the most significant 9 bits are exercised Similarly 8 bit monotonicity is guaranteed when only the most significant 8 bits are exercised 2 0 DOUBLE BUFFERING These DACs are double buffered microprocessor compati ble versions of the DAC1020 10 bit multiplying DAC The addition of the buffers for the digital input data not only al lows for storage of this data but also provides a way to assemble the 10 bit input data word from two write cycles when using an 8 bit data bus Thus the next data update for the DAC output can be made with the complete new set of 10 bit data Further the double buffering allows many DACs in a system to store current data and also the next data The updating of the new data for each DAC is also not time critical When all DACs are updated a common strobe sig nal can then be used to cause all DACs to switch to their new analog output levels 3 0 TTL COMPATIBLE LOGIC INPUTS To guarantee TTL voltage compatibility of the logic inputs a novel bipolar NPN regulator circuit is used This makes the input logic thresholds equal to the forward drop of two di odes and also matches the temperature variation as oc curs naturally in TTL The basic circuit is shown in Figure 7 A curve of digital input threshold as a function of power supply voltage is shown in the Typical Performance Cha
25. n the part To prevent this source of error the Vos of the op amp has to be initially zeroed This is the zero adjust of the DAC calibration sequence and should be done first If the Vos is to be adjusted there are a few points to consid er Note that no dc balancing resistance should be used in the grounded positive input lead of the op amp This re sistance and the input current of the op amp can also create errors The low input biasing current of the BI FET op amps makes them ideal for use in DAC current to voltage applica tions The Vog of the op amp should be adjusted with a digital input of all zeros to force lour 0 mA A 1 kQ resistor can be temporarily connected from the inverting input to ground to provide a dc gain of approximately 15 to the Vos of the op amp and make the zeroing easier to sense 5 4 Full Scale Adjust The full scale adjust procedure depends on the application circuit and whether the DAC is operated in the current switching mode or in the voltage switching mode Tech niques are given below for all of the possible application circuits 5 4 1 Current Switching with Unipolar Output Voltage After doing a zero adjust set all of the digital input levels HIGH and adjust the magnitude of VreF for 1023 Vi ideal V our REF 1024 This completes the DAC calibration 11 5 4 2 Current Switching with Bipolar Output Voltage 5 4 3 Voltage Switching with a Unipola
26. nt Settling ts Vip OV Vip 5V 500 500 ns Time Write and XFER tw ViL 0V Vin 5V Pulse Width Ta 25 C 8 150 60 320 200 ns TMINE TA TMAX 9 320 100 500 250 ns Data Set Up Time tps Vip OV Vj 5V Ta 25 C 9 150 80 320 170 ns TMINE TA TMAX 320 120 500 250 ns Data Hold Time ton Vip 7 OV Viy 5V Ta 25 C 9 200 100 320 220 ns Tmin lt Ta lt TmMax 250 120 500 320 ns Control Set Up tcs Vip 0V Vj 5V Time Ta 25 C 9 150 60 320 180 ns Tmin Ta lt Tmax 320 100 500 260 ns Control Hold Time tcu V L 0V Viu 5V Ta 25 C 9 10 0 10 0 ns Tmin lt TA lt TMAX 10 0 10 0 ns Note 1 Absolute Maximum Ratings indicate limits beyond which damage to the device may occur DC and AC electrical specifications do not apply when operating the device beyond its specified operating conditions Note 2 All voltages are measured with respect to GND unless otherwise specified Note 3 This 500 mW specification applies for all packages The low intrinsic power dissipation of this part and the fact that there is no way to significantly modify the power dissipation removes concern for heat sinking Note 4 For current switching applications both Ioyt1 and IouT2 must go to ground or the Virtual Ground of an operational amplifier The linearity error is degraded by approximately Vos Vngr For example if Vage 10V then a 1 mV offset Vos on Iouti or louT2 will introduce an ad
27. obed into the input latch and the second byte causes a simultaneous strobe of the two re maining bits into the input latch and also the transfer of the complete 10 bit word from the input latch to the DAC regis ter This is shown in the following timing diagram the point in time where the analog output is updated is also indicated on this diagram DAC1006 1007 1008 20 Pin Parts LOAD Byte 1 LOAD Byte 2 amp XFER WR amp XFER LATCH LATCH DAC Byte 1 REGISTER ANALOG OUTPUT UPDATED Byte 1 Byte 2 TL H 5688 18 SIGNIFIES CONTROL INPUTS WHICH ARE DRIVEN IN PARALLEL 6 2 2 Transfer Using uP Write Stroke The input latch is loaded with the first two write strobes The XFER signal is provided by external logic as shown below to cause the transfer to be accomplished on a third write strobe This is shown in the following diagram DAC1006 1007 1008 20 Pin Parts MN S RB y ANALOG OUTPUT LATCH DAC LOAD Byte 1 LOAD Byte 2 UPDATED REGISTER Wa LATCH Byte 1 n LATCH Byte 2 XFER i a Byte 1 Byte 2 a WHERE THE XFER CONTROL CAN BE GENERATED BY USING A SECOND CHIP SELECT AS y i 1 ym AND THE BYTE CONTROL CAN BE DERIVED FROM THE ADDRESS BUS SIGNALS TL H 5688 19 6 2 3 Transfer Using an External Strobe This is similar to the previous operation except the XFER signal is not provided by the uP The timing diagram for this is DAC1006 1007 1008 20 Pin Parts ts E i Byte 1 LOAD B
28. or Using internal Rp 10V lt VpeF lt 10V 5 1 0 0 3 1 0 1 0 0 3 1 0 of FS Gain Error Tempco TMIN TAX TMAX 6 Using internal Rfb 9 0 0003 0 001 0 0006 0 002 of FS C Power Supply All digital inputs Rejection latched high Voc 14 5V to 15 5V 0 003 0 008 96 FSR V 11 5V to 12 5V 0 004 0 010 FSR V 4 75V to 5 25V 0 033 0 10 FSR V Reference Input Resistance 10 15 20 10 15 20 ko Output Feedthrough VREF 20Vp p f 100 kHz Error All data inputs 90 90 mVp p latched low Output louTi All data inputs 60 60 pF Capacitance loyr2 latched low 250 250 pF lour1 All data inputs 250 250 pF louT2 latched high 60 60 pF Supply Current Drain TuiNS TAE TMAX 6 0 5 3 5 0 5 3 5 mA Electrical Characteristics Tested at Vcc 4 75 Vpc and 15 75 Voc Ta 25 C Vngr 10 000 Vpc unless otherwise noted Continued Vec 12Vpc 5 E 659 Parameter Conditions ane to 15Vpc 5 Vec 5Vnc 5 Units Min Typ Max Min Typ Max Output Leakage Tmin lt TA lt TMAX 6 Current lout All data inputs latched low 10 200 200 nA louT2 All data inputs latched high 200 200 nA Digital Input Tmn lt Ta lt Tmax 6 Voltages Low level LCN and LCWM suffix 0 8 0 8 0 7 0 8 Vpc High level all parts 2 0 2 0 Voc Digital Input TMiN E TAX TMAX 6 Currents Digital inputs lt 0 8V 40 150 40 150 ADC Digital inputs gt 2 0V 1 0 10 1 0 10 pApc Curre
29. ow given by VIN EP V where M Digital input expressed as a QUT M fractional binary Hey 0 lt M lt 1 19 LF13333 FIGURE 22 Digital to Synchro Converter Ordering Information For Left Justified Data 20 pin package Temperature Range Accuracy 0 to 70 C 0 05 10 bit DAC1006LCN DAC1006LCWM 0 10 9 bit DAC1007LCN 0 20 8 bit DAC1008LCN Package Outline N20A M20B 3 TL H 5688 27 20 Physical Dimensions inches millimeters 0 496 0 512 12 598 13 005 20 19 18 17 16 15 314 13 12 11 A 0 394 0 418 10 008 10 643 30 TYP LEAD NO 1H IDENT 7 Y Y y 1 2 3 4 5 8 7 8 9 40 0 010 max 0 254 0 291 0 299 7 391 7 595 0 010 0 029 0 093 0 104 0 284 0 737 E 2 362 2 642 0 004 0 012 L es Lj 0 102 0 305 in SHARE 8 MAX TYP ALL iu SUM t i m A 4 PLANE 0 004 0 014 0 009 0 013 T3051 LG 0 050 0 014 0 020 AN 0 102 E 0 016 0 050 0 356 fa 22090 a 2 014 0 020 typ 0 229 0 330 ALL LEAD TIPS 10 406 1 270 3 6 1 270 0 356 0 508 TYP ALL LEADS TYP ALL LEADS TYP 0 008 qyp 0 203 zone A Order Number DAC1006LCWM NS Package Number M20B 21 Double Buffered D to A Converters DAC 1006 DAC 1007 DAC1008 uP Compatible Physical Dimensions inches millimeters Con tinued 25 73 28 42 1 013 1 04
30. r Output Voltage The circuit of Figure 12 shows the 3 adjustments needed Refer to the circuit of Figure 13 and set all digital inputs The first step is to set all of the digital inputs LOW to force LOW Trim the zero adj for Voyr 0 Vpc 1 mV Then lout1 to 0 and then trim zero adj for zero volts at the set all digital inputs HIGH and trim the FS Adj for inverting input pin 2 of OA1 Next with a code of all zeros R4 1023 still applied adjust FS adj the reference voltage for vour e v 1 oes Vour x ideal Vage The sign of the output voltage will G be opposite that of the applied reference 5 4 4 Voltage Switching with a Bipolar Output Voltage Finally set all of the digital inputs HIGH and adjust FS Refer to Figure 14 and set all digital inputs LOW Trim the adj for Vout Vngre 611 512 The sign of the output at FS Adj for Vout 2 5 Vpc Then set all digital inputs this time will be the same as that of the reference voltage HIGH and trim the FS Adj for Vout 2 5 511 512 The addition of the 2004 resistor in series with the Vref pin Vpc Test the zero by setting the MS digital input HIGH and of the DAC is to force the circuit gain error from the DAC to all the rest LOW Adjust Vos of amp 3 if necessary and be negative This insures that adding resistance to Rp with recheck the full scale values the 5002 pot will always compensate the gain error of the DAC FS ADJ 500
31. rac teristics section 4 0 APPLICATION HINTS The DC stability of the VRer source is the most important factor to maintain accuracy of the DAC over time and tem perature changes A good single point ground for the analog signals is next in importance These MICRO DAC converters are CMOS products and reasonable care should be exercised in handling them prior to final mounting on a PC board The digital inputs are pro tected but permanent damage may occur if the part is sub jected to high electrostatic fields Store unused parts in con ductive foam or anti static rails 4 1 Power Supply Sequencing amp Decoupling Some IC amplifiers draw excessive current from the Analog inputs to V when the supplies are first turned on To pre vent damage to the DAC an external Schottky diode con nected from lout1 or louT2 to ground may be required to prevent destructive currents in lour4 or loura If an LM741 or LF356 is used these diodes are not required The standard power supply decoupling capacitors which are used for the op amp are adequate for the DAC 34 VrHN lt p gt VBIAS TO OTHER INPUTS 24 VTHN TVCC Voc CMOS LOGIC 0 VTHRESHOLD 26 FIGURE 1 Basic Logic Threshold Loop TL H 5688 9 4 2 Op Amp Bias Current amp Input Leads The op amp bias current Ig CAN CAUSE DC ERRORS BI FETTM op amps have very low bias current and therefore the error introduced is neg
32. re level actuated CS Chip Select active low it will enable WR WR Write The active low WR is used to load the digital data bits Dl into the input latch The data in the input latch is latched when WR is high The 10 bit input latch is split into two latches one holds 8 bits and the other holds 2 bits The Byte1 Byte2 control pin is used to select both input latches when Byte1 Byte2 1 or to overwrite the 2 bit input latch when in the low state Byte1 Byte2 Byte Sequence Control When this control is high all ten locations of the input latch are enabled When low only two locations of the input latch are enabled and these two locations are overwritten on the second byte write On the DAC1006 1007 and 1008 the Byte1 Byte2 must be low to transfer the 10 bit data in the input latch to the DAC register XFER Transfer Control Signal active low This signal in combination with others is used to transfer the 10 bit data which is available in the input latch to the DAC register see timing diagrams 1 2 Other Pin Functions DI i 0 to 9 Digital Inputs Dlo is the least significant bit LSB and Dlg is the most significant bit MSB lout1 DAC Current Output 1 lour4 is a maximum for a digital input code of all 1s and is zero for a digital input code of all Os lour2 DAC Current Output 2 loura is a constant minus lour1 or 1023 VREF 1024 R where R 15 kQ lour1 lout2 a End Point Te
33. s of the PIA are not available it is possible to interface the DAC1006 through a single port without much effort However additional logic at the CB2 or CA2 lines or access to some of the 6800 system control lines will be required 7 3 Noise Considerations A typical digital microprocessor bus environment is a tre mendous potential source of high frequency noise which can be coupled to sensitive analog circuitry The fast edges of the data and address bus signals generate frequency components of 10 s of megahertz and can cause noise spikes to appear at the DAC output These noise spikes occur when the data bus changes state or when data is transferred between the latches of the device In low frequency or DC applications low pass filtering can reduce these noise spikes This is accomplished by over compensating the DAC output amplifier by increasing the value of the feedback capacitor Cc in Figure 3 In applications requiring a fast transient response from the DAC and op amp filtering may not be feasible Adding a latch DM74LS374 as shown in Figure 20 isolates the de vice from the data bus thus eliminating noise spikes that occur every time the data bus changes state Another meth od for eliminating noise spikes is to add a sample and hold after the DAC op amp This also has the advantage of elimi nating noise spikes when changing digital codes TL H 5688 25 FIGURE 19 DAC1000 to MC6820 1 PIA Interface 18
34. s under the control of the uP and can include more than one DAC in a simultaneous transfer or 3 a transfer which is under the control of external logic Further the data format can be either left justified or right justified When interfacing to a uP with a 16 bit data bus only two selections are available 1 operating the DAC with a single digital data buffer the transfer of one DAC does not have to be synchronized with any other DACs in the system or 2 operating with a double digital data buffer for simulta neous transfer or updating of more than one DAC For operating without a uP in the stand alone mode three options are provided 1 using only a single digital data buff er 2 using both digital data buffers double buffered or 3 allowing the input digital data to flow through to provide the analog output without the use of any data latches To reduce the required reading only the applicable sections of 6 1 through 6 4 need be considered 6 1 Interfacing to an 8 Bit Data Bus Transferring 10 bits of data over an 8 bit bus requires two write cycles and provides four possible combinations which depend upon two basic data format and protocol decisions 1 Is the data to be left justified considered as fractional binary data with the binary point to the left or right justi fied considered as binary weighted data with the binary point to the right 2 Which byte will be transferred first the most sign
35. st After Zero and FS Adj ACTUAL Y2 LSB ERROR ANALOG OUTPUT IDEAL RESPONSE DIGITAL INPUT Rep Feedback Resistor This is provided on the IC chip for use as the shunt feedback resistor when an external op amp is used to provide an output voltage for the DAC This on chip resistor should always be used not an external re sistor because it matches the resistors used in the on chip R 2R ladder and tracks these resistors over temperature Vrer Reference Voltage Input This is the connection for the external precision voltage source which drives the R 2R ladder VaeF can range from 10 to 10 volts This is also the analog voltage input for a 4 quadrant multiplying DAC application Vcc Digital Supply Voltage This is the power supply pin for the part Vcc can be from 5 to 15 Vpc Operation is optimum for 15V The input threshold voltages are nearly independent of Vcc See Typical Performance Characteris tics and Description in Section 3 0 T2L compatible logic inputs GND Ground the ground pin for the part 1 3 Definition of Terms Resolution Resolution is directly related to the number of Switches or bits within the DAC For example the DAC1006 has 210 or 1024 steps and therefore has 10 bit resolution Linearity Error Linearity error is the maximum deviation from a straight line passing through the endpoints of the DAC transfer characteristic t is measured after adjusting for zero and full sca
36. yte 2 a s VE TIN arcu Bye 1 V N urea Byte 2 oe APER XFER ANALOG H OUTPUT LATCH DAC VEDATER REGISTER TL H 5688 20 6 3 Interfacing to a 16 Bit Data Bus The interface to a 16 bit data bus is easily handled by con necting to 10 of the available bus lines This allows a wiring selected right justified or left justified data format This is shown in the connection diagram of Figure 17 where the use of DB6 to DB15 gives left justified data operation Note that any part number can be used and the Byte1 Byte2 con trol should be wired Hi 15 LEFT I DAC1006 1007 1008 20 PIN PARTS JUSTIFIED DB45 gl Dig MSB 16 BIT 10 BIT TO DATA BUS DAC CURRENT REGISTER SWITCHES Socosssooo DOcoosocoo LSB WHEN LATCH ENABLE 1 0 OUTPUTS FOLLOW D INPUTS LATCH ENABLE 0 DATA AT D IS LATCHED CONTROL BUS 653 XFER 3 teco EQUIVALENT LOGIC SHOWN Byte 1 ByleZ FOR THIS PIN HIGH TL H 5688 21 FIGURE 17 Input Connections and Logic for DAC1006 1007 1008 with 16 Bit Data Bus Three operating modes are possible flow through single 6 4 Stand Alone Operation buffered or double buffered The timing diagrams for these For applications for a DAC which are not under P control are shown below stand alone there are two basic operating modes single buffered and double buffered The timing diagrams for these 6 3 1 Single Buffered DAC1006 1007 1008 20 Pin Parts are shown below
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