IDT IDT23S08 handbook
Contents
1. 1 4V Fout 50MHz 15pF Load easured between 0 8V and 2V 30pF Load easured between 0 8V and 2V 15pF Load easured between 0 8V and 2V 30pF Load easured between 0 8V and 2V 30pF Load easured between 0 8V and 2V 15pF Load easured between 0 8V and 2V 30pF Load All outputs equally loaded All outputs equally loaded All outputs equally loaded All outputs equally loaded Measured at VDD 2 Measured at Vbp 2 on the FBK pins of devices Measured between 0 8V and 2V on 1H 2H 5H device using Test Circuit 2 Measured at 66 67 MHz loaded outputs 15pF Load Measured at 66 67 MHz loaded outputs 30pF Load Measured at 133 3 MHz loaded outputs 15pF Load Measured at 66 67 MHz loaded outputs 30pF Load Measured at 66 67 MHz loaded outputs 15pF Load Stable Power Supply valid clocks presented on REF and FBK pins IDT23S08 5H has maximum input frequency of 133 33 MHz and maximum output of 66 67MHz IDT23S08 3 3V ZERO DELAY CLOCK MULTIPLIER COMMERCIAL ANDINDUSTRIAL TEMPERATURE RANGES OPERATING CONDITIONS INDUSTRIAL symbol __aaneter TestCondions wn we o E A S TT Operating Temperature Ambient Temperature no S a O 85 cc e a E E S A A poen s NOTE 1 Applies to both REF and FBK DC ELECTRICAL CHARACTERISTICS INDUSTRIAL pe Vo Output LOW Voltage loL 8mA 1 2 3 4 Vol Output HIGH Voltage lOH 8mA 1 2 3 4 all lOH 12mA 1H 2H 5H IL IH L L2. 2 18 D T23S08 hy Fi 3 3V ZERO DELAY CLOCK IDT23S08 MULTIPLIER SPREAD SPECTRUM COMPATIBLE FEATURES DESCRIPTION e Phase Lock Loop Clock Distribution for Applications ranging The IDT23S08 is a high speed phase lock loop PLL clock multiplier Itis from 10MHz to 133MHz operating frequency designed to address high speed clock distribution and multiplication applica Distributes one clock input to two banks of four outputs tions The zero delay is achieved by aligning the phase between the incoming Separate output enable for each output bank clock and the output clock operable within the range of 10 to 133MHz External feedback FBK pin is used to synchronize the outputs The IDT23S08 hastwo banks of four outputs each thatare controlled via two to the clock input select addresses By proper selection of input addresses both banks can be Output Skew lt 200 ps put in tri state mode In test mode the PLL is turned off and the input clock e Low jitter lt 200 ps cycle to cycle directly drives the outputs for system testing purposes In the absence of an e 1x 2x 4x output options see table input clock the IDT23S08 enters power down In this mode the device will IDT23S08 1 1x drawless than 12u A for Commercial Temperature range and less than 25u A IDT23S08 2 1x 2x IDT23S08 3 2x 4x IDT23S08 4 2x IDT23S08 1H 2H and 5H for High Drive No external RC network required Operates at 3 3V VDD S
3. 30pF Load Alloutputs equally loaded Alloutputs equally loaded Alloutputs equally loaded Alloutputs equally loaded Measured at Vpp 2 Measured at Vbb 2 on the FBK pins of devices Measured between 0 8V and 2V on 1H 2H 5H device using Test Circuit 2 Measured at 66 67 MHz loaded outputs 15pF Load Measured at 66 67 MHz loaded outputs 30pF Load Measured at 133 3 MHz loaded outputs 15pF Load Measured at 66 67 MHz loaded outputs 30pF Load Measured at 66 67 MHz loaded outputs 15pF Load Stable Power Supply valid clocks presented on REF and FBK pins Conditions S _30pF Load alldevices 20pF Load 1H 2H 5H Devices _15pF Load 1 2 3 4 devioes Allouiputsequalyloaded Allouiputsequalyloaded Aloutpusequalyloaded Measuredatvoo O _Measured at Voo 2 on the FBK pins ofdevices IDT23S08 5H has maximum input frequency of 133 33 MHz and maximum output of 66 67MHz IDT23S08 3 3V ZERO DELAY CLOCK MULTIPLIER COMMERCIAL ANDINDUSTRIAL TEMPERATURE RANGES SWITCHING WAVEFORMS Duty Cycle Timing 3 3V Output OV Vpp 2 Input to Output Propagation Delay VDD 2 FBK Device 1 FBK Device 2 7 gt Device to Device Skew IDT23S08 3 3V ZERO DELAY CLOCK MULTIPLIER COMMERCIAL ANDINDUSTRIAL TEMPERATURE RANGES TEST CIRCUITS TEST CIRCUIT 1 TEST CIRCUIT 2 e s ika CK Sig 0 1uF p OUTPUTS m c 10pF LOAD l i 1KO a p VDD T
4. AL TEMPERATURE RANGES ABSOLUTE MAXIMUM RATINGS Supply Voltage Range 0 5to 4 6 Input Voltage Range REF 0 5t0 5 5 VI Input Voltage Range 0 5to except REF Vpp 0 5 lik Vi lt 0 Input Clamp Current Ooa lo Continuous Output Current 50 Vo 0 to VDD TA 55 C Maximum Power Dissipation 0 7 instill air Storage Temperature Range 65to 150 Commercial Temperature Oto 70 Co ill Industrial Temperature 40 to 85 ia a NOTES 1 Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied Exposure to absolute maximum rating conditions for extended periods may affect reliability 2 The input and output negative voltage ratings may be exceeded if the input and output clamp current ratings are observed 3 The maximum package power dissipation is calculated using a junction temperature of 150 C and a board trace length of 750 mils APPLICATIONS e SDRAM Telecom Datacom e PC Motherboards Workstations e Critical Path Delay Designs IDT23S08 3 3V ZERO DELAY CLOCK MULTIPLIER COMMERCIAL ANDINDUSTRIAL TEMPERATURE RANGES FUNCTION TABLE SELECT INPUT DECODING Oooo o oso a CLK A CLK B Output Source PLL Shut Down NOTE 1 H HIGH Voltage Level L LOW Voltage L
5. H Supply Current Unloaded Outputs Select Inputs at Voo or GND 66MHz CLKA 1H 2H 5H 3 4 33MHz CLKA 1 2 3 4 33MHz CLKA 1H 2H 5H IDT23S08 3 3V ZERO DELAY CLOCK MULTIPLIER COMMERCIAL ANDINDUSTRIAL TEMPERATURE RANGES SWITCHING CHARACTERISTICS INDUSTRIAL Parameter Output Frequency Output Frequency Output Frequency Duty Cycle t2 t1 1 2 3 4 1H 2H 5H Duty Cycle t2 t1 1 2 3 4 1H 2H 5H Rise Time 1 2 3 4 1 2 3 4 Rise Time 1H 2H 5H Fall Time 1 2 3 4 Fall Time 1 2 3 4 Fall Time 1H 5H Output to Output Skew on same Bank 1 2 3 4 Output to Output Skew 1H 2H 5H Output Bank A to Output Bank B 1 Output Bank A to Output Bank B Skew Rise Time 4 2H 5H 2 3 REF Rising Edge to FBK Rising Edge Device to Device Skew Delay Output Slew Rate Cycle to Cycle Jitter 1 1H 4 5H Cycle to Cycle Jitter 2 2H 3 PLL Lock Time NOTE 1 Conditions 30pF Load all devices 20pF Load 1H 2H 5H Devices 15pF Load 1 2 3 4 devices Measured at 1 4V Fout 66 66MHz 30pF Load Measured at 1 4V Fout 50MHz 15pF Load easured between 0 8V and 2V 30pF Load easured between 0 8V and 2V 15pF Load easured between 0 8V and 2V 30pF Load easured between 0 8V and 2V 30pF Load easured between 0 8V and 2V 15pF Load easured between 0 8V and 2V
6. O 1pF 7 E GND GND Test Circuit for all Parameters Except t8 Test Circuit for t8 Output Slew Rate On 1H 2H and 5H Device IDT23S08 3 3V ZERO DELAY CLOCK MULTIPLIER COMMERCIAL ANDINDUSTRIAL TEMPERATURE RANGES ORDERING INFORMATION IDT _XXXXX XX X Device Type Package Process Blank Commercial 0 C to 70 C Industrial 40 C to 85 C DC Small Outline DCG SOIC Green PG Thin Shrink Small Outline Package 23S08 1 23808 2 Zero Delay Clock Buffer with Standard Drive 23808 3 Spread Spectrum Compatible 23S08 4 meee Zero Delay Clock Buffer with High Drive E ibi 23508 5H Spread Spectrum Compatible IDT23S08 5HPGI 16 Pin TSSOP Industrial NOTE 1 Contact factory for availability CORPORATE HEADQUARTERS for SALES for Tech Support DT 2975 Stender Way 800 345 7015 or 408 727 6116 logichelp idt com Santa Clara CA 95054 fax 408 492 8674 408 654 6459 www idt com
7. evel AVAILABLE OPTIONS FORIDT23S08 Device FeedbackFrom Bank A Frequency BankB Frequency IDT23S08 5H Bank A or Bank B Reference 2 Reference 2 NOTES 1 Contact factory for availability 2 Output phase is indeterminant 0 or 180 from input clock SPREADSPECTRUM COMPATIBLE Many systems being designed now use atechnology called Spread Spectrum Frequency Timing Generation This productis designed notto filter offthe Spread Spectrum feature of the reference input assuming it exists When a zero delay buffer is not designed to pass the Spread Spectrum feature through the resultis a significant amount of tracking skew which may cause problems in systems requiring synchronization IDT23S08 3 3V ZERO DELAY CLOCK MULTIPLIER COMMERCIAL ANDINDUSTRIAL TEMPERATURE RANGES ZERO DELAY ANDSKEW CONTROL To close the feedback loop of the IDT23S08 the FBK pin can be driven from any of the eight available output pins The output driving the FBK pin will be driving a total load of 7pF plus any additional load that it drives The relative loading of this output with respect to the remaining outputs can adjust the input output delay For applications requiring zero input output delay all outputs including the one providing feedback should be equally loaded Ensure the outputs are loaded equally for zero output output skew OPERATING CONDITIONS COMMERCIAL al DD TA Operating Temperature Ambient Temperature CL Load Capacitance below L00MH
8. pread spectrum compatible Available in SOIC and TSSOP packages for Industrial temperature range and the outputs are tri stated The IDT23S08 is available in six unique configurations for both pre scaling and multiplication of the Input REF Clock See available options table The PLL is closed externally to provide more flexibility by allowing the user tocontrol the delay between the input clock and the outputs The IDT23S08 is characterized for both Industrial and Commercial opera tion FUNCTIONAL BLOCK DIAGRAM 2 PLL CLKA1 CLKA2 a 14 CLKA3 15 CLKA4 8 S2 ntr s xe N 6 CLKB1 7 CLKB2 10 CLKB3 11 CLKB4 The IDT logo is a registered trademark of Integrated Device Technology Inc COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES OCTOBER 2003 2003 Integrated Device Technology Inc DSC 6394 8 IDT23S08 3 3V ZERO DELAY CLOCK MULTIPLIER PIN CONFIGURATION REF 1 16 FBK CLKA1 2 15 CLKA4 CLKA2 3 14 CLKA3 VDD 4 13 Voo GND 5 12 GND cLKB1 __ 11 _ CLKB4 CLKB2 7 10 CLKB3 S2 8 91 s SOIC TSSOP TOP VIEW PIN DESCRIPTION Pin number FunetonalDesoripton Coe 6 ooun O Ps e eomas se 9 eomas i Cas o coour O NOTES 1 Weak pull down 2 Weak pull down on all outputs 3 Weak pull ups on these inputs COMMERCIAL ANDINDUSTRI
9. z Load Capacitance from 100MHz to 133MHz CIN Input Capacitance NOTE 1 Applies to both REF and FBK DC ELECTRICAL CHARACTERISTICS COMMERCIAL VoL an Output LOW Voltage VOH Output HIGH Voltage lOH 8mA 1 2 3 4 lOH 12mA 1H 2H 5H Supply Current Unloaded Outputs Select Inputs at Vop orGND 66MHz CLKA 1H 2H 5H 33MHz CLKA 1 2 3 4 2 33MHz CLKA 1H 2H 5H IDT23S08 3 3V ZERO DELAY CLOCK MULTIPLIER COMMERCIAL ANDINDUSTRIAL TEMPERATURE RANGES SWITCHING CHARACTERISTICS COMMERCIAL Parameter Output Frequency Output Frequency Output Frequency Duty Cycle t2 t1 1 2 3 4 1H 2H 5H Duty Cycle t2 t1 1 2 3 4 1H 2H 5H 1 2 3 4 Rise Time 1 2 3 4 Rise Time 1H 2H 5H Fall Time 1 2 3 4 Fall Time 1 2 3 4 Fall Time 1H 5H Output to Output Skew on same Bank Rise Time 1 2 3 4 Output to Output Skew 1H 2H 5H Output Bank A to Output Bank B 1 4 2H 5H Output Bank A to Output Bank B Skew 2 3 REF Rising Edge to FBK Rising Edge Device to Device Skew Delay Output Slew Rate Cycle to Cycle Jitter 1 1H 4 5H Cycle to Cycle Jitter 2 2H 3 PLL Lock Time NOTE T Conditions 30pF Load all devices 20pF Load 1H 2H 5H Devices 15pF Load 1 2 3 4 devices Measured at 1 4V FouT 66 66MHz 30pF Load Measured at
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IDT IDT23S08 handbook