Home

ANALOG DEVICES ADN2819 handbook

1. 1 5 5 E 2 2 0 15 2 8 fo fa E JITTER FREQUENCY Hz 8 Figure 12 SONET Jitter Tolerance Mask 100 ADN2819 10 S a 2 E m a 2 1 OC 48 SONET MASK 0 1 1 10 100 1k 10k 100k 1M 10M 02999 B 013 MODULATION FREQUENCY Hz Figure 13 OC 48 Jitter Tolerance Curve Rev B Page 10 of 24 1k JIT TOLERANCE GBE JIT TOLERANCE OC3 JIT TRANSFER GBE JIT TRANSFER OC12 JIT TOLERANCE 8 JIT TOLERANCE OC12 JIT TRANSFER 8 JIT TRANSFER 10k 100k FREQUENCY Hz IM Figure 14 Jitter Transfer and Jitter Tracking BW Table 4 Jitter Transfer and Tolerance SONET Spec vs ADN2819 TOM 100M 02999 B 014 ADN2819 Rate Jitter Transfer Jitter Tolerance SONET Spec fc ADN2819 kHz Implementation Margin Mask Corner Frequency ADN2819 SONET Spec UI ADN2819 01 Implementation Margin OC 48 OC 12 OC 3 2MHz 500 kHz 130 kHz 590 140 48 34 3 6 2 7 1 MHz 250 kHz 65 kHz 4 8 MHz 4 8 MHz 600 kHz 0 15 0 15 0 15 1 0 1 0 1 0 6 67 6 67 6 67 jitter tolerance measurements limited by test equipment capabilities Rev B Page 11 of 24 ADN2819 THEORY OF OPERATION The ADN2819 is a delay locked and phase loc
2. 1000 ppm 60 mV POWER SUPPLY VOLTAGE 3 0 3 3 3 6 V POWER SUPPLY CURRENT 150 164 215 mA PHASE LOCKED LOOP CHARACTERISTICS PIN NIN 10 mV Jitter Transfer BW OC 48 590 880 kHz GbE 310 480 kHz OC 12 140 200 kHz OC 3 48 85 kHz Jitter Peaking OC 48 0 025 dB OC 12 0 004 dB OC 3 0 002 dB Jitter Generation OC 48 12 kHz 20 MHz 0 003 UI rms 0 05 0 09 Ulp p OC 12 12 kHz 5 MHz 0 002 UI rms 0 02 0 04 Ulp p OC 3 12 kHz 1 3 MHz 0 002 Ul rms 0 02 0 04 Ulp p Jitter Tolerance OC 48 See Figure 14 600 Hz 92 UI p p 6 kHz 20 UI 100 kHz 55 UI 1 MHz 1 0 UI GbE OC 24 See Figure 14 300 Hz 16 UI p p 3 kHz 16 UI 50 kHz 7 7 UI 500 kHz 22 Ul OC 12 See Figure 14 30 Hz 100 Ul p p 300 Hz 44 Ul p p 25 kHz 5 8 UI 250 kHz 1 0 Ul p p OC 3 See Figure 14 30 Hz 50 Ul p p 300 Hz 23 5 Ul p p 6500 Hz 6 0 Ul p p 65 kHz 1 0 UI CML OUTPUTS CLKOUTP N DATAOUTP N Single Ended Output Swing See Figure 7 300 455 600 mV Differential Output Swing Vorr See Figure 7 600 910 1200 mV Output High Voltage Von VCC V Output Low Voltage referred to VCC 0 60 0 30 V Rise Time 2096 8096 150 5 Fall Time 8096 2096 150 5 Rev B Page 4 of 24 ADN2819 Parameter Conditions Min Typ Max Unit Setup Time Ts See Figure 3 OC 48 140 ps GbE 350 ps OC 12 750 ps OC 3 3145 ps Hold Time See Figure 3 OC 48 150 ps GbE 350 ps OC 1
3. Configuration Table 3 Pin Function Descriptions Pin Number Mnemonic Type Description 1 THRADJ Al LOS Threshold Setting Resistor 2 26 28 Pad VCC P Analog Supply 3 9 16 19 22 27 VEE P Ground 29 33 34 42 43 46 4 VREF AO Internal VREF Voltage Decouple to GND with 0 1 uF capacitor 5 PIN Al Differential Data lh put 6 NIN i Differential Data Input 7 SLICEP Differ ntiaf Slice Level Adjust Input 8 SLICEN Al Differential Slice Level Adjust Input 10 LOL DO Loss of Lock Indicator LVTTL active high 11 XO1 AO Crystal Oscillator 12 XO2 AO Crystal Oscillator 13 REFCLKN DI Differential REFCLK Input LVTTL LVCMOS LVPECL LVDS LVPECL LVDS only at 155 52 MHz 14 REFCLKP DI Differential REFCLK Input LVTTL LVCMOS LVPECL LVDS LVPECL LVDS only at 155 52 MHz 15 REFSEL DI Reference Source Select 0 on chip oscillator with external crystal 1 external clock source LVTTL 17 TDINP Al Differential Test Data Input CML 18 TDINN Al Differential Test Data Input CML 20 47 VCC P Digital Supply 21 CF1 AO Frequency Loop Capacitor 23 REFSEL1 DI Reference Frequency Select See Table 6 LVTTL 24 REFSELO DI Reference Frequency Select See Table 6 LVTTL 25 CF2 AO Frequency Loop Capacitor 30 SEL2 DI Data Rate Select See Table 5 LVTTL 31 SEL1 DI Data Rate Select See Table 5 LVTTL 32 SELO DI Data Rate Select See Table 5 LVTTL 35 36 VCC P Output Driver Supply 37 DATAOUTN DO Differential Retimed Data Output
4. DIFFERENT DC LEVELS V2 AND V2b DISCHARGE TO THE Vger LEVEL WHICH EFFECTIVELY INTRODUCES A DIFFERENTIAL DC OFFSET ACROSS THE AC COUPLING CAPACITORS 3 WHEN THE BURST OF DATA STARTS AGAIN THE DIFFERENTIAL DC OFFSET ACROSS THE AC COUPLING CAPACITORS IS APPLIED TO THE INPUT LEVELS CAUSING A DC SHIFT IN THE DIFFERENTIAL INPUT THIS SHIFT IS LARGE ENOUGH SUCHTHAT ONE OFTHE STATES EITHER HIGH OR LOW DEPENDING ON THE LEVELS OF V1 AND V1b WHEN THE TIA WENT TO CID IS CANCELLED OUT THE QUANTIZER WILL NOT RECOGNIZE THIS AS A VALID STATE 4 THE DC OFFSET SLOWLY DISCHARGES UNTIL THE DIFFERENTIAL INPUT VOLTAGE EXCEEDS THE SENSITIVITY OFTHE ADN2819 THE QUANTIZER WILL BE ABLE TO RECOGNIZE BOTH HIGH AND LOW STATES ATTHIS POINT 02999 B 025 Figure 25 Example of Baseline Wander Rev B Page 19 of 24 ADN2819 DC COUPLED APPLICATION The inputs to the ADN2819 can also be dc coupled This may be necessary in burst mode applications where there are long periods of CIDs and baseline wander cannot be tolerated If the inputs to the ADN2819 are dc coupled care must be taken not to violate the input range and common mode level requirements of the ADN2819 see Figure 26 Figure 27 and Figure 28 If dc coupling is required and the output levels of the TIA do not adhere to the levels shown in Figure 27 and Figure 28 there needs to be level shifting and or an attenuator between the TIA outputs and the ADN2819 inputs LOL TOGGLING DURING LOSS OF INPUT
5. SEL 0 2 One Technology Way P O Box 9106 Norwood MA 02062 9106 U S A Tel 781 329 4700 www analog com Fax 781 326 8703 2004 Analog Devices Inc All rights reserved ADN2819 TABLE CONTENTS Specificatiorisc zi n ede be et e Absolute Maximum Ratings seen Thermal Characteristics seen ESD Caution ien E recientes Pin Configuration and Function Definition of Terms er eR ERES RH qs Maximum Minimum and Typical Specifications Input Sensitivity and Input Overdrive sss Single Ended vs Differential sss LOS Response Time seen 10 Jitter Specifications xo eet tme TREE 10 Theory of Operations pusse pon pune p e 12 Functional Description th e eee n 14 Multirate Clock and Data Recovery sss 14 REVISION HISTORY 5 04 Data Sheet Changed from Rev A to Rev B Updated Format Universal Changes to Specifications seen 3 Changes to Table 7 and Table 8 sss 15 Updated Outline Dimensions see 21 Changes to Ordering Guide es 21 1 03 Data Sheet Changed from Rev 0 to Rev A Changes to Table IV 12 Updated OUTLINE DIMENSIONS 16 Limiting Amplifier see
6. single ended probe A 5 mV signal appears to drive the ADN2819 quantizer However the single ended probe measures only half the signal The true quantizer input signal is twice this value since the other quantizer input is complementary to the signal being observed Rev B Page 9 of 24 ADN2819 LOS RESPONSE TIME The LOS response time is the delay between the removal of the input signal and indication of loss of signal LOS at SDOUT The ADN28195 response time is 300 ns typ when the inputs are dc coupled In practice the time constant of ac coupling at the quantizer input determines the LOS response time JITTER SPECIFICATIONS The ADN2819 CDR is designed to achieve the best bit error rate BER performance and has exceeded the jitter transfer generation and tolerance specifications proposed for SONET SDH equipment defined in the Telcordia Technologies specification Jitter is the dynamic displacement of digital signal edges from their long term average positions measured in UI unit intervals where 1 UI 1 bit period Jitter on the input data can cause dynamic phase errors on the recovered clock sampling edge Jitter on the recovered clock causes jitter on the retimed data The following sections summarize the specifications of the jitter generation transfer and tolerance in accordance with the Telcordia document GR 253 CORE Issue 3 September 2000 for the optical interface at the equipment level and the ADN2
7. 19 REFCLKP 100kO 100kO vec CRYSTAL OSCILLATOR vec i d4 REFSEL 2 02999 B 018 Figure 18 Single Ended REFCLK Configuration Rev B Page 14 of 24 NC REFCLKN 100kQ 100kQ CRYSTAL OSCILLATOR REFSEL Figure 19 Crystal Oscillator Configuration 2 19 44MHz CI 02999 B 019 The ADN2819 can accept any of the following reference clock frequencies 19 44 MHz 38 88 MHz and 77 76 MHz at LVTTL LVCMOS LVPECL LVDS levels or 155 52 MHz at LVPECL LVDS levels via the REFCLKN P inputs independent of data rate including Gigabit Ethernet and wrapper rates The input buffer accepts any differential signal with a peak to peak differential amplitude of greater than 100 mV e g LVPECL or LVDS or a standard single ended low voltage TTL input providing maximum system flexibility The appropriate division ratio can be selected using the REFSELO 1 pins according to Table 6 Phase noise and duty cycle of the reference not critical and 100 ppm Table 6 Reference Frequency Selection Applied Reference Frequency REFSEL REFSEL 1 0 MHz 1 00 19 44 1 01 38 88 1 10 77 76 1 11 155 52 0 XX REFCLKP N Inactive Use 19 44 MHz XTAL on Pins XO1 XO2 pull REFCLKP to VCC 1000 500 LOL ADN2819 An on chip oscillator to be used with an
8. 2 750 ps OC 3 3150 ps REFCLK DC INPUT CHARACTERISTICS Input Voltage Range REFCLKP or REFCLKN 0 VCC V Peak to Peak Differential Input 100 mV Common Mode Level DC coupled single ended VCC 2 V TEST DATA DC INPUT CHARACTERISTICS TDINP N CML inputs Peak to Peak Differential Input Voltage 0 8 V LVTTL DC INPUT CHARACTERISTICS Input High Voltage 2 0 V Input Low Voltage 0 8 V Input Current Vin 0 4 V or Vn 2 4 V 5 5 Input Current SELO SEL1 Only Vin 0 4 V or Vin 24 V 5 50 LVTTL DC OUTPUT CHARACTERISTICS Output High Voltage 2 0 mA 24 V Output Low Voltage lo 2 0 mA 0 4 V 1 PIN and NIN should be differentially driven ac coupled for optimum sensitivity PWD measurement made on quantizer outputs in bypass mode 3 Jitter tolerance measurements are equipment limited TDINP N are CML inputs If the drivers to the TDINP N inputs are anything other than CML they must be ac coupled 5 SELO and SEL 1 have internal pull down resistors causing higher Rev B Page 5 of 24 ADN2819 ABSOLUTE MAXIMUM RATINGS Table 2 THERMAL CHARACTERISTICS Parameter Rating Thermal Resistance PAPE 33N 48 lead LFCSP 4 layer board with exposed paddle soldered Minimum Input Voltage All Inputs VEE 0 4 V to VCC Maximum Input Voltage All Inputs VCC 0 4 V Maximum Junction Temperature 165 C 25 C W Storage Temperature 65 C to 150 C Lead Tempera
9. 5 C Capacitance gt 3 0 uF Leakage lt 80 nA Rating gt 6 3 V 500 1000 fyco ERROR 2 ppm 8 Figure 20 Transfer Function LOL Rev B Page 15 of 24 ADN2819 ADN2819 TDINP N LOOPEN BYPASS DATAOUTP N CDR FROM RETIMED QUANTIZER DATA OUTPUT 02999 B 021 CLKOUTP N SQUELCH Figure 21 Test Modes SQUELCH MODE When the squelch input is driven to a TTL high state the clock and data outputs are set to the zero state to suppress down stream processing If desired this pin can be directly driven by the LOS loss of signal detector output SDOUT If the squelch function is not required the pin should be tied to VEE TEST MODES BYPASS AND PRT EK When the bypass input is driven to TTE high state the quantizer output is connected directly to the buffers driving the data out pins thus bypassing the clock recovery circuit see Figure 21 This feature can help the system deal with nonstandard bit rates The loopback mode can be invoked by driving the LOOPEN pin to a TTL high state which facilitates system diagnostic testing This connects the test inputs TDINP N to the clock and data recovery circuit per Figure 21 The test inputs have internal 50 Q terminations and can be left floating when not in use TDINP N are CML inputs and can only be dc coupled when being driven byjCME outputs The TDINP N inputs must be driven by anything other than CML outputs Bypass and leopback medes ares
10. 50 transmission lines are required for all high frequency input and output signals to minimize reflections including PIN NIN CLKOUTP CLKOUTN DATAOUTP and DATAOUTN also REFCLKP N for a 155 52 MHz REFCLK It is also recommended that the PIN NIN input traces are matched in length and that the CLKOUTP N and DATAOUTP N traces are matched in length All high speed CML outputs CLKOUTP N and DATAOUTP N also require 100 back termination chip resistors connected between the output pin and VCC These resistors should be placed as close as possible to the output pins These 100 resistors are in parallel with on chip 100 Q termination resistors to create a 50 Q back termination see Figure 23 The high speed inputs PIN and NIN are internally terminated with 50 to an internal reference voltage see Figure 24 0 1 capacitor is recommended between Pin 4 and GND to provide an ac ground for the inputs As with any high speed mixed signal design take care to keep all high speed digital traces away from sensitive analog nodes Soldering Guidelines for Chip Scale Package The lands on the 48 lead LFCSP are rectangular The printed circuit board pad for these should be 0 1 mm longer than the package land length and 0 05 mm wider than the package land width The land should be centered on the pad This ensures that the solder joint size is maximized The bottom of the chip scale package has a central exposed pad The pad o
11. 819 performance with respect to those specifications Jitter Generation Jitter generation specification limits the amount of jitter that can be generated by the device with no jitter and wander applied at the input For OC 48 devices the band pass filter has a 12 kHz high pass cutoff frequency with a roll off of 20 dB decade and a low pass cutoff frequency of at least 20 MHz The jitter generated should be less than 0 01 UI rms and 0 1 UI p p Jitter Transfer Jitter transfer function is the ratio of the jitter on the output signal to the jitter applied on the input signal versus the frequency This parameter measures the limited amount of jitter on an input signal that can be transferred to the output signal see Figure 11 0 1 T SLOPE 20dB DECADE E fc 3 JITTER FREQUENCY kHz 8 Figure 11 Jitter Transfer Curve Jitter Tolerance Jitter tolerance is defined as the peak to peak amplitude of the sinusoidal jitter applied on the input signal that causes a 1 dB power penalty This is a stress test that is intended to ensure no additional penalty is incurred under the operating conditions see Figure 12 Figure 13 shows the typical OC 48 jitter tolerance performance of the ADN2819 5 15 8 gt SLOPE 20dB DECADE n z
12. ANALOG Multirate to 2 7 Gb s Clock and Data DEVICES Recovery IC with Integrated Limiting Amp ADN2819 FEATURES Meets SONET requirements for jitter transfer generation tolerance Quantizer sensitivity 4 mV typical Adjustable slice level 100 mV 1 9 GHz minimum bandwidth Patented clock recovery architecture Loss of signal detect range 3 mV to 15 mV Single reference clock frequency for all rates including 15 14 796 wrapper rate Choice of 19 44 MHz 38 88 MHz 77 76 MHz or 155 52 MHz REFCLK LVPECL LVDS LVCMOS LVTTL compatible inputs LVPECL LVDS only at 155 52 MHz 19 44 MHz oscillator on chip to be used with external crystal Loss of lock indicator Loopback mode for high speed test data Output squelch and bypass features Single supply operation 3 3 V Low power 540 mW typical 7 mm x 7 mm 48 lead LFCSP APPLICATIONS TAY SONET OC 3 12 48 SDH STM 1 4 169GbE 15 14 FEC rates WDM transponders Regenerators repeaters Test equipment Backplane applications PRODUCT DESCRIPTION The ADN2819 provides the receiver functions of quantization signal level detect and clock and data recovery at rates of OC 3 OC 12 OC 48 Gigabit Ethernet and 15 14 FEC rates SONET jitter requirements are met including jitter transfer jitter generation and jitter tolerance All specifications are quoted for 40 C to 85 C ambient temperature unless otherwise noted The device is intended for WDM system appl
13. B 027 Figure 27 Minimum Allowed DC Coupled Input Levels INPUT V V PIN NIN 2 x 2 4V MAX DC COUPLED 02999 B 028 Figure 28 Maximum Allowed DC Coupled Input Levels Rev B Page 20 of 24 OUTLINE DIMENSIONS 1 00 0 85 0 80 12 MAX je 0 65 TYP 1 INDICATOR EXPOSED PAD BOTTOM VIEW 0 80 MAX 0 05 MAX v 0 02 NOM 0 50 BSC COPLANARITY 0 20 REF 0 08 COMPLIANT TO JEDEC STANDARDS MO 220 VKKD 2 Figure 29 48 Lead Lead Frame Chip Scale Package LFCSP 7mm x 7 mm Body CP 48 Dimensions shown in millimeters ADN2819 ORDERING GUIDE d Model Temperature Range Package Description Package Option ADN2819ACP CML 40 c to 85 C 48 Lead LFCSP CP 48 ADN2819ACP CML RL 40 C to 85 C 48 Lead LFCSP CP 48 ADN2819ACPZ CML 40 C to 85 C 48 Lead LFCSP CP 48 ADN2819ACPZ CML RL 40 C 85 C 48 Lead LFCSP CP 48 EVAL ADN2819 CML Evaluation Board 17 Free Rev B 21 of 24 ADN2819 NOTES waw BDTI C com AD ADN2819 NOTES waw BDTI C com AD ADN2819 NOTES 2004 Analog Devices Inc All rights reserved Trademarks and ANALOG registered trademarks are the property of their respective owners WWW ana 0 9 com Lai DEVICES Rev B Page 24 of 24
14. CML 38 DATAOUTP DO Differential Retimed Data Output CML 39 SQUELCH DI Disable Clock and Data Outputs Active high LVTTL 40 CLKOUTN DO Differential Recovered Clock Output CML 41 CLKOUTP DO Differential Recovered Clock Output CML 44 BYPASS DI Bypass CDR Mode Active high LVTTL 45 SDOUT DO Loss of Signal Detect Output Active high LVTTL 48 LOOPEN DI Enable Test Data Inputs Active high LVTTL Type P Power Analog Input AO Analog Output DI Digital Input DO Digital Output Rev B Page 7 of 24 ADN2819 CLKOUTP DATAOUTP N 02999 B 003 Figure 3 Output Timing THRADJ RESISTOR VS LOS TRIP POINT 02999 B 004 RESISTANCE Figure 4 LOS Comparator Trip Point Programming FREQUENCY FREQUENCY 0 1 2 3 4 5 6 7 8 9 410 HYSTERESIS dB HYSTERESIS dB 02999 B 005 Figure 5 LOS Hysteresis OC 3 40 C 3 6 V Figure 6 LOS Hysteresis OC 12 40 3 6 V 223 1 PRBS Input Pattern Rr 90 223 1 PRBS Input Pattern Rr 90 OUTP OUTN OUTP OUTN ov 02999 B 007 Figure 7 Single Ended vs Differential Output Specifications Rev B Page 8 of 24 02999 B 006 DEFINITION OF TERMS MAXIMUM MINIMUM AND TYPICAL SPECIFICATIONS Specifications for every par
15. DATA If the input data stream is lost due to a break in the optical link for any reason the clock output from the ADN2819 will stay within 1000 ppm of the VCO center frequency as long as there is a valid reference clock The LOL pin toggles at a rate of several kHz because the LOL pin toggles between a Logic 1 and a Logic 0 while the frequency loop and phase loop swap control of the VCO The chain of events is as follows e The ADN2819 is locked to the input data stream LOL 0 e The input data stream is lost due to a break in the link The VCO frequency drifts until the frequency error is greater than 1000 ppm LOL is asserted to a Logic as controlof the VCO is passed back to the tib quehcy loop The frequency loop pulls the VCO to within 500 ppm of its center frequency Control of the VCO is passed back to the phase loop and LOL is deasserted to a Logic 0 e The phase loop tries to acquire but there is no input data present so the VCO frequency drifts e The VCO frequency drifts until the frequency error is greater than 1000 ppm LOL is asserted to a Logic 1 as control of the VCO is passed back to the frequency loop This process is repeated until a valid input data stream is re established ADN2819 02999 B 026 Figure 26 ADN2819 with DC Coupled Inputs INPUT V V PIN NIN 2 x 10mV AT SENSITIVITY Vse 5mV MIN _ Vep 04V MIN DC COUPLED 02999
16. ain SLICEP SLICEN 0 5 V 0 11 0 20 0 30 V V Control Voltage Range SLICEP SLICEN 0 8 40 8 V SLICEP SLICEN 1 3 V Slice Threshold Offset 21 0 mV LEVEL SIGNAL DETECT SDOUT Level Detect Range See Figure 4 20 94 13 3 18 0 mV 20 25 5 3 7 6 mV 90 0 7 3 0 5 2 mV Response Time DC coupled 0 1 0 3 5 us Hysteresis Electrical OC 48 PRBS 223 Rrunesa 2 5 6 6 6 7 8 dB Rrunesa 20 3 9 6 2 8 5 dB 90 3 2 6 7 9 9 OC 12 PRBS 223 2 4 7 6 4 7 8 dB Rrunesa 20 1 8 6 0 10 0 dB 90 6 3 dB 90 25 C 4 8 6 9 8 9 dB OC 3 PRBS 223 2 3 6 6 2 8 5 dB 20 5 6 dB 90 5 6 dB 90 25 C 34 6 6 9 9 dB OC 48 PRBS 27 Rrunesa 2 5 6 6 6 7 8 dB Rrunesa 20 3 9 6 2 8 5 dB lt 90 32 6 7 9 9 dB OC 12 PRBS 27 2 5 7 6 6 7 8 dB lt 20 3 9 6 2 8 5 dB 90 32 6 7 9 9 dB Rev B Page 3 of 24 ADN2819 Parameter Conditions Min Typ Max Unit Hysteresis Electrical continued OC 3 PRBS 27 2 54 6 6 77 dB Rrunesa 20 4 6 6 4 8 2 90 3 9 6 8 9 7 dB LOSS OF LOCK DETECTOR LOL Loss of Lock Response Time From fvco error gt
17. ameter are derived from statistical analyses of data taken on multiple devices from multiple wafer lots Typical specifications are the mean of the distribution of the data for that parameter If a parameter has a maximum or a minimum that value is calculated by adding to or subtracting from the mean six times the standard deviation of the distribution This procedure is intended to tolerate production variations If the mean shifts by 1 5 standard deviations the remaining 4 5 standard deviations still provide a failure rate of only 3 4 parts per million For all tested parameters the test limits are guardbanded to account for tester variation and therefore guarantee that no device is shipped outside of data sheet specifications INPUT SENSITIVITY AND INPUT OVERDRIVE Sensitivity and overdrive specifications for the quantizer involve offset voltage gain and noise The relationship between the logic output of the quantizer and the analog voltage input is shown in Figure 8 For a sufficiently large positive input voltage the output is always Logic 1 similarly for negative inputs the output is always Logic 0 However the transitions between output Logic Levels 1 and 0 areumot at pxegisely definedjinput voltage levels but occur over a y TU input voltages Within this zone of confusion the output may be either 1 or 0 or it may even fail to attain a valid logic state The width of this zone is determined by the input voltage noise of the qu
18. antizer The center of the zone of confusion is the quantizer input offset voltage Input overdrive is the magnitude of signal required to guarantee the correct logic level with 1 x 10 confidence level OUTPUT 1 NOISE gt OFFSET gt INPUT V p p OVERDRIVE I4 SENSITIVITY ay 2x OVERDRIVE 02999 B 008 Figure 8 Input Sensitivity and Input Overdrive ADN2819 SINGLE ENDED VS DIFFERENTIAL AC coupling is typically used to drive the inputs to the quantizer The inputs are internally dc biased to a common mode potential of 0 6 V Driving the ADN2819 single ended and observing the quantizer input with an oscilloscope probe at the point indicated in Figure 9 shows a binary signal with an average value equal to the common mode potential and instantaneous values above and below the average value It is convenient to measure the peak to peak amplitude of this signal and to call the minimum required value the quantizer sensitivity Referring to Figure 8 since both positive and negative offsets need to be accommodated the sensitivity is twice the overdrive ADN2819 02999 B 009 Figure 9 Single Ended Sensitivity Measurement 5mV 02999 B 010 Figure 10 Differential Sensitivity Measurement Driving the ADN2819 differentially see Figure 10 sensitivity seems to improve by observing the quantizer input with an oscilloscope probe This is an illusion caused by the use of a
19. at the various data rates The delay locked and phase locked loops contribute to overall jitter AtAow frequencies of input jitter on the data signalthe integrator in the loop filter provides high gain to track large jitter amplitudes with small phase error In this case the VCO is frequency modulated and jitter is tracked as in an ordinary phase locked loop The amount of low frequency jitter that can be tracked is a function of the VCO tuning range A wider tuning range gives larger accommodation of low frequency jitter The internal loop control voltage remains small for small phase errors so the phase shifter remains close to the center of its range and therefore contributes little to the low frequency jitter accommodation At medium jitter frequencies the gain and tuning range of the VCO are not large enough to track the input jitter In this case the VCO control voltage becomes large and saturates and the VCO frequency dwells at one or the other extreme of its tuning range The size of the VCO tuning range therefore has only a small effect on the jitter accommodation The delay locked loop control voltage is now larger thus the phase shifter takes on the burden of tracking the input jitter The phase shifter range in UI can be seen as a broad plateau on the jitter tolerance curve The phase shifter has a minimum range of 2 UI at all data rates Rev B Page 12 of 24 The gain of the loop integrator is smal
20. external crystal is also provided as an alternative to using the REFCLKN P inputs Details of the recommended crystal are given in Table 7 Table 7 Required Crystal Specifications Parameter Value Mode Series Resonant Frequency Overall Stability 19 44 MHz 100 ppm Frequency Accuracy 100 ppm Temperature Stability 100 ppm Aging 100 ppm ESR 50 O max REFSEL must be tied to VCC when the REFCLKN P inputs are active or tied to VEE when the oscillator is used No connection between the XO pin and the REFCLK input is necessary see Figure 17 Figure 18 and Figure 19 Note that the crystal should operate in series resonant mode which renders it insensitive to external parasitics No trimming capacitors are required LOCK DETECTOR OPERATION The lock detector monitors the frequency difference between the VCO and the reference clock and deasserts the loss of lock signal when the VCO is within 500 ppm of center frequency This enables the phase loop which then maintains phase lock unless the frequency error exceeds 0 196 Should this occur the loss of lock signal is reasserted and control returns to the fre quen y loop Whith all feacquire and maintain a stable clock signal atthe output The fr quency loop requires a single exter nal capacitor between CF1 and CF2 The capacitor specification is given in Table 8 Table 8 Recommended Cr Capacitor Specification Parameter Value Temperature Range 40 C to 8
21. ications and can be used with either an external reference clock or an on chip oscillator with external crystal Both native rates and 15 14 rate digital wrappers are supported by the ADN2819 without any change of reference clock This device together with a PIN diode and a TIA preamplifier can implement a highly integrated low cost low power fiber optic receiver The receiver front end signal detect circuit indicates when the input signal level has fallen below a user adjustable threshold The signal detect has to prevent chatter at the Qutput The ADN2819 is available in a compact 7 mm x 7 mm 48 lead chip scale package FUNCTIONAL BLOCK DIAGRAM SLICEP N 1 LOOP FILTER PIN REFCLKP N FREQUENCY ig LOCK 1 NIN DETECTOR XTAL 4 F Ed FRACTIONAL VREF DIVIDER DATAOUTP N CLKOUTP N Rev B Information furnished by Analog Devices is believed to be accurate and reliable However no responsibility is assumed by Analog Devices for its use nor for any infringements of patents or other rights of third parties that may result from its use Specifications subject to change without notice No license is granted by implication or otherwise under any patent or patent rights of Analog Devices Trademarks and registered trademarks are the property of their respective owners DIVIDER DATA RETIMING 1214116 Figure 1 02999 0 001
22. ion Circuit vce vec vec ADN2819 VTERM 1000 5 10005 0 4nF 500 500 500 500 ADN2819 VERM Figure 23 AC Coupled Output Configuration 02999 B 023 Figure 24 AC Coupled Input Configuration Rev B Page 18 of 24 02999 B 022 02999 B 024 CHOOSING AC COUPLING CAPACITORS The choice of ac coupling capacitors at the input PIN NIN and output DATAOUTP DATAOUTN of the ADN2819 must be chosen such that the device works properly at the lower OC 3 and higher OC 48 data rates When choosing the capacitors the time constant formed with the two 50 Q resistors in the signal path must be considered When a large number of consecutive identical digits CIDs are applied the capacitor voltage can drop due to baseline wander see Figure 23 causing pattern dependent jitter PDJ 1 Cin E A Vib Cin V2 V2b VTH ADN2819 QUANTIZER THRESHOLD NOTES ADN2819 ADN2819 For the ADN2819 to work robustly at both OC 3 and OC 48 minimum capacitor of 1 6 uF to PIN NIN and 0 1 uF on DATAOUTP DATAOUTN should be used This is based on the assumption that 1000 CIDs must be tolerated and that the PDJ should be limited to 0 01 UI p p Cour DaTAouTP Cour DATAOUTN VREF VTH 1 DURING DATA PATTERNS WITH HIGH TRANSITION DENSITY DIFFERENTIAL DC VOLTAGE AT V1 AND V2 IS 0 2 WHEN THE OUTPUT OF THE GOES TO CID V1 AND V1b ARE DRIVEN TO
23. ked loop circuit for clock recovery and data retiming from an NRZ encoded data stream The phase of the input data signal is tracked by two separate feedback loops that share a common control voltage A high speed delay locked loop path uses a voltage controlled phase shifter to track the high frequency components of the input jitter A separate phase control loop comprised of the VCO tracks the low frequency components of the input jitter The initial frequency of the VCO is set by a third loop that compares the VCO frequency with the reference frequency and sets the coarse tuning voltage The jitter tracking phase locked loop controls the VCO by the fine tuning control The delay and phase locked loops together track the phase of the input data signal For example when the clock lags input data the phase detector drives the VCO to a higher frequency and increases the delay through the phase shifter Both of these actions serve to reduce the phase error between the clock and data The faster clock picks up phase while the delayed data loses phase Since the loop filter is an integrator the static phase error is driven to zero Another view of the circuit is that the phase shifter implements the zero required for the frequency compensation of a second order phase locked loop This zerousplagedfin ithe feedback path and therefore does not appear transfer function Jitter peaking in a conventional second order phase locked l
24. l for high jitter frequencies so larger phase differences are needed to make the loop control voltage big enough to tune the range of the phase shifter Large phase errors at high jitter frequencies cannot be tolerated In this region the gain of the integrator determines the jitter accommodation Since the gain of the loop integrator declines linearly with frequency jitter accommodation is lower with higher jitter frequency At the highest frequencies the loop gain is very small and little tuning of the phase shifter can be expected In this case jitter accommodation is determined by the eye opening of the input data the static phase error and the residual loop jitter generation The jitter accommodation is roughly 0 5 UI in this region The corner frequency between the declining slope and the flat region is the closed loop bandwidth of the delay locked loop which is roughly 5 MHz for OC 12 OC 48 and GbE data rates and 600 kHz for OC 3 data rates Rev B Page 13 of 24 ADN2819 JITTER PEAKING y IN ORDINARY PLL JITTER yrs ADN2819 Z s X s d psh n psh 8 016 f kHz 02999 Figure 16 Jitter Response vs Conventional PLL ADN2819 FUNCTIONAL DESCRIPTION MULTIRATE CLOCK AND DATA RECOVERY The ADN2819 will recover clock and data from serial bit streams at OC 3 OC 12 OC 48 and GbE data rates as well as the 15 14 FEC rates The output of the 2 5 GHz VCO is divided down in order to suppo
25. n 14 Slice AdjUst coitu oT ERREUR ERE 14 Loss of Signal LOS Detector sss 14 Reference Clock aie nO 14 Lock Detector Operation sse 15 Sq elch Mode cr Sen em 16 Test Modes Bypass and Loopback sss 16 Applications Information 17 PCB Design Guidelines see 17 Choosing AC Coupling Capacitors eee 19 DC Coupled Application seen 20 LOL Toggling During Loss of Input 20 Outline Dimensions esent 21 Ordering Guide sees eret eR 21 Rev B Page 2 of 24 SPECIFICATIONS Table 1 Tmn to Tmax VCC Vmn to Vmax VEE 0 Cr 4 7 uF SLICEP SLICEN VCC unless otherwise noted ADN2819 Parameter Conditions Min Typ Max Unit QUANTIZER DC CHARACTERISTICS Input Voltage Range PIN or NIN dc coupled 0 12 V Peak to Peak Differential Input 24 V Input Common Mode Level DC coupled See Figure 28 0 4 V Differential Input Sensitivity PIN NIN ac coupled BER 1 x 10779 4 10 mV p p Input Overdrive See Figure 8 2 5 mV Input Offset 500 uV Input rms Noise BER 1 x 10779 244 uV rms QUANTIZER AC CHARACTERISTICS Upper 3 dB Bandwidth 1 9 GHz Small Signal Gain Differential 54 dB 511 2 5 GHz 15 dB Input Resistance Differential 100 Q Input Capacitance 0 65 pF Pulse Width Distortion 10 ps QUANTIZER SLICE ADJUSTMENT G
26. n the printed circuit board should be at least as large as this exposed pad The user must connect the exposed pad to analog VCC If vias are used they should be incorporated into the pad at 1 2 mm pitch grid The via diameter should be between 0 3 mm and 0 33 mm the via barrel should be plated with 1 oz copper to plug the via Rev B Page 17 of 24 ADN2819 vcc 500 4 x 1000 TRANSMISSION LINES CLKOUTP vec uc 0 CLKOUTN 10uF DATAOUTP i 6 DATAOUTN xz amp 2 2 EF E OJ 2 2 gt gt 4101 0 Q 2 lt ojoj lt Of X X SJE ke gt S 3 01 lt a gt a a gt gt O a ee a 48 47 46 45 44 43 42 41 40 39 38 37 RTH THRADJ vec 1 vec 2 as vec 0 1uF 1nF vee 1nF 0 1uF X A V 0 1uF VREF 4 VEE 500 FR EXPOSED PAD SEED 0 5 TIED OFFTO 32 V NIN VCC PLANE SEL1 0 SLICER 6 WITH VIAS 31 uc 500 Cin 7 50 SLICEN VEE VCC 8 29 VEE 9 28 V LoL VEE 1nF 0 1uF uC 27 VCC 19 44MHz CI 2 ADN2819 CF2 13 14 15 16 17 18 19 20 21 22 23 24 4 7uF 2 SEETABLE 8 FOR SPECS epa 2 lt 2 gt 575 gt uu a On a a H re ALE 74 2 64 20 7 2 2 V gt vcc T por Figure 22 Typical Applicat
27. nutually exclusive only one of these modes can be used at any given time The ADN2819 is put into an indeterminate state if both the BYPASS and LOOPEN pins are set to Logic 1 at the same time Rev B Page 16 of 24 ADN2819 APPLICATIONS INFORMATION PCB DESIGN GUIDELINES Proper RF PCB design techniques must be used for optimal performance Power Supply Connections and Ground Planes Use of one low impedance ground plane to both analog and digital grounds is recommended The VEE pins should be soldered directly to the ground plane to reduce series inductance If the ground plane is an internal plane and connections to the ground plane are made through vias multiple vias may be used in parallel to reduce the series inductance especially on Pins 33 and 34 which are the ground returns for the output buffers Use of a 10 electrolytic capacitor between and GND is recommended at the location where the 3 3 V supply enters the PCB Use of 0 1 uF and 1 nF ceramic chip capacitors should be placed between IC power supply VCC and GND as close as possible to the ADN2819 VCC pins Again if connections to the supply and ground are made through vias the use of multiple vias in parallel will help to reduce series inductance especially on Pins 35 and 36 which supply power to the high speed CLKOUTP N and DATAOUTP N output buffers Refer to the schematic in Figure 22 for recommended connections Transmission Lines Use of
28. oop is caused by the presence of this zero in the closed loop transfer function Since this circuit has no zero in the closed loop transfer jitter peaking is minimized The delay and phase locked loops together simultaneously provide wideband jitter accommodation and narrow band jitter filtering The linearized block diagram in Figure 15 shows that the jitter transfer function Z s X s is a second order low pass providing excellent filtering Note that the jitter transfer has no zero unlike an ordinary second order phase locked loop This means the main PLL loop has low jitter peaking see Figure 16 which makes this circuit ideal for signal regenerator applica tions where jitter peaking in a cascade of regenerators can contribute to hazardous jitter accumulation RECOVERED CLOCK d PHASE DETECTOR GAIN JITTER TRANSFER FUNCTION o VCO GAIN 28 i LOOP INTEGRATOR psh PHASE SHIFTER GAIN X s pen n DIVIDE RATIO TRACKING ERROR TRANSFER FUNCTION 5 _ 52 X s s d psh 02999 8 015 52 Figure 15 PLL DLL Architecture The error transfer e s X s has the same high pass form as an ordinary phase locked loop This transfer function is free to be optimized to give excellent wideband jitter accommodation since the jitter transfer function Z s X s provides the narrow band jitter filtering See Table 4 for error transfer bandwidths and jitter transfer bandwidths
29. rt the lower data rates The data rate is selected by the SEL 2 0 inputs see Table 5 Table 5 Data Rate Selection SEL 2 0 Rate Frequency MHz 000 OC 48 2488 32 001 GbE 1250 00 010 OC 12 622 08 011 OC 3 155 52 100 OC 48 FEC 2666 06 101 GbE FEC 1339 29 110 OC 12 FEC 666 51 111 OC 3 FEC 166 63 LIMITING AMPLIFIER The limiting amplifier has differential inputs PIN NIN that are internally terminated with 50 to an on chip voltage reference VREF 0 6 V typically These inputs are normally ac coupled although dc coupling is possible as long as theinput common mode voltage remains jabovye see Figute 26 Figure 27 and Figure 28 in the Applications Information section Input offset is factory trimmed to achieve better than 4 mV typical sensitivity with minimal drift The limiting amplifier can be driven differentially or single ended SLICE ADJUST The quantizer slicing level can be offset by 100 mV to mitigate the effect of amplified spontaneous emission ASE noise by applying a differential voltage input of 0 8 V to SLICEP N inputs If no adjustment of the slice level is needed SLICEP N should be tied to VCC LOSS OF SIGNAL LOS DETECTOR The receiver front end level signal detect circuit indicates when the input signal level has fallen below a user adjustable threshold The threshold is set with a single external resistor from Pin 1 THRADJ to GND The LOS comparator trip point versu
30. s the resistor value is illustrated in Figure 4 this is only valid for SLICEP SLICEN VCC If the input level to the ADN2819 drops below the programmed LOS threshold SDOUT Pin 45 will indicate the loss of signal condition with a Logic 1 The LOS response time is 300 ns by design but it is dominated by the RC time constant in ac coupled applications If the LOS detector is used the quantizer slice adjust pins must both be tied to VCC This is to avoid interaction with the LOS threshold level Note that it is not expected to use both LOS and slice adjust at the same time Systems with optical amplifiers need the slice adjust to evade ASE However a loss of signal in an optical link that uses optical amplifiers causes the optical amplifier output to be full scale noise Under this condition the LOS would not detect the failure In this case the loss of lock signal indicates the failure because the CDR circuitry is unable to lock onto a signal that is full scale noise REFERENCE CLOCK There are three options for providing the reference frequency to the ADN2819 differential clock single ended clock or crystal oscillator See Figure 17 Figure 18 and Figure 19 for example configurations 1 ADN2819 REFCLKP 100kQ 100kO REFCLKN 1 2 deeem X02 ISCILLATOR I VCC 4REFSEL 02999 B 017 Figure 17 Differential REFCLK Configuration vec ADN28
31. ture Soldering 10 sec 300 C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device This is a stress rating only functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied Exposure to absolute maximum rating conditions for extended periods may affect device reliability ESD CAUTION ESD electrostatic discharge sensitive device Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection Although this product features WARNING S proprietary ESD protection circuitry permanent damage may occur on devices subjected to high energy electrostatic discharges Therefore proper ESD precautionsaresecommended to avoid performance degradation or loss of functionality ESD SENSITIVE DEVICE Rev B Page 6 of 24 PIN CONFIGURATION AND FUNCTION DESCRIPTI ADN2819 ce NS az 2 o FEFODQD E 55200 amp 5 lt 4 g9uggulloopaa fos sb sb THRADJ 1 i 36 VCC vcc 2 INDICATOR 35VCC VEE 3 34VEE VREF 4 33VEE PIN 5 32 SELO NIN 6 ADN2819 31SEL1 SLICEP 7 30 SEL2 SLICEN 8 TOPVIEW 29VEE VEE 9 28VCC LOL 10 27 XO1 11 26 VCC 12 25 2 383525398888 90 FF gre ec E Figure 2 48 Lead LFCSP Pin

ANALOG DEVICES ADN2819 handbook

Contents

Download Pdf Manuals

Related Search

Related Contents