texas instruments THS14F01 THS14F03 14-BIT 1 MSPS/ 3 MSPS DSP COMPATIBLE ANALOG-TO-DIGITAL CONVERTERS WITH FIFO INTERNAL REFERENCE AND PGA Manual
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1. REF 10kQ 400 pr Ny THS14F01 3 IN REF 10 ko 10 ko 1 Figure 18 Single Ended With Level Shift The following table shows the input voltages for negative full scale output zero output and positive full scale output AIN V OUTPUT AREF full scale 0 0 AREF full scale Note that the resistors of the op amp and the op amp all introduce gain and offset errors Those errors can be trimmed by varying the values of the resistors Because of the added offset the op amp does not necessarily operate in the best region of its transfer curve best linearity around zero and therefore may introduce unacceptable distortion For ac signals an alternative is described in the following section 5 TEXAS INSTRUMENTS POST OFFICE BOX 655303 DALLAS TEXAS 75265 19 THS14F01 THS14F03 14 BIT 1 MSPS 3 MSPS DSP COMPATIBLE ANALOG TO DIGITAL CONVERTERS WITH FIFO INTERNAL REFERENCE AND PGA SLAS285 JUNE 2000 APPLICATION INFORMATION ac coupled single ended configuration 20 N 10 ko 10 ko If the application does not require the signal bandwidth to include dc the level shift shown in Figure 4 is not necessary 10 10 ko IN REF THS14F01 3 IN REF Figure 19 Single Ended With Level Shift IN VPEAK Because the signal swing on the op amp2. 30 31 42 Digital power supply D 13 0 11 12 13 16 17 18 19 21 22 23 24 27 28 29 ug Ea EN p E y o Data inputs outputs per 0 serere up Tis pinreaieratrgFempasbriEARN vag 2 1 Reference input This pin requires a Em absolute maximum ratings over operating free air temperature unless otherwise noted t FOVL Avon Ne m INT REF Supply voltage AVpp to AGND ttt a a teens 4V Supply voltage DVpp to cee ene eens 4V Reference input voltage range 6 0 3 V to AVpp 0 3 V Analog input voltage range 0 8 V to AVpp 0 3 V Digital input voltage range ssssssssesee III 0 3 V to DVpp 0 3 V Operating free air temperature range Ta C suffix 0 C to 70 C ISOME 40 to 85 Storage temperature range Tstg seep sema vex ex exe pee rra d o b d hh 65 to 150 C Lead temperature 1 6 mm 1 16 inch from case for 10 seconds 260 C t Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device These are stress ratings only and functional operation of the device at these or any other condition
3. out of range indication The OV output of the ADC indicates an out of range condition Every time the difference on the analog inputs exceeds the differential reference this signal is asserted This signal is updated the same way as the digital data outputs and therefore subject to the same pipeline delay offset compensation With the offset register it is possible to automatically compensate system offset errors including errors caused by additional signal conditioning circuitry If the offset compensation is enabled D7 OFF in the control register the value in the offset register address 2 is automatically subtracted from the output of the ADC In order to set the correct value of the offset compensation register the ADC result when the input signal is 0 must be read by the host processor and written to the offset register address 2 test modes The ADC core operation can be tested by selecting one of the available test modes see control register description The test modes apply various voltages to the differential input depending on the setting in the control register digital 1 0 The digital inputs and outputs of the THS14F01 3 ADC are 3 V CMOS compatible In order to avoid current feed back errors the capacitive load on the digital outputs should be as low as possible 50 pF max Series resistors 100 on the digital outputs can improve the performance by limiting the current during output transitions The parallel i
4. tw CLK tw CLK il Pf J Ff etd 10 Figure 1 Sample Timing INT goes active if the programmed FIFO level is reached INT is either low or high active depending on the polarity bit IP within the control word This signal is set synchronously to the CLK signal It is reset by a read access to the FIFO once the number of samples in the FIFO is below the programmed threshold level 35 TEXAS INSTRUMENTS 6 POST OFFICE BOX 655303 9 DALLAS TEXAS 75265 THS14F01 THS14F03 14 BIT 1 MSPS 3 MSPS DSP COMPATIBLE ANALOG TO DIGITAL CONVERTERS WITH FIFO INTERNAL REFERENCE AND PGA SLAS285 JUNE 2000 PARAMETER MEASUREMENT INFORMATION The parallel interface of the THS14F01 3 ADC features 3 state buffers making it possible to directly connect it to a data bus The output buffers are enabled by driving the OE input low Besides the sample results it is also possible to read back the values of the control register the PGA register and the control register Which register is read is determined by the address inputs A 1 0 The ADC results are available at address 0 The timing of the control signals is described in the following sections The FIFO can be disabled by setting FC to 0 FIFO reset default at power on This makes it possible to access the device synchronously In this case the data is updated on every clock cycle S11 S12 59 _ Input tw
5. 14 BIT 1 MSPS 3 MSPS DSP COMPATIBLE ANALOG TO DIGITAL CONVERTERS WITH FIFO INTERNAL REFERENCE AND PGA SLAS285 JUNE 2000 TYPICAL CHARACTERISTICS DIFFERENTIAL NONLINEARITY 1 N 08 gt 0 6 2 04 5 02 z 0 S 02 5 E Lala da s TETN 0 4 0 6 B ____ __ __ _ _____ 1 5 0 2048 4096 6144 8192 10240 12288 14336 16384 Samples Figure 11 DIFFERENTIAL NONLINEARITY 0 1 0 8 E gs dal I 7 ro pum rnm opp rre Tome m mp am qe no men tin 02 2 0 02 9 0 4 2 06 0 8 1 5 0 2048 4096 6144 8192 10240 12288 14336 16384 Samples Figure 12 35 TEXAS INSTRUMENTS POST OFFICE BOX 655303 9 DALLAS TEXAS 75265 THD Total Harmonic Distortion dB TYPICAL CHARACTERISTICS TOTAL HARMONIC DISTORTION vs FREQUENCY 15 3 MSPS fj at 1 dB SNR Signal to Noise Ratio dB 10 100 1000 1500 f Frequency Hz Figure 13 35 TEXAS THS14F01 THS14F03 14 BIT 1 MSPS 3 MSPS DSP COMPATIBLE ANALOG TO DIGITAL CONVERTERS WITH FIFO INTERNAL REFERENCE AND PGA SLAS285 JUNE 2000 SIGNAL TO NOISE RATIO 15 3 MSPS fj at 1 dB vs FREQUENCY INSTRUMENTS POST OFFICE BOX 655303 DALLAS TEXAS 75265 100 1000 1500 f Frequency Hz Figure 14 THS14F01
6. 4 POST OFFICE BOX 655303 9 DALLAS TEXAS 75265 THS14F01 THS14F03 14 BIT 1 MSPS 3 MSPS DSP COMPATIBLE ANALOG TO DIGITAL CONVERTERS WITH FIFO INTERNAL REFERENCE AND PGA SLAS285 JUNE 2000 electrical characteristics continued PARAMETER TEST CONDITIONS MIN TYP UNIT Reference Voltage Bandgap voltage internal mode 1 425 1 5 1 575 V y 0 5 Positive reference voltage REF Negative reference voltage Reference difference AREF REF REF Accuracy internal reference Temperature coefficient ppm C Voltage coefficient Analog Inputs Positive analog input IN Negative analog input IN Analog input voltage difference Input impedance PGA range PGA step size PGA gain error Digital Inputs Digital Outputs oz Oupacwenhimedaxe fCLK Clock frequency 0 1 1 1 MHz UNE __ ________ _______________ __ ___ 95 n T 5 TEXAS INSTRUMENTS POST OFFICE BOX 655303 DALLAS TEXAS 75265 5 THS14F01 THS14F03 14 BIT 1 MSPS 3 MSPS DSP COMPATIBLE ANALOG TO DIGITAL CONVERTERS WITH FIFO INTERNAL REFERENCE AND PGA SLAS285 JUNE 2000 PARAMETER MEASUREMENT INFORMATION sample timing The THS14F01 3 core is based on a pipeline architecture with a latency of 9 5 samples The conversion results are stored in the FIFO 9 5 clock cycles after the input signal was sampled 511 512 59 Analog 510 Input
7. THS14F03 14 BIT 1 MSPS 3 MSPS DSP COMPATIBLE ANALOG TO DIGITAL CONVERTERS WITH FIFO INTERNAL REFERENCE AND PGA SLAS285 JUNE 2000 PRINCIPLES OF OPERATION registers The device contains several registers The A register is selected by the values of bits and 0 at ao Register 0 Convesionresut 1 L3 9 Tables 1 and 2 describe how to read the conversion results and how to configure the data converter The default values were applicable show the state after a power on reset Table 1 Conversion Result Register Address 0 Read sss wen E FE iss The output can be configured for two s complement or straight binary format see D11 control register The output code is given by 2s complement Straight binary 8192 at AIN 0 at AIN CAREF 0 at AIN 2 0 8192 atAIN 0 8191 CAREF 1 LSB 16383 at AREF 1 LSB 2AREF 16384 Table 2 PGA Gain Register Address 1 Read Write Do pe pz pe os Da pa po fe L The PGA gain is determined by writing to G2 0 Gain dB 188 x G2 0 max 7dB The range of G2 0 is 0 to 7 Table 3 Offset Register Address 2 Read Write The offset correction range is from 128 to 127 LSB This value is added to the conversion results from the ADC 35 TEXAS INSTRUMENT
8. cycles THS14F0x read access 7 clock cycles If for example 10 samples need to be read from the ADC without the FIFO the memory interface will be allocated for 10 7 x 16 272 clock Melee eer in total With a FIFO programmed to a 10 sample threshold the memory interface will be allocated for 16 7 x 10 86 clock cycles in total BUS Available for Other Peripheral R R R R 000000000000000 000000000 Busarb R R R driving the analog input The THS14F01 3 ADCs have a fully differential input A differential input is advantageous with respect to SNR SFDR and THD performance because the signal peak to peak level is 5096 of a comparable single ended input There are three basic input configurations Fully differential Transformer coupled single ended to differential Single ended 5 TEXAS INSTRUMENTS POST OFFICE BOX 655303 DALLAS TEXAS 75265 17 THS14F01 THS14F03 14 BIT 1 MSPS 3 MSPS DSP COMPATIBLE ANALOG TO DIGITAL CONVERTERS WITH FIFO INTERNAL REFERENCE AND PGA SLAS285 JUNE 2000 APPLICATION INFORMATION fully differential configuration In this configuration the ADC converts the difference AIN of the two input signals on IN and IN 220 100 pF 220 w 100 pF Figure 16 Differential Input The resistors and capacitors on the inputs decouple the driving source output from the ADC input and also serve as first order low pass f
9. is centered around ground it is more likely that the signal stays within the linear region of the op amp transfer function thus increasing the overall ac performance OUTPUT PEAK AREF full scale 0 0 AREF full scale 35 TEXAS INSTRUMENTS Compared to the transformer coupled configuration the swing on IN is twice as big which can decrease the ac performance SNR SFD and THD POST OFFICE BOX 655303 9 DALLAS TEXAS 75265 THS14F01 THS14F03 14 BIT 1 MSPS 3 MSPS DSP COMPATIBLE ANALOG TO DIGITAL CONVERTERS WITH FIFO INTERNAL REFERENCE AND PGA SLAS285 JUNE 2000 APPLICATION INFORMATION internal external reference operation The THS14F01 3 ADC can either be operated using the built in band gap reference or using an external precision reference in case very high dc accuracy is needed The REF and REF outputs are given by 3 3 If the built in reference is used VBG equals 1 5 V which results in REF 2 5 V REF 0 5 V and AREF 2 V The internal reference can be disabled by writing 1 to D12 REF in the control register address 3 The band gap reference is then disconnected and can be substituted by a voltage on the VBG pin REF vec 2 and REF 1 2 programmable gain amplifier The on chip programmable gain amplifier PGA has eight gain settings The gain can be changed by writing to the PGA gain register address 1 The range is 0 to 7dB in steps of one dB
10. ARACTERISTICS POWER SUPPLY CURRENT vs vs FREQUENCY TIME 284 90 282 80 70 280 lt 1 60 gt 278 E 50 5 5 276 40 o o 274 2 2 272 9 2 270 10 268 0 0 1 1 10 0 50 100 150 200 250 300 f Frequency MHz t Time ns Figure 5 Figure 6 FAST FOURIER TRANSFORM 15 1 MSPS dB Ld M LLL i Figure 7 35 TEXAS INSTRUMENTS 10 POST OFFICE BOX 655303 9 DALLAS TEXAS 75265 THS14F01 THS14F03 14 BIT 1 MSPS 3 MSPS DSP COMPATIBLE ANALOG TO DIGITAL CONVERTERS Output dB INL Integral Nonlinearity LSB inet fedis i eus Mad s alice eor 1 Rer n WITH FIFO INTERNAL REFERENCE AND PGA SLAS285 JUNE 2000 TYPICAL CHARACTERISTICS FAST FOURIER TRANSFORM 0 4 0 7 1 1 3 f Frequency MHz Figure 8 INTEGRAL NONLINEARITY Un y Me Ww LI Wi A _ wer 2048 4096 6144 8192 10240 12288 14336 16384 Samples Figure 9 INTEGRAL NONLINEARITY o 7 fs 3 MSPS E 2 o z 2 0 2048 4096 6144 8192 10240 12288 14336 16384 Samples Figure 10 vip TEXAS INSTRUMENTS POST OFFICE BOX 655303 DALLAS TEXAS 75265 THS14F01 THS14F03
11. CLK p tw CLk gt e ta gt 4 ten 4 16 gt gt lsu OE ACS gt th CS 4 Figure 2 Sample Timing 5 TEXAS INSTRUMENTS POST OFFICE BOX 655303 DALLAS TEXAS 75265 7 THS14F01 THS14F03 14 BIT 1 MSPS 3 MSPS DSP COMPATIBLE ANALOG TO DIGITAL CONVERTERS WITH FIFO INTERNAL REFERENCE AND PGA SLAS285 JUNE 2000 PARAMETER MEASUREMENT INFORMATION read timing 15 pF load tsu OE ACS Address and chip select setup time Output enable NOTE All timing parameters refer to a 50 level p a 4 gt lt th CS tsu OE ACS pid ten 4 dis OV 4 tha Figure 3 Read Timing 35 5 INSTRUMENTS 8 POST OFFICE BOX 655303 9 DALLAS TEXAS 75265 THS14F01 THS14F03 14 BIT 1 MSPS 3 MSPS DSP COMPATIBLE ANALOG TO DIGITAL CONVERTERS WITH FIFO INTERNAL REFERENCE AND PGA SLAS285 JUNE 2000 PARAMETER MEASUREMENT INFORMATION write timing 15 pF load twH WE Write pulse duration high NOTE All timing parameters refer to a 50 level tsu WE CS 4 0 K tsu DA gt 4 th DA X ADDRESS X Figure 4 Write Timing 5 TEXAS INSTRUMENTS POST OFFICE BOX 655303 DALLAS TEXAS 75265 9 THS14F01 THS14F03 14 BIT 1 MSPS 3 MSPS DSP COMPATIBLE ANALOG TO DIGITAL CONVERTERS WITH FIFO INTERNAL REFERENCE AND PGA SLAS285 JUNE 2000 TYPICAL CH
12. S 14 POST OFFICE BOX 655303 9 DALLAS TEXAS 75265 THS14F01 THS14F03 14 BIT 1 MSPS 3 MSPS DSP COMPATIBLE ANALOG TO DIGITAL CONVERTERS WITH FIFO INTERNAL REFERENCE AND PGA SLAS285 JUNE 2000 BIT PRINCIPLES OF OPERATION Table 4 Control Register Address 3 Read an os oe on 013 D12 PWD Power down 0 normal operation 1 power down REF Reference select 0 internal reference 1 external reference FOR Output format 0 straight binary 1 25 complement TM2 0 Test mode 000 normal operation 001 both inputs REF 010 IN at IN at REF 011 IN at REF IN at REF 100 normal operation 101 both inputs REF 110 IN at REF IN at 111 IN at REF IN at REF OFF Offset correction 0 enable 1 disable IP INT polarity 0 low active 1 high active FP FIFO FOVL polarity 0 low active 1 high active FC FIFO control 0 disable FIFO 1 enable FIFO F3 0 FIFO threshold Sets the FIFO threshold for the INT signal in steps of 2 ranging from 0 to 30 3 EXAS INSTRUMENTS POST OFFICE BOX 655303 9 DALLAS TEXAS 75265 15 THS14F01 THS14F03 14 BIT 1 MSPS 3 MSPS DSP COMPATIBLE ANALOG TO DIGITAL CONVERTERS WITH FIFO INTERNAL REFERENCE AND PGA SLAS285 JUNE 2000 APPLICATION INFORMATION FIFO description The FIFO is based on a circular buffer see Figure 15 in this example the FIFO is 16 words long The buffer is accessed using two pointer
13. TH S14FO1 hy Fi THS14F01 THS14F03 1 MSPS 3 MSPS DSP COMPATIBLE ANALOG TO DIGITAL CONVERTERS WITH FIFO INTERNAL REFERENCE AND PGA SLAS285 JUNE 2000 features applications 14 Bit Resolution xDSL Front Ends 1 MSPS and 3 MSPS Speed Grades Communication Available Industrial Control On Chip FIFO For Optimized Data Transfer Instrumentation Differential Nonlinearity DNL 0 6 LSB Automotive Integral Nonlinearity INL 1 5 LSB Internal Reference Differential Inputs Programmable Gain Amplifier uP Compatible Parallel Interface Timing Compatible With TI 6000 DSP Family 3 3 V Single Supply Power Down Mode Monolithic CMOS Design PFB PACKAGE TOP VIEW NC No internal connection Please be aware that an important notice concerning availability standard warranty and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet PRODUCTION DATA information is current as of publication date Copyright 2000 Texas Instruments Incorporated Products conform to specifications per the terms of Texas Instruments LJ Producton processing does not necessarily include X I EXAS INSTRUMENTS POST OFFICE BOX 655303 9 DALLAS TEXAS 75265 1 THS14F01 THS14F03 14 BIT 1 MSPS 3 MSPS DSP COMPATIBLE ANALOG TO DIGITAL CONVERTERS WITH FIFO INTERNAL REFERENCE AND PGA SLAS285 J
14. UNE 2000 description The THS14F01 and THS14F03 are 14 bit 1 MSPS 3 MSPS single supply analog to digital converters with a FIFO internal reference differential inputs programmable input gain and an on chip sample and hold amplifier Implemented with a CMOS process the device has outstanding price performance and power speed ratios The THS14F01 and THS14F03 are designed for use with 3 3 V systems and with a high speed uP compatible parallel interface making them the first choice for solutions based on high performance DSPs like the TI TMS320C6000 series The THS14F01 and THS14F03 are available in a TQFP 48 package in standard commercial and industrial temperature ranges functional block diagram VBG e gt REF 5 BG IN 32 Word FIFO D 13 0 OV bit Buffer A 1 0 cs WR OE INT FOVL CLK CONTROL LOGIC AVAILABLE OPTIONS PACKAGED DEVICE Ta TQFP PFB THS14FO1CPFB 0 C to 70 THS14F03CPFB THS14FO1IPFB 40 85 THS14F03IPFB 35 5 INSTRUMENTS 2 POST OFFICE BOX 655303 9 DALLAS TEXAS 75265 THS14F01 THS14F03 14 BIT 1 MSPS 3 MSPS DSP COMPATIBLE ANALOG TO DIGITAL CONVERTERS WITH FIFO INTERNAL REFERENCE AND PGA SLAS285 JUNE 2000 Terminal Functions TERMINAL yo DESCRIPTION NAME A 1 0 40 41 Address input AGND 7 8 44 Analog ground 45 46 Fo m DGND 9 15 25 33 34 Digital ground DVpp 14 20 26
15. ht be or are used Tl s publication of information regarding any third party s products or services does not constitute Tl s approval warranty or endorsement thereof Copyright 2000 Texas Instruments Incorporated
16. ilters to attenuate out of band noise The input range on both inputs is 0 V to AVpp The full scale value is determined by the voltage reference The positive full scale output is reached if AIN equals AREF the negative full scale output is reached if AIN equals AREF AIN V OUTPUT 0 0 AREF full scale transformer coupled single ended to differential configuration Ifthe application requires the best SNR SFDR and THD performance the input should be transformer coupled The signal amplitude on both inputs of the ADC is one half as high as in a single ended configuration thus increasing the ADC ac performance 220 N 100 pF R E 220 100 pF _ 1 0 1 uF Figure 17 Transformer Coupled IN VPEAK OUTPUT PEAK full scalet 0 0 AREF full scalet 1 winding ratio The resistor R of the transformer coupled input configuration must be set to match the signal source impedance R n Rs where Rs is the source impedance and n is the transformer winding ratio 35 TEXAS INSTRUMENTS 18 POST OFFICE BOX 655303 9 DALLAS TEXAS 75265 THS14F01 THS14F03 14 BIT 1 MSPS 3 MSPS DSP COMPATIBLE ANALOG TO DIGITAL CONVERTERS WITH FIFO INTERNAL REFERENCE AND PGA SLAS285 JUNE 2000 APPLICATION INFORMATION single ended configuration In this configuration the input signal is level shifted by AREF 2 10 10
17. nterface of the THS14F01 3 ADC features 3 state buffers making it possible to directly connect it to a data bus The output buffers are enabled by driving the OE input low Refer to the read and write timing diagrams in the parameter measurement information section for information on read and write access 35 TEXAS INSTRUMENTS POST OFFICE BOX 655303 DALLAS TEXAS 75265 21 THS14F01 THS14F03 14 BIT 1 MSPS 3 MSPS DSP COMPATIBLE ANALOG TO DIGITAL CONVERTERS WITH FIFO INTERNAL REFERENCE AND PGA SLAS285 JUNE 2000 MECHANICAL DATA S PQFP G48 PLASTIC QUAD FLATPACK 0 13 NOM 1 12 T 5 50 a 7 20 6 80 59 Y Gave Plane 9 20 8 80 SO 0 25 1 0 05 MIN 1 05 0 95 Som Seating Plane 1 20 MAX 006 NOTES A Alllinear dimensions are in millimeters B This drawing is subject to change without notice C Falls within JEDEC MS 026 4073176 B 10 96 35 TEXAS INSTRUMENTS 22 POST OFFICE BOX 655303 9 DALLAS TEXAS 75265 IMPORTANT NOTICE Texas Instruments and its subsidiaries TI reserve the rightto make changes to
18. s one for the ADC writing to the FIFO one for the processor DSP reading from the buffer Both pointers move in a clockwise direction If the distance between the ADC write pointer and the DSP read pointer is greater or equal a programmable threshold the INT signal is asserted If this INT signal is connected to an external interrupt pin ofthe processor itis possible to read out the stored values in the FIFO at once during the interrupt service routine If the ADC write pointer reaches the position of the DSP read pointer an overflow occurs In this case the overflow bit in the ADC register is set and the FOVL is asserted Figure 15 Circular Buffer 35 TEXAS INSTRUMENTS 16 POST OFFICE BOX 655303 9 DALLAS TEXAS 75265 THS14F01 THS14F03 14 BIT 1 MSPS 3 MSPS DSP COMPATIBLE ANALOG TO DIGITAL CONVERTERS WITH FIFO INTERNAL REFERENCE AND PGA SLAS285 JUNE 2000 APPLICATION INFORMATION DMA transfer and FIFO The FIFO makes it possible to use the available interface bandwidth of the host processor more efficiently The following is a description based on the TMS320C6201 DSP from TI The TMS320C6201 memory interface has a limited bandwidth for example 200MWPS at a clock rate of 200 MHz The THS14F04x interface is asynchronous with a maximum speed of 300MWPS which is approximately 7 clock cycles If the DSP uses the DMA controller to read data from the DSP the following conditions exist bus arbitration 16 clock
19. s beyond those indicated under recommended operating conditions is not implied Exposure to absolute maximum rated conditions for extended periods may affect device reliability 5 TEXAS INSTRUMENTS POST OFFICE BOX 655303 DALLAS TEXAS 75265 3 THS14F01 THS14F03 14 BIT 1 MSPS 3 MSPS DSP COMPATIBLE ANALOG TO DIGITAL CONVERTERS WITH FIFO INTERNAL REFERENCE AND PGA SLAS285 JUNE 2000 recommended operating conditions wax THS14F01 0 1 1 1 MHz Clock frequency THS14F03 0 1 3 3 Operating free air temperature 40 25 85 electrical characteristics over recommended operating conditions Diu ania reo me Do aeea t uM l DC Characteristicst mme BRL THS14F01 15 25 INL Integral nonlinearity THS14F03 Best fit 15 25 11 2 AC Characteristics NER THS14F01 3 fj 100 kHz ___ THD Total harmonic distortion SNR Signal to noise ratio THS14F03 fj 1 MHz 70 72 SINAD Signal to noise ratio distortion THS14F03 fj 1 MHz 69 70 THS14F01 3 fi 100 kHz 80 SFDR Spurious free dynamic range THS14F03 fi 1 MHz 73 80 ERES _____________ wm tFIFO trigger level 10 samples Performance is ensured with the output enable signal OE being low during no more than one rising clock edge on CLK 0 3 81 35 TEXAS INSTRUMENTS
20. their products or to discontinue any product or service without notice and advise customers to obtain the latest version of relevant information to verify before placing orders that information being relied on is current and complete products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment including those pertaining to warranty patent infringement and limitation of liability TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with Tl s standard warranty Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty Specific testing of all parameters of each device is not necessarily performed except those mandated by government requirements Customers are responsible for their applications using TI components In order to minimize risks associated with the customer s applications adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards Tl assumes no liability for applications assistance or customer product design TI does not warrant or represent that any license either express or implied is granted under any patent right copyright mask work right or other intellectual property right of TI covering or relating to any combination machine or process in which such semiconductor products or services mig
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