ANALOG DEVICES EE-181 Interfacing the ADSP-BF535 Blackfin Processor to Single-Chip CIF Digital Camera OV6630 Over the External Memory Bus Manual
Contents
1. of these burst patterns to analyze how many cycles are taken for each access Prevu Tees gt a fs se ee 3 00V 1A 84 0ns AL 1 233ns Ch Freq i 121 0MH2 it Secscfuscofvccohccsefccssfesusfrocopccecdocse esecptscohoocahecasseveohcocopescehonc peneeseccoposvehvesspereep al 5 00V CA2 5 00V M20 0ns A Ch2 2 30V 5 Jun 2002 m gt 229 200ns 09 55 30 Figure 3 3 The peripheral clock SCLK is displayed in channel 1 and channel 2 shows the ARE pin After eight read strobes are done nine extra cycles are taken to place the data into internal memory Interfacing the ADSP BF535 Blackfin Processor to Single CHIP CIF Digital Camera OV6630 over the External Memory Bus EE 181 Page 3 of 10 4 Interface the ADSP BF535 Processor into the OV6630 The ADSP BF535 is configured to make full use of its 32 bit external memory interface in order to gain maximum throughput Two 16 bit words from the camera will be packed into one 32 bit word before being read by the Blackfin Processor To interface to the single chip camera LVT16374 latches are used These parts are able to fetch the data received from the video device and latch it until the Asynchronous Interface has been read The 8 867 MHz PCLK of the OV6630 clocks a 74HC74 configured as a 2 divider The 4 43 MHz output then clocks an LVT16374 to fetch the data transmitted by Y 7 0 and UV 7 0 at the rising edge The data will be held in the LVT163742. 08010 80108010 80108010 80108010 F000052C 80108010 80108010 80108010 80108010 80108010 80108010 80108010 80108010 80108010 80108010 80108010 80108010 F000055C 80108010 80108010 80108010 80108010 80108010 80108010 80108010 80108010 80108010 80108010 80108010 80108010 F000058C 80108010 80108010 80108010 80108010 80108010 80108010 80108010 80108010 80108010 80108010 80108010 80108010 FO000S5BC 80108010 80108010 80108010 80108010 80108010 80108010 80108010 80108010 80108010 0108010 80108010 80108010 F00005EC 80108010 80108010 80108010 80108010 80108010 80108010 80108010 80108010 80108010 80108010 80108010 80108010 F000061C 80108010 80108010 80108010 60108010 80108010 60108010 80108010 60108010 80108010 80108010 80108010 60108010 F000064C 80108010 80108010 80108010 80108010 80108010 80108010 80108010 80108010 80108010 80108010 80108010 80108010 F000067C 73E98010 75EE75EB BEA 7FO 7 DED6FEA 7 LEC6BEF 7 6ED6DED 84ED7 QEA 82ED74ED 7BEC 7 SEF 80EC83EB 7 3EC8AED 61EA86EB FOO006AC 69EA 7FEC 6BEC 9E8 71EC7FF0 amp 81EC83ED 80E979E9 SBEB 7SEA 7 4EB 7DEB 61EE83EC 75ED7FF0 87EC76EC 83EE6FEC 71EC75EE F00006DC 57EF 73ED S6ED 7FFO 6EEE BEE 7 4EE6CEE 64EF6EEE 65EE80F0 6BEES6EF 6BEC84EC SDEC DEC 71ED 7FEF 87EE8BED 83ED8 9EE F000070C 6BEF76ED 63ED 75F0 BEEE 4ED 6FEE 9EE 7 1LEF CEF 7 SEDS3EF 7AEDSSEF 81EF7FEB 8BEC75EF 91E 774E7 SAEBS7EA 76F088EB F000073C 63EC81EE 67ED8DEF 7 8EC8BEE S4EC 7 FEC 7 EEE6BEB 7FEE69FO 7 SEF69EE 76EE 76F0 7 7EE 3ED 7 3EE6CED 6
3. 2 x 288 The actual resolution is limited due to the limitation of Blackfins external port timing the DMA structure and the internal memory The external port halts during the I O processor loads the next DMA descriptor when it has been expired That causes a large gap in the timing mentioned in chapter 3 and would not meet the requirement set by the camera A way out of this problem is to set up the DMA downloading each frame separately So a DMA expires after receiving each frame and will be reloaded during the camera send blank data anyway The camera sends blank data between each line and each frame The DMA Word Count Register is limited to the maximum of 65 536 2416 A frame of CIF format video in 4 2 2 standard is represented by 202 752 bytes 352 288 pixels 2 bytes The Processor accesses over a 32 bit interface results in 50 688 words 202 752bytes 4 bytes word That fits in the DMAs Word Count Register Resolutions higher than CIF could probably not be served by the DMA on a frame by frame ANALOG DEVICES basis That causes the DMA to become reloaded during active video pixel transfers and results in data misses Building an interface like it is done in this note the access to SDRAM or SRAM is not supported anymore Except the use of the PCI SPORT SPI and USB data can just be stored in L1 or L2 memory The ADSP BF535 provides 52k of L1 memory and 256k bytes of L2 memory L2 memory is be able to keep one fr
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7. Engineer To Engineer Note EE 181 ANALOG Technical Notes on using Analog Devices DSP components and development tools Contact our technical support by phone 800 ANALOG D or e mail dsp support analog com DEVICES Or visit our on line resources http www analog com dsp and http www analog com dsp EZAnswers Interfacing the ADSP BF535 Blackfin Processor to Single CHIP CIF Digital Camera OV6630 over the External Memory Bus Contributed by Thorsten Lorenzen 1 Introduction The purpose of this note is to describe how to hook up video devices like a CIF Common Interface Format Single Chip Digital Camera to the external bus of the ADSP BF535 Blackfin Processor Because of its architecture and video processing capabilities Blackfin Processors will interface with video devices The ADSP BF535 as the first part of the Blackfin family is not equipped with a standard interface that glueless interact with video devices This note is dedicated to show how the Asynchronous Interface can be used to receive video in CIF SIZES 2 Output Format of the OV6630 The OV6630 is a CMOS Image sensor provided as a single chip video imaging camera device designed to provide a high level functionality in a single small footprint package For more details about the functionality it is referred to the internet address below In order to explain the way been accessed by the ADSP BF535 Processor see the schematic of the required output pins in figur
8. ame of video in CIF consisting of 202 752 bytes Higher resolutions does not fit in it A picture of the system is shown in figure Cl Video transfers with higher resolutions than CIF it is revered to the Note Interfacing the ADSP BF535 to ADV7185 3 NTSC PAL video decoder over the External Memory Bus This Note is available soon Interfacing the ADSP BF535 Blackfin Processor to Single CHIP CIF Digital Camera OV6630 over the External Memory Bus EE 181 Page 8 of 10 ANALOG DEVICES Figure C1 References www ovt com OV6630 Datasheet OV7610MD Eva Board ADSP BF535 Datasheet ADSP BF535 Blackfin DSP Hardware Reference VisualDSP 3 0 Interfacing the ADSP BF535 Blackfin Processor to Single CHIP CIF Digital Camera OV6630 over the External Memory Bus EE 181 Page 9 of 10 ANALOG DEVICES Document History April 17 2003 Ported code example to VisualDSP 3 1 Changed according to new Blackfin naming convention January 23 2003 Typos Schematics Gerber files and PDFs are attached to the web site January 09 2003 Initial release Interfacing the ADSP BF535 Blackfin Processor to Single CHIP CIF Digital Camera OV6630 over the External Memory Bus EE 181 Page 10 of 10
9. e 2 1 The datasheet for the OV6630 can be found at www ovt com As it can be seen in figure 2 1 the pins Y 7 0 and UV 7 0 are required to transfer data The PCLK represents the clock aligned to the data Each raising edge of the PCLK will indicate valid data on the bus These pins are necessary April 17 2003 and must be linked to the ADSP BF535 for data transfers Additionally some pins are required for device control and configuration purposes The pin HREF asserted polarity can be chosen indicates active video pixels image data Y 7 0 Analog Pressing UV 7 0 Formatter Video port Column Sense Amp S Exposure WB lt lt lt Detect Detect e Exposure WB SCCB Control Control Interface 356x292 Image Array Video Timig Generator yi a p am H XCLK1 VSYNC FODD CHSYNC AGCEN AWBTH AWBTM SIO 1 SI0 0 SCCEB Figure 2 1 Because of the programmable sensor size as it 1s discussed below HREF provides a way to distinguish between active video pixels and blank data The blank data of the modified senor field will also be transferred and is represented by hex 10 on Y 7 0 and hex 80 UV 7 0 Figure 2 2 shows a transfer of one pixel blanking and HREF indicating an active pixel Due to the configuration the sensor is set to output over a 16 bit bus in this note One pixel exists of one byte of luminance and one byte of Copyright 2003 Analog Devices I
10. ms x Figure 3 1 As mentioned in the ADSP BF535_ Blackfin Hardware Reference Manual after a read cycle is initiated the Async Memory Select line AMS Async Ouput Enable line AOE and the Async Read Enable line ARE become asserted After a multicycle Read Access delay Configured by the Async Interface Bank Control Register the ARE pin normally de assert to complete the read operation But if the interface 1s configured to extend the access the ARE pin remains low until the ARDY pin has been sampled high The data will be fetched one cycle after this happened Due to the architecture of the ADSP BF535 a DMA controlled data download is somewhat non intuitive Each data transfer is split into bursts of eight read access After the burst a gap appears because of internal bus activity Figure 3 2 illustrates this As shown in the figure the first DMA 1s set up to read 32 data words shown as Channel 2 the ARE signal The large gap before the next DMA is required for loading the next DMA descriptor ANALOG Prevu i To p mm nn nn S Ss D i Xi Ch1 Freq 127 7MH2 Chi 5 00V WB 5 00V M200nsl A Ch2 2 40V 24 Apr 2002 iy 37 200ns je ra ae A Figure 3 2 Note also that each DMA transfer is split into bursts of eight accesses in this configuration four bursts per DMA execution Understanding this behavior is crucial for developing a proper DMA interface Figure 3 3 zooms into one
11. nc All rights reserved Analog Devices assumes no responsibility for customer product design or the use or application of customers products or for any infringements of patents or rights of others which may result from Analog Devices assistance All trademarks and logos are property of their respective holders Information furnished by Analog Devices Applications and Development Tools Engineers is believed to be accurate and reliable however no responsibility is assumed by Analog Devices regarding technical accuracy and topicality of the content provided in Analog Devices Engineer to Engineer Notes chrominance information that can be transferred the same time PCLK HREF Y 7 0 UV 7 0 Repeat for all data bytes Pixel Data 16 bit Timing PCLK rising edge latches data bus Figure 2 2 The windowing feature of the OV6630 image sensors allows user definable window sizing as required by the application Window size setting in pixels ranges from 2 x 2 to 356 x 292 and can be positioned anywhere inside the 356 x 292 boundary Note that modifying window size and or position does not change frame or data rate The OV6630 imager alters the assertion of the HREF signal to be consistent with the programmed horizontal and vertical region The default output window is 352 x 288 Figure 2 3 shows it graphically column start column end HREF column re J 5 v m Display Window ne eb o Sensor Array Fig
12. o transfers The memory will be filled just with active video data To detect the first line of each frame the VSYNC signal can be used as mentioned in section 2 VSYNC is connected to a programmable flag and generates an interrupt before the start of a frame This interrupt will enable the DMA transfer Figure 5 1 shows how the timing requirements of the camera and the Processor are met Interfacing the ADSP BF535 Blackfin Processor to Single CHIP CIF Digital Camera OV6630 over the External Memory Bus EE 181 Page 4 of 10 ANALOG DEVICES LYT las i4 iE am LA T a Lr Ch O Vee sO GPIO GPIO PTO CLO ETM SCC BSCL SCC Bis Da FWDH AC CLE1I 17 27 MHz Figure 4 1 Interfacing the ADSP BF535 Blackfin Processor to Single CHIP CIF Digital Camera OV6630 over the External Memory Bus EE 181 Page 5 of 10 ANALOG DEVICES OV6630 PCLCK 8 867 MHz OV6630 Data Port a CM XX AK XX AA XK o 74HC74 Q0 to Top LVT16374 CK mesrone ETP LLLP LP LPL Bottom LVT16374 CK l ARDY AOE Top LVT16374 Q 15 0 To DSP D 15 0 Figure 5 1 Interfacing the ADSP BF535 Blackfin Processor to Single CHIP CIF Digital Camera OV6630 over the External Memory Bus EE 181 Page 6 of 10 ANALOG DEVICES BLACKFIN Memory Hex32 DESTINATION1 FO0002BC 69ED 7ED 6DE96FEC BES 74E6 83E985E 7FEFSOEA 7 BEES OEC 7 9EC8DEF 7 SEC6FEC 7LEA SE
13. until the next rising edge of the CLOCK CK appears When OE asserts the Processor reads the data latched by the LVT16374 The ARDY pin is used to synchronize the video data with the ADSP BF535 As long as the ARDY pin is low the access is held off This way the camera is able to control the asynchronous memory interface By routing a GPIO pin to the PWDN pin of the OV6630 the sensor can be turned off without the lose of configurations done during setup time by the SCCB bus By routing a GPIO pin to the PWDN pin of the OV6630 the sensor can be turned off without the lose of configurations done during setup time by the SCCB bus 5 Data Structure and Improvements As mentioned in section 2 the camera sends active data plus blanking data sequentially Blanking data does fill the internal memory but doesn t contain any useful information ANALOG DEVICES The ADSP BF535 provides 256kBytes of internal L2 Memory One frame of CIF video contains 352 X 288 pixels Each pixel can be represented in two bytes under the 4 2 2 digital component video representation This equates to 202 752 bytes per frame As shown in Figure 5 2 storing the blanking data as well would obviously cause the memory to overflow The use of the AND gate shown in Figure 4 1 stops the data transfer to avoid storing blanking data to the internal memory The AND gate is controlled by the HREF signal of the camera HREF remains high during active vide
14. ure 2 3 In order to detect the first line of each frame the signal VSYNC asserts before Figure 2 4 shows ANALOG DEVICES the VSYNC pin on channel 1 and the HREF pin on channel 4 It can be seen 1f the sensor is set to transfer e g 200 lines the HREF will be asserted 200 times also Each start of frame will be indicated by VSYNC around 2 ms before HREF asserts Prevyu i TE D perm EE E E 200mMY i 100mY LA 32 6ms 1 87ms Chi Freq E 22 21 H2 Low signal amplitude tA a a x Par 28 May 2002 uy 3 27000ms 10 50 47 Figure 2 4 The video output port of the OV6630 image sensor provides a number of output format standard options to suit many different application requirements These formats are user programmable through Omnivision s SCCB two wire control interface The OV6630 imager supports both ITU 601 and ITU 656 output formats in different configurations In this note the sensor is set to provide differential video signals YUV 4 2 2 16 bit wide and clocked at 8 867MHz PCLK 3 Asynchronize Interface of the ADSP BF535 Blackfin Processor The Processors asynchronous interface is used to receive the video data 32 bit data can be fetched in a manner it is shown in figure 3 1 Interfacing the ADSP BF535 Blackfin Processor to Single CHIP CIF Digital Camera OV6630 over the External Memory Bus EE 181 Page 2 of 10 Setup Programmed Read Access Ready Sampled Latched m
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ANALOG DEVICES EE 181 Interfacing the ADSP BF535 Blackfin Processor to Single Chip CIF Digital Camer