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TEXAS INSTRUMENTS THS1050 handbook

1. AVss 1 11 13 41 Analog ground return for internal analog circuitry 42 44 46 CLK 15 Clock input CLK 16 Complementary clock input D9 D0 25 34 Digital data output bits LSB DO MSB D9 2s complement output format d TEXAS INSTRUMENTS 2 POST OFFICE BOX 655303 DALLAS TEXAS 75265 THS1050 10 BIT 50 MSPS IF SAMPLING COMMUNICATIONS ANALOG TO DIGITAL CONVERTER SLAS278 APRIL 2000 detailed description The THS1050 uses a differential pipeline architecture and assures no missing codes over the full operating temperature range The device uses a 1 bit per stage architecture in order to achieve the highest possible bandwidth The differential analog inputs are terminated with a 900 resistor The inputs are then fed to a unity gain buffer followed by the S H sample and hold stage This S H stage is a switched capacitor operational amplifier based circuit see Figure 3 The pipeline is a typical 1 bit per stage pipeline as shown in the functional block diagram The digital output of the 10 stages and the last 1 bit flash are sent to a digital correction logic block which then outputs the final 10 bits absolute maximum ratings over operating free air temperature unless otherwise noted t Supply voltage range AVDD 0 5 V to 7 V DVDD EE 0 5 V to 7 V BEA DIS EE 0 5 V to 7 V Voltage between AV ee and DV ee na tn NN EE NEEN n na NEEN ana la aa ak SEENEN ea 0 3 V to 0 5 V Voltage between DRVpp and
2. 7 n D0 D 11 Timing DVpp D gt gt CLK Vss DVss Figure 5 Digital Outputs Figure 4 Clock Inputs d TEXAS INSTRUMENTS POST OFFICE BOX 655303 9 DALLAS TEXAS 75265 7 THS1050 10 BIT 50 MSPS IF SAMPLING COMMUNICATIONS ANALOG TO DIGITAL CONVERTER SLAS278 APRIL 2000 TYPICAL CHARACTERISTICSt OUTPUT POWER SPECTRUM VS FREQUENCY Fs 50 MSPS fin 2 2 MHz VIN 2 dBFS e 8K Point Discrete Fourier m Transform o I z o a f Frequency MHz Figure 6 OUTPUT POWER SPECTRUM VS FREQUENCY Fs 50 MSPS fin 15 5 MHz VIN 2 dBFS o 8K Point Discrete Fourier E Transform o I z o a f Frequency MHz Figure 7 t AVpp 5 V DVpp 5 V DRVpp 3 3 V TA 25 C unless otherwise noted d TEXAS INSTRUMENTS POST OFFICE BOX 655303 DALLAS TEXAS 75265 THS1050 10 BIT 50 MSPS IF SAMPLING COMMUNICATIONS ANALOG TO DIGITAL CONVERTER SLAS278 APRIL 2000 TYPICAL CHARACTERISTICS OUTPUT POWER SPECTRUM VS FREQUENCY Fg 50 MSPS fin 31 MHz VIN 2 dBFS 8K Point Discrete Fourier Transform f Frequency MHz Figure 8 OUTPUT POWER SPECTRUM VS FREQUENCY Fs 50 MSPS fin 69 MHz VIN 2 dBFS 8K Point Discrete Fourier Transform Power dBFS f Frequency MHz Figure
3. The copper alloy plate or PowerPAD is exposed on the bottom of the device package for a direct solder attachment to a PCB land or conductive pad The land dimensions should have minimum dimensions equal to the package dimensions minus 2 mm see Figure 24 For a multilayer circuit board a second land having dimensions equal to or greater than the land to which the device is soldered should be placed on the back of the circuit board see Figure 25 A total of 9 thermal vias or plated through holes should be used to connect the two lands to a ground plane buried or otherwise having a minimum total area of 3 inches square in 1 oz copper For the THS1050 package the thermal via centers should be spaced at a minimum of 1 mm The ground plane need not be directly under or centered around the device footprint if a wide ground plane thermal run having a width on the order of the device is used to channel the heat from the vias to the larger portion of the ground plane The THS1050 package has a standoff of 0 19 mm or 7 5 mils In order to apply the proper amount of solder paste to the land a solder paste stencil with a 6 mils thickness is recommended for this device Too thin a stencil may lead to an inadequate connection to the land Too thick a stencil may lead to beading of solder in the vicinity of the pins which may lead to shorts For more information refer to Texas Instruments literature number SLMA002 PowerPAD Thermally Enhanced Package Power
4. be chosen to ensure appropriate levels at the device s input If the clock signal is fed through a transmission line of characteristic impedance Zo then the secondary of the transformer should be terminated with a resistor of nZo where n is the transformer s impedance ratio 1 n as shown in Figure 20 Alternatively a series termination resistor having impedance equal to the characteristic impedance of the transmission line can be used at the clock source d TEXAS INSTRUMENTS POST OFFICE BOX 655303 DALLAS TEXAS 75265 THS1050 10 BIT 50 MSPS IF SAMPLING COMMUNICATIONS ANALOG TO DIGITAL CONVERTER SLAS278 APRIL 2000 APPLICATION INFORMATION to Impedance Ratio 1 4 5V p p 0 1 uF Y CLK T4 1H E ac Signal Source I A R 4Zo 0 01 uF 0 1 uF Figure 20 Driving the Clock From an Impedance Matched Source The clock signals CLK and CLK should be well matched and must both be driven A transformer ensures minimal skew between the two complementary channels However skew levels of up to 500 ps between CLK and CLK can be tolerated with some performance degradation The clock input can also be driven differentially with a 5 V TTL signal by using an RF transformer to convert the TTL signal to a differential signal The TTL signal is ac coupled to the positive primary terminal with a high pass circuit The negative terminal of the transformer is connected to ground s
5. references The option of internal or external reference is provided by allowing for an external connection of the internal reference to the reference inputs This type of reference selection offers the lowest noise possible by not relying on any active switch to make the selection Compensating each reference output with a 1 uF and 0 01 uF chip capacitor is required as shown in Figure 18 The differential analog input range is equal to 2 VREFOUT VREFOUT When using external references it is best to decouple the reference inputs with a 0 1 uF and 0 01 uF chip capacitor as shown in Figure 19 VREFIN VREFOUT External Reference 0 01 uF 0 01 uF VREFIN VREFOUT External Reference 0 01uF 1pF 0 01 uF 0 1uF Figure 18 Internal Reference Usage Figure 19 External Reference Usage using the THS1050 clock input The THS1050 is a high performance A D converter In order to obtain the best possible performance care should be taken to ensure that the device is clocked appropriately The optimal clock to the device is a low jitter square wave with sharp rise times 2ns at 50 duty cycle The two clock inputs CLK and CLK should be driven with complementary signals that have minimal skew and nominally swing between 0 V and 5 V The device will still operate with a peak to peak swing of 3 V on each clock channel around the 2 5 V midpoint Use of a transfo
6. spectral components excluding dc referenced to full scale signal to noise ratio SNR When tested with a single tone the ratio of the signal power to the sum of the power of all other power spectral components excluding dc and the first 9 harmonics referenced to full scale effective number of bits ENOB For a sine wave SINAD can be expressed in terms of the effective number of bits using the following formula SINAD 1 76 6 02 spurious free dynamic range SFDR The ratio of the signal power to the power of the worst spur excluding dc The worst spurious component may or may not be a harmonic The ratio is reported in dBc that is degrades as signal levels are lowered ENOB d TEXAS INSTRUMENTS 6 POST OFFICE BOX 655303 DALLAS TEXAS 75265 THS1050 10 BIT 50 MSPS IF SAMPLING COMMUNICATIONS ANALOG TO DIGITAL CONVERTER SLAS278 APRIL 2000 Sample N Ma S ua YO di CNN t BI k ta A td Pipe pi tp H JA tp L VIL NA NY NZ XY NL ATA A M te Digital Output DO D9 Figure 1 Timing Diagram equivalent circuits R2 42 OO R1 BAND VCM mr e VREFOUT ai R1 R2 s 91 o o e e e 900 Q AVpp oo e e e VIN d di 600 Q b 0 Vom Vom 590 Q oO 2 AVss Figure 3 Analog Input Stage Figure 2 References DVpp VDD CLK Det 102 DVss m
7. 050 results in SFDR performance that is exceptional for a 10 bit analog to digital converter The THS1050 can operate with either internal or external references Internal reference usage selection is accomplished simply by externally connecting reference output terminals to reference input terminals AVAILABLE OPTIONS PACKAGE TA 48 TQFP PHP 40 C to 85 C THS10501 0 C to 70 C THS1050C Please be aware that an important notice concerning availability standard warranty and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet PRODUCTION DATA information is current as of publication date Copyright 2000 Texas Instruments Incorporated Products conform to specifications per the terms of Texas Instruments LJ Meri ofall paren Producton processing does not necessarily include X I EXAS INSTRUMENTS POST OFFICE BOX 655303 9 DALLAS TEXAS 75265 1 THS1050 10 BIT 50 MSPS IF SAMPLING COMMUNICATIONS ANALOG TO DIGITAL CONVERTER SLAS278 APRIL 2000 functional block diagram AVpp DVpp DRVpp Stage 1 Stages 2 9 Stage 10 Buffer VREFIN VREFOUT Reference VREFOUT 20V AVpp 2 VREFIN Vcml Hee ge RMN L L d L L L L E j AVss DVss DRVss D9 D8 D7 D6 D5 D4 D3 D2 Di DO Terminal Functions TERMINAL I O DESCRIPTION NAME NO AVDD 2 5 12 43 Analog power supply 45 47
8. 15 5 MHz VIN 2 dBFS 5 10 15 20 25 30 35 40 45 50 55 60 65 70 Clock Frequency MHz Figure 13 d TEXAS INSTRUMENTS POST OFFICE BOX 655303 9 DALLAS TEXAS 75265 11 THS1050 10 BIT 50 MSPS IF SAMPLING COMMUNICATIONS ANALOG TO DIGITAL CONVERTER SLAS278 APRIL 2000 Power dB DNL LSBs TYPICAL CHARACTERISTICS NOISE AND DISTORTION VS DUTY CYCLE SFDR dBc SINAD dBFS Fs 50 MSPS fin 15 5 MHz VIN 2 dBFS 40 45 50 55 60 Duty Cycle Figure 14 DIFFERENTIAL NONLINEARITY VS OUTPUT CODE 0 256 512 768 1023 Output Code Figure 15 d TEXAS INSTRUMENTS POST OFFICE BOX 655303 DALLAS TEXAS 75265 THS1050 10 BIT 50 MSPS IF SAMPLING COMMUNICATIONS ANALOG TO DIGITAL CONVERTER SLAS278 APRIL 2000 TYPICAL CHARACTERISTICS INTEGRAL NONLINEARITY VS OUTPUT CODE 1 00 INL LSBs o o e 1 00 0 256 512 768 1023 Output Code LSBs Figure 16 LARGE SIGNAL ANALOG INPUT BANDWIDTH N D m 5 I z a Fs 50 MSPS 3 dB Point 82 MHz 0 20 40 60 80 100 f Analog Input Frequency MHz Figure 17 d TEXAS INSTRUMENTS POST OFFICE BOX 655303 9 DALLAS TEXAS 75265 13 THS1050 10 BIT 50 MSPS IF SAMPLING COMMUNICATIONS ANALOG TO DIGITAL CONVERTER SLAS278 APRIL 2000 APPLICATION INFORMATION using the THS1050
9. 9 d TEXAS INSTRUMENTS POST OFFICE BOX 655303 9 DALLAS TEXAS 75265 9 THS1050 10 BIT 50 MSPS IF SAMPLING COMMUNICATIONS ANALOG TO DIGITAL CONVERTER SLAS278 APRIL 2000 90 00 80 00 70 00 60 00 Power dB 50 00 40 00 Power dBFS TYPICAL CHARACTERISTICS NOISE AND DISTORTION VS ANALOG INPUT FREQUENCY d Fs 50 MSPS VIN 2dBFS 2nd 3rd Harmonic Harmonic SFDR dBc SINAD dBc dBc dBFS SNR dBFS 10 20 30 40 50 60 70 80 90 f Analog Input Frequency MHz Figure 10 TWO TONE OUTPUT POWER SPECTRUM VS FREQUENCY Fs 50 MSPS F1 14 9 MHz F2 15 6 MHz each 9 8 dBFS 8K Point Discrete Fourier Transform f Frequency MHz Figure 11 d TEXAS INSTRUMENTS POST OFFICE BOX 655303 DALLAS TEXAS 75265 Power dB Power dB THS1050 10 BIT 50 MSPS IF SAMPLING COMMUNICATIONS ANALOG TO DIGITAL CONVERTER SLAS278 APRIL 2000 TYPICAL CHARACTERISTICS NOISE AND DISTORTION VS ANALOG INPUT POWER LEVEL 90 F5 50 MSPS 80 L fy 15 5 MHz SFDR dBc 20 SNR dBFS SINAD dBFS 50 45 40 35 30 25 20 15 10 5 0 Input Power dBFS Figure 12 NOISE AND DISTORTION VS CLOCK FREQUENCY 100 40 SFDR dBc SNR dBFS SINAD dBFS 10 fin
10. DVDD adi xalk aka a aa lele l aa hama RII 0 5 V to 5 V Voltage between AVpp and DVDD lele eee e cd xan nw na 0 b id n II 0 5 V to 5 V Digital data output e EELER Rees RR EG eR Rx EIEE RH 0 3 V to DVpp 0 3 V CLK peak inip b current wow we a deed peste bead oe be ely e i oe bed Rend boda pode a e E del deba de 20 mA Peak total input current all inputS sack b kya nk Wak ka AA a AA kk a a kk a ka kn a aa an 30 mA Operating free air temperature range Ta THS1050C 0 C to 70 G fe CAE 40 C to 85 C Storage temperature range 65 C to 150 C Lead temperature 1 6 mm 1 16 inch from the case for 10 seconds 260 C T Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied Exposure to absolute maximum rated conditions for extended periods may affect device reliability recommended operating conditions x PANE NI NOM MAX UNT d TEXAS INSTRUMENTS POST OFFICE BOX 655303 9 DALLAS TEXAS 75265 3 THS1050 10 BIT 50 MSPS IF SAMPLING COMMUNICATIONS ANALOG TO DIGITAL CONVERTER SLAS278 APRIL 2000 electrical characteristics over reco
11. ITIONS MIN TYP MAX UNIT 61 Signal to noise ratio fiy 215 5 MHz 58 61 IM 231 MHz 60 5 fiy 2 2 MHz 60 5 SINAD Signal to noise and distortion fiy 215 5 MHz 56 60 8 60 2 fin 31 MHz ENOB Effective number of bits fiy 215 5 MHz THD Total harmonic distortion IM 215 5 MHz o SFDR Spurious free dynamic range fIN 215 5 MHz fIN 2 2 MHz 2nd Harmonic Distortion DN 215 5 MHz fIN 31 MHz 77 3rd Harmonic Distortion fiN 215 5 MHz 73 65 dBc IM 31 MHz F1 14 9 MHz F2 15 6 MHz T All typical values are at TA 25 C o o c operating characteristics over recommended operating conditions AVpp DVpp z 5 V DRVpp 3 3 VT switching specifications awmwedeayt DER O ES CCS Output delay ou After falling edge of CLK PENC CLK T All typical values are at TA 25 C d TEXAS INSTRUMENTS POST OFFICE BOX 655303 9 DALLAS TEXAS 75265 5 THS1050 10 BIT 50 MSPS IF SAMPLING COMMUNICATIONS ANALOG TO DIGITAL CONVERTER SLAS278 APRIL 2000 definitions of specifications analog bandwidth The analog input frequency at which the spectral power of the fundamental frequency of a large input signal is reduced by 3 dB aperture delay The delay between the 50 point of the rising edge of the clock and the instant at which the analog input is sampled aperture uncertainity jitter The sample to sample variation in aperture delay differential nonlinearity Th
12. PAD is a trademark of Texas Instruments d TEXAS INSTRUMENTS POST OFFICE BOX 655303 9 DALLAS TEXAS 75265 17 THS1050 10 BIT 50 MSPS IF SAMPLING COMMUNICATIONS ANALOG TO DIGITAL CONVERTER SLAS278 APRIL 2000 APPLICATION INFORMATION package continued 1 25mm 4 2x1 25 mm 1 25 mm 2x1 25 mm 0 33 mm Diameter Plated Through Hole lt gt 5 mm Figure 24 Thermal Land top view PHP S PQFP G48 Plated Through Hole PWB Figure 25 Top and Bottom Thermal Lands With Plated Through Holes side view d TEXAS INSTRUMENTS 18 POST OFFICE BOX 655303 DALLAS TEXAS 75265 THS1050 10 BIT 50 MSPS IF SAMPLING COMMUNICATIONS ANALOG TO DIGITAL CONVERTER SLAS278 APRIL 2000 MECHANICAL DATA PHP S PQFP G48 PowerPAD PLASTIC QUAD FLATPACK Thermal Pad see Note D 0 13 NOM 5 50 se n Lem Planet y 7 2 sa 6 80 0 25 1 8 80 sa Seating Plane 1 20 MAX L A 0 08 4146927 A 01 98 NOTES A Alllinear dimensions are in millimeters This drawing is subject
13. THS1050 10 BIT 50 MSPS IF SAMPLING COMMUNICATIONS ANALOG TO DIGITAL CONVERTER SLAS278 APRIL 2000 TH S1050 AY PS features applications 50 MSPS Maximum Sample Rate Wireless Local Loop 10 Bit Resolution Wireless Internet Access No Missing Codes Cable Modem Receivers On Chip Sample and Hold Medical Ultrasound 73 dB Spurious Free Dynamic Range at e Magnetic Resonant Imaging fin 15 5 MHz e iqi 48 PHP PACKAGE 5 V Analog and Digital Supply TOP VIEW e 3 V and 5 V CMOS Compatible Digital Output 9 7 Bit ENOB at fiy 31 MHz 60 dB SNR at fin 31 MHz e 382 MHz Bandwidth AVss 1 Internal or External Reference Non N DD L 2 e Buffered 900 O Differential Analog Input Vins 3 SC Vin L 4 description AVpp 15 The THS1050 is a high speed low noise 10 bit VREFOUT CMOS pipelined analog to digital converter A VREFIN differential sample and hold minimizes even order VREFIN L 8 harmonics and allows for a high degree of VREFOUT lo common mode rejection at the analog input A Vgc L 10 buffered analog input enables operation with a AVss Un constant analog input impedance and prevents AVpp L 12 transient voltage spikes from feeding backward to the analog input source Full temperature DNL performance allows for industrial application with the assurance of no missing codes The typical integral nonlinearity INL for the THS1050 is less than one LSB The superior INL curve of the THS1
14. e average deviation of any output code from the ideal width of 1 LSB clock pulse width duty cycle Pulse width high is the minimum amount of time that the clock pulse should be left in logic 1 state to achieve rated performance pulse width low is the minimum time clock pulse should be left in low state At a given clock rate these specs define acceptable clock duty cycles offset error The difference between the analog input voltage at which the analog to digital converter output changes from negative full scale to one LSB above negative full scale and the ideal voltage at which this transition should occur gain error The maximum error in LSBs between a digitized ideal full scale low frequency offset corrected triangle wave analog input from the ideal digitized full scale triangle wave divided by the full scale range in this case 1024 harmonic distortion The ratio of the power of the fundamental to a given harmonic component reported in dBc integral nonlinearity The deviation of the transfer function from an end point adjusted reference line measured in fractions of 1 LSB Also the integral of the DNL curve output delay The delay between the 50 point of the falling edge of the clock and signal and the time when all output data bits are within valid logic levels not including pipeline delay signal to noise and distortion SINAD When tested with a single tone the ratio of the signal power to the sum of the power of all other
15. ee Figure 21 The transformer secondary is connected to the CLK inputs Impedance Ratio 1 4 5 V TTL CLK D CLK T4 1H THS1050 CLK 0 01 uF F lt X 0 1 pF Figure 21 TTL Clock Input d TEXAS INSTRUMENTS POST OFFICE BOX 655303 9 DALLAS TEXAS 75265 15 THS1050 10 BIT 50 MSPS IF SAMPLING COMMUNICATIONS ANALOG TO DIGITAL CONVERTER SLAS278 APRIL 2000 APPLICATION INFORMATION using the analog input The THS1050 obtains optimum performance when the analog signal inputs are driven differentially The circuit below shows the optimum configuration see Figure 22 The signal is fed to the primary of an RF transformer Since the input signal must be biased around the common mode voltage of the internal circuitry the common mode VcM reference from the THS1050 is connected to the center tap of the secondary To ensure a steady low noise Vc reference the best performance is obtained when the Vcm output is connected to ground with a 0 1 uF and 0 01 uF low inductance capacitor Ro 20 509 mnn VIN 50 Q an 7 THS1050 ac Signal Source VIN Figure 22 Driving the THS1050 Analog Input With Impedance Matched Transmission Line When it is necessary to buffer or apply a gain to the incoming analog signal it is also possible to combine a single ended amplifier with an RF transformer as shown in Figure 23 For this application a wide band current mode
16. feedback amplifier such as the THS3001 is best The noninverting input to the op amps is terminated with a resistor having an impedance equal to the characteristic impedance of the wave guide or trace that sources the IF input signal The single ended output allows the use of standard passive filters between the amplifier output and the primary In this case the SFDR of the op amp is not as critical as that of the A D converter While harmonics generated from within the A D converter fold back into the first Nyquist zone harmonics generated externally in the op amps can be filtered out with passive filters 1 kQ 1 kQ Impedance Ratio 1 n 10 0 IF Input THS3001 RT 2 THS1050 VIN 0 1uF zz X 0 01 uF Figure 23 IF Input Buffered With THS3001 Op Amp 35 TEXAS INSTRUMENTS 16 POST OFFICE BOX 655303 9 DALLAS TEXAS 75265 THS1050 10 BIT 50 MSPS IF SAMPLING COMMUNICATIONS ANALOG TO DIGITAL CONVERTER SLAS278 APRIL 2000 APPLICATION INFORMATION digital outputs The digital outputs are in 2s complement format and can drive either TTL 3 V CMOS or 5 V CMOS logic The digital output high voltage level is equal to DRVpp Table 1 shows the value of the digital output bits for full scale analog input voltage midrange analog input voltage and negative full scale input voltage To reduce capacitive loading each digital output of the THS1050 should drive only one digital input The CMOS outp
17. mmended operating free air temperature range AVpp DVpp 5 V DRVpp 3 3 V internal references CLK 50 MHz unless otherwise noted t dc accuracy DNL Differential nonlinearity No missing codes INL Integral nonlinearity EO Offset error EG Gain error T All typical values are at TA 25 C power supply T All typical values are at TA 25 C reference Vmerour _Negaive erence outptvotage TT TT ST ie e osfv VREFOUT Positive reference ouputvotage Jes gt v e C pe fen Weeen Exemaneemnespied L 5 Y Dag Comenmdeomuwtue gt gt v_ Wa cmmemdepuone gt Lx T All typical values are at TA 25 C analog input DEER o o Se o Diferent input capaciancs fen reiege v p Bierchen C 2 v gt T All typical values are at TA 25 C digital outputs PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VoH High level output voltage loH 50 uA 0 8DRVpp VOL Low level output voltage loL 50 pA 0 2DRVpp T All typical values are at TA 25 C d TEXAS INSTRUMENTS 4 POST OFFICE BOX 655303 DALLAS TEXAS 75265 THS1050 10 BIT 50 MSPS IF SAMPLING COMMUNICATIONS ANALOG TO DIGITAL CONVERTER SLAS278 APRIL 2000 ac specifications over recommended operating free air temperature range AVpp DVpp 5 V DRVpp 3 3 V internal references CLK 50 MHz analog input at 2 dBFS unless otherwise noted t PARAMETER TEST COND
18. order to minimize risks associated with the customer s applications adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards Tl assumes no liability for applications assistance or customer product design TI does not warrant or represent that any license either express or implied is granted under any patent right copyright mask work right or other intellectual property right of TI covering or relating to any combination machine or process in which such semiconductor products or services might be or are used Te publication of information regarding any third party s products or services does not constitute Tl s approval warranty or endorsement thereof Copyright 2000 Texas Instruments Incorporated
19. rmer coupled clock input ensures minimal skew between the CLK and CLK signals If the available clock signal swing is not adequate a step up transformer can be used in order to deliver the required levels to the converter s inputs see Figure 20 For example if a 3 3 V standard CMOS logic is used for clock generation a minicircuits T4 1H transformer can be used for 2x voltage step up This provides greater than 6 V differential swing at the secondary of the transformer which provides greater than 3 V swings to both CLK and CLK terminals of THS1050 The center tap of the transformer secondary is connected to the Vcm terminal of the THS1050 for proper dc biasing Both the transformer and the clock source should be placed close to THS1050 to avoid transmission line effects 3 3 V TTL logic is not recommended with T4 1H transformer due to TTLs tendency to have lower output swings If the input to the transformer is a square wave such as one generated by a digital driver care must be taken to ensure that the transformer s bandwidth does not limit the signal s rise time and effectively alter its shape and duty cycle characteristics For a 50 MSPS rate the transformer s bandwidth should be at least 300 MHz A low phase noise sinewave can also be used to effectively drive the THS1050 In this case the bandwidth of the transformer becomes less critical as long as it can accommodate the frequency of interest for example 50 MHz The turns ratio should
20. to change without notice Body dimensions do not include mold flash or protrusions Thepackage thermal performance may be enhanced by bonding the thermal pad to an external thermal plane This padis electrically and thermally connected to the backside of the die and possibly selected leads Falls within JEDEC MO 153 g om m PowerPAD is a trademark of Texas Instruments d TEXAS INSTRUMENTS POST OFFICE BOX 655303 9 DALLAS TEXAS 75265 19 IMPORTANT NOTICE Texas Instruments and its subsidiaries TI reserve the right to make changes to their products or to discontinue any product or service without notice and advise customers to obtain the latest version of relevant information to verify before placing orders that information being relied on is current and complete All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment including those pertaining to warranty patent infringement and limitation of liability TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with Tl s standard warranty Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty Specific testing of all parameters of each device is not necessarily performed except those mandated by government requirements Customers are responsible for their applications using TI components In
21. ut drivers are capable of handling up to a 15 pF load For better SNR performance use 3 3 V for DRVpp Resistors of 200 Q in series with the digital output can be used for optimizing SNR performance Table 1 Digital Outputs ANALOG INPUT VIN OR V N D9 D8 D7 Ds os b D b2 bt po etr EHNEN pt i JJ i j vv popo popopopopopopo fol vet pi tO TO To fo fo fo fo fo fo power supplies Best performance is obtained when AVpp is kept separate from DVpp Regulated or linear supplies as opposed to switched power supplies must be used to minimize supply noise It is also recommended to partition the analog and digital components on the board in such a way that the analog supply plane does not overlap with the digital supply plane in order to limit dielectric coupling between the different supplies package The THS1050 is packaged in a small 48 pin quad flat pack PowerPAD package The die of the THS1050 is bonded directly to copper alloy plate which is exposed on the bottom of the package Although the PowerPAD provides superior heat dissipation when soldered to ground land it is not necessary to solder the bottom of the PowerPAD to anything in order to achieve minimum performance levels indicated in this specification over the full recommended operating temperature range If the device is to be used at ambient temperatures above the recommended operating temperatures use of the PowerPAD is suggested

TEXAS INSTRUMENTS THS1050 handbook

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