intersil HUF75542P3 HUF75542S3S handbook
Contents
1. PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS OFF STATE SPECIFICATIONS Drain to Source Breakdown Voltage BVpss Ip 250A Ves OV Figure 11 80 V Zero Gate Voltage Drain Current Ipss Vps 75V Vas 0V 1 uA Vps 70V Vas OV 150 C 250 pA Gate to Source Leakage Current lass Vas 20V 100 ON STATE SPECIFICATIONS Gate to Source Threshold Voltage Vas Vps Ip 250pA Figure 10 2 4 V Drain to Source On Resistance p 75A 10V Figure 9 0 012 0 014 Q THERMAL SPECIFICATIONS Thermal Resistance Junction to Case 220 263 5 0 65 C W Thermal Resistance Junction to RoJA 62 C W Ambient SWITCHING SPECIFICATIONS Vcs 10V Turn On Time ton Vpp 40V Ip 75A 195 ns VGs 10V Turn On Delay Time Regs 3 90 12 5 ns Rise Time tr eerie 117 ns Turn Off Delay Time td OFF 50 ns Fall Time tf 80 ns Turn Off Time toFF 195 ns GATE CHARGE SPECIFICATIONS Total Gate Charge Qg rOT Vas OV to 20V Vpp 40V 150 180 nC Gate Charge at 10V Qg 10 Vas OV to 10V p 1 0mA E 80 96 nC Threshold Gate Charge Qg TH Vas OV to 2V Figures 13 16 17 5 7 7 nC Gate to Source Gate Charge Qgs 15 nC Gate to Drain Miller Charge2. 33 nC CAPACITANCE SPECIFICATIONS Input Capacitance Ciss Vps 25V Ves OV 2750 Output Capacitance Coss CM 1 2 700 pF Reverse Transfer Capacitance Crss 250 pF Source to Drain Diode Specifications PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS Source to Drain Diode Voltage Vsp Isp 75A 1 25 V Isp 37 5A 1 00 V Reverse Recovery Time trr Isp 75A digp dt 100A us n 102 ns Reverse Recovered Charge lap 75 digp dt 100A us E 255 nC 2 intersil HUF75542P3 HUF75542S3S Typical Performance Curves 1 2 1 0 POWER DISSIPATION MULTIPLIER o 25 50 75 100 125 150 175 CASE TEMPERATURE C FIGURE 1 NORMALIZED POWER DISSIPATION vs CASE Ip DRAIN CURRENT A 80 Vas 10V 60 40 20 0 25 50 75 100 125 150 175 Tc CASE TEMPERATURE 9C FIGURE 2 MAXIMUM CONTINUOUS DRAIN CURRENT vs TEMPERATURE CASE TEMPERATURE 2 DUTY CYCLE DESCENDING ORDER 1E 0 5 02 0 1 8 2 0 05 0 02 aa 0 01 a c 2 4 0 1 H 5 2 2A H J 1 HE NOTES H SINGLE PULSE DUTY FACTOR D ty to ty H PEAK Ty Ppp X ZgJc T 0 01 To iori dila d oe B e 105 104 103 10 10 100 101 t RECTANGULAR PULSE DURATION 5 FIGURE 3 NORMALIZED MAXIMUM TRANSIENT THERMAL
3. U 5542 RA HUF75542P3 HUF75542S3S Data Sheet June 2000 File Number 4845 2 75A 80V 0 014 Ohm N Channel UltraFET Power MOSFETs Packaging JEDEC TO 220AB JEDEC TO 263AB Features Ultra Low On Resistance TDS ON 0 0140 Vas 10V Simulation Models Temperature Compensated PSPICE and SABER GATE SOURCE Electrical Models Spice SABER Thermal Impedance Models DRAIN FLANGE FLANGE www intersil com HUF75542P3 HUF75542S3S Peak Current vs Pulse Width Curve UIS Rating Curve Symbol Ordering Information PART NUMBER PACKAGE BRAND G HUF75542P3 TO 220AB 75542P HUF75542S3S TO 263AB 755425 5 NOTE When ordering use the entire part number Add the suffix to obtain the variant in tape and reel e g HUF75542S3ST Absolute Maximum Ratings 25 C Unless Otherwise Specified HUF75542P3 HUF75542S3S UNITS Drain to Source Voltage Note 1 Vpss 80 V Drain to Gate Voltage Ras 20kQ Note 1 VpGR 80 V Gate to Source Voltage isses tes eere E re xh pe dx ER RE RI Ra x Vas 20 V Drain Current Continuous 25 C Vas 10V Figure 2 Ip 75 A Continuous 100 C Vas 10V Figure 2 Ip 58 A Pulsed Drain Current ve 1e npe exi RR RR eni ee den e
4. IMPEDANCE 1000 TTTTIT Tc 25 C HH FOR TEMPERATURES 1 lt 259 CURRENT AS FOLLOWS J ee 175 4 150 d J 4 a 100 ER L TRANSCONDUCTANCE L MAY LIMIT CURRENT L IN THIS REGION 50 1 po pb 105 104 t PULSE WIDTH s FIGURE 4 PEAK CURRENT CAPABILITY 3 intersil HUF75542P3 HUF75542S3S Typical Performance Curves Continued 500 BENE 1 SINGLE PULSE Ty MAX RATED 100 E H i a z 2 10 H H 5 E _ OPERATION IN THIS AREA MAY LIMITED BY rps oN 1 1 10 100 200 Vps DRAIN TO SOURCE VOLTAGE V FIGURE 5 FORWARD BIAS SAFE OPERATING AREA 150 PULSE DURATION 80us DUTY CYCLE 0 5 MAX 120 Vppz15V E 2 90 2 o z lt 60 30 0 2 3 4 5 Vas GATE TO SOURCE VOLTAGE V FIGURE 7 TRANSFER CHARACTERISTICS 2 5 PULSE DURATION 80us DUTY CYCLE 0 5 MAX 2 0 1 5 1 0 Vas 10V Ip 75A NORMALIZED DRAIN TO SOURCE ON RESISTANCE 80 40 0 40 80 120 160 Ty JUNCTION TEMPERATURE C FIGURE 9 NORMALIZED DRAIN TO SOURCE ON RESISTANCE vs JUNCTION TEMPERATURE 200 las AVALANCHE CURRENT A 1000
5. T TTTTTTIT T IfRzO L Iag 1 3 RATED BVpss Vpp IfRzO L R IN Iag R 1 3 RATED BVpss 0 001 0 01 0 1 1 10 tay TIME IN AVALANCHE ms NOTE Refer to Intersil Application Notes AN9321 and AN9322 FIGURE 6 UNCLAMPED INDUCTIVE SWITCHING CAPABILITY Ip DRAIN CURRENT A NORMALIZED GATE THRESHOLD VOLTAGE 150 120 90 60 30 PULSE DURATION 801s DUTY CYCLE 0 5 MAX 25 C 0 1 2 3 4 Vps DRAIN TO SOURCE VOLTAGE V FIGURE 8 SATURATION CHARACTERISTICS 1 2 Ves Ip 2504A E o o 80 40 0 40 80 120 160 200 Ty JUNCTION TEMPERATURE C FIGURE 10 NORMALIZED GATE THRESHOLD VOLTAGE vs JUNCTION TEMPERATURE 4 intersil HUF75542P3 HUF75542S3S Typical Performance Curves Continued 10000 Vas OV f 1MHz 1 Ciss Cas 1 Ip 2504A 1000 CAPACITANCE pF NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE 0 8 100 80 40 0 40 80 120 160 200 0 1 1 10 80 Ty JUNCTION TEMPERATURE C Vps DRAIN TO SOURCE VOLTAGE V FIGURE 11 NORMALIZED DRAIN TO SOURCE BREAKDOWN FIGURE 12 CAPACITANCE vs DRAIN TO SOURCE VOLTAGE VOLTAGE vs JUNCTION TEMPERATURE WAVEFORMS IN DESCENDING ORDER Ip 75A Ip 50A
6. 3 12 13 8 S1BMOD 52 6 15 14 13 S2ZAMOD S2B 13 15 14 13 S2BMOD VBAT 22 19 DC 1 LGATE RLGATE rev 15 Feb 2000 CA DPLCAP 5 10 RSLC1 51 RSLC2 i ESLC 50 RDRAIN oo EVTHRES 14 19 EVTEMP ERE H ET 9 20 MSTRO IN 8 S1A 9 52 12 13 14 15 8 13 S1B 9 9 S2B 13 CB i 14 cos es 1 ESLC 51 50 VALUE V 5 51 ABS V 5 51 PWR V 5 51 1e 6 230 2 5 MMED DBREAK 11 EBREAK MWEAK RSOURCE RBREAK 17 RVTHRES LDRAIN RLDRAIN DBODY LSOURCE RLSOURCE 18 RVTEMP 19 22 MODEL DBODYMOD D IS 2 5e 12 RS 2 85 3 XTI 5 5 TRS1 2e 3 TRS2 1e 6 CJO 3 2e 9 TT 5 5e 8 M 0 6 MODEL DBREAKMOD D RS 2 9e 1 TRS1 1e 3 TRS2 1e 6 MODEL DPLCAPMOD D CJO 3 4e 9 IS 1e 30 M 0 8 N 10 MODEL MMEDMOD NMOS VTO 3 06 KP 4 8 IS 1 30 N 10 TOX 11 tu MODEL MSTROMOD NMOS VTO 3 5 KP 80 IS 1e 30 N 10 TOX 1 MODEL MWEAKMOD NMOS VTO 2 67 KP 0 08 IS 1e 30 N 10 TOX MODEL RBREAKMOD RES TC1 1 3e 3 TC2 9e 7 MODEL RDRAINMOD RES TC1 1 1e 2 TC2 2 5e 5 MODEL RSLCMOD RES TC1 4 5e 3 TC2 1e 5 MODEL RSOURCEMOD RES TC1 0 TC2 0 MODEL RVTHRESMOD RES TC1 2 5e 3 TC2 1 1e 5 MODEL RVTEMPMOD RES TC1 2 75e 3 TC2 0 MODEL S1AMOD VSWITCH MODEL S1BMOD VSWITCH RON 1e 5 ROFF 0 1 VON RON 1e 5 ROFF 0 1 VON 4 5 VOFF 6 0 1 1L 6 0 VOFF 4 5 MODEL S2AMO
7. 5 1 15 1 39 4 5 Lo bo 0 310 7 88 2 Y 0 018 0 022 0 46 0 55 4 5 FE L4 0 405 0 425 10 29 10 79 Y 1 lp E 0 395 0 405 10 04 10 28 b b N 0 100 2 54 7 gt lt lt gt 1 0 200 BSC 5 08 BSC 7 lt el Koh H4 0 045 0 055 1 15 1 39 TERM 4 4 0 095 0 105 242 2 66 y L 0 175 0 195 4 45 4 95 L4 0 090 0 110 2 29 2 79 4 6 0 350 Lo 0 050 0 070 1 27 1 77 3 8 89 0 315 8 01 2 0 700 d NOTES 17 78 1 These dimensions are within allowable dimensions of Rev C of JEDEC TO 263AB outline dated 2 92 0 150 2 L3 and bo dimensions established a minimum mounting surface 3 81 for terminal 4 Y MINIMUM PAD SIZE RECOMMENDED FOR SURFACE MOUNTED APPLICATIONS 1 5mm DIA HOLE Solder finish uncontrolled in this area 3 0 080 2 03 gt 4 0 062 TYP 1 58 7 Dimension without solder Add typically 0 002 inches 0 05mm for solder plating L4 is the terminal length for soldering Position of lead to be measured 0 120 inches 3 05mm from bottom of dimension D Controlling dimension Inch Revision 10 dated 5 99 TO 263AB 24mm TAPE AND REEL GENERAL INFORMATION 1 800 PIECES PER REEL 2 ORDER IN MULTIPLES OF FULL REELS ONLY 3 MEETS EIA 481 REVISION A SPECIFICATIONS COVER TAPE 40mm MIN ACCESS HOLE gt 30 4mm 10 intersil HUF75542P3 HUF75542S3S TO 220AB 3 LEAD JED
8. D VSWITCH RON 1e 5 ROFF 0 1 VON 0 5 VOFF 0 5 MODEL S2BMOD VSWITCH RON 1e 5 ROFF 0 1 VON 0 5 VOFF 0 5 ENDS DRAIN SOURCE 3 NOTE For further discussion of the PSPICE model consult A New PSPICE Sub Circuit for the Power MOSFET Featuring Global Temperature Options IEEE Power Electronics Specialist Conference Records 1991 written by William J Hepp and C Frank Wheatley 7 intersil HUF75542P3 HUF75542S3S SABER Electrical Model REV 15 Feb 00 template huf75542p3 n2 n1 n3 electrical n2 n1 n3 var i iscl dp model dbodymod is 2 5e 12 rs 2 85e 3 xti 5 5 trs1 2 3 1 52 1e 6 cjo 3 2e 9 tt 5 5e 8 m 0 6 dp model dbreakmod rs 2 9e 1 trs1 1e 3 trs2 1e 6 dp model dplcapmod cjo 3 4e 9 is 1 30 m 0 8 nl 10 m model mmedmod type _n vto 3 06 kp 4 8 is 1e 30 tox 1 m model mstrongmod type _n vto 3 5 kp 80 is 1e 30 tox 1 m model mweakmod type n vto 2 67 kp 0 08 is 1e 30 tox 1 LDRAIN Sw vcsp model s1amod ron 1e 5 roff 0 1 von 6 0 voff 4 5 DPLCAP 5 DRAIN Sw vcsp model s1bmod ron 1 5 roff 0 1 von 4 5 voff 6 0 wee 2 sw_vcsp model s2amod ron 1 5 roff 0 1 von 0 5 voff 0 5 10 sw vcsp model s2bmod ron 16 5 roff 0 1 von 0 5 voff 0 5 RSLC1 RLDRAIN Geb nIS nid 426 9 c cb n15 n14 4 2e c cin n6 n8 2 5e 9 ISL dp dbody n7
9. EC TO 220AB PLASTIC PACKAGE iiu TERM 4 gt J INCHES MILLIMETERS SYMBOL MIN MAX MIN MAX NOTES 0170 0480 432 457 A1 0 048 0 052 1 22 1 32 b 0 030 0 034 0 77 0 86 3 4 b4 0 045 0 055 1 15 1 39 2 3 0 014 0 019 0 36 0 48 2 3 4 D 0 590 0 610 14 99 15 49 D4 2 0 160 4 06 0 395 0 410 10 04 10 41 5 Ey z 0 030 0 76 0 100 2 54 5 1 0 200 BSC 5 08 BSC 5 H4 0 235 0 255 5 97 6 47 J4 0 100 0 110 2 54 2 79 6 L 0 530 0 550 13 47 13 97 Ly 0 130 0 150 3 31 3 81 2 0 149 0 153 3 79 3 88 0 102 0 112 2 60 2 84 NOTES 1 CO These dimensions are within allowable dimensions of Rev J of JEDEC TO 220AB outline dated 3 24 87 Lead dimension and finish uncontrolled in L4 Lead dimension without solder Add typically 0 002 inches 0 05mm for solder coating Position of lead to be measured 0 250 inches 6 35mm from bot tom of dimension D Position of lead to be measured 0 100 inches 2 54mm from bot tom of dimension D Controlling dimension Inch Revision 2 dated 7 97 All Intersil semiconductor products are manufactured assembled and tested under ISO9000 quality systems certification Intersil semiconductor products are sold by description only Intersil Corporation reserves the right to make changes in circuit design and or spec
10. Ip 25A Vas GATE TO SOURCE VOLTAGE V 0 20 40 60 80 100 Qg GATE CHARGE nC NOTE Refer to Intersil Application Notes AN7254 and AN7260 FIGURE 13 GATE CHARGE WAVEFORMS FOR CONSTANT GATE CURRENT Test Circuits and Waveforms Vps BVpss VARY tp TO OBTAIN REQUIRED PEAK lAs Ves tp ov tav FIGURE 14 UNCLAMPED ENERGY TEST CIRCUIT FIGURE 15 UNCLAMPED ENERGY WAVEFORMS 5 intersil HUF75542P3 HUF75542S3S Test Circuits and Waveforms continued DUT Ig REF FIGURE 16 GATE CHARGE TEST CIRCUIT Vas DUT FIGURE 18 SWITCHING TIME TEST CIRCUIT Ig REF 0 FIGURE 17 GATE CHARGE WAVEFORMS PULSE WIDTH FIGURE 19 SWITCHING TIME WAVEFORM 6 intersil HUF75542P3 HUF75542S3S PSPICE Electrical Model SSUBCKT HUF75542P3 213 CA 128 4 4e 9 CB 15 14 4 2e 9 CIN 6 8 2 5e 9 DBODY 7 5 DBODYMOD DBREAK 5 11 DBREAKMOD DPLCAP 10 5 DPLCAPMOD EBREAK 11 7 17 1887 2 EDS 14 8 5 81 EGS 138 6 81 ESG 610681 EVTHRES 6 21 198 1 EVTEMP 20 6 18 22 1 IT 8 17 1 LDRAIN 2 5 1 0e 9 LGATE 1 92 6e 9 GATE LSOURCE 3 7 1 1e 9 10 MMED 16 6 8 8 MMEDMOD MSTRO 16 6 8 8 MSTROMOD MWEAK 16 21 8 8 MWEAKMOD RBREAK 17 18 RBREAKMOD 1 RDRAIN 50 16 RDRAINMOD 5 5e 3 RGATE 9 20 1 0 RLDRAIN 2 5 10 RLGATE 1 9 26 RLSOURCE 3 7 11 RSLC1 5 51 RSLCMOD 1 6 RSLC2 5 50 1e3 RSOURCE 8 7 RSOURCEMOD 3 3e 3 RVTHRES 22 8 RVTHRESMOD 1 RVTEMP 18 19 RVTEMPMOD 1 S1A 6 12 13 8 S1AMOD S1B 1
11. aer i open IDM Figure 4 Pulsed Avalanche Rating UIS Figures 6 14 15 Power Dissipation eee dae hee a Reb geese Pp 230 D rate Above 25 C sesto p 1 54 w c Operating and Storage Ty TstG 55 to 175 oc Maximum Temperature for Soldering Leads at 0 063in 1 6mm from Case for 106 TL 300 Package Body for 10s See Techbrief 4 Tpkg 260 C NOTE 1 Ty 25 C to 150 C CAUTION Stresses above those listed in Absolute Maximum Ratings may cause permanent damage to the device This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied 1 CAUTION These devices are sensitive to electrostatic discharge Follow proper ESD Handling Procedures UltraFET is a trademark of Intersil Corporation PSPICE is a registered trademark of MicroSim Corporation 1 888 INTERSIL or 321 724 7143 Intersil and Design is a trademark of Intersil Corporation Copyright intersil Corporation 2000 SABERG is a Copyright of Analogy Inc HUF75542P3 HUF75542S3S Electrical Specifications 25 C Unless Otherwise Specified
12. ifications at any time with out notice Accordingly the reader is cautioned to verify that data sheets are current before placing orders Information furnished by Intersil is believed to be accurate and reliable However no responsibility is assumed by Intersil or its subsidiaries for its use nor for any infringements of patents or other rights of third parties which may result from its use No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries For information regarding Intersil Corporation and its products see web site www intersil com Sales Office Headquarters NORTH AMERICA EUROPE Intersil Corporation Intersil SA P O Box 883 Mail Stop 53 204 Mercure Center Melbourne FL 32902 100 Rue de la Fusee TEL 321 724 7000 1130 Brussels Belgium FAX 321 724 7240 TEL 32 2 724 2111 FAX 32 2 724 22 05 ASIA Intersil Ltd 8F 2 96 Sec 1 Chien kuo North Taipei Taiwan 104 Republic of China TEL 886 2 2515 8508 FAX 886 2 2515 8369 11 intersil
13. l v n51 n50 v n5 n51 1e 9 abs v n5 n51 abs v n5 n51 1e6 230 2 5 8 intersil HUF75542P3 HUF75542S3S SPICE Thermal Model REV 15 Feb 00 175542 CTHERM th 6 4 1e 3 CTHERM2 6 5 5 5e 3 CTHERNG 5 4 8 3 CTHERMA 4 3 1 5e 2 CTHERMS 3 2 1 6e 2 CTHERM6 2 tl 6 5e 2 RTHERM1 th 6 2 0e 4 2 6 5 3 5e 3 RTHERMS 5 4 2 5e 2 RTHERM4 4 3 9 0e 2 RTHERMS 3 2 1 6e 1 RTHERM6 2 tl 2 3e 1 SABER Thermal Model SABER thermal model t75542 template thermal model th tl thermal c th tl ctherm ctherm1 th 6 4 1 3 ctherm ctherm2 6 5 5 5e 3 ctherm ctherm3 5 4 8 6e 3 ctherm ctherm4 4 3 1 5e 2 ctherm ctherm5 3 2 1 6e 2 ctherm ctherm6 2 tl 6 5e 2 rtherm rtherm1 th 6 2 0e 4 rtherm rtherm2 6 5 3 5e 3 rtherm rtherm3 5 4 2 5e 2 rtherm rtherm4 4 3 9 0e 2 rtherm rtherm5 2 1 6e 1 rtherm rtherm6 2 tl 2 3e 1 RTHERM1 RTHERM2 RTHERM4 RTHERMS5 6 JUNCTION CTHERM1 CTHERM2 CTHERM3 CTHERM4 5 CTHERM6 9 intersil HUF75542P3 HUF75542S3S TO 263AB SURFACE MOUNT TO 263AB PLASTIC PACKAGE lt m A gt 5 MILLIMETERS x gt A1 SYMBOL MIN MAX MIN MAX NOTES 0 170 0 180 4 32 4 57 4 A1 0 048 0 052 1 22 1 32 4 5 D b 0 030 0 034 0 77 0 86 4 5 by 0 045 0 05
14. n5 model dbodymod 50 DBREAK dp dbreak n5 n11 model dbreakmod 2 dp dplcap n10 n5 model dplcapmod ESG ARRAN 11 iitn8 n17 1 T ea ERI LGATE EVTEMP NERIS DBODY l ldrain n2 n5 1e 9 GATE RGATE 16 ligate n1 n9 2 6e 9 1 6 z e I MMED EBREAK l source n3 n7 1 1e 9 SIGE 20 e m mmed n16 n6 n8 n8 model mmedmod 1 w 1u CIN LSOURCE SOURCE m mstrong n16 n6 n8 n8 model mstrongmod I 1u w 1u 8 7 SE 53 m mweak n16 n21 n8 n8 model mweakmod I 1u w 1u RSOURCE ied res rbreak n17 n18 1 tc1 1 3e 3 tc2 9e 7 1 9 S2A res rdrain n50 n16 5 5e 3 tcl 1 1e 2 tc2 2 5e 5 12 15 RBREAK res rgate n9 n20 1 0 13 1 17 18 res ridrain n2 n5 10 res rlgate n1 n9 26 S1B o o S2B RVTEMP res rlsource n3 n7 11 13 CB 19 res rslc1 n5 n51 1e 6 tcl 4 5e 3 tc2 16 5 CA NET 4 res rsic2 n5 n50 163 res rsource n8 n7 3 3e 3 tc1 0 tc2 0 EGS EDS res rvtemp n18 n19 1 tcl 2 75e 3 tc2 0 res rvthres n22 n8 1 tc1 2 5e 3 tc2 1 1 5 8 22 RVTHRES Spe ebreak n11 n7 n17 n18 87 2 spe eds n14 n8 n5 n8 1 spe egs n13 n8 n6 n8 1 spe esg n6 n10 n6 n8 1 Spe evtemp n20 n6 n18 n22 1 spe evthres n6 n21 n19 n8 1 Sw vcsp s1a n6 n12 n13 n8 model s1amod sw vcsp sib n13 n12 n13 n8 model s1bmod Sw vcsp s2a n6 n15 n14 n13 model s2amod Sw vcsp s2b n13 n15 n14 n13 model s2bmod v vbat n22 n19 dc 1 equations i n51 gt n50 iscl isc
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