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ANALOG DEVICES AD625 handbook

1. 0 1 0 2 0 3 0 40 5 0 6 0 7 0 8 0 WARM UP TIME Minutes Figure 7 Offset Voltage RTI Turn On Drift REV D 20 OUTPUT VOLTAGE SWING V Typical Performance Characteristics AD625 0 5 10 15 SUPPLY VOLTAGE V 20 Figure 2 Output Voltage Swing VS nN o POWER RESPONSE V p p 3 Supply Voltage a 10k 100k FREQUENCY Hz Figure 5 Large Signal Frequency Response 160 140 100 POWER SUPPLY REJECTION dB Vs 15V dc V p p SINE 0 10 100 1k 10k FREQUENCY Hz 100k Figure 8 Negative PSRR vs Frequency GAIN POWER SUPPLY REJECTION dB OUTPUT VOLTAGE SWING V p p nN o o aa 0 10 100 1k 10k LOAD RESISTANCE Q Figure 3 Output Voltage Swing vs Load Resistance 100k FREQUENCY Hz Figure 6 Gain vs Frequency Vg 15V dc V p p SINEWAVE 0 10 100 1k 10k 100k FREQUENCY Hz Figure 9 Positive PSRR vs Frequency INPUT CURRENT nA o 30 40 1235 75 235 235 75 125 TEMPERATURE C Figure 10 Input Bias Current vs Figure 11 Overrange and Gain Figure 12 Gain Overrange Recovery Temperature Switching Test Circuit G 8 G
2. STATUS D ANALOG dy oT O D INPUT AD574A SIGNAL CONVERTER OOOO O22 icine ae l lt o DIGITAL COMMON ANALOG POWER GROUND Figure 34 Basic Grounding Practice for a Data Acquisition System REV D 11 AD625 GROUND RETURNS FOR BIAS CURRENTS Input bias currents are those currents necessary to bias the input transistors of a dc amplifier There must be a direct return path for these currents otherwise they will charge external capaci tances causing the output to drift uncontrollably or saturate Therefore when amplifying floating input sources such as transformers or ac coupled sources there must be a dc path from each input to ground as shown in Figure 35 Vs O TO POWER SUPPLY GROUND Figure 35a Ground Returns for Bias Currents with Transformer Coupled Inputs Vs 9 Figure 35b Thermocouple Input TO POWER 100k SUPPLY GROUND Figure 35c Ground Returns for Bias Currents with AC Coupled Inputs AUTOZERO CIRCUITS In many applications it is necessary to maintain high accuracy At room temperature offset effects can be nulled by the use of offset trimpots Over the operating temperature range however offset nulling becomes a problem For these applications the autozero circuit of Figure 36 provides a hardware solution OTHER CONSIDERATIONS One of the more overlooked problems in designing ultralow drift dc amplifiers is thermo
3. AD7524 8 BIT DAC 3 Figure 30 Software Controllable Offset An instrumentation amplifier can be turned into a voltage to current converter by taking advantage of the sense and reference inals as shown in Figure 31 G Figure 31 Voltage to Current Converter By establishing a reference at the low side of a current setting resistor an output current may be defined as a function of input voltage gain and the value of that resistor Since only a small current is demanded at the input of the buffer amplifier A1 the forced current I will largely flow through the load Offset and drift specifications of A2 must be added to the output offset and drift specifications of the In Amp INPUT AND OUTPUT OFFSET VOLTAGE Offset voltage specifications are often considered a figure of merit for instrumentation amplifiers While initial offset may be adjusted to zero shifts in offset voltage due to temperature variations will cause errors Intelligent systems can often correct for this factor with an autozero cycle but this requires extra circuitry REV D Offset voltage and offset voltage drift each have two compo in distributed stray capacitances In many applications shielded nents input and output Input offset is that component of offset cables are used to minimize noise This technique can create that is generated at the input stage Measured at the output it is directly proportional to gain i e input offset as mea
4. Rx Rp and Rg then the resis tor values will match exactly Rri y2 7 6 Round T t is advised to carry ag many all the values can be used to cafcul heneces y e be set of gains This formula yields a network with a total resistance of 40 kQ A dummy variable j serves as a counter to keep a AD75xx running total of the preceding feedback resistors To illustrate how the formula can be applied an example similar to the calculation used for the resistor network in Figure 38 is exam ined below TO GAIN SENSE TO GAIN SENSE PIN 2 PIN 15 1 Unity gain is treated as a separate case It is implemented 20k 20k with separate 20 kQ feedback resistors as shown in Figure 41 CONNECTIE UNITY CONNECTIE UNIV It is then ignored in further calculations GAINS DESIRED SAINTS DESIRED TO GAIN DRIVE TO GAIN DRIVE 2 Before making any calculations it is advised to draw a resistor PIN 5 PIN 12 network similar to the network in Figure 41 The network will have 2 x M 1 resistors where M number of gains For Figure 38 M 3 4 16 64 therefore the resistor string will have seven resistors plus the two 20 kQ side resistors for unity gain Figure 41 Resistors for a Gain Setting Network 14 REV D OUTLINE DIMENSIONS Dimensions shown in inches and mm 16 Lead Plastic DIP N 16 16 Lead Ceramic DIP D 16 0 755 19 18 0 430 a 0 745 18 93 W 10 922 gt o 040r 16 0
5. 1 o x i x VOLT NSD nV V Hz NOISE SPECTRAL DENSITY fA V Hz AMPLIFIER QUIESCENT CURRENT pA 0 5 20 1 10k 100k SUPPLY VOLTAGE V FREQUENCY Hz FREQUENCY Hz Figure 13 Quiescent Current vs Figure 14 RTI Noise Spectral Figure 15 Input Current Noise Supply Voltage Density vs Gain dle L Ja i i m hin i en Bb wha oe i Figure 16 Low Frequency Voltage Figure 17 Noise Test Circuit Figure 18 Low Frequency Voltage Noise G 1 System Gain 1000 Noise G 1000 System Gain 100 000 6 REV D oe a 21 AOA Se FEF eb ae leer Nit ee VT TY a A ALLJ LLL e e EE U E EEEREN Sonia EDn sos E ae 10 20 30 40 50 60 70 Figure 19 Large Signal Pulse See eee Figure 21 Large Signal Pulse Response and Settling Time G 1 Figure 20 Settling Time to 0 01 Response and Settling Time G 100 yr TTT BEJE ee Ses oes ee Ea Ni E KE Ey Fh Ea U Ce ae a ole Tt fT Ee 0 eS N PT TT Te yy TT ES eragtne Pes se BERR ESRI Figure 2 se Response an tt Time G REV D 7 AD625 THEORY OF OPERATION The AD625 is a monolithic instrumentation amplifier based on a modification of the classic three op amp approach Monolithic construction and laser wafer trimming allow the tight matching and tracking of circuit components This insures the
6. vs Temperature 20 50 50 10 25 40 10 15 uV C Offset Referred to the Input vs Supply G 1 70 75 75 85 80 90 dB G 10 85 95 90 100 95 105 dB G 100 95 100 105 110 110 120 dB G 1000 100 110 110 120 115 140 dB INPUT CURRENT Input Bias Current 20 25 nA vs Temperature 50 pA C Input Offset Gur 1 Ci nA vs meme AN AVE 20 pA C INPUT Input Impedance Differential Resistance 1 1 1 GQ Differential Capacitance 4 4 4 pF Common Mode Resistance 1 1 1 GQ Common Mode Capacitance 4 4 4 pF Input Voltage Range Differ Input Linear Vpr 10 10 10 V Common Mode Linear Vey 12V e x Vp 12V e x Vp 12V e x Vp Common Mode Rejection Ratio dc to 60 Hz with 1 KQ Source Imbalance G 1 70 75 75 85 80 90 dB G 10 90 95 90 105 100 115 dB G 100 100 105 105 115 110 125 dB G 1000 110 115 110 125 120 140 dB OUTPUT RATING 10 V 10 V 10 V 5 mA 5 mA 5mA DYNAMIC RESPONSE Small Signal 3 dB G 1 Rp 20 kQ 650 650 650 kHz G 10 400 400 400 kHz G 100 150 150 150 kHz G 1000 25 25 25 kHz Slew Rate 5 0 5 0 5 0 V us Settling Time to 0 01 20 V Step G 1 to 200 15 15 15 us G 500 35 35 35 us G 1000 75 75 75 us 2 REV D AD625 AD625A J S AD625B K AD625C Model Min Typ Max Min Typ Max Min Typ Max Unit NOISE Voltage Noise 1 kHz RTL 4 4 4 nV VHz R T O 75 75 75 nV VHz R T I 0 1 Hz to 10 Hz G 1 10 10 10 uV p p G 10 1 0 1 0 1 0 uV p p G 100 0 3 0 3 0 3 uV p p G 1000 0 2 0 2 0 2 uV p p Current Noise 0
7. 1 Hz to 10 Hz 60 60 60 pA p p SENSE INPUT Rw 10 10 10 kQ In 30 30 30 uA Voltage Range 10 10 10 V Gain to Output 1 0 01 1 0 01 1 0 01 REFERENCE INPUT Rw 20 20 20 kQ In 30 30 30 uA Voltage Range 10 10 10 V Gain to Output 1 0 01 1 0 01 1 0 01 TEMPERATURE RANGE Specified Performance J K Grades 0 70 0 70 C A B C Grades 40 85 40 85 0 85 C S Grade 125 C Storage 150 65 5 150 C POWER S L C Power Supply Range 6 to 18 6 to 18 6 to 18 V Quiescent Current 3 5 5 3 5 5 3 5 5 mA NOTES 1Gain Error and Gain TC are for the AD625 only Resistor Network errors will add to the specified errors Vpz is the maximum differential input voltage at G 1 for specified nonlinearity Vpr at other gains 10 V G Vp actual differential input voltage Example G 10 Vp 0 50 Vey 12 V 10 2 x 0 50 V 9 5 V Specifications subject to change without notice All min and max specifications are guaranteed Specifications shown in boldface are tested on all production units at final electrical test Results from those tests are used to calculate outgoing quality levels REV D AD625 ABSOLUTE MAXIMUM RATINGS Supply Voltage oee sci care cow ah e eace eae testte 18 V Internal Power Dissipation 05 450 mW Input Voltages ee cock ion cscetiuie we se ee eae oe Pa tVs Differential Input Voltage 0 eee eee eee tVs Output Short Circuit Duration Ind
8. 1 and 10 000 with completely user selected gain steps For the highest precision the AD625C offers an input offset voltage drift of less than 0 25 uV C output offset drift below 15 pV C and a maximum nonlinearity of 0 001 at G 1 All grades exhibit excellent ac performance a 25 MHz gain band width product 5 V us slew rate and 15 us settling time The AD625 is available in three accuracy grades A B C for industrial 40 C to 85 C temperature range two grades J K for commercial 0 C to 70 C temperature range and one S grade rated over the extended 55 C to 125 C tempera ture range REV D Information furnished by Analog Devices is believed to be accurate and reliable However no responsibility is assumed by Analog Devices for its use nor for any infringements of patents or other rights of third parties which may result from its use No license is granted by implication or otherwise under any patent or patent rights of Analog Devices REFERENCE PRODUCT HIGHLIGHTS 1 The AD625 affords up to 16 bit precision for user selected fixed gains from 1 to 10 000 Any gain in this range can be er and a resistor programmed by 3 external resistors ho amplifier designs does not affect the gain 2 A 12 bit software programmablaga fier can be config ure usi OS network ing the accuracy 3 The gain accuracy and gain temperature coefficient of the amplifier circuit are prima
9. 16 Rr Rp 15 kQ Rp 3 75 kQ Rr 20 kQ Rr Rp Re 1 16 64 Ry Rr Rp 18 75 RQ Rp 937 5 Q 4 The center resistor Rg of the highest gain setting is deter mined last Its value is the remaining resistance of the 40 kQ string and can be calculated with the equation M Rg 40 kQ 2 Ry 1 4 16 64 256 1024 4096 j 0 GAIN Ro 40 kQ 2 Rg Re Re Rr Figure 40 Time to 0 01 of a 20 V Step Input for 40 RO 39 375 kQ 625 Q SPGA with AD625 5 If different resistor values are desired all the resistors in the network can be scaled by some convenient factor However DETERMINING SPGA RESISTOR NETWORK VALUES raising the impedance will increase the RTO errors lowering The individual resistors in the gain network can be calculated sequentially using the formula given below The equation deter mines the resistors as labeled in Figure 41 The feedback resis tors and the gain setting resistors are interactive therefore the formula must be a series where the present term is dependent on the preceding term s The formula the total network resistance below 20 kQ can result in ampli fier instability More information on this phenomenon is given in the RPGA section of the data sheet The scale factor will not affect the unity gain feedback resistors The resistor network in Figure 38 has a scaling factor of 650 625 1 04 if this factor is used on Rg
10. high level of performance inherent in this circuit architecture A preamp section Q1 Q4 provides additional gain to Al and A2 Feedback from the outputs of Al and A2 forces the collec tor currents of Q1 Q4 to be constant thereby impressing the input voltage across Rg This creates a differential voltage at the outputs of Al and A2 which is given by the gain 2Rg Rg 1 times the differential portion of the input voltage The unity gain subtracter A3 removes any common mode signal from the output voltage yielding a single ended output Vourn referred to the potential at the reference pin The value of Rg is the determining factor of the transconduc tance of the input preamp stage As Rg is reduced for larger gains the transconductance increases This has three important advantages First this approach allows the circuit to achieve a very high open loop gain of 3 x 10 at programmed gains gt 500 thus reducing gain related errors Second the gain bandwidth product which is determined by C3 C4 and the input trans conductance increases with gain thereby optimizing frequency response Third the input voltage noise is reduced to a value determined by the collector current of the input transistors 4 nV VHz INPUT PROTECTION Differential input es outside of their erations when applyi t continuous input current must be limited to less than 10 mA and 2 that input voltages must not exceed either supply by more t
11. 26 6 61 0 310 0 01 0 265 0 290 0 010 0 24 6 1 7 874 0 254 6 73 7 37 0 254 ATT F 0 306 7 78 4 PIN 1 0 294 7 47 PIN1 0 800 0 010 0 300 0 17 4 32 0 14 3 56 20 32 0 254 7 62 max y HHH HAHAH 0 12 3 05 ery zez B 0 889 0 254 wae a PLANE 0 095 emi i 0 085 2 159 12 3 05 ejja gt je He 0 012 0 305 0 180 0 03 F 0 02 0 508 0 015 2 67 0 065 1 66 0 008 0 203 0 125 3 175 A 4 57 0 762 0 075 0 381 0 095 2 42 0 045 7 15 aaa ie fan ied AR Percy 047 0 SEATING 010 0 1 19 0 18 0 017 oe PLANE 0 254 0 05 0 076 0 43 O08 0 100 254 BSC 0 700 17 78 BSC 20 Terminal Leadless Chip Carrier E 20A Y 0 025 0 003 F 0 635 0 075 0 040 x 45 1 02 x 45 REF 3 PLCS REV D 15 C00780c 0 6 00 rev D PRINTED IN U S A
12. 4 19 6 KQ 38 3 Q SENSE TERMINAL The sense terminal is the feedback point for the AD625 output amplifier Normally it is connected directly to the output If heavy load currents are to be drawn through long leads voltage drops through lead resistance can cause errors In these in stances the sense terminal can be wired to the load thus putting AD625 the I x R drops inside the loop and virtually eliminating this error source Typically IC instrumentation amplifiers are rated for a full 10 volt output swing into 2 KQ In some applications however the need exists to drive more current into heavier loads Figure 29 shows how a high current booster may be connected inside the loop of an instrumentation amplifier By using an external power boosting circuit the power dissipated by the AD625 will remain low thereby minimizing the errors induced by self heating The effects of nonlinearities offset and gain inaccura cies of the buffer are reduced by the loop gain of the AD625 s output amplifier Figure 29 AD625 Instrumentation Amplifier with Output Current Booster REFERENCE TERMINAL The reference terminal may be used to offset the output by up to 10 V This is useful when the load is floating or does not share a ground with the rest of the syste direct means of inj ise offset ev remembered that fth a winglis J ground to be shafted een signal and The AD625 reference terminal must be presented wi
13. ANALOG DEVICES Programmable Gain Instrumentation Amplifier FUNCTIONAL BLOCK DIAGRAM FEATURES User Programmed Gains of 1 to 10 000 Low Gain Error 0 02 Max Low Gain TC 5 ppm C Max Low Nonlinearity 0 001 Max Low Offset Voltage 25 pV Low Noise 4 nV VHz at 1 kHz RTI Gain Bandwidth Product 25 MHz 16 Lead Ceramic or Plastic DIP Package 20 Terminal LCC Package Standard Military Drawing Available MIL Standard Parts Available Low Cost PRODUCT DESCRIPTION The AD625 is a precision instrumentation amplifier specifically designed to fulfill two major areas of application 1 Circuits re quiring nonstandard gains i e gains not easily achievable with devices such as the AD524 and AD624 iring low cost igi ifi For low noi JNiis the most cost e available An additional three resistors allow the user to set any gain from 1 to 10 000 The error contribution of the AD625JN is less than 0 05 gain error and under 5 ppm C gain TC performance limitations are primarily determined by the external resistors Common mode rejection is independent of the feedback resistor matching A software programmable gain amplifier SPGA can be config ured with the addition of a CMOS multiplexer or other switch network and a suitable resistor network Because the ON resistance of the switches is removed from the signal path an AD625 based SPGA will deliver 12 bit precision and can be programmed for any set of gains between
14. C 16 Lead Ceramic DIP D 16 Standard Military Drawing Available CAUTION ESD non AVAYAL de BDH G co accumulate on the human body and test equipment and can discharge without detection Although the AD625 features proprietary ESD protection circuitry permanent damage may occur on devices subjected to high energy electrostatic discharges Therefore proper ESD precautions are recommended to avoid performance degradation or loss of functionality ESD SENSITIVE DEVICE PIN CONNECTIONS Ceramic DIP D and Plastic DIP N Packages INPUT 1 GAIN SENSE 2 GAIN DRIVE 5 Not to Scale 12 INPUT TOP VIEW NC NO CONNECT 15 GAIN SENSE RTO NULL RTO NULL GAIN DRIVE Leadless Chip Carrier E Package W W on on Z zZ W W Op rO z2 Z lt lt O Z 95259 3 2 1 2019 RTI NULL 4 18 RTO NULL RTI NULL 5 AD625 17 RTO NULL NC6 16 NC TOP VIEW Not to Scale 15 GAIN NULL 14 SENSE GAIN DRIVE7 NC8 9 10 11 12 13 H yee es 2 i va wi m m iva NC NO CONNECT REV D 20 15 10 INPUT VOLTAGE RANGE V 25 C 0 5 10 15 20 SUPPLY VOLTAGE V Figure 1 Input Voltage Range vs Supply Voltage G 1 CMRR dM 00 1 FREQUENCY Hz Figure 4 CMRR vs Frequency RTI Zero to 1 kQ Source Imbal ance AVog FROM FINAL VALUE pV o 7
15. couple induced offset In a circuit comprised of two dissimilar conductors i e copper kovar a current flows when the two junctions are at different tempera tures When this circuit is broken a voltage known as the Seebeck or thermocouple emf can be measured Standard IC lead material kovar and copper form a thermocouple with a 1 2 high thermoelectric potential about 35 uV C This means that care must be taken to insure that all connections especially those in the input circuit of the AD625 remain isothermal This includes the input leads 1 16 and the gain sense lines 2 15 These pins were chosen for symmetry helping to desensitize the input circuit to thermal gradients In addition the user should also avoid air currents over the circuitry since slowly fluctuating 10 Vout 9 o 0 1 F LOW LEAKAGE AD7510DIKD thermocouple voltages will appear as flicker noise In SPGA applications relay contacts and CMOS mux leads are both potential sources of additional thermocouple errors The base emitter junction of an input transistor can rectify out of band signals i e RF interference When amplifying small signals these rectified voltages act as small dc offset errors The AD625 allows direct access to the input transistors bases and emitters enabling the user to apply some first order filtering to these unwanted signals In Figure 37 the RC time constant should be chosen for desired attenuation
16. des for both input and output offset voltage adjustment This simplifies nulling in very high precision appli cations and minimizes offset voltage effects in switched gain Vs applications In such applications thd i ted Figure 33 Differential river first at the hig ed gain ther offget is adjusted at o single nu h input offset GROUNDI null should be used T ost additione herr using only orderto isofate low leyel analog si rom a noisy digital the input offset null is 0 9 uV C RTO environment many data acquisition components have two or more ground pins These grounds must eventually be tied to COMMON MODE REJECTION gether at one point It would be convenient to use a single Common mode rejection is a measure of the change in output ground line however current through ground wires and pc runs voltage when both inputs are changed by equal amounts These of the circuit card can cause hundreds of millivolts of error specifications are usually given for a full range input voltage Therefore separate ground returns should be provided to mini change and a specified source imbalance mize the current flow from the sensitive points to the system ground see Figure 34 Since the AD625 output voltage is developed with respect to the potential on the reference termi nal it can solve many grounding problems In an instrumentation amplifier degradation of common mode rejection is caused by a differential phase shift due to differences
17. ed SPGA with possible gains of 1 4 16 64 Rg equals the resistance between the gain sense lines Pins 2 and 15 of the AD625 In Figure 38 Rg equals the sum of the two 975 Q resistors and the 650 Q resistor or 2600 Q Rg equals the resistance between the gain sense and the gain drive pins Pins 12 and 15 or Pins 2 and 5 that is Rp equals the 15 6 kQ resistor plus the 3 9 KQ resistor or 19 5 KQ The gain therefore equals 2R P j 209 540 16 Rg 2 6kQ As the switches of the differential multiplexer proceed synchro nously Rg and Rg change resulting in the various programmed gain settings REV D 4 20k GAIN DRIVE C Figure 39 SPGA with Multiplexer Error Sources Figure 39 shows a complete SPGA feeding a 12 bit DAS with a 0 V 10 V input range This configuration was used in the error budget analysis shown in Table II The gain used for the RTI calculations is set at 16 As the gain is changed the ON resis tance of the multiplexer and the feedback resistance will change which will slightly alter the values in the table Table II Errors Induced by Multiplexer to an SPGA Induced Specifications Voltage Offset Error AD625C AD7520KN _Cal io Induced RTI RTIO 6 8 uV Voltag Si ce 40 nA RTI Offset Gain Sense Differential 60 nA x 6 8 Q 0 41 uV Voltage Current Switch 0 41 uV 60 nA Resistance 6 8 Q RTO Offset Feedback Differential 2 0 2 nA x 20 kQ 0 5 uV Vol
18. efinite Storage Temperature Range D E Storage Temperature Range N 65 C to 150 C 65 C to 125 C Operating Temperature Range AD625J K a wher by bickee uh pw hound apneaes 0 C to 70 C AD625A B C oonan 902 arn lather s yoi aioe 40 C to 85 C RING 25S soc Rer seach Cerne alae 55 C to 125 C 300 C Stresses above those listed under Absolute Maximum Ratings may cause perma nent damage to the device This is a stress rating only functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied Exposure to absolute maximum rating conditions for extended periods may affect device reliability ORDERING GUIDE Model Temperature Range Package Description Package Option AD625AD 40 C to 85 C 16 Lead Ceramic DIP D 16 AD625BD 40 C to 85 C 16 Lead Ceramic DIP D 16 AD625BD 40 C to 85 C 16 Lead Ceramic DIP D 16 AD625CD 40 C to 85 C 16 Lead Ceramic DIP D 16 AD625SD 55 C to 125 C 16 Lead Ceramic DIP D 16 AD625SD 883B 55 C to 125 C 16 Lead Ceramic DIP D 16 AD625SE 883B 55 C to 125 C 20 Terminal Leadless Chip Carrier E 20A AD625JN 0 C to 70 C 16 Lead Plastic DIP N 16 AD625KN 0 C to 70 C 16 Lead Plastic DIP N 16 AD625ACHIPS 40 C to 85 C Die AD625SCHIPS 55 C to 125 C Die 5962 87719012A 55 C to 125 C 20 Terminal Leadless Chip Carrier E 20A 5962 8771901EA 55 C to 125
19. ent The ON resistance of the switch should be included as part of Rg when calculating the necessary input protection resistance Figure 26c Input Protection Circuit 8 REV D Any resistors in series with the inputs of the AD625 will degrade the noise performance For this reason the circuit in Figure 26b should be used if the gains are all greater than 5 For gains less than 5 either the circuit in Figure 26a or in Figure 26c can be used The two 1 4 kQ resistors in Figure 26a will degrade the noise performance to 4bTRex 4nV Hz 7 9nV Hz RESISTOR PROGRAMMABLE GAIN AMPLIFIER In the resistor programmed mode Figure 27 only three exter nal resistors are needed to select any gain from 1 to 10 000 Depending on the application discrete components or a pretrimmed network can be used The gain accuracy and gain TC are primarily determined by the external resistors since the AD625C contributes less than 0 02 to gain error and under 5 ppm C gain TC The gain sense current is insensitive to common mode voltage making the CMRR of the resistor pro grammed AD625 independent of the match of the two feedback resistors Rp Selecting Resistor Values As previously stated each Rg provides feedback to the input stage and sets the unity gain transconductance These feedback resistors are provided by the user The AD625 is tested and specified with a value of 20 kQ for Rg Since the magnitude of RTO errors increases wi
20. han one diode drop approximately 0 6 V 25 C Under differential overload conditions there is Rg 100 Q in series with two diode drops approximately 1 2 V between the plus and minus inputs in either direction With no external protec tion and Rg very small i e 40 Q the maximum overload voltage the AD625 can withstand continuously is approximately 2 5 V Figure 26a shows the external components necessary to protect the AD625 under all overload conditions at any gain Vs INO GAIN GAIN SENSE SENSE Figure 25 Simplified Circuit of the AD625 The diodes to the supplies are only necessary if input voltages outside of the range of the supplies are encountered In higher gain applications where differential voltages are small back to back Zener diodes and smaller resistors as shown in Figure 26b provides adequate protection Figure 26c shows low cost FETs with a maximum ON resistance of 300 Q configured to offer input protection with minimal degradation to noise 5 2 nVNHz compared to normal noise performance of 4 nV Hz During differential overload conditions excess current will flow through the gain sense lines Pins 2 and 15 This will have no effect in fixed gain applications However if the AD625 is being used in an SPGA application with a CMOS multiplexer this current should be taken into consideration The current capa bilities of the multiplexer may be the limiting factor in allowable overflow curr
21. of the interfering signals In the case of a resistive transducer the capacitance alone work ing against the internal resistance of the transducer may suffice Figure 37 Circuit to Attenuate RF Interference REV D These capacitances may also be incorporated as part of the external input protection circuit see section on Input Protec tion As a general practice every effort should be made to match the extraneous capacitance at Pins 15 and 2 and Pins 1 and 16 to preserve high ac CMR SOFTWARE PROGRAMMABLE GAIN AMPLIFIER An SPGA provides the ability to externally program precision gains from digital inputs Historically the problem in systems requiring electronic switching of gains has been the ON resis tance Ron of the multiplexer which appears in series with the gain setting resistor Rg This can result in substantial gain errors and gain drifts The AD625 eliminates this problem by making the gain drive and gain sense pins available Pins 2 15 5 12 see Figure 39 Consequently the multiplexer s ON resistance is removed from the signal current path This transforms the ON resistance error into a small nullable offset error To clarify this point an error budget analysis has been performed in Table II based on the SPGA configuration shown in Figure 39 AD7502 TTL DTL TO CMOS LEVEL TRANSLATOR DECODER DRIVER i LS GAIN DRIVE Figure 38 SPGA in a Gain of 16 Figure 38 shows an AD625 bas
22. rily dependent on the user selected external resistors 4 The AD625 provides totally independent input and output offset nulling terminals for high precision applications This minimizes the effects of offset voltage in gain ranging applications 5 The proprietary design of the AD625 provides input voltage noise of 4 nV VHz at 1 kHz 6 External resistor matching is not required to maintain high common mode rejection One Technology Way P O Box 9106 Norwood MA 02062 9106 U S A Tel 781 329 4700 World Wide Web Site http www analog com Fax 781 326 8703 Analog Devices Inc 2000 AD625 SPEC FI CATI 0 NS typical Vs 15 V R 2 kQ and T 25 C unless otherwise noted AD625A J S AD625B K AD625C Model Min Typ Max Min Typ Max Min Typ Max Unit GAIN 2 Rp 2 Rp 2 Rr Gain Equation Res 1 Ro 1 Ro 1 Gain Range 1 10 000 1 10 000 1 110 000 Gain Error 035 0 05 0 02 0 03 0 01 0 02 Nonlinearity Gain 1 256 0 005 0 002 0 001 Gain gt 256 0 01 0 008 0 005 Gain vs Temp Gain lt 1000 5 5 5 ppm C GAIN SENSE INPUT Gain Sense Current 300 500 150 250 50 100 nA vs Temperature 5 20 2 15 2 10 nA C Gain Sense Offset Current 150 500 75 250 50 100 nA vs Temperature 2 15 1 10 2 10 nA C VOLTAGE OFFSET May be Nulled Input Offset Voltage 50 200 25 50 10 25 uV vs Temperature 1 2 2 0 25 0 50 1 0 1 0 25 uVv C Output Offset Voltage 5 2 3 1 2 mV
23. sured at the Vs output at G 100 is 100 times greater than that measured at G 1 Output offset is generated at the output and is constant for all gains The input offset and drift are multiplied by the gain while the output terms are independent of gain therefore input errors dominate at high gains and output errors dominate at low gains The output offset voltage and drift is normally specified at G 1 where input effects are insignificant while input offset Figure 32 Common Mode Shield Driver and drift is given at a high gain where output effects are negli gible All input related parameters are specified referred to the input RTD which is to say that the effect on the output is G times larger Offset voltage vs power supply is also specified as an RTT error common mode rejection errors unless the shield is properly driven Figures 32 and 33 show active data guards which are configured to improve ac common mode rejection by boot strapping the capacitances of the input cabling thus minimiz ing differential phase shift By separating these errors one can evaluate the total error inde pendent of the gain For a given gain both errors can be com bined to give a total error referred to the input RTT or output RTO by the following formula Total Error RTI input error output error gain INPUT O Vout Total Error RTO Gain x input error output error REFERENCE The AD625 provi
24. tage Resistance Leakage 8 uV 16 20 KQ Current Is 0 2 nA 0 2 nA RTO Offset Feedback Differential 2 1 nA x 20 kQ 2 5 uV Voltage Resistance Leakage 40 uV 16 20 kQ Current dour 1 nA 1 nA Total error induced by a typical CMOS multiplexer to an SPGA at 25 C 10 21 pA NOTES The resistor for this calculation is the user provided feedback resistance Rp 20 kQ is recommended value see Resistor Programmable Gain Amplifier section The leakage currents Is and Ioyr will induce an offset voltage however the offset will be determined by the difference between the leakages of each half of the differential multiplexer The differential leakage current is multiplied by the feedback resistance see Note 1 to determine offset voltage Because differential leakage current is not a parameter specified on multiplexer data sheets the most extreme difference one most positive and one most negative was used for the calculations in Table II Typical performance will be much better The frequency response and settling will be affected by the ON resistance and internal capacitance of the multiplexer Figure 40 shows the settling time vs ON resistance at different gain settings for an AD625 based SPGA xSwitch resistance and leakage current errors can be reduced by using relays 13 3 Begin all calculations with Gp 1 and Rp 0 Rp 20 kQ Rp 1 1 4 Rp 0 Rp 15 kQ Rg 20 kQ Rp Re 1 4
25. th increasing feedback resistance values much above 20 kQ are not recommended values below 10 kQ feedback re formula Rg Figure 27 AD625 in Fixed Gain Configuration A list of standard resistors which can be used to set some com mon gains is shown in Table I For single gain applications only one offset null adjust is neces sary in these cases the RTI null should be used REV D RTO NOISE RTO OFFSET VOLTAGE N E e 300 5 i zs Q 200 zZ A z f z2 lt 100 4 gt o gt 10k 20k 30k 40k 50k 60k FEEDBACK RESISTANCE Q 10k 20k 30k 40k 50k 60k FEEDBACK RESISTANCE Q BANDWIDTH RTO OFFSET VOLTAGE DRIFT 6 a gt 6 o x FREQUENCY Hz 2 MULTIPLYING FACTOR 1 10k 20k 30k 40k 50k 60k 1 10 100 1k FEEDBACK RESISTANCE Q FEEDBACK RESISTANCE Q Figure 28 RTO Noise Offset Drift and Bandwidth vs Feedback Resistance Normalized to 20 kQ Table I Common Gains Nominally Within 0 5 Error Using Standard 1 Resistors GAIN 3 Rg 0 co COMPADI Paa 0 10 kQ 10 20 kQ 4 42 KQ 20 20 kQ 2 1 kQ 50 19 6 kQ 806 Q 100 20 kQ 402 Q 200 20 5 kQ 205 Q 500 19 6 kQ 78 7Q 1000 19 6 kQ 39 2 Q 4 20 kQ 13 3 kQ 8 19 6 KQ 5 62 kQ 16 20 kQ 2 67 kQ 32 19 6 kQ 1 27 kQ 64 20 kQ 6349 128 20 kQ 316Q 256 19 6 kQ 154Q 512 19 6 kQ 76 8 Q 102
26. th nearly zero impedance Any significant resistance including those caused by PC layouts or other connection techniques will in crease the gain of the noninverting signal path thereby upset ting the common mode rejection of the in amp Inadvertent thermocouple connections created in the sense and reference lines should also be avoided as they will directly affect the out put offset voltage and output offset voltage drift In the AD625 a reference source resistance will unbalance the CMR trim by the ratio of 10 kQ Rpgegr For example if the refer ence source impedance is 1 Q CMR will be reduced to 80 dB 10 kQ 1 Q 80 dB An operational amplifier may be used to provide the low impedance reference point as shown in Figure 30 The input offset voltage characteristics of that amplifier will add directly to the output offset voltage performance of the instrumentation amplifier The circuit of Figure 30 also shows a CMOS DAC operating in the bipolar mode and connected to the reference terminal to provide software controllable offset adjustments The total offset range is equal to Vprer 2 xX R5 R4 however to be symmetri cal about 0 V R3 2 x R4 The offset per bit is equal to the total offset range divided by 25 where N number of bits of the DAC The range of offset for Figure 30 is 120 mV and the offset is incremented in steps of 0 9375 mV LSB 10 GND Vpp Vss O Vout REFERENCE MSB DATA INPUTS LSI

ANALOG DEVICES AD625 handbook

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