PHILIPS PDI1394P11A 3-port physical layer interface handbook(1)
Contents
1. VDD LINK LAYER CONTROLLER INTERFACE LINK LAYER CONTROLLER INTERFACE SV01074 Figure 3 External Component Connections CABLE POWER PAIR PDI1394P11 SV00236 Figure 4 Twisted pair cable interface connections 1999 Mar 10 10 Philips Semiconductors 3 port physical layer interface 17 1 Arbitrated short Bus Reset A 1394 1995 software initiated bus reset assumes that the state of the bus is unknown when reset occurs and requires that the reset be long enough to permit the longest transaction to finish and still complete reset 167s min to 250us max The total duration of bus initialization is longer than the nominal isochronous cycle time 125us and may disrupt two isochronous periods This compels device designers to add additional buffer depth to preserve the smooth flow of isochronous data from the perspective of their application If a node that initiates a reset arbitrates for control of the bus prior to asserting reset arbitration time can be shortened significantly 1 3us min to 80us max This 1394a concept is known as Arbitrated short Bus Reset and is incorporated in the PDI1394P11A The TESTM2 pin 21 pins is used to enable Arbitrated short Bus Reset mode In 1394 1995 mode this pin is tied high In this2. bus reset mode set TESTM1 high and TESTM2 low See section 17 1 for more information on ISBR mode 1999 Mar 10 13 Preliminary specification PDI1394P11A 18 9 Cable Power Status input CPS pin 23 This is normally connected to the cable power through an external resistor The circuit drives an internal comparator which is used to detect the presence of cable power This information is maintained in an internal register and is available to the link layer controller through a register read See section 17 2 for information on setting the CPS trip point 18 10 Bus or lsochronous Resource Manager Capable input or Link On output C LKON pin 27 On hardware reset this pin is used to set the default value of the contender status indicated during self ID The bit value programming is done by tying the pin through a 10 KQ resistor to Vpp high bus manager capable or to GND low not bus manager capable Using either a pull up or pull down resistor allows the link on output to override the input value when necessary After hardware reset this pin is used as an output to signal the reception of a Link On packet A 6 114 MHz signal is supplied until the LPS input is active at which point the C LKON output goes low 18 11 Power Class bits 0 through 2 inputs PC 0 2 pins 30 29 28 Used as inputs to set the bit values of the three Power Class bits in the self ID packet bits 21 22 and 23 These bits can be programmed by tying the p
3. erroneously powering up the part as is seen in some other Phys SYMBOL PARAMETER CONDITION source power node Vic too Common mode voltage source power node TPB cable inputs 100Mbit or speed signaling OFF TPB cable inputs 100Mbit or speed signaling OFF non source power node TPB cable inputs 200Mbit or speed signaling TPB cable inputs 200Mbit or speed signaling non source power node Vic 200sp Common mode voltage TPA TPB cable inputs 100Mbit operation Receive input jitter TPA TPB cable inputs 200Mbit operation Between TPA and TPB cable inputs 100Mbit operation Between TPA and TPB cable inputs 200Mbit Receive input skew operation o SYSCLK lo l utput current Io I OLOM SR Control Data CNA C LKON Crystal frequency Parallel resonant fundamental mode crystal 24 5735 24 576 24 5785 Operating ambient 7 temperature range in free air eQ Cc 1999 Mar 10 5 Philips Semiconductors Preliminary specification 3 port physical layer interface PDI1394P11A 9 0 ABSOLUTE MAXIMUM RATINGS 2 In accordance with the Absolute Maximum Rating System IEC 134 Voltages are referenced to GND ground OV LIMITS SYMBOL PARAMETER CONDITION V yv o DC input voltage Inputs CPS TPAn TPBn FILTER XI DD VI TE ee NOTES 1 Stresses beyond those listed may cause permanent damage to the device These are stress ratings only and functional operation of the device at t
4. PC 0 2 inputs cd o jm Ipu Pullup current RESET input r a E VDD Pulldown current RESET input PD high Power up reset time RESET input C 0 1 uf Positive arbitration comparator threshold voltage Vu Negative arbitration comparator threshold 168 mV TH voltage Speedsgnalmputthreshodvotage O O O f e f o Positive g input threshold voltage ae going input threshold voltage ove LREQ CTLn Dn inputs 999 Vop 2 0 12 Vo TPBIASn output voltage 1 665 2 015 na Absolute value of bus holding current _h 7 13 0 THERMAL CHARACTERISTICS LIMITS SYMBOL PARAMETER TEST CONDITION ee UNIT srmo paame La E a ROjA Junction to free air thermal resistance Board mounted no air flow Js ecw R jC _ Junction to case thermal resistance Tt Pec 1999 Mar 10 7 Philips Semiconductors Preliminary specification 3 port physical layer interface PDI1394P11A 14 0 AC SWITCHING CHARACTERISTICS SYMBOL PARAMETER Transmit jitter Transmit fall time 90 to 10 i Dn CTLn LREQ input setup time to SYSCLK 50 to 50 3 Dn CTLn LREQ input hold time a from SYSCLK 0 to 50 See Figure 1 Delay time SYSCLK to Dn CTLn 50 to 50 See Figure 2 2 15 0 SWITCHING WAVEFORMS SYSCLK SYSCLK 50 to Ln 50 Dn CTLn LREQ Dn CT SV00238 SV00239 Figure 1 Dn CTLn LREQ input setup and hold times Figure 2 Dn CTLn output delay relative to SYSCLK 1999 Mar 10 8 Philips Semiconductor
5. Right to make changes Philips Semiconductors reserves the right to make changes without notice in the products including circuits standard cells and or software described or contained herein in order to improve design and or performance Philips Semiconductors assumes no responsibility or liability for the use of any of these products conveys no license or title under any patent copyright or mask work right to these products and makes no representations or warranties that these products are free from patent copyright or mask work right infringement unless otherwise specified Philips Semiconductors Copyright Philips Electronics North America Corporation 1999 811 East Arques Avenue All rights reserved Printed in U S A P O Box 3409 Sunnyvale California 94088 3409 Date of release 03 99 Telephone 800 234 7381 Document order number 9397 750 05499 Lett make things beter ee PHILIPS
6. The optimum values for the external shunt capacitors are dependent on the specifications of the crystal used the suggested values of 12 pF are appropriate for one specified for 15 pF loads Philips Semiconductors 3 port physical layer interface 18 17 Current setting resistor R 0 1 pins 59 60 An internal reference voltage is applied across the resistor connected between these two pins to set the internal operating and the cable driver output currents A low TCR lt 150ppm C temperature coefficient with a value of 6 34 kQ 1 should be used to meet the 1394 standard output voltage limits 18 18 Isolation Barrier disable ISO pin 62 When ISO is high busholder circuits are enabled on the LREQ PD and LPS input pins and on the CTL and Data bidirectional pins This mode also allows isolation using a single 1nF capacitor per signal line Details for this kind of isolation can be found in the Philips Isolation Application Note AN2452 When ISO is low busholder circuits are disabled and isolation can be realized by using the scheme explained in Annex J of the 1394 1995 spec 18 19 Supply filters AVDD pins 24 25 51 55 DVDD pins 5 6 19 20 and PLLVDD pin 58 A combination of decoupling capacitors is suggested for each supply group such as paralleled 10 uF and 0 1 uF The high frequency 0 1 uF capacitors should be mounted as close as possible to the PDI1394P11A device supply leads These supply lines are separated
7. being sent from the phy to the link 10 Receive An incoming packet is being sent from the phy to the link Grant The link has been given control of the bus to send an outgoing packet When the link has control of the bus phy permission the CTL 0 1 lines are encoded as follows 1999 Mar 10 14 Preliminary specification PDI1394P11A DESCRIPTION OF ACTIVITY The link releases the bus transmission has been completed The link is holding the bus while data is being prepared for transmission or sending another packet without arbitrating Transmit An outgoing packet is being sent from the link to the phy 19 2 Request When the link layer controller wishes to request the bus or access a register that is located in the PDI1394P11A a serial stream of information is sent across the LREQ line The length of the stream will vary depending on whether the transfer is a bus request a read command or a write command Regardless of the type of transfer a start bit of 1 is required at the beginning of the stream and a stop bit of 0 is required at the end of the stream Bit 0 is the most significant and is transmitted first The LREQ line will be required to idle low logic level 0 19 2 1 Link Layer Controller Bus Request For a Bus Request the length of the LREQ data stream is 7 bits as follows eIr s NAME DESCRIPTION _ d Start Bit Indicates the beginning of the transfer always 1 Request Type I
8. information to the link the phy will continue to The cycle master uses a normal priority request to send a cycle start attempt to transfer the contents of the register until it is successful message After receiving a cycle start the link can issue an isochronous bus request When arbitration is won the link proceeds For write requests the phy will load the data field into the with the isochronous transfer of data The isochronous request will appropriately addresses register as soon as the transfer has been be cleared by the phy once the link sends another type of request or completed The link will be allowed to request read or write when the isochronous transfer has been completed operations at any time The ImmReq request is issued when the link needs to send an 19 5 Status acknowledgment after reception of a packet address to it This request must be issued during packet reception This is done to minimize the delays that a phy would have to wait between the end of a packet and the transmittal of an acknowledgment As soon as the packet ends the phy immediately grants access of the bus to the link the link will send an acknowledgment to the sender unless the header CRC of the packet turns out to be bad In this case the link will release the bus immediately it will not be allowed to send another type of packet on this grant To guarantee this the link will be forced to wait 160 ns after the end of the packet is received The phy t
9. mode an arbitrated bus reset cannot be initiated from this node and will be treated as a long bus reset if initiated by another node In accordance with the 1394 1995 spec all bus resets on the entire bus will be long To enable Arbitrated short Bus Reset mode set TESTM2 low With the part in this mode writing a 1 to the ISBR Initiate Short Bus Reset bit bit 7 of Phy register 9 initiates an arbitrated bus reset This mode also allows the Phy to recognize arbitrated bus resets initiated by other nodes Non arbitrated bus resets can still be initiated from this node and are recognized and processed correctly when initiated by another node 17 2 Setting the CPS Trip Point The Cable Power Status CPS pin pin 23 is used to monitor the cable power When cable power voltage has dropped too low for reliable operation internal circuitry trips which clears the CPS bits in the Phy registers bit 7 of register 0 and bit 2 of register 6 This action causes a cable power status interrupt which sets the CPSint bit in the Phy registers bit 1 of register 6 This bit can be cleared by a hardware reset or by writing a 0 to the CPSint bit However if the CPS input is still low another cable power status interrupt immediately occurs The cable voltage at which these events occur is adjustable on the PDI1394P11A 1999 Mar 10 11 Preliminary specification PDI1394P11A The external resistor R needed to set the CPS trip
10. serial data stream The serial data stream is converted to two or four parallel bit streams resynchronized to the internal 49 152 MHz clock and sent to the Philips Semiconductors 3 port physical layer interface associated link controller The received data is also transmitted out the other active cable ports The cable status bus initialization and arbitration states are monitored through the cable interface using differential comparators The outputs of these comparators are used by internal logic to determine cable and arbitration status The TPA channel monitors the incoming cable common mode voltage value during arbitration to determine the speed of the next packet transmission The TPB channel monitors the incoming cable common mode voltage for the 8 0 RECOMMENDED OPERATING CONDITIONS Preliminary specification PDI1394P11A presence of the remotely supplied twisted pair bias voltage indicating the cable connection status The PDI1394P11A provides a nominal 1 85 V for driver load termination This bias voltage when seen through a cable by a remote receiver is used to sense the presence of an active connection The value of this bias voltage has been chosen to allow inter operability between transceiver chips operating from either 5 V nominal supplies or 3 3 V nominal supplies This bias voltage source should be stabilized by using an external filter capacitor When not powered the PDI1394P11A prevents the bias voltage from
11. voltage Veable to a desired voltage can be calculated using the following equation Vian 1 85V cable T0uA The external and internal circuitry associated with the CPS pin is illustrated in Figure 5 R COMPARATOR Phy SV00921 Figure 5 Some typical threshold voltage values and their associated resistor values are shown in Table 1 Table 1 Typical threshold voltage values Veable DETECTOR TOLERANCE WITH Philips Semiconductors 3 port physical layer interface 17 3 Bushold and Link PHY single capacitor galvanic isolation 17 3 1 Bushold The PDI1394P11A uses an internal bushold circuit on each of the indicated pins to keep these CMOS inputs from floating while being driven by a 3 Stated device or input coupling capacitor Unterminated high impedance inputs react to ambient electrical noise which cause internal oscillation and excess power supply current draw The following pins have bushold circuitry enabled when the ISO pin is in the logic 1 state Pin No Name Function 2 LPS Link power status line 3 LREQ Link request line 7 PD Power down pin 11 CTLO Phy Link Interface bi directional control line 0 12 CTL1 Phy Link Interface bi directional control line 1 13 DO Phy Link Interface bi directional data line 0 14 D1 Phy Link Interface bi directional data line 1 15 D2 Phy Link Interface bi directional data line 2 16 D3 Phy Link Interface bi directional d
12. DWG 64 pin plastic LQFP 0 C to 70 C PDI1394P11A BD PD1394P11A BD SOT314 2 4 0 PIN CONFIGURATION PLLVDD PLLGND PLLGND 58 53 52 PBIAS3 PBIAS2 PBIAS1 PA1 PA1 PB1 PD DGND SYSCLK DGND CTLO CTL1 Do D1 D2 D3 PDI1394P11A olle IN yp Poy Ry Py pm 21 TESTM2 SV01073 1999 Mar 10 2 Philips Semiconductors Preliminary specification 3 port physical layer interface PDI1394P11A 5 0 PIN DESCRIPTION PIN NUMBER PIN SYMBOL NAME AND FUNCTION RESET pr Phy reset active LOW L Link Layer Controller LLC power status LREQ Link request from controller D n DVDD Should be connected to the LLC Vpp supply when a 5V LLC is connected to the Phy and should be connected to the Phy DVDD when a 3V LLC is used ory T TESTM 1 2 Test Mode Control pins 11 1394 1995 mode 10 1394a mode 00 01 Reserved m Cabiepowersiaus SSCSC C lt lt c o omenana SSCS TENTER E TEENS EE ro i i an tr capa 5 6 19 20 8 10 17 18 63 64 11 12 13 14 15 16 22 21 QO U n 24 25 51 55 26 32 41 49 50 61 NI 30 29 28 gt 36 40 45 35 39 44 34 38 43 33 37 42 46 47 48 52 53 TRIAS P enstatosattercomeston SY FO exstalosataercomesion SY E lez x lt XJ x lt O PLLVDD PLL circuit power R 0 1 External current setting resistor ISO Link interface isolation statu
13. N 000 ImmReq Immediate request Upon detection of an idle take control of the bus immediately no arbitration lsochronous request Arbitrate for the bus no gaps Priority request Arbitrate after a subaction gap ignore fair protocol Fair request Arbitrate after a subaction gap follow fair protocol Return the specified register contents through a status transfer Write to the specified register Reserved 19 3 Operation of LREQ V00232 Figure 8 LREQ Input Sequence each cell represents one SYSCLK sample time For fair or priority access the link requests control of the bus at least removed The only side effect would be the loss of the intended one clock after the phy link interface becomes idle If the link senses acknowledgment packet this will be handled by the higher layer that the CTL pins are in a receive state CTL 0 1 10 then it will protocol know that its request has been lost This is true anytime during or after the link sends the bus request transfer Additionally the phy will 19 4 Read Write Requests ignore any fair or priority requests if it asserts the receive state while When the link requests to read the specified register contents the the link is requesting the bus The link will then reissue the request phy will send the contents of the register to the link through a status one clock after the next interface idle transfer If an incoming packet is received while the phy is transferring status
14. a 0 to this bit but if the loop configuration has not been corrected it will promptly return to a 1 CPSint 1 Rd Wr Indicates that the cable power has dropped too low for guaranteed reliable operation It can be cleared by writing a 0 to the bit but it will immediately return if CPS is still LOW Cable Power Status is also included in this register to expedite handling the CPSint a ae Rd Wr Indicates that the last bus reset was initiated in the PDI1394P11A This bit is also included in the self ID packet Ic st RA If set this node is a contender for the role of bus or Isochronous Resource Manager Pez ji RG The least significant power class bit Pea o fio fR e The middle power class bit Peco ji Ra The most significant power class bit ISBR 1 Rd Wr Initiate Short Bus Reset Instructs the PDI1394P11A to initiate an arbitrated short bus reset See Section 17 1 1999 Mar 10 9 Philips Semiconductors Preliminary specification 3 port physical layer interface PDI1394P11A 17 0 APPLICATION INFORMATION TPBIAS TP CABLES TP CABLES f Nf AGND AGND CNA OUT AVDD POWER CLASS PLLGND PROGRAMMING PLLGND FILTER C LKON 10K AVDD AGND E E xI AVDD X PDI1394P11A AOD L Vpp PLLVDD CPS 400K CABLE POWER RO TESTM1 R1 TESTM2 boo DVDD VoD So DVDD DGND DGND TPBIAS3 TPBIAS2 TPBIAS1 CONTENDER PROGRAMMING
15. ata line 3 Philips bushold circuitry is designed to provide a high resistance pull up or pull down on the input pin This high resistance is easily overcome by the driving device when its state is switched Figure 6 shows a typical bushold circuit applied to a CMOS input stage Two weak MOS transistors are connected to the input An inverter is also connected to the input pin and supplies gate drive to both transistors When the input is LOW the inverter output drives the lower MOS transistor and turns it on This re enforces the LOW on the input pin If the logic device which normally drives the input pin were to be 3 Stated the input pin would remain pulled down by the weak MOS transistor If the driving logic device drives the input pin HIGH the inverter will turn the upper MOS transistor on re enforcing the HIGH on the input pin If the driving logic device is then 3 Stated the upper MOS transistor will weakly hold the input pin HIGH APPLICATION 3 3V ISO_N Preliminary specification PDI1394P11A The PHY s outputs can be 3 Stated and single capacitor isolation can be used with the Link both situations will allow the Link inputs to float With bushold circuitry enabled these pins are provided with dc paths to ground and power by means of the bushold transistors this arrangement keeps the inputs in known logical states p INTERNAL e INPUT PIN CIRCUITS Svoog11 Figure 6 Bushold
16. b s The transmit state is held on the CTL pins until the last bits of data have been sent The link will then assert Idle on the CTL lines for one clock cycle after which it releases control of the interface However there will be times when the link will need to send another packet without releasing the bus For example the link may want to send consecutive isochronous packets or it may want to attach a response to an acknowledgment To do this the link will assert hold 22 1 TRANSMIT TIMING WAVEFORMS 0000 Preliminary specification PDI1394P11A instead of Idle when the first packet of data has been completely transmitted Hold in this case informs the phy that the link needs to send another packet without releasing control of the bus The phy will then wait a set amount of time before asserting transmit The link can then proceed with the transmittal of the second packet After all data has been transmitted and the link has asserted Idle on the CTL pins the phy will assert its own Idle state on the CTL lines When sending multiple packets in this fashion it is required that all data be transmitted at the same speed This is required because the transmission speed is set during arbitration and since the arbitration step will be skipped there will be no way of informing the network of a change in speed The PDI1394P11A includes a digital camera single port Phy interoperability enhanc
17. ce This pin is equipped with Bus Hold circuitry and supports an optional isolation barrier 18 4 Power Down input PD pin 7 This input powers down all device functions with the exception of the CNA circuit to conserve power in portable or battery powered applications It must be held high for at least 3 5ms to assure a successful reset after power down This pin is equipped with Bus Hold circuitry and supports an optional isolation barrier 18 5 System Clock output SYSCLK pin 9 Provides a 49 152 MHz clock signal synchronized with the data transfers to the link layer controller This pin supports an optional isolation barrier 18 6 Control I Os CTL 0 1 pins 11 12 These are bi directional signals used in the communication between the PDI1394P11A and the link layer controller that control passage of information between the two devices These pins are equipped with Bus Hold circuitry and support an optional isolation barrier 18 7 Data I Os D 0 3 pins 13 14 15 16 These are bi directional information signals used in the communication between the PDI1394P11A and the link layer controller These pins are equipped with Bus Hold circuitry and support an optional isolation barrier 18 8 Test Mode control and ISBR mode inputs TESTM 1 2 pins 22 21 These two logic signals are used in manufacturing to enable production line testing of the PDI1394P11A For normal use these should be tied to Vpp To enable ISBR Arbitrated short
18. circuit 17 3 2 Single capacitor isolation The circuit example Figure 7 shows the connections required to implement basic single capacitor Link PHY isolation The RESET C LKON PD and LPS pins need special consideration to implement an isolation scheme Details can be found in the Philips Isolation Application Note AN2452 NOTE The isolation enablement pins on both devices are in their 1 states activating the bushold circuits on each part The bushold circuits provide local dc ground references to each side of the isolating coupling capacitors Also note that ground isolation signal coupling must be provided in the form of a parallel combination of resistance and capacitance as indicated in IEEE 1394 1995 ISOLATED PHY DO J LINK PHY D1 PDI1394P11A PDI1394Lxx PHY D2 PHY D3 J PHYCTLO PHYCTLO PHYCTL1 PHYCTL1 fc LREQ LREQ SCLK SYSCLK 1MEG Q APPLICATION GROUND a Cc 0 001 uF Cr 0 1uF ISOLATED PHY GROUND SV01048 Figure 7 Single capacitor Link PHY isolation 1999 Mar 10 Philips Semiconductors 3 port physical layer interface 18 0 EXTERNAL COMPONENTS AND CONNECTIONS 18 1 Logic Reset input RESET pin 1 Forcing this pin low causes a Bus Reset condition on the active cable ports and resets the internal logic to the Reset Start state SYSCLK remains active For power up and after power down is asserted a 2 ms delay is re
19. e cable topology or that the cable power has dropped below the threshold for reliable operation These bits hold the address of the phy register whose contents will be transferred to the link The data that is to be sent to the link 21 0 STATUS TRANSFER TIMING PHY _ Xe Xe XX Xe Xe XX PHY D 0 1 SV00233 Figure 9 Status Transfer Timing 1999 Mar 10 16 Philips Semiconductors 3 port physical layer interface 22 0 TRANSMIT When the link wants to transmit information it will first request access to the bus through the LREQ pin Once the phy receives this request it will arbitrate to gain control of the bus When the phy wins ownership of the serial bus it will grant the bus to the link by asserting the transmit state on the CTL pins for at least one SYSCLK cycle followed by idle for one clock cycle The link will take control of the bus by asserting either hold or transmit on the CTL lines hold is used by the link to keep control of the bus if it needs some time to prepare the data for transmission The phy will keep control of the bus for the link by asserting a data prefix state on the bus It is not necessary for the link to use hold if it is ready to transmit as soon as bus ownership is granted When the link is prepared to send data it will assert transmit on the CTL lines as well as sending the first four bits of the packet on the D 0 3 lines assuming 200 M
20. ement When a node is root and consequently cycle master and is sending Isochronous data it does not need to arbitrate for the bus by default it would win any such arbitration This fact was overlooked by some early 100 Mbps single port Phy manufacturers whose chips are too slow to handle the absence of the arbitration time This causes their Phys to see a header CRC error and the packet to be discarded The PDI1394P11A compensates for this by extending the Data_Prefix time before sending the packet This makes the PDI1394P11A fully compatible with all existing 100 Mbps Phys on the market 2X 2X 2X 2X 0 aS oK Key EAEE n TO a sits zz Ti NOTE ZZ High Impedance State Po gt Py Packet Data NOTE ZZ High Impedance State PO gt Pn Packet data 0000 0000 0000 SV00235 Figure 10 Transmit Timing Waveforms 1999 Mar 10 17 Philips Semiconductors Preliminary specification 3 port physical layer interface PDI1394P11A 23 0 RECEIVE When data is received by the phy from the serial bus it will transfer the data to the link for further processing The phy will assert Receive on the CTL lines and 1 on each D pin The phy indicates the start of the packet by placing the speed code on the data bus The phy will then proceed with the transmittal of the packet to the link on the D lines while still keeping the Receive status on the CTL pins Once the packet has been completely transferred the phy wi
21. hen gains control of the bus and the ack with the CRC error is sent Then the bus is released and allowed to proceed with another request A status transfer is initiated by the phy when it has status information to transfer to the link The phy will wait until the interface is idle before starting the transfer The transfer is initiated by asserting the following on the control pins CTL 0 1 01 along with the first two bits of status information on the D 0 1 pins The phy maintains CTL 0 1 01 for the duration of status transfer The phy may prematurely end a status transfer by asserting something other than CTL 0 1 01 on the control pins This could be caused by an incoming packet from another node The phy will continue to attempt to complete the transfer until the information has been successfully transmitted There must be at least one idle cycle in between consecutive status transfers The phy normally sends just the first four bits of status to the link These bits are status flags which are needed by the link state machines The phy sends an entire status packet to the link after a request transfer which contains a read request or when the phy has pertinent information to send to the link or transaction layers The only defined condition when the phy automatically sends a register to the link is after self ID when it sends the physical ID register which contains the new node address Although highly improbable it is conceivable
22. hese or any other conditions beyond those indicated under recommended operating conditions is not implied Exposure to absolute maximum rated conditions for extended periods may affect device reliability 2 The performance capability of a high performance integrated circuit in conjunction with its thermal environment can create junction temperatures which are detrimental to reliability The maximum junction temperature of this integrated circuit should not exceed 150 C 3 The input and output voltage ratings may be exceeded if the input and output clamp current ratings are observed 10 0 CABLE DRIVER SYMBOL PARAMETER TEST CONDITION NOTES 1 Limits defined as algebraic sum of TPA and TPA driver currents Limits also apply to TPB and TPB algebraic sum of driver currents 2 Limits defined as one half of the algebraic sum of currents flowing into TPB and TPB 11 0 CABLE RECEIVER 1999 Mar 10 6 Philips Semiconductors Preliminary specification 3 port physical layer interface PDI1394P11A 12 0 OTHER DEVICE I O LIMITS SYMBOL PARAMETER TEST CONDITION Supply current oo 236V Powerdownmede 78 2 5 ma_ Vp Gable Power ThreshoaVotage A 400KmI00PSpn___ dt ar dT 7s Vou _ Hohievetouputvotage____ lon Max Voo Min voos _ fv Vo Fowieveluputvetage l Min Voo Mex S dT os Input current LREQ LPS PD n na i E TESTM1 2 e PTT te OFF state output current CTLn E a Dn C LKON I Os
23. i INTEGRATED CIRCUITS DATA SAHEET PDI1394P11A 3 port physical layer interface Preliminary specification 1999 Mar 10 i s PHILIPS Semiconductors DH l LI PS Philips Semiconductors Preliminary specification SSS SSS SSS SSS 3 port physical layer interface PDI1394P11A 1 0 FEATURES 2 0 DESCRIPTION The Philips Semiconductors PDI1394P11A is an IEEE1394 1995 compliant Physical Layer interface The PDI1394P11A provides the Supports 100Mb s and 200Mb s transfers analog physical layer functions needed to implement a three port node in a cable based IEEE 1394 1995 network Additionally the device manages bus initialization and arbitration cycles as well as 3 cable interface ports Interfaces to any 1394 standard Link Layer Controller 5V tolerant I Os with Bus Hold Circuitry transmission and reception of data bits The Link Layer Controller ear interface is compatible with both 3V and 5V Link Controllers While Single 3 3V supply voltage providing a maximum transmission data rate of 200 Mb s the Arbitrated short Bus Reset 1394a feature PDI1394P11A is compatible with current 100 Mb s Physical Layer ICs The PDI1394P11A is available in the LQFP64 package Fully compatible with existing 100 Mbps Phys on the market Prevents a TpBias voltage driven into a non powered PDI1394P11A from erroneously powering up the part 3 0 ORDERING INFORMATION PACKAGE TEMPERATURE RANGE OUTSIDE NORTH AMERICA NORTH AMERICA PKG
24. ins high to Vpp or low to GND 18 12 Cable Not Active output CNA pin 31 This pin outputs the cable connection status If all ports are disconnected this pin outputs a high If any port has a cable connected then this pin outputs a low 18 13 Twisted Pair I O s TPA 1 3 pins 45 40 36 TPA 1 3 pins 44 39 35 TPB 1 3 pins 43 38 34 TPB 1 3 pins 42 37 33 These pins send and receive differential data over the twisted pair cables Two series connected external 56 Q cable termination resistors are required at each twisted pair Each unused TPB pin must be tied through a 5kQ resistor to ground The TPA pins can be left floating 18 14 Twisted Pair Bias outputs TPBIAS 1 3 pins 46 47 48 These outputs provide the 1 86 V nominal bias voltage needed for proper operation of the twisted pair cable drivers and for signaling to the remote nodes that there is a valid cable connection Three TPBIAS outputs are provided for separate connection to each of the three TPA twisted pairs to provide electrical isolation A 1uF capacitor to ground must be connected to each TPBIAS pin whether it is used or not 18 15 PLL Filter FILTER pin 54 This pin is connected to an external filter capacitor used in a lag lead filter for a PLL frequency multiplier running off of the crystal oscillator 18 16 Oscillator crystal XI pin 56 amp XO pin 57 These pins connect to a 24 576 MHz parallel resonant fundamental mode crystal
25. ll assert Idle on the CTL pins which will complete the receive operation NOTE The speed is a phy link protocol and not included in the CRC 23 1 RECEIVE TIMING WAVEFORMS PHY CTL O1 PHY D 0 3 os 0000 Brees sees 0000 X 0000 Yeeee NOTE SPD Speed Code Po Ph Packet Data SV00234 NOTE SPD Speed Code Po Pn packet data Figure 11 Receive Timing Waveforms The speed code for the receiver is as follows NOTE X transmitted as 0 ignored on receive 24 0 POWER CLASS BITS IN SELF ID PACKET The settings of the PC 0 2 pins appear in the pwr field of the self ID packet Bit 21 is transmitted first followed by bit 22 and then bit 23 Node may be powered from the bus and is using up to 1 W An additional 2 W is needed to enable the LLC and higher layers Node may be powered from the bus and is using up to 1 W An additional 5 W is needed to enable the LLC and higher layers 111 Node may be powered from the bus and is using up to 1 W An additional 9 W is needed to enable the LLC and higher layers Node may be powered from the bus and is using up to 1 W 1999 Mar 10 18 Philips Semiconductors Preliminary specification 3 port physical layer interface PDI1394P11A LQFP64 plastic low profile quad flat package 64 leads body 10 x 10 x 1 4 mm SOT314 2 7 CAAA 77 a3 oo Ol A2 Li Aa 0 2 5 5mm DIMENSIONS mm are the original dimensio
26. ndicates the type of bus request see the table below for the encoding of this field os Request Speed This should be 00 for PDI1394P11A s 100 Mbit s speed and 01 for 200 Mbit s speed Stop Bit Indicates the end of the transfer always 0 19 2 2 Link Layer Controller Requests Read Register Access For a Read Register Request the length of the LREQ data stream is 9 bits as follows Bme NAME DESCRIPTION d Start Bit Indicates the beginning of the transfer always 1 1 3 Request Type Always a 100 indicating that this is a read register request The address of the phy register to be read Beo Siop Bit Indicates the end of the transfer always 0 19 2 3 Link Layer Controller Requests Write Register Access For a Write Register Request the length of the LREQ data stream is 17 bits The details of bits are as shown below Eme NAME DESCRIPTION Start Bit Indicates the beginning of the transfer always 1 1 3 Request Type Always a 101 indicating that this is a write register request 4 7 Address The address of the phy register to be written to 8 15 Data The data that is to be written to the specified register address Stop Bit Indicates the end of the transfer always 0 Philips Semiconductors Preliminary specification 3 port physical layer interface PDI1394P11A 19 2 4 Other Requests and LREQ The three bit Request Type field has the following possible values Eme NAME DESCRIPTIO
27. ns A UNIT max A1 A2 As bp D E e Hp He L Lp v w y Zo ze 6 o 1 60 0 20 1 45 0 25 0 27 0 18 10 1 10 1 05 12 15 12 15 10 0 75 0 69 02 10121 0 1 1 45 1 45 7 uR 0 05 1 35 0 17 0 12 9 9 9 9 11 85 11 85 0 45 0 59 1 05 1 05 0 Note 1 Plastic or metal protrusions of 0 25 mm maximum per side are not included OUTLINE REFERENCES EUROPEAN VERSION IEC JEDEC EIAJ PROJECTION OT314 2 95 12 19 ISSUE DATE 1999 Mar 10 19 Philips Semiconductors Preliminary specification 3 port physical layer interface PDI1394P11A Data sheet status Data sheet Product Definition 1 status status Objective Development This data sheet contains the design target or goal specifications for product development specification Specification may change in any manner without notice Preliminary Qualification This data sheet contains preliminary data and supplementary data will be published at a later date specification Philips Semiconductors reserves the right to make chages at any time without notice in order to improve design and supply the best possible product Product Production This data sheet contains final specifications Philips Semiconductors reserves the right to make specification changes at any time without notice in order to improve design and supply the best possible product 1 Please consult the most recently is
28. on the IC to provide noise isolation They should be tied together at a low impedance point on the circuit board Individual filter networks are desirable Details of a phy link Interface supporting an optional isolation barrier are provided in Annex J of the 1394 standard 19 0 PRINCIPLES OF OPERATION The PDI1394P11A is designed to operate with a link layer controller These devices use an interface such as described in Annex J of the 1394 standard The following describes the operation of the phy link interface 19 1 Data Transfer and Clock rates The PDI1394P11A supports 100 200 Mbit s data transfer and has four bi directional data lines D 0 3 crossing the interface In 100 Mbit s operation only D 0 1 pins are used in 200 Mbit s operations all D 0 3 pins are used for data transfer The unused D n pins are driven low In addition there are two bi directional control lines CTL 0 1 the 50 MHz SYSCLK line from the phy to the link and the link request line LREQ from the link to the phy The PDI1394P11A has control of all the bi directional pins The link is allowed to drive these pins only after it has been given permission by the phy The dedicated LREQ request pin is used by the link for any activity which it wishes to initiate When the phy has control of the bus the CTL 0 1 lines are encoded as follows CTL 0 1 NAME DESCRIPTION OF ACTIVITY i No activity is occurring this is the default mode Status information is
29. quired to assure proper PLL operation An internal pull up resistor is connected to Vpp so only an external delay capacitor is required This input is a standard logic buffer and may also be driven by an open drain logic output buffer The RESET pin also has a n channel pull down transistor activated by the Power Down pin For a reset during normal operation a 10 us low pulse on this pin will accomplish a full PHY reset This pulse as well as the 2 ms power up pulse could be microprocessor controlled in which case the external delay capacitor would not be needed For more details on using single capacitor isolation with this pin please refer to the Philips Isolation Application Note AN2452 18 2 Link Power Status input LPS pin 2 In anon isolated implementation a 10kQ resistor is connected to the Vpp supplying the link layer controller to monitor the link s power status In an isolated implementation a square wave with a minimum frequency of 500 kHz can be applied to the LPS pin to indicate the pin is powered If the link is not powered on the Control I O s pins 11 12 Data I O s pins 13 16 and SYSCLK output pin 9 are disabled and the PDI1394P11A will perform only the basic repeater functions required for network initialization and operation This pin is equipped with Bus Hold circuitry 18 3 Link Request input LREQ pin 3 LREQ is a signal from the link layer controller used to request the PDI1394P11A to perform some servi
30. rfaces The PDI1394P11A provides the transceiver functions needed to implement a three port node in a cable based 1394 network Each cable port incorporates two differential line transceivers In addition to transmission and reception of packet data the line transceivers 1999 Mar 10 TRANSMIT DATA ENCODER CRYSTAL OSCILLATOR PLL SYSTEM amp TRANSMIT CLOCK GENERATOR FILTER SV00228 monitor conditions on the cable to determine connection status data speed and bus arbitration states The PDI1394P11A receives data to be transmitted over the bus from two or four parallel data paths to the Link Controller D 0 3 These data paths are latched and synchronized with the 49 152 MHz clock The parallel bit paths are combined serially encoded and transmitted at either 98 304 Mb s or 196 608 Mb s depending whether the transaction is a 100 Mb s or 200 Mb s transfer respectively The transmitted data is encoded as data strobe information with the data information being transmitted on the TPB cable pairs and the strobe information transmitted on the TPA cable pairs During packet reception the TPA and TPB transmitters of the receiving cable port are disabled and the receivers for that port are enabled The encoded data information is received on the TPA cable pair and the strobe information is received on the TPB cable pair The combination of the data and strobe signals is decoded to recover the receive clock signal and the
31. s Preliminary specification 3 port physical layer interface PDI1394P11A 16 0 INTERNAL REGISTER CONFIGURATION The accessible internal registers of this device are listed in the following tables Lh ee ee 0000 Physical ID a B E E E E a Oc a e100 Ase _sstare one con Fesoned_ a Ass ___sstara___ _ons_ cons _Fesoned_ A a a E Reserved Reserved ISBR a De A Co eR i Rawr rate Bus Reset instructs the POITG9APTTA orate Bus Reset atthe nex opporuniy eo fe rawr Gap count Used to opimize the gap ines based on the size of he network See 1394 standard Tor dorais SPD 2 Indicates the top signaling speed of the local ports For the PDI1394P11A this field is 01b indicating S200 speed capability INP fa RA The number of ports on this device set to 0011 AStat n 2 The line state of TPA of port n 00 invalid data state Power up reset initializes to this line state Also this line state is output during transmit and receive operations The line state outputs are generally valid during arbitration and idle conditions on the bus BStat n 2 R The line state of TPB of port n The encoding is the same as AStat n Ch n ao R If 1 then port n is a child otherwise it is a parent Conn f2 Ra If 1 then port n is connected otherwise it is disconnected Loopint 1 Rd Wr Indicates that the PDI1394P11A times out in tree ID waiting for child signal from two or more ports The Loopint can be cleared by writing
32. s input NOTE Indicates 5V tolerant structure 1999 Mar 10 3 Philips Semiconductors Preliminary specification 3 port physical layer interface PDI1394P11A 6 0 BLOCK DIAGRAM BIAS VOLTAGE AND CURRENT GENERATOR RECEIVED DATA DECODER TIMER SYSCLK LREQ LINK INTERFACE CTLO CTL1 DO D1 D2 D3 ARBITRATION AND CONTROL STATE MACHINE PCO PC1 LOGIC PC2 C LKON TESTM1 TESTM2 7 0 FUNCTIONAL SPECIFICATION The PDI1394P11A is an IEEE1394 1995 High Performance Serial Bus Specification compliant physical layer interface device It provides an interface between an attached link layer controller and three 1394 cable interface ports In addition to the interface function the PDI1394P11A performs bus initialization and arbitration functions as well as monitoring line conditions and connection status 7 1 Clocking The PDI1394P11A utilizes a stable internal reference clock of 196 608 MHz The reference clock is generated using an external 24 576 MHz crystal and an internal Phase Locked Loop PLL The PLL clock is divided down to 49 152 MHz and 98 304 MHz clock signals The 49 152 MHz clock is used for internal logic and provided as an output to clock a link layer controller The 196 608 MHz and 98 304 MHz clocks are used for synchronization of the transmitted strobe and data information 7 2 Port Inte
33. sued datasheet before initiating or completing a design Definitions Short form specification The data in a short form specification is extracted from a full data sheet with the same type number and title For detailed information see the relevant data sheet or data handbook Limiting values definition Limiting values given are in accordance with the Absolute Maximum Rating System IEC 134 Stress above one or more of the limiting values may cause permanent damage to the device These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied Exposure to limiting values for extended periods may affect device reliability Application information Applications that are described herein for any of these products are for illustrative purposes only Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification Disclaimers Life support These products are not designed for use in life support appliances devices or systems where malfunction of these products can reasonably be expected to result in personal injury Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application
34. that the two separate nodes will believe that an incoming packet is intended for them The nodes then issue a ImmReq request before checking the CRC of the packet Since both phys will seize control of the bus at the same time a temporary localized collision of the bus will occur somewhere between the competing nodes This collision would be interpreted by the other nodes on the network as being a ZZ line state not a bus reset As soon as the two nodes check the CRC the mistaken node will drop its request and the false line state will be The definition of the bits in the status transfer are shown below 1999 Mar 10 15 Philips Semiconductors Preliminary specification 3 port physical layer interface PDI1394P11A 20 0 STATUS REQUEST LENGTH OF STREAM 16 BITS BIT S NAME DESCRIPTION Arbitration reset gap Indicates that the phy has detected that the bus has been idle for an arbitration reset gap time this time is defined in the P1394 standard This bit is used by the link in its busy retry state machine Subaction gap Indicates that the phy has detected that the bus has been idle for a subaction gap time this time is defined in the P1394 standard This bit is used by the link to detect the completion of an isochronous cycle Bus Reset Indicates that the phy has entered the bus reset state 3 State Time out or Indicates that the phy stayed in a particular state for too long a period which is usually the effect of a loop CPS in th
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PHILIPS PDI1394P11A 3 port physical layer interface handbook(1)