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philips ADC0803/0804 CMOS 8-bit A/D converters handbook

1. 2002 Oct 17 15 Philips Semiconductors Product data CMOS 8 bit A D converters ADC0803 0804 DIP20 plastic dual in line package 20 leads 300 mil SOT146 1 seating plane 5 scale DIMENSIONS inch dimensions are derived from the original mm dimensions inches Note 1 Plastic or metal protrusions of 0 25 mm maximum per side are not included OUTLINE REFERENCES EUROPEAN VERSION JEDEC EIAJ PROJECTION ISSUE DATE SOT146 1 MS 001 SC 603 EI ee 2002 Oct 17 16 Philips Semiconductors Product data CMOS 8 bit A D converters ADC0803 0804 REVISION HISTORY ET EEE 3 20021017 Product data third version supersedes data of 2001 Aug 03 Engineering Change Notice 853 0034 28949 date 20020916 Modifications Add Topside Marking column to Ordering Information table 20010803 Product data second version 9397 750 08926 Engineering Change Notice 853 0034 26832 date 20010803 19940831 Product data initial version Engineering Change Notice 853 0034 13721 date 19940831 2002 Oct 17 17 Philips Semiconductors Product data CMOS 8 bit A D converters ADC0803 0804 Data sheet status Product Definitions 1 Level Data sheet status tatus 2 3 Objective data Development This data sheet contains data from the objective specification for product development Philips Semiconductors reserves the right
2. D gt a oO 3 a Z Q g O I vakt gt o CLK IN THRESHOLD VOLTAGE V OUTPUT CURRENT mA 4 75 5 00 5 25 i 4 l 0 25 50 75 100 125 Vcc SUPPLY VOLTAGE V Voc SUPPLY VOLTAGE V AMBIENT TEMPERATURE C Delay From RD Falling Full Scale Error vs Edge to Data Valid vs Conversion Time Load Capacitance Voc 5 0 V Vcoc 5 0V VREF 2 2 5 V Tamb 25 C 20 40 60 80 200 400 600 800 1000 CONVERSION TIME us LOAD CAPACITANCE pF 8L00018 Figure 3 Typical Performance Characteristics 2002 Oct 17 9 Philips Semiconductors Product data CMOS 8 bit A D converters ADC0803 0804 3 STATE TEST CIRCUITS AND WAVEFORMS ADC0801 1 DATA OUTPUT 10 kQ DATA 1050 OUTPUT DATA DATA OUTPUT GND ______ cal 10 pF OUTPUT GND tOH 8L00019 Figure 4 3 State Test Circuits and Waveforms ADC0801 1 TIMING DIAGRAMS All timing is measured from the 50 voltage points START CONVERSION BUSY DATA IS VALID IN ACTUAL INTERNAL NOT BUSY OUTPUT LATCHES STATUS OF THE CONVERTER AST DATA WAS READ 1TO8X Viak lt INTERNAL To gt INTR LAST DATA WAS NOT READ INT ASSERTED DATA THREE STATE OUTPUTS tacc lt PER tty to Output Enable and Reset INTR
3. NOTE Read strobe must occur 8 clock periods 8 CLK after assertion of interrupt to guarantee reset of INTR SL00020 Figure 5 Timing Diagrams 2002 Oct 17 10 Philips Semiconductors Product data CMOS 8 bit A D converters ADC0803 0804 330 Q TO Vper 2 FS OFFSET T 0 1 uF ADJUST s OFFSET 2 ADJUST DIGITAL CIRCUITS SL00022 Figure 7 Offsetting the Zero Scale and Adjusting the Input Range Span 10 V NOTE The Vpep 2 voltage is either 1 2 the Vcc voltage or is that which is forced at Pin 9 SL00021 Figure 6 Internal Reference Design VOLTAGE REFERENCE VreF 2 a Fixed Reference b Fixed Reference Derived from Vcc c Optional Full Scale Adjustment SL00023 Figure 8 Absolute Mode of Operation 2002 Oct 17 11 Philips Semiconductors Product data CMOS 8 bit A D converters ADC0803 0804 TRANSDUCER FULL SCALE OPTIONAL 100 Q 2ko SL00024 Figure 9 Ratiometric Mode of Operation with Optional Full Scale Adjustment 19 CLK R Tt uF TO T 100 uF SL00025 Figure 10 Connection for Continuous Conversion CLKR 19 CLKIN 4 feLK 1 1 7RC R 10kQ 19 CLKR SL00026 Figure 11 Self Clocking the Converter ANALOG INPUTS ADDRESS DECODE LOGIC Figure 12 Interfacing to 8080A Microprocessor SL00027 2002 Oct 17 12 Philips Semicondu
4. RD input Pin 2 which may be grounded to constantly have the latest conversion present at the output 2002 Oct 17 Product data ADC0803 0804 TEST CONDITIONS fork 1 MHz w Aajo o i 5 fork 1 MHz INTR tied to WR CS 0 CS 0 C 100 pF CL 10 pF R 10kQ See 3 State test circuit ANALOG OPERATION Analog Input Current The analog comparisons are performed by a capacitive charge summing circuit The input capacitor is switched between Vin 4 and Vin while reference capacitors are switched between taps on the reference voltage divider string The net charge corresponds to the weighted difference between the input and the most recent total value set by the successive approximation register The internal switching action causes displacement currents to flow at the analog inputs The voltage on the on chip capacitance is switched through the analog differential input voltage resulting in proportional currents entering the Vin 4 input and leaving the Vin input These transient currents occur at the leading edge of the internal clock pulses They decay rapidly so do not inherently cause errors as the on chip comparator is strobed at the end of the clock period Input Bypass Capacitors and Source Resistance Bypass capacitors at the input will average the charges mentioned above causing a DC and an AC current to flow through the output resistance of the analog signal sources This charge pumping ac
5. displayed while either button is depressed and for a short time after it is released At other times the ambient temperature could be displayed The set temperature is stored in an SCN8051 internal register The A D conversion is started by writing anything at all to the A D with port pin P10 set high The desired temperature is compared with the digitized actual temperature and the heater is turned on or off by clearing setting port pin P12 If desired another port pin could be used to turn on or off an air conditioner The display drivers are NE587s if common anode LED displays are used Of course it is possible to interface to LCD displays as well Philips Semiconductors Product data CMOS 8 bit A D converters ADC0803 0804 TYPICAL PERFORMANCE CHARACTERISTICS Power Supply Current vs Clock Frequency vs Input Current vs Temperature Clock Capacitor Applied Voltage at Vrerj2 Pin Voc 5 0 V Tamo 25 C CLOCK FRQ MHz POWER SUPPLY CURRENT mA MIN 50 25 0 25 50 75 100 125 20 40 6080100 200 400 6001000 2 3 4 AMBIENT TEMPERATURE C CLOCK CAP pF APPLIED VREF 2 V Logic Input Threshold CLK IN Threshold Voltage vs Output Current vs Voltage vs Supply Voltage Supply Voltage Temperature T T 55 C lt Tamb lt 125 C Vec 5 0V 55 C
6. errors The source resistance for these inputs should generally be below 5 kQ to help avoid undesired noise pickup Input bypass capacitors at the analog inputs can create errors as described previously Full scale adjustment with any input bypass capacitors in place will eliminate these errors Reference Voltage For application flexibility these A D converters have been designed to accommodate fixed reference voltages of 5V to Pin 20 or 2 5 V to Pin 9 or an adjusted reference voltage at Pin 9 The reference can be set by forcing it at Vrgr 2 input or can be determined by the supply voltage Pin 20 Figure 6 indicates how this is accomplished 2002 Oct 17 Product data ADC0803 0804 Reference Voltage Span Adjust Note that the Pin 9 Vpegr 2 voltage is either 1 2 the voltage applied to the Vcc supply pin or is equal to the voltage which is externally forced at the Vrep 2 pin In addition to allowing for flexible references and full span voltages this also allows for a ratiometric voltage reference The internal gain of the Vrep 2 input is 2 making the full scale differential input voltage twice the voltage at Pin 9 For example a dynamic voltage range of the analog input voltage that extends from 0 to 4 V gives a span of 4 V 4 0 so the Vpgr 2 voltage can be made equal to 2 V half of the 4 V span and full scale output would correspond to 4 V at the input On the other hand if the dynamic input voltage had a range of 0 5 t
7. have additional flexibility due to the analog differential voltage input The Vin input Pin 7 can be used to subtract a fixed voltage from the input reading tare correction This is also useful in a 4 20 mA current loop conversion Common mode noise can also be reduced by the use of the differential input The time interval between sampling Vin and Vin is 4 5 clock periods The maximum error due to this time difference is given by V max Vp 2fcm 4 5 foLk where V error voltage due to sampling delay Vp peak value of common mode voltage fom common mode frequency For example with a 60 Hz common mode frequency fom and a 1 MHz A D clock fork keeping this error to 1 4 LSB about 5 mV would allow a common mode voltage Vp which is given by _ Mmax fox P 2fom 4 5 or 5 x 10 3 104 6 28 60 4 5 Vp 2 95V The allowed range of analog input voltages usually places more severe restrictions on input common mode voltage levels than this however An analog input span less than the full 5 V capability of the device together with a relatively large zero offset can be easily handled by use of the differential input See Reference Voltage Span Adjust Noise and Stray Pickup The leads of the analog inputs Pins 6 and 7 should be kept as short as possible to minimize input noise coupling and stray signal pick up Both EMI and undesired digital signal coupling to these inputs can cause system
8. of the A D output allowing better response time POWER SUPPLIES Noise spikes on the Vcc line can cause conversion errors as the internal comparator will respond to them A low inductance filter capacitor should be used close to the converter Vcc pin and values of 1 uF or greater are recommended A separate 5 V regulator for the converter and other 5 V linear circuitry will greatly reduce digital noise on the Vcc supply and the attendant problems WIRING AND LAYOUT PRECAUTIONS Digital wire wrap sockets and connections are not satisfactory for breadboarding this or any A D converter Sockets on PC boards can be used All logic signal wires and leads should be grouped or kept as far as possible from the analog signal leads Single wire analog input leads may pick up undesired hum and noise requiring the use of shielded leads to the analog inputs in many applications A single point analog ground separate from the logic or digital ground points should be used The power supply bypass capacitor and the self clocking capacitor if used should be returned to digital ground Any Vrer 2 bypass capacitor analog input filter capacitors and any input shielding should be returned to the analog ground point Proper grounding will minimize zero scale errors which are present in every code Zero scale errors can usually be traced to improper board layout and wiring Philips Semiconductors CMOS 8 bit A D converters APPLICATIONS Microprocess
9. output latch Conversion begins with the arrival of a pulse at the WR input if the CS input is low On the High to Low transition of the signal at the WR or the CS input the SAR is initialized the shift register is reset and the INTR output is set high The A D will remain in the reset state as long as the CS and WR inputs remain low Conversion will start from one to eight clock periods after one or both of these inputs makes a Low to High transition After the conversion is complete the INTR pin will make a High to Low transition This can be used to interrupt a processor or otherwise signal the availability of a new conversion result A read RD operation with CS low will clear the INTR line and enable the output latches The device may be run in the free running mode as described later A conversion in progress can be interrupted by issuing another start command Digital Control Inputs The digital control inputs CS WR RD are compatible with standard TTL logic voltage levels The required signals at these inputs correspond to Chip Select START Conversion and Output Enable control signals respectively They are active Low for easy interface to microprocessor and microcontroller control buses For applications not using microprocessors the CS input Pin 1 can be grounded and the A D START function is achieved by a negative going pulse to the WR input Pin 3 The Output Enable function is achieved by a logic low signal at the
10. reference voltage will require an initial adjustment Errors due to an improper reference voltage value appear as full scale errors in the A D transfer function ERRORS AND INPUT SPAN ADJUSTMENTS There are many sources of error in any data converter some of which can be adjusted out Inherent errors such as relative accuracy cannot be eliminated but such errors as full scale and zero scale offset errors can be eliminated quite easily See Figure 7 Zero Scale Error Zero scale error of an A D is the difference of potential between the ideal 1 2 LSB value 9 8 mV for Vref 2 2 500 V and that input voltage which just causes an output transition from code 0000 0000 to a code of 0000 0001 If the minimum input value is not ground potential a zero offset can be made The converter can be made to output a digital code of 0000 0000 for the minimum expected input voltage by biasing the Vin input to that minimum value expected at the Vin input to that minimum value expected at the Vjj input This uses the differential mode of the converter Any offset adjustment should be done prior to full scale adjustment Philips Semiconductors CMOS 8 bit A D converters Full Scale Adjustment Full scale gain is adjusted by applying any desired offset voltage to Vin then applying the Vin a voltage that is 1 1 2 LSB less than the desired analog full scale voltage range and then adjusting the magnitude of Vrer 2 input voltage or the Vcc s
11. ING INFORMATION DESCRIPTION rele ORDER CODE TOPSIDE MARKING DWG 20 pin plastic smalloutine SO package ABSOLUTE MAXIMUM RATINGS Ts Tv Operating temperature range ADC0803LCD ADC0804LCD 40 to 85 ADC0803LCN ADC0804LCN 40 to 85 ADC0803CD ADC0804CD 0 to 70 ADC0803CN ADC0804CN 0 to 70 Pp y Pp y Tstg Storage temperature Tsld Lead soldering temperature 10 seconds Maximum power dissipation Tamb 25 C still air N package 1690 D package 1390 NOTE 1 Derate above 25 C at the following rates N package at 13 5 mW C D package at 11 1 mW C 2002 Oct 17 2 Philips Semiconductors CMOS 8 bit A D converters BLOCK DIAGRAM LADDER AND DECODER AUTO ZERO COMPARATOR Product data ADC0803 0804 SHIFT REGISTER OUTPUT LATCHES CLKIN Figure 2 Block diagram 2002 Oct 17 3 CLKR SL00017 Philips Semiconductors Product data CMOS 8 bit A D converters ADC0803 0804 DC ELECTRICAL CHARACTERISTICS Voc 5 0 V foLk 1 MHZ Tmin lt Tamb lt Tmax unless otherwise specified LIMITS Control inputs Clock in and clock R T Clock in positive going threshold voltage 1 27 30 35 Vic Clock in negative going threshold voltage 15 ag 21 voc VoL Logical 0 clock R output voltage loL 360uA Voo 475Voo 1 04 Y V
12. O INTEGRATED CIRCUITS DATA SHE ADC0803 0804 CMOS 8 bit A D converters Product data 2002 Oct 17 Supersedes data of 2001 Aug 03 Philips PHILIPS Semiconductors FA l LI PS Philips Semiconductors Product data E CMOS 8 bit A D converters ADC0803 0804 DESCRIPTION PIN CONFIGURATION The ADC0803 family is a series of three CMOS 8 bit successive approximation A D converters using a resistive ladder and D N PACKAGES capacitive array together with an auto zero comparator These converters are designed to operate with microprocessor controlled buses using a minimum of external circuitry The 3 State output data lines can be connected directly to the data bus The differential analog voltage input allows for increased common mode rejection and provides a means to adjust the zero scale offset Additionally the voltage reference input provides a means of encoding small analog voltages to the full 8 bits of resolution FEATURES Compatible with most microprocessors Differential inputs TOP VIEW 3 State outputs 8L00016 Logic levels TTL and MOS compatible Figure 1 Pin configuration Can be used with internal or external clock APPLICATIONS Transducer to microprocessor interface Analog input range 0 V to Vcc Single 5 V supply we Digital thermometer Guaranteed specification with 1 MHz clock Digitally controlled thermostat Microprocessor based monitoring and control systems ORDER
13. ctors CMOS 8 bit A D converters al 19 CLKR 4 CLKIN SCN8051 OR SCN80C51 ANALOG 7 Vrer2 INPUTS 12 AGND NE5521 Product data ADC0803 0804 8 BIT BUFFER N74LS241 N74LS244 N74L5541 DE SL00029 Figure 14 Buffering the A D Output to Drive High Capacitance Loads and for Driving Off Board Loads FULL SCALE ADJUST SL00030 Figure 15 Digitizing a Transducer Interface Output 2002 Oct 17 13 Philips Semiconductors Product data CMOS 8 bit A D converters ADC0803 0804 1 4 HEF4071 mg 1 4 HEF4071 SCC80C51 29 P12 20 GND 2N3906 1N4148 3 TO HEATER e LL V SL00031 Figure 16 Digital Thermostat 2002 Oct 17 14 Philips Semiconductors Product data CMOS 8 bit A D converters ADC0803 0804 5020 plastic small outline package 20 leads body width 7 5 mm SOT163 1 5 scale DIMENSIONS inch dimensions are derived from the original mm dimensions 0 012 0 096 0 019 0 51 0 30 inches 9 10 4 994 0088 91 0014 0 49 0 29 Note 1 Plastic or metal protrusions of 0 15 mm maximum per side are not included OUTLINE REFERENCES EUROPEAN VERSION IEC JEDEC EIAJ PROJECTION SOT163 1 075E04 MS 013 EI amp a ISSUE DATE
14. hilips Semiconductors assumes no responsibility or liability for the use of any of these products conveys no license or title under any patent copyright or mask work right to these products and makes no representations or warranties that these products are free from patent copyright or mask work right infringement unless otherwise specified Contact information Koninklijke Philips Electronics N V 2002 For additional information please visit All rights reserved Printed in U S A http www semiconductors philips com Fax 31 40 27 24825 Date of release 10 02 Document order number 9397 750 10538 Lett make things better LAR PHILIPS For sales offices addresses send e mail to sales addresses www semiconductors philips com
15. m IEC 60134 Stress above one or more of the limiting values may cause permanent damage to the device These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied Exposure to limiting values for extended periods may affect device reliability Application information Applications that are described herein for any of these products are for illustrative purposes only Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification Disclaimers Life support These products are not designed for use in life support appliances devices or systems where malfunction of these products can reasonably be expected to result in personal injury Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application Right to make changes Philips Semiconductors reserves the right to make changes in the products including circuits standard cells and or software described or contained herein in order to improve design and or performance When the product is in full production status Production relevant changes will be communicated via a Customer Product Process Change Notification CPCN P
16. o 3 5 V the span or dynamic input range is 3 V 3 5 0 5 To encode this 3 V span with 0 5 V yielding a code of zero the minimum expected input 0 5 V in this case is applied to the Vin pin to account for the offset and the Vper 2 pin is set to 1 2 the 3 V span or 1 5 V The A D converter will now encode the Vin signal between 0 5 and 3 5 V with 0 5 V atthe input corresponding to a code of zero and 3 5 V at the input producing a full scale output code The full 8 bits of resolution are thus applied over this reduced input voltage range The required connections are shown in Figure 7 Operating Mode These converters can be operated in two modes 1 absolute mode 2 ratiometric mode In absolute mode applications both the initial accuracy and the temperature stability of the reference voltage are important factors in the accuracy of the conversion For Vrgr 2 voltages of 2 5 V initial errors of 10 mV will cause conversion errors of 1 LSB due to the gain of 2 at the Vrer 2 input In reduced span applications the initial value and stability of the Vrep 2 input voltage become even more important as the same error is a larger percentage of the Vrer 2 nominal value See Figure 8 In ratiometric converter applications the magnitude of the reference voltage is a factor in both the output of the source transducer and the output of the A D converter and therefore cancels out in the final digital code See Figure 9 Generally the
17. oH Logical 1 clock R output voltage lon 360 pA Vcc 4 75Voo 24 Yw Data output and INTR og lt M ical 1 output voltage Voc Output short circuit current Vout 0 V Tamb 25 C 45 12 mac fork 1 MHz Vgepf 2 OPEN Power supply current CS Logical 1 Tamb 25 C 3 0 3 5 mA NOTES 1 Analog inputs must remain within the range 0 05 lt Vin lt Vcc 0 05 V 2 See typical performance characteristics for input resistance at Voc 5 V 3 VRrer 2 and Vin must be applied after the Vcc has been turned on to prevent the possibility of latching Vor L 2002 Oct 17 4 Philips Semiconductors CMOS 8 bit A D converters AC ELECTRICAL CHARACTERISTICS SYMBOL PARAMETER TO t I me Clock frequency Clock duty cycle Free running conversion rate R WR L Start pulse width N 3 State control Output INTR delay INTR ar I jw oO Logic input capacitance Cour 3 State output capacitance NOTE 1 Accuracy is guaranteed at fork 1 MHz Accuracy may degrade at higher clock frequencies FUNCTIONAL DESCRIPTION These devices operate on the Successive Approximation principle Analog switches are closed sequentially by successive approximation logic until the input to the auto zero comparator Vin Vin matches the voltage from the decoder After all bits are tested and determined the 8 bit binary code corresponding to the input voltage is transferred to an
18. or Interfacing This family of A D converters was designed for easy microprocessor interfacing These converters can be memory mapped with appropriate memory address decoding for CS read input The active Low write pulse from the processor is then connected to the WR input of the A D converter while the processor active Low read pulse is fed to the converter RD input to read the converted data If the clock signal is derived from the microprocessor system clock the designer programmer should be sure that there is no attempt to read the converter until 74 converter clock pulses after the start pulse goes high Alternatively the INTR pin may be used to interrupt the processor to cause reading of the converted data Of course the converter can be connected and addressed as a peripheral in I O space as shown in Figure 12 A bus driver should be used as a buffer to the A D output in large microprocessor systems where the data leaves the PC board and or must drive capacitive loads in excess of 100 pF See Figure 14 Interfacing the SCN8048 microcomputer family is pretty simple as shown in Figure 13 Since the SCN8048 family has 24 I O lines one of these shown here as bit 0 or port 1 can be used as the chip select signal to the converter eliminating the need for an address decoder The RD and WR signals are generated by reading from and writing to a dummy address Digitizing a Transducer Interface Output Circuit Description Figure 15 sho
19. tion is worse for continuous conversions with the Vin input at full scale This current can be a few microamps so bypass capacitors should NOT be used at the analog inputs of the Vrepf 2 input for high resistance sources gt 1 kQ If input bypass capacitors are desired for noise filtering and a high source resistance is desired to minimize capacitor size detrimental effects of the voltage drop across the input resistance can be eliminated by adjusting the full scale with both the input resistance and the input bypass capacitor in place This is possible because the magnitude of the input current is a precise linear function of the differential voltage Philips Semiconductors CMOS 8 bit A D converters Large values of source resistance where an input bypass capacitor is not used will not cause errors as the input currents settle out prior to the comparison time If a low pass filter is required in the system use a low valued series resistor lt 1 kQ for a passive RC section or add an op amp active filter low pass For applications with source resistances at or below 1 kQ a 0 1 uF bypass capacitor at the inputs will prevent pickup due to series lead inductance or a long wire A 100 Q series resistor can be used to isolate this capacitor both the resistor and capacitor should be placed out of the feedback loop from the output of the op amp if used Analog Differential Voltage Inputs and Common Mode Rejection These A D converters
20. to change the specification in any manner without notice Il Preliminary data Qualification This data sheet contains data from the preliminary specification Supplementary data will be published at a later date Philips Semiconductors reserves the right to change the specification without notice in order to improve the design and supply the best possible product Ill Product data Production This data sheet contains data from the product specification Philips Semiconductors reserves the right to make changes at any time in order to improve the design manufacturing and supply Relevant changes will be communicated via a Customer Product Process Change Notification CPCN 1 Please consult the most recently issued data sheet before initiating or completing a design 2 The product status of the device s described in this data sheet may have changed since this data sheet was published The latest information is available on the Internet at URL http www semiconductors philips com 3 For data sheets describing multiple type numbers the highest level product status determines the data sheet status Definitions Short form specification The data in a short form specification is extracted from a full data sheet with the same type number and title For detailed information see the relevant data sheet or data handbook Limiting values definition Limiting values given are in accordance with the Absolute Maximum Rating Syste
21. upply if there is no Vrer 2 input connection for a digital output code which just changes from 1111 1110 to 1111 1111 The ideal Vin voltage for this full scale adjustment is given by Vmax T Vein 255 Vin Vin 1 5 x where Vmax high end of analog input range ground referenced Vein low end zero offset of analog input ground referenced CLOCKING OPTION The clock signal for these A Ds can be derived from external sources such as a system clock or self clocking can be accomplished by adding an external resistor and capacitor as shown in Figure 11 Heavy capacitive or DC loading of the CLK R pin should be avoided as this will disturb normal converter operation Loads less than 50pF are allowed This permits driving up to seven A D converter CLK IN pins of this family from a single CLK R pin of one converter For larger loading of the clock line a CMOS or low power TTL buffer or PNP input logic should be used to minimize the loading on the CLK R pin Restart During a Conversion A conversion in process can be halted and a new conversion began by bringing the CS and WR inputs low and allowing at least one of them to go high again The output data latch is not updated if the conversion in progress is not completed the data from the previously completed conversion will remain in the output data latches until a subsequent conversion is completed Continuous Conversion To provide continuous conversion of inp
22. ut data the CS and RD inputs are grounded and INTR output is tied to the WR input This INTR WR connection should be momentarily forced to a logic low upon power up to insure circuit operation See Figure 10 for one way to accomplish this 2002 Oct 17 Product data ADC0803 0804 DRIVING THE DATA BUS This CMOS A D converter like MOS microprocessors and memories will require a bus driver when the total capacitance of the data bus gets large Other circuitry tied to the data bus will add to the total capacitive loading even in the high impedance mode There are alternatives in handling this problem The capacitive loading of the data bus slows down the response time although DC specifications are still met For systems with a relatively low CPU clock frequency more time is available in which to establish proper logic levels on the bus allowing higher capacitive loads to be driven see Typical Performance Characteristics At higher CPU clock frequencies time can be extended for I O reads and or writes by inserting wait states 8880 or using clock extending circuits 6800 8035 Finally if time is critical and capacitive loading is high external bus drivers must be used These can be 3 State buffers low power Schottky is recommended such as the N74LS240 series or special higher current drive products designed as bus drivers High current bipolar bus drivers with PNP inputs are recommended as the PNP input offers low loading
23. ws an example of digitizing transducer interface output voltage In this case the transducer interface is the NE5521 an LVDT Linear Variable Differential Transformer Signal Conditioner The diode at the A D input is used to insure that the input to the A D does not go excessively beyond the supply voltage of the A D See 2002 Oct 17 Product data ADC0803 0804 the NE5521 data sheet for a complete description of the operation of that part Circuit Adjustment To adjust the full scale and zero scale of the A D determine the range of voltages that the transducer interface output will take on Set the LVDT core for null and set the Zero Scale Scale Adjust Potentiometer for a digital output from the A D of 1000 000 Set the LVDT core for maximum voltage from the interface and set the Full Scale Adjust potentiometer so the A D output is just barely 1111 1111 A Digital Thermostat Circuit Description The schematic of a Digital Thermostat is shown in Figure 16 The A D digitizes the output of the LM35 a temperature transducer IC with an output of 10 mV per C With Vpgp 2 set for 2 56 V this 10 mV corresponds to 1 2 LSB and the circuit resolution is 2 C Reducing Vrep 2 to 1 28 yields a resolution of 1 C Of course the lower VRrerf 2 is the more sensitive the A D will be to noise The desired temperature is set by holding either of the set buttons closed The SCC80C451 programming could cause the desired set temperature to be

philips ADC0803/0804 CMOS 8-bit A/D converters handbook

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