ANALOG DEVICES AD7720 English products handbook
Contents
1. 5 5 22 RESET Reset Logic Input RESET 15 asynchronous input When RESET is taken high the sigma delta modulator is reset by shorting the integrator capacitors in the modulator D VAL goes low for 20 M CLK cycles while the modulator is being reset 27 REF1 Reference Input O utput REF 1 connects via a resistor to the output of the internal 2 5 V reference and to the input of a buffer amplifier that drives the sigma delta modulator T his pin can also be overdriven with an external 2 5 V reference REV 0 AD7720 TERMINOLOGY IDEAL FIR FILTER USED WITH AD7720 FIGURE 1 Integral Nonlinearity T his is the maximum deviation of any code from a straight line passing through the endpoints of the transfer function T he endpoints of the transfer function are zero scale not to be con fused with bipolar zero a point 0 5 LSB below the first code transition 100 00 to 100 01 bipolar mode and 000 00 000 01 unipolar mode and full scale point 0 5 LSB above the last code transition 011 10 to 011 11in bipolar mode and 111 10to 111 11 unipolar mode T he error is expressed in LSBs Differential Nonlinearity T his is the difference between the measured and the ideal 1 LSB change between two adjacent codes in the ADC Common Mode Rejection Ratio T he ability of a device to reject the effect of a voltage applied to both input terminals simultaneously often through variat2. 0 20000 40000 65535 CODE Figure 13 Differential Nonlinearity REV 0 AD7720 INL ERROR LSB 20000 40000 65535 CODE Figure 14 Integral Nonlinearity Error dB 0 10 20 30 40 50 T T T1 60 70 80 90 100 110 120 130 0 6 25 FREQUENCY MHz Figure 15 Modulator Output 0 Hz to MCLK 2 0 20 CLKIN 12 5MHz SNR 90 1dB 40 S N D 89 2dB SFDR 99 5dB 60 THD 96 6dB 2ND 100 9dB 5 80 3RD 106 0dB 99 5dB 100 120 140 154 0 0 10E 3 20 3 30E 3 40E 3 50 3 60 3 70 3 80 3 90E 3 98E 3 Figure 16 16K Point FFT 0 20 12 288MHz SNR 89 0dB 40 S N D 87 8dB SFDR 94 3dB 60 THD 93 2ND 94 80 3RD 108 5dB 105 7dB 154 0E 0 10 3 20E 3 30 3 40 3 50E 3 60 3 70 3 80 3 90 3 96E 3 Figure 17 16K Point FFT REV 0 dB 100 110 I 120 130 0 393 295 kHz FREQUENCY kHz Figure 18 Modulator Output 0 to 393 295 kHz AIN 90kHz CLKIN 12 5 MHz SNR 89 6dB S N D 89 6dB SFDR 108 0dB dB 100 120 140 1
3. and fa 2fb AD7720 Typical Characteristics AVDD DVDD 5 0 V Ty 25 C CLKIN 12 5 MHz 20 kHz Bipolar Mode 0 V to 2 5 V V 1 25 V unless otherwise noted 110 SFDR 0 40 30 20 10 0 INPUT LEVEL dB Figure 5 S N 4D and SFDR vs Analog Input Level SNR Vin Vi 1 25 95 Vem 2 5V 9 100 THD SFDR 0 20 40 60 80 100 INPUT FREQUENCY kHz Figure 8 SNR THD and SFDR vs Input Frequency 50 25 0 25 50 75 100 TEMPERATURE Figure 11 vs Temperature AIN 1 5 BW dB 0 50 100 150 200 250 300 OUTPUT DATA RATE kSPS Figure 6 S N4D vs Output Sample Rate AIN 1 5 BW Vin Vin 1 25 Vow 2 5 0 50 100 150 200 250 300 OUTPUT DATA RATE kSPS Figure 9 S N4D vs Output Sample Rate FREQUENCY OF OCCURENCE CODES Figure 12 Histogram of Output Codes with DC Input 0 20 40 60 80 100 INPUT FREQUENCY kHz Figure 7 SNR THD and SFDR vs Input Frequency T 90 5 2 o TEMPERATURE Figure 10 SNR vs Temperature DNL ERROR LSB
4. for a sine wave input is given by Signal to N oise Distortion 6 02 1 76 dB where N is the number of bits Total Harmonic Distortion T otal armonic Distortion TH D is the ratio of the rms sum of harmonics to the rms value of the fundamental For the AD7720 THD is defined as V 24V 24V 23V 24V 2 Vi where is the rms amplitude of the fundamental and V3 V4 Vs and Vg arethe rms amplitudes of the second through the sixth harmonic THD ood Spurious Free Dynamic Range Spurious free dynamic range is the difference in dB between the peak spurious or harmonic component in the AD C output spectrum up to fyc 128 and excluding dc and the rms value of the fundamental N ormally the value of this specification will be determined by the largest harmonic in the output spectrum of the FFT For input signals whose second harmonics occur in the stop band region of the digital filter a spur in the noise floor limits the spurious free dynamic range Intermodulation Distortion With inputs consisting of sine waves at two frequencies fa and fb any active device with nonlinearities will create distortion products at sum and difference frequencies of mfa nfb where m n 0 1 2 3 etc Intermodulation distortion terms are those for which neither m or n are equal to zero For example the second order terms include fa fb and fa fb while the third order terms include 2fa fb 2fa fb fa 2fb
5. the calibra tion cycle On changing to a different analog input mode a new calibration must be performed Before calibrating ensure that the supplies have settled and that the voltage on the analog input pins is between the supply voltages Standby T he part can be put into a low power standby mode by taking ST BY high During standby the clock to the modulator is turned off and bias is removed from all analog circuits Reset TheRESET pin is used to reset the modulator to a known state When RESET istaken high the integrator capacitors of the modulator are shorted and D VAL goes low and remains low until 20 M CLK cycles after RESET is deasserted H owever an additional 1000 M CLK cycles should be allowed before reading the modulator bit stream as the modulator circuitry needs to settle after the reset DVAL TheDVAL pin is used to indicate that an overrange input signal has resulted in invalid data at the modulator output As with all single bit DAC high order sigma delta modulators large overloads on the inputs can cause the modulator to go unstable T he modulator is designed to be stable with signals within the input bandwidth that exceed full scale by 2096 When instability is detected by internal circuits the modulator is reset to a stable state and DVAL is held low for 20 clock cycles Grounding and Layout Since the analog inputs are differential most of the voltages in the analog modulator are common mode voltages T h
6. to 2 5 V signal at the VIN 4 pin to form a differential signal around an initial bias voltage of 1 25 V For single ended applications best TH D performance is obtained with VIN set to 1 25 V rather than 2 5 V Theinput to the AD 7720 can also be driven differen tially with a complementary input as shown in Figure 29 In this case the input common mode voltage is set to 2 5 V The2 5 V p p full scale differential input is obtained with a 1 25 V p p signal at each input in antiphase T his configuration minimizes the required output swing from the amplifier circuit and is useful for single supply applications 2115 DIFFERENTIAL INPUT 2 5 VIN BIAS VOLTAGE 1 25V Figure 28 Single Ended Analog Input for Bipolar Mode Operation 12pF AIN 0 625V Q VIN DIFFERENTIAL INPUT 2 5V p p COMMON MODE VOLTAGE 2 5V Figure 29 Single Ended to Differential Analog Input Circuit for Bipolar Mode Operation Thel nF capacitors at each ADC input store charge to aid the amplifier settling as the input is continuously switched A resis tor in series with the drive amplifier output and the 1 nF input capacitor may also be used to create an antialias filter Clock Generation The AD7720 contains an oscillator circuit to allow a crystal or an external clock signal to generate the master clock for the ADC The connection diagram for use with the crystal is shown in Figure 30 Consult the crystal manufa
7. to the clock and will produce excess jitter T he jitter can cause unwanted degradation in the signal to noise ratio and also produce un wanted harmonics T his can be somewhat remedied by transmitting the sampling clock signal as a differential one using either a small RF trans former or a high speed differential driver and receiver such as PECL In either case the original master system clock should be generated from a low phase noise crystal oscillator 2125 REV 0 AD7720 Offset and Gain Calibration T he analog inputs of the AD 7720 can be configured to measure offset and gain errors Pins M ZERO and GC are used to config ure the part Before calibrating the device the part should be reset so that the modulator is in a known state at calibration When M ZERO istaken high the analog inputs are tied to AGN D unipolar mode and Vaer in bipolar mode After taking M ZERO high 1000 M CLK cycles should be allowed for the circuitry to settle before the bit stream is read from the device T he ideal ones density is 5096 when bipolar operation is selected and 37 596 when unipolar mode is selected When istaken high VIN is tied to ground while VIN is tied to Again 1000 M CLK cycles should be allowed for the circuitry to settle before the bit stream is read T he ideal ones density is 62 596 T he calibration results apply only for the particular analog input mode unipolar bipolar selected when performing
8. 0 3 to AVDD 0 3 V Input Current to Any Pin Except Supplies 10 mA O perating T emperature R ange Industrial B Version 40 to 85 Storage T emperatureRange 65 to 150 M aximum Junction Temperature 150 TSSOP Package Oja Thermal Impedance 120 C W Lead T emperature Soldering Vapor Phase 60 sec 215 Infrared 15 sec 220 BUT NO CONNECT NOTES Stresses above those listed under Absolute M aximum Ratings may cause perma nent damageto the device T his is a stress rating only functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied Exposure to absolute maximum rating conditions for extended periods may affect device reliability T ransient currents of up to 100 mA will not cause SCR latchup ORDERING GUIDE Temperature Package Package Model Range Description Option AD 7720BRU 40 to 85 28 1 ead T hin Shrink Small Outline RU 28 CAUTION ESD electrostatic discharge sensitive device Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection WARNING Although the AD 7720 features proprietary ESD protection circuitry permanent damage epit occur on devices subjected to high energy el
9. 54 0 0 10 3 20 3 30 3 40 3 50E 3 60 3 70 3 80 3 90 3 98 3 Figure 19 16K Point FFT AIN 90kHz XTAL 12 288MHz SNR 88 1dB 0 SFDR 103 7dB dB 154 OE 0 10 3 20 3 30 3 40E 3 50 3 60 3 70 3 80 3 90 3 96E 3 Figure 20 16K Point FFT AD7720 CIRCUIT DESCRIPTION Sigma Delta ADC The AD7720 ADC employs a sigma delta conversion technique that converts the analog input into a digital pulse train The analog input is continuously sampled by a switched capacitor modulator at twice the rate of the clock input frequency 2 x T he digital data that represents the analog input is in the one s density of the bit stream at the output of the sigma delta modulator T he modulator outputs the bit stream at a data rate equal to fuci D ue to the high oversampling rate which spreads the quantiza tion noise from 0 to 2 the noise energy contained in the band of interest is reduced Figure 21a T o reduce the quanti zation noise further a high order modulator is employed to shape the noise spectrum so that most of the noise energy is shifted out of the band of interest Figure 21b QUANTIZATION NOISE e BAND OF INTEREST a NOISE SHAPING fucik 2 BAND OF INTEREST b Figure 21 Sigma Delta ADC USING THE AD7720 ADC Differential Inputs The AD 7720 uses differential inputs to provide common mode noise r
10. ANALOG DEVICES CMOS Sigma Delta Modulator 07720 5 12 5 MHz Master Clock Frequency OV to 432 5 V or 1 25 V Input Range Single Bit Output Stream 90 dB Dynamic Range Power Supplies AVDD DVDD 5 V 5 On Chip 2 5 V Voltage Reference 28 Lead TSSOP GENERAL DESCRIPTION T his device is a 7th order sigma delta modulator that converts the analog input signal into a high speed 1 bit data stream T he part operates from a 5 V supply and accepts a differential input range of 0 V to 42 5 V or 1 25 V centered about a common mode bias T he analog input is continuously sampled by the analog modulator eliminating the need for external sample and hold circuitry T he input information is contained in the output stream as a density of ones T he original information can be reconstructed with an appropriate digital filter T he part provides an accurate on chip 2 5 V reference A refer ence input output function is provided to allow either the inter nal reference or an external system reference to be used as the reference source for the part T he device is offered in a 28 lead T SSOP package and designed to operate from 40 to 85 REV 0 Information furnished by Analog Devices is believed to be accurate and reliable However no responsibility is assumed by Analog Devices for its use nor for any infringements of patents or other rights of third parties which may result from its use No license is gra
11. REF1 and AGND If the internal reference is required to bias external circuits use an external precision op amp to buffer REF 1 COMPARATOR REFERENCE BUFFER SWITCHED CAP DAC REF Figure 25 Reference Circuit Block Diagram REV 0 The AD 7720 can operate with its internal reference or an external reference can be applied in two ways An external reference can be connected to REF 1 overdriving the internal reference H ow ever there will be an error introduced due to the offset of the internal buffer amplifier For lowest system gain errors when using an external reference REF 1 is grounded disabling the internal buffer and the external reference is connected to REF 2 In all cases since the REF 2 voltage connects to the analog modulator a 220 nF capacitor must connect directly from REF2to AGND The external capacitor provides the charge required for the dynamic load presented at the REF2 pin Figure 26 SWITCHED CAP DAC REF MCLK Figure 26 REF2 Equivalent Circuit The AD 780 is ideal to use as an external reference with the AD 7720 Figure 27 shows a suggested connection diagram Figure 27 External Reference Circuit Connection Input Circuits Figures 28 and 29 show two simple circuits for bipolar mode operation Both circuits accept a single ended bipolar signal source and create the necessary differential signals at the input to the ADC T he circuit in Figure 28 creates a 0 V
12. amp the amplitude will momentarily drop T he op amp will try to correct the situation and in the process hits its slew rate limit T his nonlinear response which can cause excessive ring ing can lead to distortion T o remedy the situation a low pass RC filter can be connected between the amplifier and the input to the AD 7720 as shown in Figure 23 T he external capacitor at each input aids in supplying the current spikes created during the sampling process T he resistor in this diagram as well as creating the pole for the antialiasing isolates the op amp from the transient nature of the load ANALOG INPUT Figure 23 Simple RC Antialiasing Circuit T he differential input impedance of the AD 7720 switched capacitor input varies as a function of the M CLK frequency given by the equation Zin 109 8 Even though the voltage on the input sampling capacitors may not have enough time to settle to the accuracy indicated by the resolution of the AD 7720 as long as the sampling capacitor charging follows the exponential curve of RC circuits only the gain accuracy suffers if the input capacitor is switched away too early An alternative circuit configuration for driving the differential inputs to the AD 7720 is shown in Figure 24 REV 0 AD7720 2 7nF VIN 2 7nF Figure 24 Differential Input with Antialiasing A capacitor between the two input pins sources or sinks ch
13. arge to allow most of the charge that is needed by one input to be effectively supplied by the other input T his minimizes undesir able charge transfer from the analog inputs to and from ground T he series resistor isolates the operational amplifier from the current spikes created during the sampling process and provides a pole for antialiasing T he 3 dB cutoff frequency fs of the antialias filter is given by Equation 1 and the attenuation of the filter is given by Equation 2 1 2 Rext 1 2 Attenuation 20 log Y 2 T he choice of the filter cutoff frequency will depend on the amount of roll off that is acceptable in the passband of the digital filter and the required attenuation at the first image frequency T he capacitors used for the input antialiasing circuit must have low dielectric absorption to avoid distortion ilm capacitors such as Polypropylene Polystyrene or Polycarbonate are suitable If ceramic capacitors are used they must have N PO dielectric Applying the Reference T he reference circuitry used in the AD 7720 includes an on chip 2 5 V bandgap reference and a reference buffer circuit T he block diagram of the reference circuit is shown in Figure 25 T he internal reference voltage is connected to REF 1 via resistor and is internally buffered to drive the analog modulator s switched capacitor DAC REF2 When using the internal reference connect 100 nF between
14. cturer s recommenda tion for the load capacitors Figure 30 Crystal Oscillator Connection An external clock must be free of ringing and have a minimum rise time of 5 ns Degradation in performance can result as high edge rates increase coupling that can generate noise in the sam pling process T he connection diagram for an external clock source Figure 31 shows a series damping resistor connected between the clock output and the clock input to the AD 7720 T he optimum resistor will depend on the board layout and the impedance of the trace connecting to the clock input 25 1500 CLOCK CIRCUITRY Figure 31 External Clock Oscillator Connection A low phase noise clock should be used to generate the ADC sampling clock because sampling clock jitter effectively modu lates the input signal and raises the noise floor T he sampling clock generator should be isolated from noisy digital circuits grounded and heavily decoupled to the analog ground plane T he sampling clock generator should be referenced to the ana log ground plane in a split ground system H owever this is not always possible because of system constraints many cases the sampling clock must be derived from a higher frequency multipurpose system clock that is generated on the digital ground plane If the clock signal is passed between its origin on a digital plane to the AD 7720 on the analog ground plane the ground noise between the two planes adds directly
15. e excellent REV 0 common mode rejection of the part will remove common mode noise on these inputs T he analog and digital supplies to the AD 7720 are independent and separately pinned out to minimize coupling between analog and digital sections of the device T he printed circuit board that houses the AD 7720 should be designed so that the analog and digital sections are separated and confined to certain areas of the board T his facilitates the use of ground planes which can easily be separated A minimum etch technique is generally best for ground planes as it gives the best shielding Digital and analog ground planes should only be joined in one place If the AD 7720 is the only device requir ing an AGND to DGND connection the ground planes should be connected at the AGND and DGND pins of the AD 7720 If the AD 7720 is a system where multiple devices require AGND to DGND connections the connection should still be made at one point only a star ground point that should be established as close as possible to the AD 7720 Avoid running digital lines under the device as these will couple noise onto the die T he analog ground plane should be allowed to run under the AD 7720 to avoid noise coupling The power supply lines to the AD 7720 should use as large a trace as pos sibleto provide low impedance paths and reduce the effects of glitches on the power supply line Fast switching signals like clocks should be shielded with digital g
16. ectrostatic discharges Therefore proper ESD precautions are recommended to avoid performance degradation or loss of functionality ESD SENSITIVE DEVICE REV 0 5 PIN FUNCTION DESCRIPTIONS Pin No Mnemonic Function 1 REF2 Reference Input O utput REF2 connects to the output of an internal buffer amplifier used to drive the sigma delta modulator When REF2 is used as an input REF 1 must be con nected to AGND 2 14 18 20 24 26 AGND Ground reference point for analog circuitry 3 13 NC N o Connect 4 ST BY Standby Logic Input When ST BY is high the device is placed in a low power mode When ST BY islow the device is powered up 5 DVAL D ata Valid Logic Output A logic high on DVAL indicates that the data bit stream from the AD 7720 is an accurate digital representation of the analog voltage at the input to the sigma delta modulator T he DVAL pin is set low for 20 M CLK cycles if the analog input is overranged 6 15 DGND Ground reference for the digital circuitry 7 GC Digital Control Input When GC is high the gain error of the modulator can be calibrated 8 BIP Analog Input Range Select Logic Input A logic low on this input selects unipolar mode A logic high selects bipolar mode 9 M ZERO Digital Control Input When M ZERO is high the modulator inputs are internally grounded i e tied to AGND in unipolar mode and REF2 in bipolar mode M ZERO allows on chip offsets to be calibrated out M ZERO is low
17. ejection i e the converted result will correspond to the differential voltage between the two inputs T he absolute volt age both inputs must lie between AGND and AVDD In the unipolar mode the full scale input range VIN VIN is 0 V to Vref In the bipolar mode configuration the full scale analog input range is 2 The bipolar mode allows complementary input signals Alternatively VIN can be connected to a dc bias voltage to allow a single ended input on VIN equal to Vgias 2 Differential Inputs T he analog input to the modulator is a switched capacitor de sign T he analog input is converted into charge by highly linear sampling capacitors A simplified equivalent circuit diagram of the analog input is shown in Figure 22 A signal source driving the analog input must be able to provide the charge onto the sampling capacitors every half M CLK cycle and settle to the required accuracy within the next half cycle 10 AC GROUND Figure 22 Analog Input Equivalent Circuit Since the AD 7720 samples the differential voltage across its analog inputs low noise performance is attained with an input circuit that provides low differential mode noise at each input T he amplifiers used to drive the analog inputs play a critical role in attaining the high performance available from the AD 7720 When a capacitive load is switched onto the output of an op
18. for normal operation 10 DATA M odulator Bit Stream T he digital bit stream from the sigma delta modulator is output at DATA 11 SCLK Serial Clock Logic Output T he bit stream from the modulator is valid on the rising edge of SCLK 12 RESETO Reset Logic Output T he signal applied to the RESET pin is made available as an output at RESETO 16 XTAL1 M CLK CMOS Logic Clock Input The XT AL1 M CLK pin interfaces the device s internal oscillator circuit to an external crystal or an external clock A parallel resonant fundamental frequency microprocessor grade crystal and a 1 resistor should be connected between the C L K and XTAL pins with two capacitors connected from each pin to ground Alternatively the XTAL1 MCLK pin can be driven with an external CM OS compatible clock T he part is specified with a 12 5 M H z master clock 17 XTAL2 Oscillator Output The XT AL2 pin connects the internal oscillator output to an external crystal If an external clock is used XT AL2 should be left unconnected 19 DVDD Digital Supply Voltage 5 V 596 21 23 VIN VIN Analog Input In unipolar operation the analog input range on VIN is VIN to VIN for bipolar operation the analog input range on VIN is VIN 2 T he absolute analog input range must lie between 0 and AVDD T he analog input is con tinuously sampled and processed by the analog modulator 25 28 AVDD Analog Positive Supply Voltage
19. ilter Consists of 2 FIR Filters This filter is implemented on the AD7722 REV 0 3 AD7720 NG CHARACTE RI STICS AVDD 5 V 5 DVDD 5 V 596 AGND 0 V 72 5 V unless otherwise noted Limit at Twin Tmax Parameter B Version Units Conditions Comments fucik 100 kH z min M aster Clock Frequency 15 M Hz max 12 5 M H z for Specified Performance 67 ns min M aster Clock Period t 0 45 x tucik ns min M aster Clock Input High T ime t 0 45 x ns min M aster Clock Input Low T ime t 15 ns min D ata Hold T ime After SCLK Rising Edge t 10 nsmin RESET Pulsewidth tc 10 ns min RESET Low T ime Before M CLK Rising t 20 x ns max DVAL High D elay after RESET Low NOTE Guaranteed by design SCLK O id NOTE O SIGNIFIES AN OUTPUT Figure 3 Data Timing SES x AT E E NC NN t RESET ts k lt DVAL 0 SIGNIFIES AN INPUT O SIGNIFIES AN OUTPUT Figure 4 RESET Timing 4 REV 0 AD7720 ABSOLUTE MAXIMUM RATINGS PIN CONFIGURATION T4 25 C unless otherwise noted DVDDtoDGND 0 3 V to 7 V AVDD to AGND 0 3 V to 7 V AVDD to DVDD 0 3 V to 0 3 V AGND toDGND 0 3 V to 40 3V Digital Input Voltageto 0 3V to DVDD 0 3 V Analog Input Voltage to AGND
20. ion of a ground level is specified as a common mode rejection ratio CMRR isthe ratio of gain for the differential signal to the gain for the common mode signal Unipolar Offset Error U nipolar offset error is the deviation of the first code transition from the ideal VIN voltage which is VIN 0 5 LSB when operating in the unipolar mode Bipolar Offset Error This is the deviation of the midscale transition 111 11 to 000 00 from the ideal VIN voltage which is VIN 0 5 LSB when operating in the bipolar mode Gain Error T he first code transition should occur at an analog value 1 2 LSB above minus full scale T he last code transition should occur for an analog value 3 2 LSB below the nominal full scale Gain error is the deviation of the actual difference between first and last code transitions and the ideal difference between first and last code transitions Signal to Noise Distortion Signal to N oise Distortion is measured signal to noise at the output of the ADC T he signal is the rms magnitude of the REV 0 fundamental N oise plus distortion is the rms sum of all of the nonfundamental signals and harmonics to half the output word rate 128 excluding dc Signal to N oise Distortion is dependent on the number of quantization levels used in the digitization process the more levels the smaller the quantiza tion noise T he theoretical Signal to N oise Distortion ratio
21. ls 515 olo es 0 006 0 15 Te 0 0433 69 nx nn nin uin TF 0 028 0 70 0 0256 0 65 0 0118 0 30 0 0 020 0 50 SEATING BSC 0 0075 0 19 2 0079 0 20 0 0035 0 090 14 REV 0 215 L6 01 8 SECEO V S n NI GALNIdd 16
22. nted by implication or otherwise under any patent or patent rights of Analog Devices FUNCTIONAL BLOCK DIAGRAM AVDD AGND SIGMA DELTA MODULATOR DVDD DGND REF1 2 5V REFERENCE One Technology Way P O Box 9106 Norwood MA 02062 9106 U S A Tel 781 329 4700 World Wide Web Site http www analog com Fax 781 326 8703 Analog Devices Inc 1997 AD7720 SPECIFICATIONS AVDD 5 5 DVDD 5 V 5 AGND 0 V 12 5 MHz REF2 2 5 V Ta to unless otherwise noted Parameter B Version Units Test Conditions C omments STATIC PERFORMANCE When T ested with Ideal FIR Filter asin Figure 1 Resolution 16 Bits Differential N onlinearity t1 LSB max Guaranteed M onotonic Integral N onlinearity 2 LSB typ Precalibration Offset Error t6 mV typ Precalibration Gain Error 0 6 FSR typ Postcalibration Offset Error 1 5 mV typ Postcalibration Gain Error 3 0 3 FSR typ Offset Error D rift 1 LSB C typ Gain Error D rift REF2 Isan Ideal Reference REF1 AGND Unipolar M ode 1 LSB C typ Bipolar M ode 0 5 LSB C typ ANALOG INPUTS Signal Input Span VIN VIN Bipolar M ode tVner2 2 V max Unipolar M ode to BIP V M aximum Input Voltage AVDD V Minimum Input Voltage 0 V Input Sampling Capacitance 2 pF typ Input Sampling Rate 2 fucik MHz Differential Input Impedance 1098 KQ typ REFERENCE INPUTS REF1 Outpu
23. round to avoid radiating noise to other sections of the board and clock signals should never be run near the analog inputs Avoid crossover of digital and analog signals T races on opposite sides of the board should run at right angles to each other T his will reduce the effects of feedthrough through the board A microstrip technique is by far the best but is not always possible with a double sided board In this technique the component side of the board is dedi cated to ground planes while signals are placed on the other side G ood decoupling is important when using high resolution AD C s All analog and digital supplies should be decoupled to AGND and DGND respectively with 100 nF ceramic capacitors in parallel with 10 uF tantalum capacitors T o achieve the best from these decoupling capacitors they should be placed as close as possible to the device ideally right up against the device In systems where a common supply voltage is used to drive both the AVDD and DVDD ofthe AD 7720 it is recommended that the system s AVDD supply is used T his supply should have the recommended analog supply decoupling between the AVDD pin of the AD 7720 and AGND and the recommended digital supply decoupling capacitor between the DVDD pins and DGND 13 AD7720 OUTLINE DIMENSIONS Dimensions shown in inches and mm 28 Lead Thin Shrink Small Outline RU 28 0 386 9 80 0 378 9 60 H Ji 88 88 Ex eje 2 lt als s
24. t Voltage 2 32 to 2 62 V min max REF 1 Output Voltage Drift 60 ppm C typ REF1 Output Impedance 3 typ Reference Buffer Offset Voltage t12 mV max Offset Between REF 1 and REF2 Using Internal Reference REF 2 Output Voltage 2 32 to 2 62 V min max REF 2 Output Voltage D rift 60 ppm C typ U sing External Reference REF1 AGND REF 2 Input Impedance 109 16 KQ typ External Reference V oltage Range 2 32 to 2 62 V min max Applied to REF2 DYNAMIC SPECIFICATIONS When T ested with Ideal FIR Filter asin Figure 1 Bipolar M ode Vem 22 5 V VIN VIN 1 25 V or VIN 1 25 V VIN 0 V to 2 5 V Signal to N oise Distortion 90 dB typ Input BW 0 kHz 90 625 kHz 86 84 5 dB min T otal H armonic Distortion 90 88 dB max Input BW 0 z 90 625 kHz Spurious F ree D ynamic Range 90 dB max Input BW 0 kHz 90 625 kHz U nipolar M ode V VIN 20V 0 to2 5V Signal to oise Distortion 88 dB typ Input BW 0 kHz 90 625 kHz 84 5 83 dB min T otal H armonic Distortion 89 87 dB max Input BW 0 kHz 97 65 kHz Spurious F ree D ynamic Range 90 dB max Input BW 0 kHz 97 65 kHz Intermodulation D istortion 93 dB typ AC CMRR 96 dB typ VIN VIN 2 5 V Vey 1 25 V to 3 75 V 20 kHz Overall Digital F ilter Response See Figure 1 for Characteristics of FIR Filter 0 kH z 90 625 kHz X 0 005 dB max 96 92 kHz 3 dB min 104 6875 kHz to 12 395 MHz 90 dB typ CLOCK MCLK D
25. uty Ratio 45 to 55 96 max For Specified O peration High Voltage 4 V min MCLK Uses CMOS Logic Low Voltage 0 4 V max REV 0 AD7720 Parameter B Version Units Test Conditions C omments LOGIC INPUTS Viu Input H igh Voltage 2 V min Vit Input Low Voltage 0 8 V max ling Input Current 10 uA max Cin Input Capacitance 10 pF max LOGIC OUTPUTS Output High Voltage 2 4 V min lt 200 pA Output Low Voltage 0 4 V max lt 1 6 mA POWER SUPPLIES AVDD 4 75 5 25 V min V max DVDD 4 75 5 25 V min V max lbp Total for AVDD DVDD Digital Inputs Equal to 0 V or DVDD Active M ode 43 mA max Standby M ode 25 pA max NOTES Operating temperature range is as follows B Version 40 C to 85 Gain Error excludes reference error he modulator gain is calibrated w r t the voltage on the REF2 pin 3Applies after calibration at temperature of interest M easurement Bandwidth 0 5 x Input Level 0 05 dB 25 C to 85 C T 4 T m n to Tmax Specifications subject to change without notice 16 BIT OUTPUT BITSTREAM 90 625kHz 90 625kHz DECIMATE DECIMATE BY 32 BY2 FILTER 1 292 969kHz FILTER 2 104 687kHz BANDWIDTH 90 625 kHz BANDWIDTH 90 625 kHz TRANSITION 292 969kHz TRANSITION 104 687kHz ATTENUATION 120dB ATTENUATION 90dB COEFFICIENTS 384 COEFFICIENTS 151 Figure 1 Digital F
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ANALOG DEVICES AD7720 English products handbook