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ANALOG DEVICES ADIS16305 English products handbook0

1. 18 Theory aUe eda UE 9 Gyroscope Bias Optimization esee 18 Basic or ena OMIM dee 9 Outline Dimensions oet te da ha 19 Reading Sensor 9 Orderino GUS xis aen I RE P dp vated 19 Device Config UAL OM esie rein 9 REVISION HISTORY 7110 Revision 0 Initial Version Rev 0 Page 2 of 20 SPECIFICATIONS Ta 25 C 5 0 V angular rate 0 sec dynamic range 300 sec 1 g unless otherwise noted Table 1 Parameter GYROSCOPE Dynamic Range Initial Sensitivity Sensitivity Temperature Coefficient Misalignment Nonlinearity Initial Bias Error In Run Bias Stability Angular Random Walk Bias Temperature Coefficient Linear Acceleration Effect on Bias Voltage Sensitivity Output Noise Rate Noise Density 3 dB Bandwidth Sensor Resonant Frequency Self Test Change in Output Response ACCELEROMETERS Dynamic Range Initial Sensitivity Sensitivity Temperature Coefficient Misalignment Nonlinearity Initial Bias Error In Run Bias Stability Velocity Random Walk Bias Temperature Coefficient Output Noise Noise Density 3 dB Bandwidth Sensor Resonant Frequency Self Test Change in Output Response ADC INPUT Resolution Integral Nonlinearity Differential Nonlinearity Offset Error Gain Error Input Range Input Capacitance Ta 25 C dynamic range 300 sec Ta 25 C dynamic range 150 sec 25
2. ALM CTRL 0x76C7 OxAEC7 Alarm 1 input YACCL OUT Alarm 2 input ZACCL OUT Rate of change comparison unfiltered data DIO2 output indicator positive polarity OxB601 SMPL PRD 0x0001 Sample rate 819 2 SPS OxAA08 ALM_SMPL1 0x0008 Alarm 1 rate of change period 9 77 ms OxAC50 ALM SMPL2 0x0050 Alarm 2 rate of change period 97 7 ms 0xA783 ALM 0x8341 0xA641 Alarm 1 is true when A XACCL OUT gt 0 5 period of 9 77 ms OxA93C ALM MAG2 Ox3CBF OxA8BF Alarm 1 is true when A XACCL OUT lt 0 5 over a period of 97 7 ms PRODUCT IDENTIFICATION Table 35 provides a summary of the registers that identify the product PROD ID which identifies the product type LOT_ID1 and LOT ID2 the 32 bit lot identification code and SERIAL NUM which displays the 12 bit serial number All four registers are two bytes in length When using the SERIAL NUM value to calculate the serial number mask off the upper four bits and convert the remaining 12 bits to a decimal number Table 35 Identification Registers Register Name Description LOT ID1 Lot Identification Code 1 LOT ID2 Lot Identification Code 2 PROD ID ADIS16305 Ox3FB1 16 305 SERIAL NUM Serial number 0 to 4095 Rev 0 Page 17 of 20 ADIS16305 APPLICATIONS INFORMATION INTERFACE PRINTED CIRCUIT BOARD PCB The ADIS16305 PCBZ includes one ADIS16305ALMZ one interface PCB and one interface flex This combination simplifies the process o
3. The sampling capacitor C2 has a typical value of 16 pF 1 C2 o w C1 D 09020 015 Figure 15 Equivalent Analog Input Circuit Conversion Phase Switch Open Track Phase Switch Closed Table 15 ADC Measurement Offset Binary Format Input Voltage Binary 3 3V 4095 LSB XXXX 11111111 1111 1V 1241 LSB XXXX 0100 1101 1001 1 6118 mV 2 LSB XXXX 0000 0000 0010 805 9 uV 1 LSB XXXX 0000 0000 0001 OV 0 LSB XXXX 0000 0000 0000 Rev 0 Page 12 of 20 CALIBRATION Manual Bias Calibration The bias offset registers in Table 16 and Table 17 provide a manual adjustment function for the output of each sensor For example if GYRO OFF Ox1FF6 DIN 0 9 0x9AF6 the GYRO OUT offset shifts by 10 LSBs or 0 125 sec Table 16 GYRO OFF Bit Descriptions Bits Description Default 0x0000 15 13 Not used 12 0 Data bits Twos complement 0 0125 sec LSB Typical adjustment range 50 sec Table 17 XACCL OFF YACCL OFF ZACCL OFF Bit Descriptions Bits Description Default 0x0000 15 12 Not used 11 0 Data bits Twos complement 0 6 mg LSB Typical adjustment range 1 22 g Frame Alignment The PITCH OFF and ROLL OFF registers see Table 18 provide the angular orientation difference between the inertial frame internal and the external frame package They follow the same orientation as PITCH OUT and ROLL OUT as shown in Figure 14 Table 18 PITCH OFF
4. SMPI2 Bit Descriptions Bits Description 15 8 Not used 7 0 Data bits number of samples both 0x00 and 0x01 1 Table 32 ALM Bit Designations Bits Description 15 12 Alarm 2 trigger source selection Disable Power supply output Gyroscope output Not used Not used X axis accelerometer output Y axis accelerometer output Z axis accelerometer output Temperature output Pitch angle output Roll angle output Auxiliary ADC measurement Alarm 1 trigger source selection see Bits 15 12 Rate of change ROC enable for Alarm 2 1 rate of change 0 static level Rate of change ROC enable for Alarm 1 1 rate of change 0 static level Not used 4 Comparison data filter setting 1 filtered data 0 unfiltered data 3 Not used 2 Alarm output enable 1 enable 0 disable 1 Alarm output polarity 1 high 0 low 0 Alarm output line select 1 0102 0 DIO1 1 Incline outputs pitch roll always use filtered data in this comparison ADIS16305 Table 33 Alarm Configuration Example 1 DIN Description OxAF55 ALM_CTRL 0x5517 OxAE17 Alarm 1 input XACCL_OUT Alarm 2 input XACCL_OUT Static level comparison filtered data DIO2 output indicator positive polarity 0xA783 ALM MAG1 0x8341 OxA641 Alarm 1 is true if XACCL_OUT gt 0 5 OxA93C ALM_MAG2 Ox3CBF OxA8BF Alarm 2 is true if XACCL_OUT lt 0 5 Table 34 Alarm Configuration Example 2 DIN Description OxAF76
5. m sec Vhr mg C mg rms mg rms ug VHz rms ug VHz rms Hz kHz LSB LSB Bits ADIS16305 Parameter DAC OUTPUT Resolution Relative Accuracy Differential Nonlinearity Offset Error Gain Error Output Range Output Impedance Output Settling Time LOGIC INPUTS Input High Voltage Input Low Voltage Vint CS Wake Up Pulse Width Logic 1 Input Current Logic 0 Input Current lint All Pins Except RST RST Pin Input Capacitance Cin DIGITAL OUTPUTS Output High Voltage Vou Output Low Voltage Vo FLASH MEMORY Data Retention FUNCTIONAL TIMES4 Power On Start Up Time Reset Recovery Time Sleep Mode Recovery Time Flash Memory Test Time Automatic Self Test Time CONVERSION RATE Clock Accuracy Sync Input Clock POWER SUPPLY Power Supply Current Min Typ Unit 5 kO 100 pF to GND For Code 101 to Code 4095 CS signal to wake up from sleep mode 3 3 V V 0V lsourc 1 6 mA Isink 1 6 mA Endurance 10 000 Cycles T 285 C 20 Years Time until data is available Normal mode SMPL PRD x 0x09 Low power mode SMPL PRD gt 0x0A Normal mode SMPL PRD x 0x09 Low power mode SMPL PRD gt 0x0A Normal mode SMPL PRD x 0x09 Low power mode SMPL PRD gt Ox0A SMPL PRD 0x01 to OxFF Operating voltage range VCC Low power mode at 25 Normal mode at 25 Sleep mode at 25 digital signals are driven by an internal 3 3 V supply and the inputs are 5 V tol
6. 09020 002 o O 09020 003 Figure 3 Stall Time and Data Rate DATA READY SYNC CLOCK DIO4 09020 004 Figure 4 Input Clock Timing Diagram Rev 0 Page 5 of 20 ADIS16305 ABSOLUTE MAXIMUM RATINGS Table 3 Parameter Rating Acceleration Any Axis Unpowered 2000 g Any Axis Powered 2000 g VCC to GND 0 3 V to 6 0 V Digital Input Voltage to GND 0 3V to 5 3 V Digital Output Voltage to GND 0 3 V to VCC 0 3 V Analog Input to GND 0 3V to 3 6V Operating Temperature Range 40 to 85 65 to 125 C Storage Temperature Range 1 Extended exposure to temperatures outside the specified temperature range of 40 to 85 can adversely affect the accuracy of the factory calibration For best accuracy store the parts within the specified operating range of 40 C to 85 Although the device is capable of withstanding short term exposure to 150 long term exposure threatens internal mechanical integrity Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device This is a stress rating only functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied Exposure to absolute maximum rating conditions for extended periods may affect device reliability Table 4 Package Characteristics Package Type On Device Weight 24 L
7. C dynamic range 75 sec 40 lt TA lt 85 C Reference to z axis accelerometer T4 25 Best fit straight line 25 1 25 1 o SMPL PRD 0 01 Ta 25 1 o SMPL PRD 0 01 40 lt TA lt 85 C Any axis 1 o MSC CTRL Bit 7 1 VCC 4 75 V to 5 25 V Ta 25 300 5 range no filtering Ta 25 C f 25 Hz 300 sec no filtering 300 sec range setting Each axis 25 40 lt TA lt 85 Axis to axis Ta 25 C A 90 ideal Axis to frame package Ta 25 C Best fit straight line 25 10 25 1 o SMPL PRD 0x01 25 C 1 o X axis and Y axis Ta 25 1 o Z axis 40 lt TA lt 85 T4 25 C no filtering X axis and Y axis Ta 25 C no filtering Z axis T4 25 C no filtering X axis and Y axis Ta 25 C no filtering Z axis X axis and Y axis Z axis During acquisition Rev 0 Page 3 of 20 300 350 0 0495 0 05 0 025 0 0125 20 0 1 0 1 3 0 006 1 85 0 006 0 02 0 32 0 73 0 04 330 14 5 696 1400 3 3 6 0 594 0 6 25 0 1 0 5 0 3 60 0 037 0 1 0 16 0 3 4 25 6 5 500 ADIS16305 Min Typ Unit sec sec LSB sec LSB sec LSB ppm C Degrees of FS Vhr sec g sec V sec rms sec VHz rms Hz mg LSB ppm C Degrees Degrees of FS mg mg m sec Ahr
8. Clocks input on SCLK rising edge 6 CS SPI Chip Select 7 9 DIO1 DIO2 Configurable Digital Input Output 8 RST Reset 10 11 12 VCC Power Supply 13 14 15 GND Power Ground 16 17 18 19 22 23 24 DNC Do Not Connect 20 AUX_DAC Auxiliary 12 Bit DAC Output 21 AUX_ADC Auxiliary 12 Bit ADC Input is input output is input is output S is supply and N A is not applicable Rev 0 Page 7 of 20 ADIS16305 TYPICAL PERFORMANCE CHARACTERISTICS 9 o S9 Z 9 4 5 lt LIII gt gt z z 4 4 4 0 01 E cc t Tau a 09020 007 Figure 7 Gyroscope Allan Variance Rev 0 Page 8 of 20 0 01 0 001 0 0001 Tau E Figure 8 Accelerometer Allan Variance 09020 008 THEORY OF OPERATION BASIC OPERATION The ADIS16305 is an autonomous sensor system that starts up after it has a valid power supply voltage and begins producing inertial measurement data After each sample cycle the sensor data is loaded into the output registers and DIOI pulses high which provides a new data ready control signal for driving system level interrupt service routines In a typical system a master processor accesses the output data registers through the SPI interface using the connection diagram shown in Figure 9 Table 6 provides a generic functional description for each pin on the master processor Table 7 describes the typical master processo
9. ROLL OFF Bit Descriptions Bits 15 10 9 0 Description Not used Data bits Twos complement 0 014 LSB Gyroscope Automatic Bias Null Calibration Set GLOB CMDJ 0 1 DIN 0xBE01 to execute the automatic bias null calibration function This function measures the gyroscope output register and then loads the gyroscope offset register with the opposite value to provide a quick bias calibration All sensor data is then reset to 0 and the flash memory is updated automatically within 50 ms see Table 19 Gyroscope Precision Automatic Bias Null Calibration Set GLOB CMDf 4 1 DIN 0 10 to execute the precision automatic bias null calibration function This function takes the sensor offline for 30 sec while it collects a set of data and calculates more accurate bias correction factors for each gyroscope After this function is executed the newly calculated correction factor is loaded into the gyroscope offset registers all sensor data is reset to 0 and the flash memory is updated automatically within 50 ms see Table 19 Restoring Factory Calibration Set GLOB_CMD 1 1 DIN OxBE02 to execute the factory calibration restore function This function resets each user calibration register to 0x0000 see Table 16 and Table 17 resets all sensor data to 0 and automatically updates the flash memory within 50 ms see Table 19 ADIS16305 Linear Acceleration Bias Compensation Gyroscope Set MSC CTRL 7 1 DI
10. additional information for digital filter umm NSOR D D 404Hz 757Hz ACCELERATION SENSOR D 330Hz Fu a 2m SENS AVG 2 0 Figure 16 MEMS Analog and Digital Filters 09020 016 Digital Filtering The N blocks in Figure 16 are part of the programmable low pass filter which provides additional noise reduction on the inertial sensor outputs This filter contains two cascaded averaging filters that provide a Bartlett window FIR filter response see Figure 17 For example set SENS AVG 2 0 100 DIN OxB804 to set each stage to 16 taps When used with the default sample rate of 819 2 SPS this value reduces the sensor bandwidth to approximately 16 Hz 5 gt MAGNITUDE dB 09020 017 FREQUENCY mus Figure 17 Bartlett Window FIR Filter Frequency Response Phase Delay N Samples Dynamic Range The SENS AVG 10 8 bits provide three dynamic range settings for this gyroscope The lower dynamic range settings 75 and 150 sec limit the minimum filter tap sizes to maintain resolution For example set SENS AVG 10 8 010 DIN 0xB902 for a measurement range of 150 sec Because this setting can influence the filter settings program SENS AVG 10 8 and then SENS AVG 2 0 if more filtering is required Table 22 SENS AVG Bit Descriptions Bit s Description 15 11 Not used 10 8 Measurement range sensitivity selection 100 300 sec default condition 010
11. numerical examples of this format Table 13 Power Supply Offset Binary Format Supply Voltage Binary 5 25V 2171 LSB XXXX 1000 0111 1011 5 002418 V 2069 LSB XXXX 1000 0001 0101 5V 2068 LSB XXXX 1000 0001 0100 4 997582 V 2067 LSB XXXX 1000 0001 0011 4 75V 1964 LSB XXXX 0111 1010 1100 Internal Temperature The TEMP_OUT register provides an internal measurement for temperature and uses 12 bit twos complement for its digital format Table 14 provides several numerical examples of this format This is an internal temperature measurement which can vary from ambient conditions outside of the package Table 14 Temperature Twos Complement Format Temperature 105 588 LSB 0010 0100 1100 85 441 LSB XXXX 0001 1011 1001 25 272 2 LSB XXXX 0000 0000 0010 25 136 1 LSB XXXX 0000 0000 0001 25 0 LSB XXXX 0000 0000 0000 24 864 C 1 LSB XXXX 1111 1111 1111 24 728 2 LSB XXXX 1111 1111 1110 40 478 LSB XXXX 1110 0010 0010 Analog Input ADC The AUX_ADC register provides access to the auxiliary ADC input channel measurements and uses 12 bit offset binary as its digital format The ADC is a 12 bit successive approximation converter that has an input circuit equivalent to the one shown in Figure 15 The maximum input is 3 3 V The ESD protection diodes can handle 10 mA without causing irreversible damage The on resistance R1 of the switch has a typical value of 100
12. 150 sec filter taps gt 4 Bits 2 0 gt 0x02 001 75 5 filter taps gt 16 Bits 2 0 gt 0x04 7 3 Not used 2 0 Number of taps in each stage 2M maximum setting 6 110 2 64 taps stage Rev 0 Page 14 of 20 INPUT OUTPUT FUNCTIONS General Purpose I O DIO1 DIO2 DIO3 and DIO4 are configurable general purpose I O lines that serve multiple purposes according to the following control register priority MSC_CTRL ALM_CTRL and GPIO_CTRL For example set GPIO_CTRL 0x080C DIN 0xB20C and then 0xB308 to configure DIO1 and DIO2 as inputs and DIO3 and DIO4 as outputs with DIO3 set low and DIO4 set high In this configuration read GPIO_CTRL DIN 0x3200 to monitor the digital state of DIO1 and DIO2 Table 23 GPIO CTRL Bit Descriptions Description Not used General Purpose I O Line 4 General Purpose Line 3 General Purpose I O Line 2 General Purpose I O Line 1 Not used General Purpose I O Line 4 DIO4 direction control 1 output 0 input General Purpose I O Line 3 DIO3 direction control 1 output 0 input General Purpose I O Line 2 DIO2 direction control 1 output 0 input General Purpose I O Line 1 DIO1 direction control 1 output 0 input data level data level data level data level 0104 0103 0102 0101 SN DN Input Clock Configuration The input clock function allows for external control over sampling in the ADIS16305 Set SMPL
13. 17 ZACCL OFF 0x24 0x0000 Z axis acceleration bias offset factor See Table 17 ALM MAG1 0x26 0x0000 Alarm 1 amplitude threshold See Table 30 ALM MAG2 0x28 0x0000 Alarm 2 amplitude threshold See Table 30 ALM SMPL1 Ox2A 0x0000 Alarm 1 sample size See Table 31 ALM SMPL2 Ox2C 0x0000 Alarm 2 sample size See Table 31 ALM CTRL Ox2E 0x0000 Alarm control See Table 32 AUX DAC 0x30 0x0000 Auxiliary DAC data See Table 25 CTRL 0x32 0x0000 Auxiliary digital input output control See Table 23 MSC CTRL 0x34 0x0006 Miscellaneous control data ready self test See Table 24 SMPL PRD 0x36 0x0001 Internal sample period rate control See Table 20 SENS AVG 0x38 0x0402 Dynamic range and digital filter control See Table 22 SLP_CNT Ox3A 0x0000 Sleep mode control See Table 21 DIAG STAT Ox3C 0x0000 System status See Table 29 GLOB CMD Ox3E 0x0000 System command See Table 19 Reserved 0x40 to 0x51 N A Reserved N A LOT ID1 0x52 N A Lot Identification Code 1 See Table 35 LOT ID2 0x54 N A Lot Identification Code 2 See Table 35 PROD ID 0x56 Ox3FB1 Product identification See Table 35 SERIAL NUM 0x58 N A Serial number See Table 35 Each register contains two bytes The address of the lower byte is displayed The address of the upper byte is equal to the address of the lower byte plus 1 N A stands for not applicable Rev 0 Page 10 of 20 BURST READ DATA COLLECTION Burst read data collection is a process efficient method for collecting data from the ADIS1630
14. 5 In burst read all output registers are clocked out on DOUT 16 bits at a time in sequential data cycles each separated by one SCLK period To start a burst read sequence set DIN 0x3E00 The contents of each output register are then shifted out on DOUT starting with SUPPLY OUT and ending with AUX_ADC see Figure 13 The addressing sequence shown in Table 8 determines the order of the outputs in burst read OUTPUT DATA REGISTERS Each output data register uses the format in Figure 12 and Table 9 Figure 6 shows the positive direction for each inertial sensor The ND bit is equal to 1 when the register contains unread data The EA bit is high when any error alarm flag in the DIAG STAT register is equal to 1 MSB FOR 14 BIT OUTPUT 09020 012 MSB FOR 12 BIT OUTPUT Figure 12 Output Register Bit Assignments Table 9 Output Data Register Formats Name Address Scale Reference SUPPLY OUT Power supply Table 13 GYRO OUT Gyroscope Table 10 XACCL OUT Acceleration x Table 11 YACCL OUT Acceleration y Table 11 ZACCL OUT Acceleration z Table 11 TEMP OUT Temperature Table 14 PITCH OUT Pitch angle Table 12 ROLL OUT Roll angle Table 12 AUX ADC ADC measurement Table 15 1 Assumes that the scaling is set to 300 sec This factor scales with the range 2 0x0000 25 C 5 Note that the codes in Table 10 Table 11 Table 12 Table 13 Table 14 and Table 15 assume typical sensitivity values SCLK ADIS1
15. 6305 Gyroscopes The gyroscope output register GYRO_OUT uses a 14 bit twos complement digital format When using the factory default range of 300 sec each LSB translates into 0 05 sec Table 10 offers some examples for translating the digital data into rotation rate measurements When the dynamic rage is set to 150 sec divide the rotation rate numbers in Table 10 by a factor of two When the dynamic rage is set to 75 sec divide the rotation rate numbers in Table 10 by a factor of four Table 10 Rotation Rate Twos Complement Format Rotation Rate Decimal Binary 300 sec 6000 LSB 0 1770 XX01 0111 0111 0000 0 1 sec 2 LSB 0x0002 XX00 0000 0000 0010 0 05 sec 1 LSB 0x0001 XX00 0000 0000 0001 0 5 0 LSB 0x0000 XX00 0000 0000 0000 0 05 sec 1 LSB Ox3FFF XX11 1111 1111 1111 0 1 sec 2 LSB Ox3FFE XX11 111111111110 300 sec 6000 LSB 0 2890 XX10 1000 1001 0000 Accelerometers The accelerometer output registers XACCL_OUT YACCL_OUT and ZACCL_OUT use a 14 bit twos complement digital format Table 11 offers some examples for translating the digital data into linear acceleration measurements Table 11 Acceleration Twos Complement Format 5500 LSB 0x157C XX01 0101 0111 1100 2 LSB 0 0002 XX00 0000 0000 0010 1 LSB 0 0001 XX00 0000 0000 0001 0 LSB 0 0000 XX00 0000 0000 0000 1 LSB Ox3FFF XX11 111111111111 2 LSB Ox3FFE XX11111111111110 5500L
16. ANALOG FEATURES Digital gyroscope with range scaling 75 sec 150 sec 300 sec settings Triaxis digital accelerometer 3 g Wide sensor bandwidth 330 Hz Autonomous operation and data collection No external configuration commands required Start up time 180 ms Sleep mode recovery time 4 ms Factory calibrated sensitivity bias and alignment Calibration temperature range 40 C to 85 C SPI compatible serial interface Embedded temperature sensor Programmable operation and control Automatic and manual bias correction controls Bartlett window FIR filter length number of taps Digital 1 0 data ready alarm indicator general purpose Alarms for condition monitoring Sleep mode for power management DAC output voltage Enable external sample clock input up to 1 2 kHz Single command self test Single supply operation 4 75 V to 5 25 V 2000 g shock survivability Operating temperature range 40 C to 85 C APPLICATIONS Medical instrumentation Robotics Platform controls Navigation GENERAL DESCRIPTION The iSensor ADIS16305 is a complete inertial system that includes a gyroscope and triaxis accelerometer Each sensor in the ADIS16305 combines industry leading iIMEMS technology with signal conditioning that optimizes dynamic performance The factory calibration characterizes each sensor for sensitivity bias alignment and linear acceleration gyro bias As a result each sensor has its own dynamic compensation formu
17. N 0xB486 to enable correction for low frequency acceleration influences on gyroscope bias Note that the DIN sequence also preserves the factory default condition for the data ready function see Table 24 OPERATIONAL CONTROL Global Commands The GLOB CMD register provides trigger bits for several useful functions Setting the assigned bit to 1 starts each operation which returns the bit to 0 after completion For example set GLOB CMD 7 1 DIN OxBE80 to execute a software reset which stops the sensor operation and runs the device through its start up sequence This sequence includes loading the control registers with their respective flash memory locations prior to producing new data Reading the GLOB_CMD register DIN 0x3E00 starts the burst read sequence Table 19 Bit Descriptions Description Not used Software reset command Not used Precision autonull command Flash update command Auxiliary DAC data latch Factory calibration restore command Autonull command Internal Sample Rate The SMPL PRD register provides discrete sample rate settings using the bit assignments in Table 20 and the following equation fs fg x Ns 1 For example when SMPL PRD 7 0 0x0A the sample rate is 149 SPS Table 20 SMPL PRD Bit Descriptions Bit s Description Default 0x0001 15 8 Not used 7 Time base ts 0 61035 ms 1 18 921 ms 6 0 Increment setting Ns Internal sample period t
18. S16305 uses a pinout that is compatible with the ADIS1635x ADIS1636x and ADIS1640x families when used with an interface flex connector This compact module is approximately 23 mm x 31 mm x 8 mm and provides a standard connector interface which enables horizontal or vertical mounting One Technology Way P O Box 9106 Norwood MA 02062 9106 U S A Tel 781 329 4700 www analog com Fax 781 461 3113 2010 Analog Devices Inc All rights reserved ADIS16305 TABLE OF CONTENTS 1 eat imu IM MM M 10 1 Borst Read Data Collectio uin aceite tries 11 Functional Block ERRORES 1 Output Data 11 General not modd 1 Orientation d ped edid 12 REVISION FISIO P 2 RP 13 ota edu NM MEM 3 Obperatiofial CofftFol so p REDI ERN NIE 13 Timing SPECIE CATIONS oeste e RUSSE 5 lapur Output PUNCHONS oce ase dope m dan tests I5 Absolute Maximum Ratings esent 6 Diao hos UCS 16 6 Product IdentifiCatlODi erp retro ord i bes 17 Pin Configuration and Function Descriptions 7 Applications Information eese ttes 18 Typical Performance Characteristics esses 8 Interface Printed Circuit Board
19. SB 0x2A84 XX10 1010 1000 0100 e DOUT PREVIOUS SUPPLY OUT GYRO OUT XACCL OUT YACCL OUT ROLL OUT AUX ADC 09020 013 Figure 13 Burst Read Sequence Rev 0 Page 11 of 20 ADIS16305 ORIENTATION ANGLES The ROLL_OUT and PITCH_OUT registers provide a tilt angle calculation based on the accelerometer measurements The zero reference is the point at which the z axis faces gravity for a north east down NED configuration Table 12 displays a number of examples for the 13 bit twos complement digital format in both of these registers Figure 14 provides the physical references and formulas that produce these orientation angles Table 12 Orientation Angles Twos Complement Format Angle Binary 180 OxOFFB 1111 1111 1011 90 0x07FD XXX0 0111 1111 1101 0 088 0 0002 XXX0 0000 0000 0010 0 044 0 0001 XXXO 0000 0000 0001 0 0x0000 XXX0 0000 0000 0000 0 044 Ox1FFF XXX1 11111111 1111 0 088 Ox1FFE XXX1 111111111110 90 0x1803 XXX1 1000 0000 0011 179 96 0x1006 XXX1 0000 0000 0110 Z AXIS Y AXIS Z AXIS PITCH SIDE VIEW X AXIS PITCH OUT aTAN amp A AAe A PPITCH x SIN Pro i az COS em 09020 014 Figure 14 Orientation for PITCH OUT and ROLL OUT Angles Power Supply The SUPPLY OUT register provides an internal measurement for the power supply voltage and uses a 12 bit offset binary digital format Table 13 provides several
20. _PRD 7 0 0x00 DIN 0xB600 to enable this function See Table 2 and Figure 4 for timing information Data Ready 1 0 Indicator The factory default sets DIO1 as a positive data ready indicator signal The MSC_CTRL 2 0 bits provide configuration options for changing the default For example set MSC_CTRL 2 0 100 DIN 0xB404 to change the polarity of the data ready signal on DIOI for interrupt inputs that require negative logic inputs for activation The pulse width is between 100 us and 200 us over all conditions ADIS16305 Table 24 MSC_CTRL Bit Descriptions Bit s Description 15 12 Not used 11 Memory test cleared upon completion 1 enabled 0 disabled 10 Internal self test enable cleared upon completion 1 enabled 0 disabled 9 Manual self test negative stimulus 1 enabled 0 disabled 8 Manual self test positive stimulus 1 enabled 0 disabled 7 Linear acceleration bias compensation for gyroscopes 1 enabled 0 disabled 6 Point of percussion alignment accelerometer 1 enabled 0 disabled 5 3 Not used 2 Data ready enable 1 enabled 0 disabled 1 Data ready polarity 1 active high 0 active low 0 Data ready line select 1 DIO2 0 DIO1 Auxiliary DAC The 12 bit AUX DAC line can drive its output to within 5 mV of the ground reference when it is not sinking current As the output approaches 0 V the linearity begins to degrade 100 LSB beginn
21. ash memory E ____ DIN DOUT 015 914 D13 012 btt j j pa j j De j ps p2 p j po NOTES 1 DOUT BITS ARE PRODUCED ONLY WHEN THE PREVIOUS 16 BIT DIN SEQUENCE STARTS WITH R W 0 09020 011 Figure 11 SP Communication Bit Sequence Rev 0 Page 9 of 20 ADIS16305 MEMORY MAP Table 8 User Register Memory Map Name d Backup Address Default Register Description Bit Function FLASH CNT 0x00 N A Flash memory write count See Table 28 SUPPLY OUT 0x02 N A Power supply measurement See Table 9 GYRO OUT 0x04 N A Gyroscope output See Table 9 Reserved 0x06 N A Reserved N A Reserved 0x08 N A Reserved N A XACCL OUT Ox0A N A X axis accelerometer output See Table 9 YACCL OUT OxOC N A Y axis accelerometer output See Table 9 ZACCL OUT OxOE N A Z axis accelerometer output See Table 9 TEMP OUT 0x10 N A Gyroscope temperature measurement See Table 9 PITCH OUT 0x12 N A Pitch angle output x axis See Table 9 ROLL OUT 0x14 N A Roll angle output y axis See Table 9 AUX ADC 0x16 N A Auxiliary ADC output See Table 9 Reserved 0x18 N A Reserved N A GYRO OFF Ox1A 0x0000 Gyroscope bias offset factor See Table 16 PITCH OFF Ox1C N A Pitch angle offset factor See Table 18 ROLL OFF Ox1E N A Roll angle offset factor See Table 18 XACCL OFF 0x20 0x0000 X axis acceleration bias offset factor See Table 17 YACCL OFF 0x22 0x0000 Y axis acceleration bias offset factor See Table
22. ead Module 39 8 C W 14 2 C W 6 1 grams max ESD CAUTION ESD electrostatic discharge sensitive device Charged devices and circuit boards can discharge without detection Although this product features patented or proprietary protection circuitry damage may occur on devices subjected to high energy ESD Therefore proper ESD precautions should be taken to avoid performance degradation or loss of functionality bias Rev 0 Page 6 of 20 ADIS16305 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS ADIS16305 TOP VIEW Not to Scale x 3 co T N 957 Z209008 22288 8 a o Oo Aas 6 AA lt a8 1 3 5 7 9 11 17 19 23 OUUOddO 0 O 000000 OU 2 4 6 8 10 12 18 20 24 2 FF o a 9 gt gt A A a a 3 gt a NOTES 1 MATING CONNECTOR SAMTEC FTSH 112 03 OR EQUIVALENT 2 DO NOT CONNECT 09020 005 Figure 5 ADIS16305 Pin Configuration NOTES 1 THE ARROW DIRECTION ASSOCIATED WITH az ay AND gz INDICATES THE DIRECTION OF MOTION THAT PRODUCES A POSITIVE RESPONSE IN EACH ACCELEROMETER AND GYROSCOPE OUTPUT REGISTER 09020 006 Figure 6 Axial Orientation Table 5 Pin Function Descriptions Pin No Mnemonic Type Description I O 1 DIO3 Configurable Digital Input Output 2 DIO4 CLKIN Configurable Digital Input Output or Sync Clock Input 3 SCLK SPI Serial Clock 4 DOUT SPI Data Output Clocks output on SCLK falling edge 5 DIN SPI Data Input
23. elf test function for investigation of potential failures Table 27 outlines an example test flow for using this option to verify the gyroscope function Table 27 Manual Self Test Example Sequence DIN Description OxB601 SMPL_PRD 7 0 0x01 sample rate 819 2 SPS OxB904 SENS AVG 15 8 0x04 gyro range 300 sec OxB802 SENS AVG 7 0 0x02 four tap averaging filter Delay 50 ms 0x0400 Read GYRO OUT OxB502 MSC CTRL 9 1 gyroscope negative self test Delay 50 ms 0x0400 Read GYRO OUT Determine whether the bias in the gyroscope output changed according to the self test response specified in Table 1 OxB501 MSC CTRL 9 8 01 gyroscope accelerometer positive self test Delay 50 ms 0x0400 Read GYRO OUT Determine whether the bias in the gyroscope output changed according to the self test response specified in Table 1 OxB500 MSC CTRL 15 8 0x00 While the self test still functions when the device is in motion zero motion typically produces the most reliable results The settings in Table 27 are flexible and allow for optimization around speed and noise influence For example using fewer filtering taps decreases delay times but increases the possibility of noise influence Flash Memory Management The FLASH CNT register see Table 28 provides a tool for managing the flash memorys endurance The FLASH register increments every time there is a write to the flash memory Figure 18 quantifies the rela
24. erant Endurance is qualified as per JEDEC Standard 22 Method A117 and measured at 40 25 85 and 125 3 The retention lifetime equivalent is at a junction temperature of 85 C as per Standard 22 Method A117 Retention lifetime decreases with junction temperature These times do not include thermal settling and internal filter response times 330 Hz bandwidth which may impact overall accuracy Rev 0 Page 4 of 20 ADIS16305 TIMING SPECIFICATIONS Ta 25 C VCC 5 V unless otherwise noted Table 2 Normal Mode Low Power Mode SMPL lt 0x09 SMPL_PRD gt 0x0A Burst Read Parameter Description Min Typ Min Typ Max Min Max Unit Serial clock 0 01 MHz tsTALL Stall period between data 1 Us tREADRATE Read rate Us te Chip select to clock edge ns toav DOUT valid after SCLK edge ns tosu DIN setup time before SCLK rising edge ns DIN hold time after SCLK rising edge ns tscixr tscLKr SCLK rise fall times not shown in figures ns tor tor DOUT rise fall times not shown in figures ns tsrs CS high after SCLK edge ns ti Input sync positive pulse width us tx Input sync low time Us t Input sync to data ready output us 3 Input sync period us 1 Guaranteed by design and characterization but not tested in production Timing Diagrams SCLK Figure 2 SPI Timing and Sequence tREADRATE lsrALL
25. f prototype connections of the ADIS16305AMLZ with an existing processor system Jl and J2 are dual row 2 mm pitch connectors that work with a number of ribbon cable systems including 3M Part Number 152212 0100 GB ribbon crimp connector and 3M Part Number 3625 12 ribbon cable Figure 19 provides a hole pattern design for installing the ADIS16305 PCBZ so that the flex fits well in between the ADIS16305AMLZ and the interface PCB Figure 20 provides the pin assignments for each connector and the pin descriptions match those listed in Table 5 The ADIS16305 does not require external capacitors for normal operation therefore the interface PCB does not use the C1 C2 pads not shown in Figure 19 33 77 02 20 x 2 ADIS16305AMLZ SCF 140379 01 09020 019 INTERFACE PCB Figure 19 Physical Diagram for Mounting the ADIS16305 PCBZ RST 1 2 SCLK AUX ADC 3 2 GND cs 4 pour auxpac 3 4 DNC 5 6 DIN GND 5 6 0104 09020 020 9 9 vcc 11 12 po2 11 12 001 Figure 20 J1 J2 Pin Assignments for Interface PCB GYROSCOPE BIAS OPTIMIZATION The factory calibration addresses initial bias errors along with temperature dependent bias behaviors Installation and certain environmental conditions can introduce modest bias errors The precision autonull command provides a simple predeployment method for correcting these errors to an accuracy of approximately 0 008 sec usin
26. g an average of 30 sec Set GLOB_CMD 4 1 DIN BE10 to start this operation Averaging the sensor output data for 100 sec can provide incremental performance gains as well Controlling device rotation power supply and temperature during these averaging times helps to ensure optimal accuracy during this process Refer to the AN 1041 Application Note for more information about optimizing performance Rev 0 Page 18 of 20 ADIS16305 OUTLINE DIMENSIONS 31 25 31 00 30 75 13 60 13 50 4 13 50 13 40 23 25 2 20 THRU HOLE 23 00 2 PLACES 22 75 e m 9 13 8 88 8 63 p OBEN DETAIL A 8 00 MAX 2 95 END VIEW 2 30 DETAIL A 04 06 2010 A Figure 21 24 Lead Module with Connector Interface ML 24 4 Dimensions shown in millimeters ORDERING GUIDE Model Temperature Range Package Description Package Option ADIS16305AMLZ 40 to 85 C 24 Lead Module with Connector Interface ML 24 4 ADIS16305 PCBZ Interface Board 1 Z RoHS Compliant Part Rev 0 Page 19 of 20 ADIS16305 NOTES 2010 Analog Devices Inc All rights reserved Trademarks and registered trademarks are the property of their respective owners 009020 0 7 10 0 mE Rev 0 Page 20 of 20
27. ing point As the sink current increases the nonlinear range increases The DAC latch command moves the values of the DAC register into the DAC input register enabling both bytes to take effect at the same time Table 25 AUX DAC Bit Descriptions Bits 15 12 11 0 Description Not used Data bits scale factor 0 8059 mV LSB Offset binary format 0 V 0 LSB Table 26 Setting AUX_DAC 1V DIN Description OxBOD9 AUX DAC 7 0 0 09 217 LSB OxB104 AUX DAC 15 8 0x04 1024 LSB OxBEO4 GLOB CMD 2 1 Move values into the DAC input register resulting in a 1 V output level Rev 0 Page 15 of 20 ADIS16305 DIAGNOSTICS Self Test The self test function allows the user to verify the mechanical integrity of each MEMS sensor It applies an electrostatic force to each sensor element which results in mechanical displacement that simulates a response to actual motion Table 1 lists the expected response for each sensor which provides pass fail criteria Set MSC_CTRL 10 1 DIN 0xB504 to run the internal self test routine which exercises all inertial sensors measures each response makes pass fail decisions and reports them to error flags in the DIAG_STAT register This process takes 35 ms to complete and report the results to DIAG STAT 5 DIAG_STAT 10 and DIAG_STAT 15 13 MSC_CTRL 10 resets itself to 0 after completing the routine The MSC_CTRL 9 8 bits provide manual control over the s
28. las that provide accurate sensor measurements over a variety of conditions The ADIS16305 provides a simple cost effective method for integrating accurate multiaxis inertial sensing into industrial systems especially when compared with the complexity and investment associated with discrete designs All necessary motion Rev 0 Information furnished by Analog Devices is believed to be accurate and reliable However no responsibility is assumed by Analog Devices for its use nor for any infringements of patents or other rights of third parties that may result from its use Specifications subject to change without notice No license is granted by implication or otherwise under any patent or patent rights of Analog Devices Trademarks and registered trademarks are the property of their respective owners gt DEVICES Precision Four Degrees of Freedom Sensor ADIS16305 FUNCTIONAL BLOCK DIAGRAM AUX _ _ ADC DAC CALIBRATION AND DIGITAL PROCESSING TRIAXIS MEMS ACCELERATION SENSOR SELF TEST ADIS16305 DIGITAL CONTROL eve in O O _ OOO RST DIO1 DIO2 DIO3 DIO4 09020 001 Figure 1 testing and calibration are part of the production process at the factory greatly reducing system integration time Tight orthogonal alignment simplifies inertial frame alignment in navigation systems An improved SPI interface and register structure provide faster data collection and configuration control The ADI
29. r settings for communicating with the ADIS16305 LINES ARE COMPATIBLE WITH 3 3V OR 5V LOGIC LEVELS SYSTEM PROCESSOR SPI MASTER ADIS16305 SPI SLAVE 09020 009 Figure 9 Electrical Connection Diagram Table 6 Generic Master Processor Pin Names and Functions Pin Name Function SS Slave select IRQ Interrupt request MOSI Master output slave input MISO Master input slave output SCLK Serial clock Table 7 Generic Master Processor SPI Settings Processor Setting Description Master ADIS16305 is a slave SCLK Rate lt 2 MHz Normal mode SMPL PRD 7 0 x 0x09 SPI Mode 3 CPOL 1 polarity 1 phase MSB First Mode Bit sequence 16 Bit Mode Shift register data length 1 For burst read SCLK rate lt 1 MHz For low power mode SCLK rate lt 300 kHz ADIS16305 The user registers provide addressing for all input output operations on the SPI interface Each 16 bit register has two 7 bit addresses one for its upper byte and one for its lower byte Table 8 lists the lower byte address for each register and Figure 10 shows the generic bit assignments UPPER BYTE LOWER BYTE 4 Figure 10 Generic Register Bit Assignments READING SENSOR DATA Although the ADIS16305 produces data independently it operates as an SPI slave device that communicates with system master processors using the 16 bit segments displa
30. s te x Ns 1 The default sample rate setting of 819 2 SPS provides optimal performance For systems that value slower sample rates keep the internal sample rate at 819 2 SPS Use the programmable filter SENS AVG to reduce the bandwidth which helps to prevent aliasing The data ready function MSC CTRL can drive an interrupt routine that uses a counter to help ensure data coherence at reduced rates Rev 0 Page 13 of 20 ADIS16305 Power Management Setting SMPL_PRD 0x0A also sets the sensor to low power mode For systems that require lower power dissipation in system characterization helps users to quantify the associated performance trade offs In addition to sensor performance this mode affects SPI data rates see Table 2 Set SLP_CNT 8 DIN 0 1 to start the indefinite sleep mode which requires a CS assertion high to low reset or power cycle to wake up Use SLP CNT 7 0 to put the device into sleep mode for a specified period For example SLP CNT 7 0 0x64 DIN 0xBA64 puts the ADIS16305 to sleep for 50 sec Table 21 SLP CNT Bit Descriptions Bit s Description 15 9 Not used 8 Indefinite sleep mode set to 1 7 0 Programmable sleep time bits 0 5 sec LSB Sensor Bandwidth The signal chain for each MEMS sensor has several filter stages which shape their frequency response Figure 16 provides a block diagram for both gyroscope and accelerometer signal paths Table 22 provides
31. ss 4 Sensor overrange 1 fail 0 pass 3 SPI communication failure 1 fail 0 pass 2 Flash update failure 1 fail O 2 pass 1 Power supply 5 25 V 1 2 power supply 5 25 V 0 power supply x 5 25 V 0 Power supply 4 75 V 1 2 power supply 4 75 V 0 power supply gt 4 75 V 1 The SPI error flag in DIAG STAT 3 goes to 1 when the number of SCLKs is not equal to an integer multiple of 16 Rev 0 Page 16 of 20 Alarm Registers The alarm function provides monitoring for two independent conditions The ALM CTRL register provides control inputs for trigger source data filtering prior to comparison static comparison dynamic rate of change comparison and output indicator configurations The ALM MAGx registers establish the trigger threshold and polarity configurations Table 33 gives an example of how to configure a static alarm The ALM SMPLx registers provide the number of samples to use in the dynamic rate of change configuration The period equals the number in the ALM SMPLx register multiplied by the sample period time which is established by the SMPL PRD register See Table 34 for an example of how to configure the sensor for this type of function Table 30 ALM _ 2 Bit Descriptions Bit s 15 14 13 0 Description Comparison polarity 1 greater than 0 less than Not used Data matches the format of the trigger source Table 31 ALM_SMPL1
32. tionship between data retention and junction temperature Table 28 FLASH Bit Descriptions Bits Description 15 0 Binary counter for writing to flash memory RETENTION Years 30 70 85 100 125 135 150 UNE TEMPERATURE 09020 018 Figure 18 Flash EE Memory Data Retention Checksum Test Set MSC CTRL 11 1 DIN 0x9D08 to verify the flash memory integrity against the factory check sum and read DIAG STAT 6 to check the results 20 ms after the command Status The error flags provide indicator functions for common system level issues All of the flags are cleared set to 0 after each STAT register read cycle If an error condition remains the error flag returns to 1 during the next sample cycle The DIAG_STATT 1 0 bits do not require a read of this register to return to 0 If the power supply voltage goes back into range these two flags are cleared automatically Table 29 DIAG STAT Bit Descriptions Bit s Description 15 Z axis accelerometer self test failure 1 fail O pass 14 Y axis accelerometer self test failure 1 fail O 2 pass 13 X axis accelerometer self test failure 1 fail O 2 pass 12 11 Not used 10 Gyroscope self test failure 1 fail O pass 9 Alarm 2 status 1 active 0 inactive 8 Alarm 1 status 1 active 0 inactive 7 Not used 6 Flash test checksum flag 1 fail O pass 5 Self test diagnostic error flag 1 0 pa
33. yed in Figure 11 Individual register reads require two of these 16 bit sequences The 010 09020 first 16 bit sequence provides the read command bit R W 0 and the target register address A6 to A0 The second sequence transmits the register contents D15 to D0 on the DOUT line For example if DIN 0x0A00 the contents of XACCL are shifted out on the DOUT line during the next 16 bit sequence The SPI operates in full duplex mode which means that the master processor can read the output data from DOUT while using the same SCLK pulses to transmit the next target address on DIN DEVICE CONFIGURATION The user register memory map see Table 8 identifies configuration registers with either a W or R W Configuration commands also use the bit sequence shown in Figure 11 If the MSB 1 the last eight bits DC7 to DCO in the DIN sequence are loaded into the memory address associated with the address bits to A0 For example if DIN OxA11E OxIF is loaded into Address 0x21 XACCL OFF upper byte at the conclusion of the data frame The master processor initiates the backup function by setting CMD 3 1 DIN OxBE04 This command copies the user registers into their assigned flash memory locations and requires the power supply to stay within its normal operating range for the entire 50 ms process The FLASH CNT register provides a running count of these events for monitoring the long term reliability of the fl

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