Home

CATALYST SEMICONDUCTOR CAT24WC256 256K-Bit I 2 C Serial CMOS EEPROM Manual

1. SCL STATE COUNTERS Ao SLAVE A1 ADDRESS COMPARATORS Catalyst Semiconductor is licensed by Philips Corporation to carry the I2C Bus Protocol 2004 by Catalyst Semiconductor Inc Characteristics subject to change without notice 1 Doc No 1031 Rev F CAT24WC256 ABSOLUTE MAXIMUM RATINGS Temperature Under Bias 55 C to 125 C Storage Temperature 65 C to 150 C Voltage on Any Pin with Respect to Ground 2 0V to Vcc 2 0V Vcc with Respect to Ground 2 0V to 7 0V Package Power Dissipation Capability Ta 25 00 sssssssneeeseneeneseneneneee 1 0W Lead Soldering Temperature 10 secs 300 C Output Short Circuit Current RELIABILITY CHARACTERISTICS COMMENT Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device These are stress ratings only and functional operation of the device at these or any other conditions outside of those listed in the operational sections of this specification is not implied Exposure to any absolute maximum rating for extended periods may affect device performance and reliability Symbol Parameter Reference Test Method Min Typ Max Units NENo Endurance MIL STD 883 Test Method 1033 100 000 Cycles Byte Tor Data Retention MIL STD
2. 883 Test Method 1008 100 Years Vzapl ESD Susceptibility MIL STD 883 Test Method 3015 2000 Volts ILtH 9 4 Latch up JEDEC Standard 17 100 mA D C OPERATING CHARACTERISTICS Vcc 1 8V to 6 0V unless otherwise specified Symbol Parameter Test Conditions Min Typ Max Units lcci Power Supply Current Read fscL 100 KHz 1 mA Voc 5V lcc2 Power Supply Current Write fscL 100KHz 3 mA Voc 5V Isp 5 Standby Current Vin GND or Voc 1 uA Voc 5V IL Input Leakage Current Vin GND to Vcc 1 uA ILO Output Leakage Current Vour GND to Vcc 1 uA VIL Input Low Voltage 1 Vcc x 0 3 V VIH Input High Voltage Vcc x 0 7 Vcc 0 5 V VoL1 Output Low Voltage Vcc 3 0V loL 3 0 mA 0 4 V VoL2 Output Low Voltage Vcc 1 8V lol 1 5 mA 0 5 V CAPACITANCE Ta 25 C f 1 0 MHz Vcc 5V Symbol Test Conditions Min Typ Max Units Cro Input Output Capacitance SDA Vio OV 8 pF Cin Input Capacitance SCL WP AO A1 Vin OV 6 pF Note 1 The minimum DC input voltage is 0 5V During transitions inputs may undershoot to 2 0V for periods of less than 20 ns Maximum DC voltage on output pins is Voc 0 5V which may overshoot to Vcc 2 0V for periods of less than 20ns 2 Output shorted for no more than one second No more than one output shorted at a time 3 This parameter is tested initially and after a design or process change that affects the parameter 4 Latch up protection is provided for stresses up to 100 mA on
3. all data into and out of the device The SDA pin is an open drain output and can be wire ORed with other open drain or open collector outputs WP Write Protect This input when tied to GND allows write operations to the entire memory When this pin is tied to Vcc the entire memory is write protected When left floating memory is unprotected A0 A1 Device Address Inputs These pins are hardwired or left connected When hardwired up to four CAT24WC256 s may be addressed on a single bus system When the pins are left uncon nected the default values are zero tsu STO t oj BUF sDaour VOV Figure 2 Write Cycle Timing SDA 8THBIT ACK s BYTEn STOP CONDITION Figure 3 Start Stop Timing SDA SCL START BIT Doc No 1031 Rev F START ADDRESS CONDITION STOP BIT PC BUS PROTOCOL The features of the I2C bus protocol are defined as follows 1 Data transfer may be initiated only when the bus is not busy 2 During a data transfer the data line must remain stable whenever the clock line is high Any changes in the data line while the clock line is high will be interpreted as a START or STOP condition START Condition The START Condition precedes all commands to the device and is defined as a HIGH to LOW transition of SDA when SCL is HIGH The CAT24WC256 monitors the SDA and SCL lines and will not respond until this condition is met STOP Condition A LOW to HIGH tra
4. available upon request Notes 1 The device used in the above example is a 24WC256KI 1 8TE13 SOIC Industrial Temperature 1 8 Volt to 6 Volt Operating Voltage Tape amp Reel 2 Product die revision letter is marked on top of the package as a suffix to the production date code e g AYWWB For additional information please contact your Catalyst sales office 9 Doc No 1031 Rev F REVISION HISTORY Date Revision Comments Added CAT24WC256 not recommended for new designs See CAT24FC256 data sheet 04 18 04 D Delete data sheet designation Update Features 02 03 2004 C Update Ordering Information 07 23 04 E Add die revision to Ordering Information 08 05 04 F Update DC Operating Characteristics table and notes Copyrights Trademarks and Patents Trademarks and registered trademarks of Catalyst Semiconductor include each of the following DPP TM AE TM Gatalyst Semiconductor has been issued U S and foreign patents and has patent applications pending that protect its products For a complete list of patents issued to Catalyst Semiconductor contact the Company s corporate office at 408 542 1000 CATALYST SEMICONDUCTOR MAKES NO WARRANTY REPRESENTATION OR GUARANTEE EXPRESS OR IMPLIED REGARDING THE SUITABILITY OF ITS PRODUCTS FOR ANY PARTICULAR PURPOSE NOR THAT THE USE OF ITS PRODUCTS WILL NOT INFRINGE ITS INTELLECTUAL PROPERTY RIGHTS OR THE RIGHTS OF THIRD PARTIES WITH RESPECT TO ANY PARTICU
5. C CATALYST E CAT24WC256 wae 256K Bit I C Serial CMOS EEPROM CAT24WC256 not recommended for new designs See CAT24FC256 data sheet 6 AD Em FEATURES m 1MHz PC bus compatible m Write protect feature m 1 8 to 6 volt operation entire array protected when WP at V m Low power CMOS technology m 100 000 program erase cycles m 64 byte page write buffer m 100 year data retention m Self timed write cycle with auto clear m 8 pin DIP or 8 pin SOIC m Commercial industrial and automotive m Green package options available temperature ranges DESCRIPTION The CAT24WC256is a 256K bit Serial CMOS EEPROM internally organized as 32 768 words of 8 bits each Catalyst s advanced CMOS technology substantially reduces device power requirements The CAT24WC256 PIN CONFIGURATION DIP Package P L Ao 1e1 8 Vcc A1 2 7 Ewe NCC 3 6 SCL Vss CJ 4 5 SDA PIN FUNCTIONS Pin Name Function A0 A1 Address Inputs SDA Serial Data Address SCL Serial Clock WP Write Protect Vcc 1 8V to 6 0V Power Supply Vss Ground NC No Connect features a 64 byte page write buffer The device oper ates via the I C bus serial interface and is available in 8 pin DIP or 8 pin SOIC packages BLOCK DIAGRAM EXTERNAL LOAD SENSE AMPS SHIFT REGISTERS Voc L gt WORD ADDRESS COLUMN v 512 START STOP DA EEPROM XDEC 512 512x512 CONTROL LOGIC HIGH VOLTAGE TIMING CONTROL
6. LAR USE OR APPLICATION AND SPECIFICALLY DISCLAIMS ANY AND ALL LIABILITY ARISING OUT OF ANY SUCH USE OR APPLICATION INCLUDING BUT NOT LIMITED TO CONSEQUENTIAL OR INCIDENTAL DAMAGES Catalyst Semiconductor products are not designed intended or authorized for use as components in systems intended for surgical implant into the body or other applications intended to support or sustain life or for any other application in which the failure of the Catalyst Semiconductor product could create a situation where personal injury or death may occur Catalyst Semiconductor reserves the right to make changes to or discontinue any product or service described herein without notice Products with data sheets labeled Advance Information or Preliminary and other products described herein may not be in production or offered for sale Catalyst Semiconductor advises customers to obtain the current version of the relevant product information before placing orders Circuit diagrams illustrate typical semiconductor applications and may not be complete O CATALYST Catalyst Semiconductor Inc Corporate Headquarters 1250 Borregas Avenue Sunnyvale CA 94089 Publication 1031 Phone 408 542 1000 Revison F Fax 408 542 1200 Issue date 08 05 04 www catalyst semiconductor com
7. OTECTION The Write Protection feature allows the user to protect against inadvertent programming of the memory array If the WP pin is tied to Vcc the entire memory array is protected and becomes read only The CAT24WC256 will accept both slave and byte addresses but the memory location accessed is protected from program ming by the device s failure to send an acknowledge after the first byte of data is received s T S BUS ACTIVITY A SLAVE BYTE ADDRESS T MASTER T ADDRESS A15 A8 A7 A0 DATA saine ILO pm ok A A C C C K K K K Dontt Care Bit Figure 7 Page Write Timing S T S BUS ACTIVITY A SLAVE ADR T MASTER i ADDRESS A15 A8 DATA DATA n DATA n 63 o a S K K _Don t Care Bit Doc No 1031 Rev F K K K K READ OPERATIONS The READ operation for the CAT24WC256is initiated in the same manner as the write operation with one excep tion that R W bit is set to one Three different READ operations are possible Immediate Current Address READ Selective Random READ and Sequential READ Immediate Current Address Read The CAT24WC256 s address counter contains the ad dress of the last byte accessed incremented by one In other words if the last READ or WRITE access was to address N the READ immediately following would ac cess data from address N 1 If N E where E 32767 then the counter will wrap around to address 0 and continue to clock out data After the CAT24WC256 receives its slave address i
8. address and data pins from 1V to Voc 1V 5 Maximum standby current Isg 10uA for the Automotive and Extended Automotive temperature range Doc No 1031 Rev F A C CHARACTERISTICS Vcc 1 8V to 6V unless otherwise specified Output Load is 1 TTL Gate and 100pF Read 8 Write Cycle Limits CAT24WC256 Symbol Parameter Vec 1 8V 6 0V Vcc 2 5V 6 0V Vce 3 0V 5 5V Min Max Min Max Min Max Units FscL Clock Freguency 100 400 1000 kHz taa SCL Low to SDA Data Out 0 1 3 5 0 05 0 9 0 05 0 55 us and ACK Out teur Time the Bus Must be Free Before 4 7 1 2 0 5 us a New Transmission Can Start tHD STA Start Condition Hold Time 4 0 0 6 0 25 us tLow Clock Low Period 4 7 1 2 0 6 us tHIGH Clock High Period 4 0 0 6 0 4 us tsu STA Start Condition Setup Time 4 0 0 6 0 25 us for a Repeated Start Condition thHp par Data In Hold Time 0 0 0 ns tSU DAT Data In Setup Time 100 100 100 ns ta SDA and SCL Rise Time 1 0 0 3 0 3 us tr SDA and SCL Fall Time 300 300 100 ns tsu sTO Stop Condition Setup Time 4 7 0 6 0 25 us toH Data Out Hold Time 100 50 50 ns twR Write Cycle Time 10 10 10 ms Power Up Timing 2 3 Symbol Parameter Min Typ Max Units tPUR Power Up to Read Operation 1 ms tPuw Power Up to Write Operation 1 ms Note 1 AC measurement conditions RL connects to Vcc 0 3Vcc to 0 7 Vc
9. c Input rise and fall times lt 50ns Input and output timing reference voltages 0 5 Vcc 2 This parameter is tested initially and after a design or process change that affects the parameter 3 tpun and tpuw are the delays reguired from the time Vcc is stable until the specified operation can be initiated The write cycle time is the time from a valid stop condition of a write seguence to the end of the internal program erase cycle During the write cycle the bus interface circuits are disabled SDA is allowed to remain high and the device does not respond to its slave address Doc No 1031 Rev F CAT24WC256 FUNCTIONAL DESCRIPTION The CAT24WC256 supports the I2C Bus data transmis sion protocol This Inter Integrated Circuit Bus protocol defines any device that sends data to the bus to be a transmitter and any device receiving data to be a re ceiver The transfer is controlled by the Master device which generates the serial clock and all START and STOP conditions for bus access The CAT24WC256 operates as a Slave device Both the Master device and Slave device can operate as either transmitter or re ceiver but the Master device controls which mode is activated PIN DESCRIPTIONS SCL Serial Clock The serial clock input clocks all data transferred into or out of the device Figure 1 Bus Timing SCL SDA IN IAA SDA Serial Data Address The bidirectional serial data address pin is used to transfer
10. en selected along with a write operation it responds with an acknowledge after receiving each 8 bit byte When the CAT24WC256 begins a READ mode it trans mits 8 bits of data releases the SDA line and monitors the line for an acknowledge Once it receives this ac knowledge the CAT24WC256 will continue to transmit data If no acknowledge is sent by the Master the device R ANN MASTER l t DATA OUTPUT TN FROM TRANSMITTER i DATA OUTPUT FROM RECEIVER START Figure 5 Slave Address Bits E ACKNOWLEDGE EE A a Doc No 1031 Rev F CAT24WC256 terminates data transmission and waits for a STOP condition WRITE OPERATIONS Byte Write In the Byte Write mode the Master device sends the START condition and the slave address information with the R W bit set to zero to the Slave device After the Slave generates an acknowledge the Master sends two 8 bit address words that are to be written into the address pointers of the CAT24WC256 After receiving another acknowledge from the Slave the Master device transmits the data to be written into the addressed memory location The CAT24WC256 acknowledges once more and the Master generates the STOP condi tion At this time the device begins an internal program ming cycle to nonvolatile memory While the cycle is in progress the device will not respond to any request from the Master device Page Write The CAT24WC256 writes up to 64 bytes of data ina single w
11. nformation with the R W bit set to one itissues an acknowledge then transmits the 8 bit byte requested The master device does not send an acknowledge but will generate a STOP condition Selective Random Read Selective Random READ operations allow the Master device to select at random any memory location for a READ operation The Master device first performs a dummy write operation by sending the START condi tion slave address and byte addresses of the location it Figure 8 Immediate Address Read Timing S T BUS ACTIVITY A SLAVE MASTER R ADDRESS CAT24WC256 wishes to read After CAT24WC256 acknowledges the Master device sends the START condition and the slave address again this time with the R W bit set to one The CAT24WC256 then responds with its acknowledge and sends the 8 bit byte requested The master device does not send an acknowledge but will generate a STOP condition Sequential Read The Sequential READ operation can be initiated by either the Immediate Address READ or Selective READ operations After the CAT24WC256 sends the initial 8 bit byte requested the Master will respond with an acknowledge which tells the device it requires more data The CAT24WC256 will continue to output an 8 bit byte for each acknowledge sent by the Master The operation will terminate when the Master fails to respond with an acknowledge thus sending the STOP condition The data being transmitted from CAT24WC256 is out
12. nsition of SDA when SCL is HIGH determines the STOP condition All operations must end with a STOP condition DEVICE ADDRESSING The bus Master begins a transmission by sending a START condition The Master sends the address of the particular slave device it is requesting The five most significant bits of the 8 bit slave address are fixed as 10100 Fig 5 The CAT24WC256 uses the next two bits as address bits The address bits A1 and AO allow as Figure 4 Acknowledge Timing CAT24WC256 many as four devices on the same bus These bits must compare to their hardwired input pins The last bit of the slave address specifies whether a Read or Write opera tion is to be performed When this bit is set to 1 a Read operation is selected and when set to 0 a Write opera tion is selected After the Master sends a START condition and the slave address byte the CAT24WC256 monitors the bus and responds with an acknowledge on the SDA line when its address matches the transmitted slave address The CAT24WC256 then performs a Read or Write operation depending on the state of the RW bit Acknowledge After a successful data transfer each receiving device is required to generate an acknowledge The Acknowledg ing device pulls down the SDA line during the ninth clock cycle signaling that it received the 8 bits of data The CAT24WC256 responds with an acknowledge after receiving a START condition and its slave address Ifthe device has be
13. putted sequentially with data from address N followed by data from address N 1 The READ operation address counter increments all of the CAT24WC256 address bits so that the entire memory array can be read during one operation If more than E where E 32767 bytes are read out the counter will wrap around and continue to clock out data bytes vO DATA son une T XOP SDA X smeT BIT l I I DATA OUT NO ACK STOP Doc No 1031 Rev F CAT24WC256 Figure 9 Selective Read Timing s s T T BUS ACTIVITY A SLAVE BYTE ADDRESS A SLAVE MASTER ADDRESS A15 A A7 R ADDRESS DATA 1 voaa A A A A N C C C C O K K K K A C K Don t Care Bit Figure 10 Sequential Read Timing S BUS ACTIVITY SLAVE T MASTER ADDRESS DATA n DATA n 1 DATA n 2 DATA n x gt s A k n CY m A A A A N C C C C O K K K K A C K Doc No 1031 Rev F CAT24WC256 ORDERING INFORMATION Prefix Device Suffix CAT 24WC256 K Rev B gt Temperature Range Tape 4 Reel Blank Commercial 0 70 C Industrial 40 85 C Die Revision 24WC256 A B Optional Product Company ID Number A Automotive 40 105 C Package Operating Voltage P PDIP Blank 2 5 to 6 0V K SOIC EIAJ 1 8 1 8 to 6 0V J SOIC JEDEC 3 3 0V to 5 5V L PDIP Lead free Halogen free W SOIC JEDEC Lead free Halogen free X SOIC EIAJ Lead free Halogen free 40 to 125 C is
14. rite cycle using the Page Write operation The page write operation is initiated in the same manner as the byte write operation however instead of terminating after the initial byte is transmitted the Master is allowed to send up to 63 additional bytes After each byte has been transmitted CAT24WC256 will respond with an acknowledge and internally increment the six low order address bits by one The high order bits remain un changed Figure 6 Byte Write Timing Ifthe Master transmits more than 64 bytes before sending the STOP condition the address counter wraps around and previously transmitted data will be overwritten When all 64 bytes are received and the STOP condition has been sent by the Master the internal programming cycle begins At this point all received data is written to the CAT24WC256 in a single write cycle Acknowledge Polling Disabling of the inputs can be used to take advantage of the typical write cycle time Once the stop condition is issued to indicate the end of the host s write operation CAT24WC256 initiates the internal write cycle ACK polling can be initiated immediately This involves issu ing the start condition followed by the slave address for a write operation If CAT24WC256 is still busy with the write operation no ACK will be returned If CAT24WC256 has completed the write operation an ACK will be returned and the host can then proceed with the next read or write operation WRITE PR

CATALYST SEMICONDUCTOR CAT24WC256 256K-Bit I 2 C Serial CMOS EEPROM Manual

Contents

Download Pdf Manuals

Related Search

Related Contents