NATIONAL SEMICONDUCTOR ADC0801/ADC0802/ADC0803/ADC0804/ADC0805 handbook
Contents
1. 10 100 1000 CLOCK CAPACITOR pF DS005671 41 Output Current vs Temperature N OUTPUT CURRENT mA H Vout 04 2 50 25 0 25 50 75 100 125 Ta AMBIENT TEMPERATURE C DS005671 44 Delay From Falling Edge of RD to Output Data Valid vs Load Capacitance DELAY ns 500 300 200 LOAD CAPACITANCE pF DS005671 39 Full Scale Error vs Conversion Time LINEARITY ERROR LSBs Tc CONVERSION TIME us DS005671 42 Power Supply Current vs Temperature Note 9 Icc POWER SUPPLY CURRENT mApc 640 kHz 25 50 75 100 125 AMBIENT TEMPERATURE C DS005671 45 CLK IN Schmitt Trip Levels vs Supply Voltage CLK IN THRESHOLD VOLTAGE V 3 5 3 1 2 7 2 3 4 50 4 15 5 00 5 25 5 50 Vec SUPPLY VOLTAGE DS005671 40 Effect of Unadjusted Offset Error vs 2 Voltage OFFSET ERROR LSBs Vin OV ASSUMES Vog 2 mV THIS SHOWS THE NEED FOR A ZERO ADJ IF THE SPAN IS REDUCED VrEF 2 DS005671 43 Linearity Error at Low Vrer 2 Voltages LINEARITY ERROR LSBs _ 2 2 256 ZERO AND FULL SCALE ADJUSTED LSB VALUE2. 2 Connection LSB Vrer 2 Input Resistance Pin 9 ADC0801 02 03 05 ADC0804 Note 9 kQ Analog Input Voltage Range Note 4 V or V Gnd 0 05 Voc DC Common Mode Error Over Analog Input Voltage LSB Range Power Supply Sensitivity Voc 25 Voc 10 Over t1 16 ti LSB Allowed Vin and Vin Voltage Range Note 4 AC Electrical Characteristics The following specifications apply for 5 and Tmn lt Ta lt Tmax unless otherwise specified Symbol Parameter Conditions Typ Max Units Te Conversion Time fc 640 kHz Note 6 114 us Tc Conversion Time Notes 5 6 73 Tex Clock Frequency Voc 25V Note 5 640 1460 kHz Clock Duty Cycle 40 60 96 CR Conversion Rate in Free Running INTR tied to WR with 8770 9708 conv s Mode CS 0 Voc fci 640 kHz ae twwrye Width of WR Input Start Pulse Width CS 0 Note 7 100 ns tacc Access Time Delay from Falling C 2100 pF 135 200 ns Edge of RD to Output Data Valid tin ton TRI STATE Control Delay C 210 pF R 10k 125 200 ns from Rising Edge of RD to See TRI STATE Test Hi Z State Circuits tw tni Delay from Falling Edge 300 450 ns Cin Input Capacitance of Logic 5 75 pF Control Inputs www national com S08090V 7r08090V E08000V Z08000V LO8000V AC Electrical Characteristics continued The following specifications apply for 5 and lt lt unless otherwise specified Symbol Parameter Conditions Min Typ Max Units Cour
3. Nim Semiconductor ADC0801 ADC0802 ADC0803 ADC0804 ADC0805 8 Bit uP Compatible A D Converters General Description The ADCO0801 ADCO802 ADCO803 ADCO0804 and ADCO0805 are CMOS 8 bit successive approximation A D converters that use differential potentiometric ladder similar to the 256R products These converters are designed to allow operation with the NSC800 and INS8080A derivative control bus with TRI STATE output latches directly driving the data bus These A Ds appear like memory loca tions or I O ports to the microprocessor and no interfacing logic is needed Differential analog voltage inputs allow increasing the common mode rejection and offsetting the analog zero input voltage value In addition the voltage reference input can be adjusted to allow encoding any smaller analog voltage span to the full 8 bits of resolution Features m Compatible with 8080 uP derivatives no interfacing logic needed access time 135 ns m Easy interface to all microprocessors or operates stand alone Connection Diagram ADCO80X Dual In Line and Small Outline SO Packages 1 2 3 4 5 6 7 8 9 See Ordering Information Ordering Information TEMP RANGE 0 C TO 70 C Key Specifications m Resolution 8 bits m Total error 14 LSB 14 LSB and 1 LSB m Conversion time 100 us November 1999 m Differential analog voltage inputs Logic inputs and outputs meet both MOS and TTL voltage level specifi
4. swa DS005671 91 Note 28 The 9 resistors used in the auto zero section can be 5 tolerance FIGURE 18 Gain of 100 Differential Transducer Preamp www national com 34 Functional Description Continued INVERTING ADDRESS BUFFERS 8080A ADDRESS BUS PORTA BUFFERS 158202 8080A DATA BUS DM8131 OUTPUT Vour f OUTPUTS v DUTU preamp VREF 2 8080A CONTROL SIGNALS DS005671 92 FIGURE 19 Microprocessor Interface Circuitry for Differential Preamp A flow chart for the zeroing subroutine is shown in Figure 20 It must be noted that the ADC0801 series will output an all zero code when it converts a negative input Viu gt Vin Also a logic inversion exists as all of the I O ports are buffered with inverting gates Basically if the data read is zero the differential output voltage is negative so a bit in Port B is cleared to pull Vx more negative which will make the output more positive for the next conversion If the data read is not zero the output voltage is positive so a bit in Port B is set to make Vy more positive and the output more negative This continues for 8 approximations and the differential output eventually con verges to within 5 mV of zero The actual program is given in Figure 21 All addresses used are compatible with the BLC 80 10 microcomputer system In particular Port A and the ADC0801 are at port address E4 Port B is at port address E5 Port C is
5. 1 Peto Pome act DS005671 A1 Note 22 In order for the microprocessor to service subroutines and interrupts the stack pointer must be dimensioned in the user s program FIGURE 16 ADC0801 MC6820 PIA Interface DS005671 25 www national com 30 Functional Description Continued SAMPLE PROGRAM FOR Figure 16 ADC0801 MC6820 PIA INTERFACE The following schematic and sample subroutine DATA IN may be used to interface up to 8 ADCO801 s directly to the MC6800 CPU This scheme can easily be extended to allow the interface of more converters In this configuration the converters are arbitrarily located at HEX address 5000 in the MC6800 memory space To save components the clock signal is derived from just one RC pair on the first converter This output drives the other A Ds All the converters are started simultaneously with a STORE instruction at HEX address 5000 Note that any other HEX address of the form 5XXX will be decoded by the circuit pulling all the CS inputs low This can easily be avoided by using a more definitive address decoding scheme All the interrupts are ORed together to insure that all A Ds have completed their conversion before the microprocessor is interrupted The subroutine DATA IN may be called from anywhere in the user s program Once called this routine initializes the DS005671 A2 CPU starts all the converters simultaneously and waits for the interrupt signal
6. 0 6 604 0 127 PIN NO 1 de 0 280 A OPTION 1 7 112 MIN 0 300 0 320 OPTION 2 7 620 8 128 0 130 0 005 20008 3 302 0 127 1 651 0 145 0 200 3 683 5 080 95 5 0 009 0 015 90 0 004 0 229 0 381 0 020 MI La 0 125 0 140 0 508 0 005 2 540 0 254 0018 0003 3175 3556 MIN 0 040 1 5242 0 127 0 457 20 076 0 325 0 015 1 016 0255 1018 Molded Dual In Line Package N Order Number ADC0801LCN ADC0802LCN ADC0803LCN ADC0804LCN or ADCO805LCN NS Package Number N20A N20A REV G www national com 40 Notes LIFE SUPPORT POLICY NATIONAL S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION As used herein SJ9149AUO C V 9 dqneduio dri 18 8 s09000V r08000V 08000V 20800Q0V L0800Q0V 1 Life support devices or systems are devices or 2 A critical component is any component of a life Systems which a are intended for surgical implant support device or system whose failure to perform into the body or b support or sustain life and can be reasonably expected to cause the failure of whose failure to perform when properly used in the life support device or system or to affect its accordance with instructions for use provided in the safety or effectiveness labeling can be reason
7. 96 21 LOOP JNZ EA 1B DJNZ 00 NOP 00 NOP ORG 81 INDATA MOVX AO MOV 18 INC 8901 ORL 27 CLR 93 RETR 4 2 Interfacing the Z 80 The Z 80 control bus is slightly different from that of the 8080 General RD and WR strobes are provided and sepa rate memory request MREQ and request IORQ sig nals are used which have to be combined with the general ized strobes to provide the equivalent 8080 signals An advantage of operating the A D in I O space with the 7 80 is that the CPU will automatically insert one wait state the RD and WR strobes are extended one clock period to allow more time for the I O devices to respond Logic to map the A D in I O space is shown in Figure 14 10H Program Starts at addr 10 3H 50H Interrupt jump vector 10H Main program Pl 0FEH Chip select 1 Read inthe lst data to reset the intr Pl 1 Set port pinhigh RO 20H Data address Rl Dummy address R2 10H Counter for 16 bytes A 0FFH Set for intr loop Pl 0FEH Send CS bit 0 of Pl R1 A Send WR out I Enable interrupt LOOP Wait forinterrupt R2 AGAIN If 16 bytes are read go to user s program 50H A 1 Input data CS still low GRO Store inmemory RO Increment storage counter Pl 1 Reset CS signal A Clear ACC to get out of the interrupt loop DS005671 A0 MM74C32 DS005671 23 FIGURE 14 Mapping the A D as an I O Device for Use with the Z 80 CPU Add
8. Typical Applications continued Digitizing a Current Flow 0 1 Vee LOAD 2A FULL SCALE ZERO DS005671 62 Self Clocking Multiple A Ds External Clocking CLK IN DS005671 64 100 kHzxfci 1460 kHz IF MORE THAN 5 ADDITIONAL A Ds USE A CMOS BUFFER NOT T2L DS005671 63 Use a large R value to reduce loading at CLK R output www national com 10 Typical Applications continued Self Clocking in Free Running Mode START DS005671 65 After power up a momentary grounding of the WR input is needed to guarantee operation Operating with Automotive Ratiometric Transducers Vcc 5 Vpc O A D 0 0805 DS005671 67 Vin 0 15 Voc 15 of VecsVxpre85 of Voc HP Interface for Free Running A D T STAGE BINARY CTR SYS RESET CD40248C Vg7 READY TO aP x Meu Vg PREVENTS RD DURING A D DATA UPDATE mr 72x fek RESET RESET DS005671 66 Ratiometric with Vagp 2 Forced DS005671 68 uP Compatible Differential Input Comparator with Pre Set Vos with or without Hysteresis OUTPUT 1 2 LM358A See Figure 5 to select R value DB7 1 for Vin gt Vin Vrer 2 Omit circuitry within the dotted area if hysteresis is not needed 5 Vpc 1 5k LM336 Vr 08 Vog 10k DS005671 69 www national com 508090VW 08090V 08090V 2080
9. COMMENTS 0010 DF 44 DATAIN STX TEMP Save Contents of X 0012 CE 00 2 LDX 002 Upon IRQ LOW CPU 0015 FF FF F8 STX FFF8 Jumps to 002A 0018 B7 5000 STAA 5000 Starts allA D s 001B OE CLI 001C Wait for interrupt 001D CE 50 00 LDX 5000 0020 DF 40 STX INDEX1 Reset both INDEX 0022 CE 02 00 LDX 0200 1 2 starting 0025 DF 42 STX INDEX2 addresses 0027 DE 44 LDX TEMP Baturnoframsnhroutine _ DS005671 A3 SAMPLE PROGRAM FOR Figure 17 INTERFACING MULTIPLE A D s IN AN MC6800 SYSTEM ADDRESS HEX CODE MNEMONI 0033 A7 00 STAA 0035 8C 0207 CPX 0038 27 05 BEQ 003A 08 INX 003B DF 42 STX 003D 20 EB BRA 003F 3B RETURN RTI 0040 50 00 INDEX1 FDB 0042 02 00 INDEX2 FDB 0044 00 00 TEMP FDB cs COMMENTS X Store data at X 0207 Have all A D s been read RETURN Yes branch to RETURN No increment X by one INDEX2 X INDEX2 INTRPT Branch to 002A 5000 Starting address for A D 0200 Starting address for data Storage 0000 DS005671 A4 Note 25 In order for the microprocessor to service subroutines and interrupts the stack pointer must be dimensioned in the user s program For amplification of DC input signals a major system error is the input offset voltage of the amplifiers used for the preamp Figure 18 is a gain of 100 differential preamp whose offset voltage errors will be cancelled by a zeroing subroutine which is performed by the INS8080A microprocessor sys
10. PIA Here the CS pin of the A D is grounded since the PIA is ANALOG O INPUTS Note 20 Numbers in parentheses refer to MC6800 CPU pin out already memory mapped in the M6800 system and no CS decoding is necessary Also notice that the A D output data lines are connected to the microprocessor bus under pro gram control through the PIA and therefore the A D RD pin can be grounded Asample interface program equivalent to the previous one is shown below Figure 16 The PIA Data and Control Registers of Port B are located at HEX addresses 8006 and 8007 respectively 5 0 GENERAL APPLICATIONS The following applications show some interesting uses for the A D The fact that one particular microprocessor is used is not meant to be restrictive Each of these application circuits would have its counterpart using any microprocessor that is desired 5 1 Multiple ADC0801 Series to MC6800 CPU Interface To transfer analog data from several channels to a single microprocessor system a multiple converter scheme pre sents several advantages over the conventional multiplexer single converter approach With the ADC0801 series the differential inputs allow individual span adjustment for each channel Furthermore all analog input channels are sensed simultaneously which essentially divides the microproces sor s total system servicing time by the number of channels since all conversions occur simultaneously This scheme is shown in Figure 1
11. The digital output LED display can be decoded by dividing the 8 bits into 2 hex characters the 4 most significant MS and the 4 least significant LS Table 1 shows the fractional binary equivalent of these two 4 bit groups By adding the voltages obtained from the VMS and VLS columns in Table 1 the nominal value of the digital display when Vrer 2 2 560V can be determined For example for an output LED display of 1011 0110 or B6 in hex the voltage values from the table are 3 520 0 120 or 3 640 Vpc These voltage values represent the center values of a perfect A D converter The effects of quantization error have to be ac counted for in the interpretation of the test results 23 www national com 508090V r08090V 08090V 208090V 108090V ADC0801 ADC0802 ADC0803 ADC0804 ADC0805 Functional Description Continued 5 120 Vp 8 NSL5027 8 DS005671 18 FIGURE 9 Basic A D Tester For a higher speed test system or to obtain plotted data a digital to analog converter is needed for the test set up An accurate 10 bit DAC can serve as the precision voltage source for the A D Errors of the A D under test can be expressed as either analog voltages or differences in 2 digital words A basic A D tester that uses a DAC and provides the error as an analog output voltage is shown in Figure 8 The 2 op amps can be eliminated if a lab DVM with a numerical subtraction feature is availab
12. apply when operating the device beyond its specified operating conditions Note 2 All voltages are measured with respect to Gnd unless otherwise specified The separate A Gnd point should always be wired to the D Gnd Note 3 A zener diode exists internally from Voc AC Electrical Characteristics continued Note 7 The CS input is assumed to bracket the WR strobe input and therefore timing is dependent on the WR pulse width An arbitrarily wide pulse width will hold the converter in a reset mode and the start of conversion is initiated by the low to high transition of the WR pulse see timing diagrams Note 8 None of these A Ds requires a zero adjust see section 2 5 1 To obtain zero code at other analog input voltages see section 2 5 and Figure 7 Note 9 The Vggr 2 pin is the center point of a two resistor divider connected from Vcc to ground In all versions of the ADCO801 ADC0802 ADC0803 and ADCO0805 and in the ADCO804LCJ each resistor is typically 16 In all versions of the ADC0804 except the ADCO804LCJ each resistor is typically 2 2 Note 10 Human body model 100 pF discharged through a 1 5 kQ resistor Typical Performance Characteristics Logic Input Threshold Voltage vs Supply Voltage 1 8 LOGIC INPUT THRESHOLD VOLTAGE V 4 50 4 75 5 00 5 25 5 50 Vec SUPPLY VOLTAGE Vpg DS005671 38 fci VS Clock Capacitor kHz
13. which to establish proper logic levels on the bus and therefore higher capacitive loads can be driven see typical characteristics curves At higher CPU clock frequencies time can be extended for reads and or writes by inserting wait states 8080 or using clock extending circuits 6800 Finally if time is short and capacitive loading is high external bus drivers must be used These can be TRI STATE buffers low power Schottky such as the DM74LS240 series is rec ommended or special higher drive current products which are designed as bus drivers High current bipolar bus drivers with PNP inputs are recommended 2 10 Power Supplies Noise spikes on the supply line can cause conversion errors as the comparator will respond to this noise A low inductance tantalum filter capacitor should be used close to the converter Vcc and values of 1 or greater are recommended If an unregulated voltage is available in the system a separate LM340LAZ 5 0 TO 92 5V voltage regu lator for the converter and other analog circuitry will greatly reduce digital noise on the Vec supply 2 11 Wiring and Hook Up Precautions Standard digital wire wrap sockets are not satisfactory for breadboarding this A D converter Sockets on PC boards can be used and all logic signal wires and leads should be grouped and kept as far away as possible from the analog signal leads Exposed leads to the analog inputs can cause undesired digital no
14. 336 ZERO ADJ DS005671 73 Multiplexing Differential Inputs 4 CHANNEL DIFFERENTIAL X MU CD4052 B CHANNEL SELECT FROM OUTPUT DS005671 74 PORT OR pP DS005671 75 20 Hz Uses Chebyshev implementation for steeper roll off unity gain 2nd order low pass filter Adding a separate filter for each channel increases system response time if an analog multiplexer is used Output Buffers with A D Data Enabled Increasing Bus Drive and or Reducing Time on Bus TO uP DATA BUS TRISTATES BUFFERS BUFFERS DS005671 76 Allows output data to set up at falling edge of CS A D output data is updated 1 CLK period prior to assertion of INTR P P bus TRISTATE TO uP DATA BUS DS005671 77 15 www national com 508090VW 08090W 08090V 208090V 108090V ADC0801 ADC0802 ADC0803 ADC0804 ADC0805 Typical Applications continued Sampling an AC Input Signal SAMPLI FILTER pe SKIRT 60 TO 80 dB 0 60 LOW PASS MULTI POLE FILTER ro DS005671 78 Note 11 Oversample whenever possible keep fs gt 2f 60 to eliminate input frequency folding aliasing and to allow for the skirt response of the filter Note 12 Consider the amplitude errors which are introduced within the passband of the filter 70 Power Savings by Clock Gating 1 4 74032 TO A D Complete shutdown takes 30 seconds 1 3 74004 DS005671 79 Power Sav
15. 7 TRO 4 0 RAW 34 6 Do 33 31 01 32 29 D2 31 K D3 30 H D4 29 32 D5 28 30 06 27 0 07 26 J A12 22 34 A13 23 N A14 24 M A15 25 33 1 2 092 4 5 5 GND m WXY 414243 DS005671 24 Note 21 Number or letters in brackets refer to standard M6800 system common bus code FIGURE 15 ADC0801 MC6800 CPU Interface 29 www national com S 0800QV v0800QV 08000V c0800QV L0800Q0V ADC0801 ADC0802 ADC0803 ADC0804 ADC0805 Functional Description Continued 0010 0012 0015 0018 001B 001C 001D 001F 0022 0024 0027 0028 002A 002C 002 0031 0033 0034 0056 0038 003B 003D 0913 SAMPLE PROGRAM FOR Figure 15 ADCO801 MC6800 CPU INTERFACE DF 36 DATAIN STX CE 00 2C LDX FF FF F8 STX B7 50 00 STAA CLI 3E CONVRT WAI DE 34 LDX 8C 02 OF CPX 2714 BEQ B7 50 00 STAA 08 INX DF 34 STX 20 FO BRA DE 34 INTRPT LDX B6 50 00 LDAA A7 00 STAA 3B RTI 02 00 TEMPL FDB 00 00 TEMP2 FDB CE 02 00 ENDP LDX DF 34 STX DE 36 LDX prs TEMP2 002C FFF8 5000 TEMP1 020 ENDP 5000 TEMP1 CONVRT 1 5000 X 0200 0000 0200 1 2 Save contents of X Upon IRQ low CPU jumps to 002C Start ADCO801 Wait interrupt Is final data stored Restarts ADCO801 Read data StoreitatX Starting address for data storage Reinitialize
16. 90V 108090V Typical Applications continued Handling 10V Analog Inputs Low Cost uP Interfaced Temperature to Digital Converter DS005671 70 DS005671 71 Beckman Instruments 694 3 R10K resistor array Interfaced Temperature to Digital Converter 5 Voc LM335 2 98V 25 C 10 DS005671 72 Circuit values shown are for 0 lt lt 128 Typical Applications continued Handling 5V Analog Inputs C 5 Beckman Instruments 694 3 R10K resistor array Interfaced Comparator with Hysteresis DS005671 35 DS005671 33 Read Only Interface RD DATA IS STARTS NEW QUTPUT CONVERSION DS005671 34 Protecting the Input Diodes are 1N914 DS005671 9 13 www national com 508090V 08090V 08090V 208090V 108090V ADC0801 ADC0802 ADC0803 ADC0804 ADC0805 Typical Applications continued 10 mV gt Va gt 10VO VMINREF O 710 mV pc LM389 transistors A B C D LM324A quad op amp Analog Self Test for a System 8 SYSTEM CHANNEL DC TEST ANALOG POINTS MUX CD4051 C CHANNEL SELECT FROM OUTPUT PORT OF uP A Low Cost 3 Decade Logarithmic Converter 710 DS005671 36 DS005671 37 www national com Typical Applications continued 3 Decade Logarithmic A D Converter B C LM324A a 1 2 LM394 Vin 10 mV 10V 1M 1M
17. A 1 0 1 0 200 9 1 0 0 9 256 0 180 8 1 0 0 0 160 7 0 1 1 0 140 6 0 1 1 0 120 5 0 1 0 0 100 4 0 1 0 0 080 3 0 0 1 0 060 2 0 0 1 0 040 1 0 0 0 0 020 0 0 0 0 0 Note 15 Display Output VMS Group VLS Group 25 www national com 508090V r08090V 08090V 208090V 108090V ADC0801 ADC0802 ADC0803 ADC0804 ADC0805 Functional Description Continued gt INT 14 VO WR 27 170 RD 25 TD DBO 13 DB1 16 DB2 11 DB3 9 DBA 5 085 18 DB6 20 D87 7 ANALOGO INPUTS y AD15 36 AD14 39 DM8131 BUS AD13 38 COMPARATOR AD12 37 AD11 40 AD10 1 DS005671 20 Note 16 Pin numbers for the DP8228 system controller others are INS8080A Note 17 Pin 23 of the INS8228 must be tied to 12V through a 1 KQ resistor to generate the RST 7 instruction when an interrupt is acknowledged as required by the accompanying sample program FIGURE 12 ADC0801_INS8080A CPU Interface www national com 26 Functional Description Continued SAMPLE PROGRAM FOR Figure 12 ADCO801 INS8080A CPU INTERFACE 0038 C3 00 05 RST7 JMP LD DATA e e e 0100 210002 START LXI H 0200H HL pair will point to data storage locations 0103 31 00 04 RETURN LXI SP 0400H Initialize stack pointer Note 1 0106 7D MOVA L Test of bytes entered 0107 FEOF CPIOFH If4 16 JMP to 0109 CA 1301 JZ CONT user program 010C D3 EO OUT EO H Start A D 010 Enab
18. AID5 00 MM74C374 8 bit flip flop m AID 6 01 AID 1 07 A D 7 02 A D 2 This port address also serves as the A D identifying word in 03 A D 3 the program MM74C30 rx n D4 DATA BUS e MM74C374 as 05 087 DS005671 29 FIGURE 22 Multiple A Ds with Z 80 Type Microprocessor www national com 38 Functional Description Continued INTERRUPT SERVICING SUBROUTINE LOC 0038 0039 003A 003B 003 0040 0042 0044 0045 0046 0048 0048 004C 004D 004E 0051 0052 0055 0057 0059 005A 005B 005C 005D 0060 0061 0062 0065 OBJ CODE OE 01 47 C3 51 00 Fl cl TEST NEXT LOAD DONE SOURCE STATEMENT PUSH HL PUSH BC PUSH AF LD HL X3E00 LDC X01 OUT X00 A INA X00 LDB A LDA C CP X08 JPZ DONE LDA B RRA LDB A JPC LOAD INC JP TEST INA C XOR FF LD HL A INCL LD HL C INCL JP NEXT POP AF POP BC POP HL RET COMMENT Save contents of all registers affected by this subroutine Assumed INT mode 1 earlier set Initialize memory pointer where data will be stored register will be port ADDR of A D converters Load peripheral status word into 8 bit latch Load status word into accumulator Save the status word Test to see if the status of all A D s have been checked so exit Subroutine Test asingle bit in status word by looking for 1 to be rotated into the CARRY an INT is loadedasa l If CARRY is set then load con
19. E7F MVIA 7F SDOD 4F MOV C A Return SDOE D3E5 OUTB 3D10 31AA3D LXI SP SDAA Start 015 DSE4 OUTA 3D15 FB IE 3D16 00 NOP Loop 017 C3163D JMP Loop 3D1A 7A MOV Auto Zero 3D1B Ce00 ADI 00 3010 CA2DSD JZSetC 17 CELLA K UU I un zx 9 Note 29 All numerical values are hexadecimal representations FIGURE 21 Software for Auto Zeroed Differential A D 5 3 Multiple A D Converters in a Z 80 Interrupt Driven Mode Continued The following notes apply It is assumed that the CPU automatically performs a RST 7 instruction when a valid interrupt is acknowledged CPU is in interrupt mode 1 Hence the subroutine starting address of X0038 The address bus from the Z 80 and the data bus to the Z 80 are assumed to be inverted by bus drivers A D data and identifying words will be stored in sequen tial memory locations starting at the arbitrarily chosen address X 3E00 DS005671 A5 The stack pointer must be dimensioned in the main pro gram as the RST 7 instruction automatically pushes the PC onto the stack and the subroutine uses an additional 6 stack addresses The peripherals of concern are mapped into I O space with the following port assignments 37 www national com 508090V r08090V 08090V 208090V 108090V ADC0801 ADC0802 ADC0803 ADC0804 ADC0805 Functional Description Continued HEX PORT ADDRESS PERIPHERAL 04 A D 4 HEX PORT ADDRESS PERIPHERAL 05
20. R pin do not use a standard TTL buffer 2 7 Restart During a Conversion If the A D is restarted CS and WR go low and return high during a conversion the converter is reset and a new con version is started The output data latch is not updated if the conversion in process is not allowed to be completed there fore the data of the previous conversion remains in this latch The INTR output simply remains at the 1 level 2 8 Continuous Conversions For operation in the free running mode an initializing pulse should be used following power up to ensure circuit opera tion In this application the CS input is grounded and the WR input is tied to the INTR output This WR and INTR node should be momentarily forced to logic low following a power up cycle to guarantee operation 2 9 Driving the Data Bus This MOS A D like MOS microprocessors and memories will require a bus driver when the total capacitance of the data bus gets large Other circuitry which is tied to the data bus will add to the total capacitive loading even in TRI STATE high impedance mode Backplane bussing also greatly adds to the stray capacitance of the data bus There are some alternatives available to the designer to handle this problem Basically the capacitive loading of the data bus slows down the response time even though DC specifications are still met For systems operating with a relatively slow CPU clock frequency more time is available in
21. SB A Perfect A D Transfer Function DIGITAL OUTPUT CODE DS005671 83 Error Plot 1 LSB 3 4 LSB 1 2 LSB A 1 1 ANALOG INPUT Vi DS005671 84 FIGURE 2 Clarifying the Error Specs of an A D Converter 14 LSB www national com 508090V r08090V 08090V 208090V 108090V ADC0801 ADC0802 ADC0803 ADC0804 ADC0805 Functional Description Continued Transfer Function DIGITAL OUTPUT CODE 0 005671 85 Error Plot ERROR e 1 LSB A 1 A ANALOG INPUT Viy A 1 DS005671 86 FIGURE 3 Clarifying the Error Specs of an A D Converter 12 LSB 2 0 FUNCTIONAL DESCRIPTION The ADCO0801 series contains a circuit equivalent of the 256R network Analog switches are sequenced by succes sive approximation logic to match the analog difference input voltage Vin Vin to a corresponding tap on the R network The most significant bit is tested first and after 8 comparisons 64 clock cycles a digital 8 bit binary code 1111 1111 full scale is transferred to an output latch and then an interrupt is asserted INTR makes a high to low transition A conversion in process can be interrupted by issuing a second start command The device may be oper ated in the free running mode by connecting INTR to the WR input with CS 0 To ensure start up under all possible conditions an external WR pulse is required during the first power up cycle On the hi
22. TIONAL T xt FS ADJUST DS005671 54 Note before using caps at Vin or Vngr 2 see section 2 3 2 Input Bypass Capacitors 7 www national com 508090VW 08090W 08090V 208090V 108090V ADC0801 ADC0802 ADC0803 ADC0804 ADC0805 Typical Applications continue Absolute with a 2 500V Reference 5 Vpc Q DS005671 55 For low power see also LM385 2 5 Zero Shift and Span Adjust 2V lt Vin lt 5V 5 O 12k SETS ZERO SETS VOLTAGE SPAN CODE VOLTAGE SEE SECTION 2 4 DS005671 57 Absolute with a 5V Reference VREF 5 l 1 1 1 10 1 1 1 Eccc OPTIONAL FS ADJUST DS005671 56 Span Adjust OV lt Vin lt 3V Vcc 5 Voe 2k LM336 DS005671 58 www national com Typical Applications continued Directly Converting a Low Level Signal A uP Interfaced Comparator Vec Vec 5 5 OV lt Vin lt 512 mV DS005671 60 For Vin gt Vin Output FFugx For Vin lt Vin DS005671 59 Output 00Hex 15 Vngr 2 256 mV 1 mV Resolution with uP Controlled Range 5 Vpc 8 BIT DAC 2 500 2 500 V t MICRO DACTM DACOB30 LM336 DS005671 61 Vggp 2 128 mV 1 LSB 1 mV VpacSViNS Vpac 256 mV 0 lt Vpac lt 2 5V 9 www national com 508090VW 08090V 08090V 208090V 108090V ADC0801 ADC0802 ADC0803 ADC0804 ADC0805
23. TRI STATE Output 5 7 5 pF Capacitance Data Buffers CONTROL INPUTS Note CLK IN Pin 4 is the input of a Schmitt trigger circuit and is therefore specified separately Vin 1 Logical 1 Input Voltage 5 25 2 0 15 Voc Except Pin 4 CLK IN Vin 0 Logical 0 Input Voltage 4 75 Voc Except Pin 4 CLK IN pem TT lin 1 Logical 1 Input Current Vin 5 0 005 1 All Inputs lin 0 Logical 0 Input Current Vin 0 1 0 005 All Inputs CLOCK IN AND CLOCK R CLK IN Pin 4 Positive Going Threshold Voltage CLK IN Pin 4 Negative Going Threshold Voltage CLK IN Pin 4 Hysteresis Logical 0 CLK R Output Voltage 15 360 pA Logical 0 Output Voltage Data Outputs INTR Output loyr 1 6 mA 4 75 loyr 1 0 mA 4 75 Logical 1 Output Voltage 152 360 pA 4 75 Vpc Logical 1 Output Voltage lo 10 4 75 Voc TRI STATE Disabled Output Vout 0 Vpc Leakage All Data Buffers Vout 5 Vpc 3 Isink Vou Short to Ta 25 C 9 0 16 mApc POWER SUPPLY loc Supply Current Includes fci 2640 kHz Ladder Current Vuge 22 NC 25 and CS 5V ADC0801 02 03 04LCJ 05 1 1 1 8 mA ADC0804LCN LCWM 1 9 2 5 mA Note 1 Absolute Maximum Ratings indicate limits beyond which damage to the device may occur DC and AC electrical specifications do not
24. Upon receiving the interrupt it reads the converters from HEX addresses 5000 through 5007 and stores the data successively at arbitrarily chosen HEX addresses 0200 to 0207 before returning to the user s pro gram All CPU registers then recover the original data they had before servicing DATA IN 5 2 Auto Zeroed Differential Transducer Amplifier and A D Converter The differential inputs of the ADCO0801 series eliminate the need to perform a differential to single ended conversion for a differential transducer Thus one op amp can be elimi nated since the differential to single ended conversion is provided by the differential input of the ADC0801 series In general a transducer preamp is required to take advantage of the full A D converter input dynamic range 31 www national com 508090V r08090V 08090V 208090V 108090V Functional Description Continued RAW 34 6 DATA BUS 00 33 31 D1 32 29 D2 31 K 03 30 D4 29 32 D5 28 30 06 27 1 07 26 J ANALOG O A2 11 U INPUTS A1 10 V A0 9 40 gt 0 WR p GND el 41 42 43 5 F ANALOG INPUTS 1 2 A12 22 34 6 3 O C o lt I A em 4 1 2 DM8092 A14 24 M 5 O 15 25 33 DS005671 26 Note 23 Functional Description Continued SAMPLE PROGRAM FOR Figure 17 INTERFACING MULTIPLE A D s IN AN MC6800 SYSTEM ADDRESS HEX CODE MNEMONICS
25. ably expected to result in a significant injury to the user National Semiconductor National Semiconductor National Semiconductor National Semiconductor Corporation Europe Asia Pacific Customer Japan Ltd Americas Fax 49 0 180 530 85 86 Response Group Tel 81 3 5639 7560 Email support nsc com Email europe support nsc com Tel 65 2544466 Fax 81 3 5639 7507 Deutsch Tel 49 0 69 9508 6208 Fax 65 2504466 English Tel 44 0 870 24 0 2171 Email ap support nsc com www national com Frangais Tel 33 0 1 41 91 8790 National does not assume any responsibility for use of any circuitry described no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications
26. at port address E6 PPI control word port is at port address E7 Program Counter automatically goes to ADDR 3C3D upon acknowledgement of an interrupt from the ADCO801 5 3 Multiple A D Converters in a Z 80 Interrupt Driven Mode In data acquisition systems where more than one A D con verter or other peripheral device will be interrupting pro gram execution of a microprocessor there is obviously a need for the CPU to determine which device requires servic ing Figure 22 and the accompanying software is a method of determining which of 7 ADCO801 converters has com pleted a conversion INTR asserted and is requesting an interrupt This circuit allows starting the A D converters in any sequence but will input and store valid data from the converters with a priority sequence of A D 1 being read first A D 2 second etc through A D 7 which would have the lowest priority for data being read Only the converters whose INT is asserted will be read The key to decoding circuitry is the DM74LS373 8 bit D type flip flop When the Z 80 acknowledges the interrupt the program is vectored to a data input Z 80 subroutine This subroutine will read a peripheral status word from the DM74LS373 which contains the logic state of the INTR outputs of all the converters Each converter which initiates an interrupt will place a logic 0 in a unique bit position in the status word and the subroutine will determine the identity of the converter and exe
27. cations Works with 2 5V LM336 voltage reference On chip clock generator OV to 5V analog input voltage range with single 5V supply No zero adjust required 0 3 standard width 20 pin DIP package 20 pin molded chip carrier or small outline package Operates ratiometrically or with 5 Voc 2 5 or analog span adjusted voltage reference DB7 MSB DS005671 30 0 C TO 70 C 40 C TO 85 C 14 Bit Adjusted 16 Bit Unadjusted 16 Bit Adjusted 1Bit Unadjusted PACKAGE OUTLINE ERROR Outline Z 80 is a registered trademark of Zilog Corp ADC0802LCWM ADCO804LCWM M20B Small ADCO0801LCN ADCO802LCN ADCO808LCN ADCO804LCN ADCO805LCN ADCO804LCJ N20A Molded DIP 2001 National Semiconductor Corporation DS005671 www national com SJ9149AUO C V 9 dqneduio dri 118 8 s09000V r08000V 08000V 20800Q0V L08000V ADC0801 ADC0802 ADC0803 ADC0804 ADC0805 Typical Applications TRANSDUCER 8 BIT RESOLUTION OVER ANY DESIRED ANALOG INPUT VOLTAGE RANGE SEE SECTION 2 4 1 ANY HPROCESSOR SPAN ADJ O SEE SECTION 241 0 005671 1 6800 8080 280 8048 DS005671 31 Error Specification Includes Full Scale Zero Error and Non Linearity Part Full Vrer 2 2 500 Voc Vrer 2 No Connection Number Scale No Adjustments No Adjustments Adjusted ADC0802 14 LSB ADC0804 1 LSB ADC0805 1 LSB ww
28. ce to microprocessor control busses For non microprocessor based applications the CS input pin 1 can be grounded and the standard A D Start function is obtained by an active low pulse applied at the WR input pin 3 and the Output Enable function is caused by an active low pulse at the RD input pin 2 19 www national com 508090V r08090V 08090V 208090V 108090V ADC0801 ADC0802 ADC0803 ADC0804 ADC0805 Functional Description Continued 2 2 Analog Differential Voltage Inputs and Common Mode Rejection This A D has additional applications flexibility due to the analog differential voltage input The Viy input pin 7 can be used to automatically subtract a fixed voltage value from the input reading tare correction This is also useful in 4 mA 20 mA current loop conversion In addition common mode noise can be reduced by use of the differen tial input The time interval between sampling V and V n is 4 14 clock periods The maximum error voltage due to this slight time difference between the input voltage samples is given by 4 5 AVe MAX Vp 27rfcm E where AV is the error voltage due to sampling delay Vp is the peak value of the common mode voltage fom is the common mode frequency As an example to keep this error to 14 LSB 5 mV when operating with 60 Hz common mode frequency foem and using a 640 kHz A D clock fc would allow a peak value of the common mode voltage Vp whi
29. ch is given by Vp LAVe max Fok P mies 4 5 or _ 5 10 3 640 x 103 Vp 6 28 60 4 5 which gives Vp 1 9V The allowed range of analog input voltages usually places more severe restrictions on input common mode noise lev els An analog input voltage with a reduced span and a relatively large zero offset can be handled easily by making use of the differential input see section 2 4 Reference Voltage 2 3 Analog Inputs 2 3 1 Input Current Normal Mode Due to the internal switching action displacement currents will flow at the analog inputs This is due to on chip stray capacitance to ground as shown in Figure 5 gt TIME Rs CHARGE TON l l 60 ns 1 l CSTRAY 08005671 14 VA IDISCHARGE 7 Vine of SW 1 and SW 2 5 r ron Cstray 5 x 12 pF 60 ns FIGURE 5 Analog Input Impedance Ll 2clclcl The voltage on this capacitance is switched and will result in currents entering the Vin input pin and leaving the Vin input which will depend on the analog differential input volt age levels These current transients occur at the leading edge of the internal clocks They rapidly decay and do not cause errors as the on chip comparator is strobed at the end of the clock period Fault Mode If the voltage source applied to the Vin or Vin pin exceeds the allowed operating range of 50 mV larg
30. cute a data read An identifier word which indicates which A D the data came from is stored in the next sequential memory location above the location of the data so the program can keep track of the identity of the data entered 35 www national com 508090V r08090V 08090V 208090V 108090V ADC0801 ADC0802 ADC0803 ADC0804 ADC0805 Functional Description Continued PREAMP IS ZEROED AND PROPER INPUT CONVERSIONS CAN BE DONE OPEN SW1 CLOSE SW2 START ZEROING SUBROUTINE CLOSE SW1 OPEN SW2 INITIALIZE SAR BIT POINTER REG B X 80 INITIALIZE SAR CODE IN REG C OUTPUT FIRST SAR CODE PORT B X 80 START A D AND READ DATA OR REG B WITH REG C TO CLEAR BIT IN PORT B WHEN REAPPLIED SHIFT 1 IN REG RIGHT TO POINT TO NEXT BIT IS REG B ZERO EXCLUSIVE OR REG B WITH REG C TO SET NEXT BIT IN PORT B OUTPUT NEW SAR CODE TO PORT B DS005671 28 FIGURE 20 Flow Chart for Auto Zero Routine www national com 36 Functional Description Continued Program PPI Close SW1 open SW2 Initialize SAR bit pointer Initialize SAR code Port B SAR code Dimension stack pointer Start A D Loop until INT asserted Test A D output data for zero 3000 3E90 MVI 90 002 D3E7 Out Control Port 3D04 2601 MVIHO1 Auto Zero Subroutine 006 7C MOV A H 3007 D3E6 OUT C 3D09 0680 80 008 3
31. d to directly interface with derivatives of the 8080 microprocessor The A D can be mapped into memory space using standard memory ad dress decoding for CS and the MEMR and MEMW strobes or it can be controlled as an I O device by using the I O and I O W strobes and decoding the address bits AO gt A7 or address bits 8 gt A15 as they will contain the same 8 bit address information to obtain the CS input Using the space provides 256 additional addresses and may allow a simpler 8 bit address decoder but the data can only be input to the accumulator To make use of the additional memory reference instructions the A D should be mapped into memory space An example of an A D in I O space is shown in Figure 12 www national com 24 Functional Description Continued DAC1000 10 BIT DAC 8 BIT A D UNDER TEST VANALOG OUTPUT ANALOG INPUT VOLTAGE O 100X ANALOG ERROR VOLTAGE DS005671 89 FIGURE 10 A D Tester with Analog Error Output DAC1000 DIGIT AL 10 817 DAC A D UNDER TEST DIGITAL OUTPUT 2222 0 005671 90 FIGURE 11 Basic Digital A D Tester TABLE 1 DECODING THE DIGITAL OUTPUT LEDs OUTPUT VOLTAGE FRACTIONAL BINARY VALUE FOR CENTER VALUES HEX BINARY WITH Vrer 2 2 560 Voc LS GROUP VMS VLS GROUP GROUP Note 15 Note 15 F 1 1 1 15 256 0 300 E 1 1 1 0 280 D 1 1 0 13 256 0 260 C 1 1 0 0 240 B 1 0 1 11 256 0 220
32. e input currents can flow through a parasitic diode to the pin If these currents can exceed the 1 mA max allowed spec an external diode 1N914 should be added to bypass this current to the Vec pin with the current bypassed with this diode the voltage at the V n pin can exceed the Vos voltage by the forward voltage of this diode 2 3 2 Input Bypass Capacitors Bypass capacitors at the inputs will average these charges and cause a DC current to flow through the output resis tances of the analog signal sources This charge pumping action is worse for continuous conversions with the Vin input voltage at full scale For continuous conversions with a 640 kHz clock frequency with the Vin input at 5V this DC current is at a maximum of approximately 5 pA Therefore bypass capacitors should not be used at the analog inputs or the Vagpy 2 pin for high resistance sources gt 1 If input bypass capacitors are necessary for noise filtering and high source resistance is desirable to minimize capacitor size the detrimental effects of the voltage drop across this input resistance which is due to the average value of the input current can be eliminated with a full scale adjustment while the given source resistor and input bypass capacitor are both in place This is possible because the average value of the input current is a precise linear function of the differential input voltage 2 3 3 Input Source Resistance Large valu
33. es of source resistance where an input bypass capacitor is not used will not cause errors as the input currents settle out prior to the comparison time If a low pass filler is required in the system use a low valued series resistor 1 kQ for a passive RC section or add an op amp RC active low pass filter For low source resistance applica tions lt 1 a 0 1 uF bypass capacitor at the inputs will prevent noise pickup due to series lead inductance of a long www national com 20 Functional Description Continued wire A 100Q series resistor can be used to isolate this capacitor both the R and C are placed outside the feed back loop from the output of an op amp if used 2 3 4 Noise The leads to the analog inputs pins 6 and 7 should be kept as short as possible to minimize input noise coupling Both noise and undesired digital clock coupling to these inputs can cause system errors The source resistance for these inputs should in general be kept below 5 kQ Larger values of source resistance can cause undesired system noise pickup Input bypass capacitors placed from the analog inputs to ground will eliminate system noise pickup but can create analog scale errors as these capacitors will average the transient input switching currents of the A D see section 2 3 1 This scale error depends on both a large source resistance and the use of an input bypass capacitor This error can be eliminated by doing a
34. full scale adjustment of the A D adjust 2 for a proper full scale reading see section 2 5 2 on Full Scale Adjustment with the source re sistance and input bypass capacitor in place 2 4 Reference Voltage 2 4 1 Span Adjust For maximum applications flexibility these A Ds have been designed to accommodate a 5 Vpc 2 5 Vpc or an adjusted voltage reference This has been achieved in the design of the IC as shown in Figure 6 Notice that the reference voltage for the IC is either 12 of the voltage applied to the Voc supply pin or is equal to the voltage that is externally forced at the Vr_ 2 pin This allows for a ratiometric voltage reference using the V supply a 5 Vpc reference voltage can be used for the Vcc supply or a voltage less than 2 5 can be applied to the Vagp 2 input for increased application flexibility The internal gain to the Vrer 2 input is 2 making the full scale differential input voltage twice the voltage at pin 9 An example of the use of an adjusted reference voltage is to accommodate a reduced span or dynamic voltage range of the analog input voltage If the analog input voltage were to range from 0 5 to 3 5 Vpc instead of OV to 5 Vpc the span would be 3V as shown in Figure 7 With 0 5 applied to the Vin pin to absorb the offset the reference voltage can be made equal to 14 of the 3V span or 1 5 The A D now will encode the V n signal from 0 5V to 3 5 V with t
35. gh to low transition of the WR input the internal SAR latches and the shift register stages are reset As long as the CS input and WR input remain low the A D will remain in a reset state Conversion will start from 1 to 8 clock periods after at least one of these inputs makes a low to high transition A functional diagram of the A D converter is shown in Figure 4 All of the package pinouts are shown and the major logic control paths are drawn in heavier weight lines The converter is started by having CS and WR simulta neously low This sets the start flip flop F F and the result ing 1 level resets the 8 bit shift register resets the Interrupt INTR F F and inputs a 1 to the D flop F F1 which is at the input end of the 8 bit shift register Internal clock signals then transfer this 1 to the Q output of F F1 The AND gate G1 combines this 1 output with a clock signal to provide a reset signal to the start F F If the set signal is no longer present either WR or CS is a 1 the start F F is reset and the 8 bit shift register then can have the 1 clocked in which starts the conversion process If the set signal were to still be present this reset pulse would have no effect both outputs of the start F F would momentarily be at a 1 level and the 8 bit shift register would continue to be held in the reset mode This logic therefore allows for wide CS and WR signals and the converter will start afte
36. he 0 5V input corresponding to zero and the 3 5 Vpc input corresponding to full scale The full 8 bits of resolution are therefore applied over this reduced analog input voltage range 2 4 2 Reference Accuracy Requirements The converter can be operated in a ratiometric mode or an absolute mode In ratiometric converter applications the magnitude of the reference voltage is a factor in both the output of the source transducer and the output of the A D converter and therefore cancels out in the final digital output code The ADC0805 is specified particularly for use in ratio metric applications with no adjustments required In absolute conversion applications both the initial value and the tem perature stability of the reference voltage are important fac tors in the accuracy of the A D converter For V ADC0801 ADC0802 ADC0803 ADC0804 ADC0805 Functional Description Continued 5V P MAX t 4 3 5V 7 3 2E yate min SPAN 1 0 5V 0 DS005671 87 a Analog Input Signal Example SPAN 2 T 0 005671 88 0 5 Voc 1 5 1 2 ZERO SHIFT SPAN ee ADJ ADJ Add if Vper 2 lt 1 Vpc with LM358 to draw mA to ground b Accommodating an Analog Input from 0 5V Digital Out 00 to 3 5V Digital Out FF Ex FIGURE 7 Adapting the A D Analog Input Voltages to Match an Arbitrary Input Signal Range 2 5 Errors and Reference Voltage Adjustments 2 5 1 Zero Error The zero of the A D d
37. ings by A D and Shutdown uP CONTROL BUS Use ADC0801 02 03 or 05 for lowest power consumption Note Logic inputs can be driven to Vcc with A D supply at zero volts Buffer prevents data bus from overdriving output of A D when in shutdown mode Functional Description 1 0 UNDERSTANDING A D ERROR SPECS A perfect A D transfer characteristic staircase waveform is shown in Figure 1 The horizontal scale is analog input voltage and the particular points labeled are in steps of 1 LSB 19 53 mV with 2 5V tied to the Vagp 2 pin The digital output codes that correspond to these inputs are shown as T A D DATA OUTPUT CMOS BUFFER DS005671 80 D 1 D and D 1 For the perfect A D not only will center value A 1 A A 1 analog inputs produce the correct output digital codes but also each riser the transitions between adjacent output codes will be located 16 LSB away from each center value As shown the risers are ideal and have no width Correct digital output codes will be provided for a range of analog input voltages that extend www national com 16 Functional Description Continued t LSB from the ideal center values Each tread the range of analog input voltage that provides the same digital output code is therefore 1 LSB wide Figure 2 shows a worst case error plot for the ADC0801 All center valued inputs are guaranteed to produce the correct output codes and the adjacent r
38. ise and hum pickup therefore shielded leads may be necessary in many applications A single point analog ground that is separate from the logic ground points should be used The power supply bypass capacitor and the self clocking capacitor if used should both be returned to digital ground Any 2 bypass ca pacitors analog input filter capacitors or input signal shield ing should be returned to the analog ground point A test for proper grounding is to measure the zero error of the A D converter Zero errors in excess of 14 LSB can usually be traced to improper board layout and wiring see section 2 5 1 for measuring the zero error 3 0 TESTING THE A D CONVERTER There are many degrees of complexity associated with test ing an A D converter One of the simplest tests is to apply a known analog input voltage to the converter and use LEDs to display the resulting digital output code as shown in Figure 9 For ease of testing the Vage 2 pin 9 should be supplied with 2 560 and a Vec supply voltage of 5 12 should be used This provides an LSB value of 20 mV If a full scale adjustment is to be made an analog input voltage of 5 090 Vpc 5 120 114 LSB should be applied to the Vin pin with the Vin pin grounded The value of the Vrer 2 input voltage should then be adjusted until the digital output code is just changing from 1111 1110 to 1111 1111 This value of Vagf 2 should then be used for all the tests
39. isers are guaranteed to be no closer to the center value points than 14 LSB In other words if we apply an analog input equal to the center value 14 LSB we guarantee that the A D will produce the correct digital code The maximum range of the position of the code transition is indicated by the horizontal arrow and it is guar anteed to be no more than 1 LSB The error curve of Figure 3 shows a worst case error plot for the ADCO802 Here we guarantee that if we apply an analog input equal to the LSB analog voltage center value the A D will produce the correct digital code Transfer Function DIGITAL OUTPUT CODE A 1 A A 1 ANALOG INPUT Viy DS005671 81 Next to each transfer function is shown the corresponding error plot Many people may be more familiar with error plots than transfer functions The analog input voltage to the A D is provided by either a linear ramp or by the discrete output steps of a high resolution DAC Notice that the error is continuously displayed and includes the quantization uncer tainty of the A D For example the error at point 1 of Figure 1 is 12 LSB because the digital code appeared 12 LSB in advance of the center value of the tread The error plots always have a constant negative slope and the abrupt up side steps are always 1 LSB in magnitude Error Plot 1 LSB 1 LSB A 1 A A 1 ANALOG INPUT Viy DS005671 82 FIGURE 1 Clarifying the Error Specs of an A D Converter Accuracy 0 L
40. itional I O advantages exist as software DMA routines are available and use can be made of the output data transfer which exists on the upper 8 address lines A8 to www national com 28 Functional Description Continued A15 during I O input instructions For example MUX chan nel selection for the A D can be accomplished with this operating mode 4 3 Interfacing 6800 Microprocessor Derivatives 6502 etc The control bus for the 6800 microprocessor derivatives does not use the RD and WR strobe signals Instead it employs a single R W line and additional timing if needed can be derived fom the 2 clock All I O devices are memory mapped in the 6800 system and a special signal VMA indicates that the current address is valid Figure 15 shows an interface schematic where the A D is memory mapped in the 6800 system For simplicity the CS decoding is shown using 12 DM8092 Note that in many 6800 systems already decoded 4 5 line is brought out to the common bus at pin 21 This can be tied directly to the CS pin of the A D provided that no other devices are addressed at HX ADDR 4XXX or 5XXX The following subroutine performs essentially the same func tion as in the case of the 8080A interface and it can be called from anywhere in the user s program In Figure 16 the ADC0801 series is interfaced to the M6800 microprocessor through the arbitrarily chosen Port B of the MC6820 or MC6821 Peripheral Interface Adapter
41. le interrupt 010 00 LOOP NOP Loop until end of 0110 C3 0F 01 JMP LOOP conversion 0113 CONT e e User program to process data e o o e 0300 DB EO LD DATA INEOH Load data into accumulator 0302 77 MOVM A Store data 0305 23 INXH Increment storage pointer 0304 C30301 JMP RETURN DS005671 99 Note 18 The stack pointer must be dimensioned because a RST 7 instruction pushes the PC onto the stack Note 19 All address used were arbitrarily chosen The standard control bus signals of the 8080 CS RD and WR can be directly wired to the digital control inputs of the A D and the bus timing requirements are met to allow both starting the converter and outputting the data onto the data bus A bus driver should be used for larger microprocessor systems where the data bus leaves the PC board and or must drive capacitive loads larger than 100 pF 4 1 1 Sample 8080A CPU Interfacing Circuitry and Program The following sample program and associated hardware shown in Figure 12 may be used to input data from the converter to the INS8080A CPU chip set comprised of the INS8080A microprocessor the INS8228 system controller and the INS8224 clock generator For simplicity the A D is controlled as an I O device specifically an 8 bit bi directional port located at an arbitrarily chosen port address E0 The TRI STATE output capability of the A D eliminates the need for a peripheral interface device however addres
42. le to read the difference volt age directly The analog input voltage can be sup plied by a low frequency ramp generator and an X Y plotter can be used to provide analog error Y axis versus analog input X axis For operation with a microprocessor or a computer based test system it is more convenient to present the errors digitally This can be done with the circuit of Figure 11 where the output code transitions can be detected as the 10 bit DAC is incremented This provides 14 LSB steps for the 8 bit A D under test If the results of this test are automatically plotted with the analog input on the X axis and the error in LSB s as the Y axis a useful transfer function of the A D under test results For acceptance testing the plot is not necessary and the testing speed can be increased by estab lishing internal limits on the allowed error for each code 4 0 MICROPROCESSOR INTERFACING To dicuss the interface with 8080A and 6800 microproces Sors a common sample subroutine structure is used The microprocessor starts the A D reads and stores the results of 16 successive conversions then returns to the user s program The 16 data bytes are stored in 16 successive memory locations All Data and Addresses will be given in hexadecimal form Software and hardware details are pro vided separately for each type of microprocessor 4 1 Interfacing 8080 Microprocessor Derivatives 8048 8085 This converter has been designe
43. mV ee 4 88 10 BITS 9 77 1 LSB 0 1 2 2 5 VREF 2 VOLTAGE DS005671 46 www national com 508090V 08090V 08090V 208090V 108090V ADC0801 ADC0802 ADC0803 ADC0804 ADC0805 TRI STATE Test Circuits and Waveforms t H RD O DATA cs OUTPUT CL 10k DS005671 47 ton Vcc 10k RDO DATA ts OUTPUT CL DS005671 49 tin C 210 pF Vou DATA OUTPUTS GND t 20 ns ton C 210 pF RD DATA OUTPUTS VoL tr 20 ns Timing Diag rams All timing is measured from the 50 voltage points START CONVERSION ACTUAL INTERNAL STATUS OF THE _ __ _ M CONVERTER LAST DATA WAS READ INTR LAST DATA WAS NOT READ ES BUSY NOT BUSY 1T0 8x 1 1 90 DS005671 48 10 DS005671 50 DATA IS VALID IN OUTPUT LATCHES INTERNAL Tp INT ASSERTED 1 2 0 005671 51 www national com Timing Diag ams All timing is measured from the 50 voltage points Continued Output Enable and Reset with INTR INTR RESET TRI STATE DATA OUTPUTS DS005671 52 Note Read strobe must occur 8 clock periods 8 fc after assertion of interrupt to guarantee reset of INTR Typical Applications 6800 Interface Ratiometeric with Full Scale Adjust 5 Vpc DS005671 53 LI 1 shoes OP
44. nuously enabled CS and RD both held low the INTR output will still signal the end of conversion by a high to low transition because the SET input can control the Q output of the INTR F F even though the RESET input is constantly at a 1 level in this operating mode This INTR output will therefore stay low for the duration of the SET signal which is 8 periods of the external clock frequency assuming the A D is not started during this interval When operating in the free running or continuous conversion mode INTR pin tied to WR and CS wired low see also section 2 8 the START F F is SET by the high to low tran sition of the INTR signal This resets the SHIFT REGISTER which causes the input to the D type latch LATCH 1 to go low As the latch enable input is still present the Q output will go high which then allows the INTR F F to be RESET This reduces the width of the resulting INTR output pulse to only a few propagation delays approximately 300 ns When data is to be read the combination of both CS and RD being low will cause the INTR F F to be reset and the TRI STATE output latches will be enabled to provide the 8 bit digital outputs 2 1 Digital Control Inputs The digital control inputs CS RD and WR meet standard T L logic voltage levels These signals have been renamed when compared to the standard A D Start and Output Enable labels In addition these inputs are active low to allow an easy interfa
45. oes not require adjustment If the minimum analog input voltage value Vii is not ground a zero offset can be done The converter can be made to output 0000 0000 digital code for this minimum input voltage by biasing the A D V input at this value see Applications section This utilizes the differential mode op eration of the A D The zero error of the A D converter relates to the location of the first riser of the transfer function and can be measured by grounding the Vn input and applying a small magnitude positive voltage to the Vin input Zero error is the differ ence between the actual DC input voltage that is necessary to just cause an output digital code transition from 0000 0000 to 0000 0001 and the ideal 12 LSB value 12 LSB 9 8 mV for Vagp 2 2 500 2 5 2 Full Scale The full scale adjustment can be made by applying a differ ential input voltage that is 112 LSB less than the desired analog full scale voltage range and then adjusting the mag nitude of the Vage 2 input pin 9 or the supply if pin 9 is not used for a digital output code that is just changing from 1111 1110 to 1111 1111 2 5 3 Adjusting for an Arbitrary Analog Input Voltage Range If the analog zero voltage of the A D is shifted away from ground for example to accommodate an analog input signal that does not go to ground this new zero reference should be properly adjusted first voltage that equals this desired ze
46. r at least one of these signals returns high and the internal clocks again provide a reset signal for the start F F www national com Functional Description Continued TSO T3 SET 20 9 VREF 2O LADDER AND DECODER Vin O 1 TRI STATE O MSB Note 13 CS shown twice for clarity Note 14 SAR Successive Approximation Register OUTPUT LATCHES INPUT 1 RESET SHIFT REGISTER 0 BUSY AND QUIESCENT STATE INPUT PROTECTION FOR ALL LOGIC INPUTS TO INTERNAL CIRCUITS START CONVERSION IF RESET 0 SAR LATCH NOTE 2 LE D LATCH 1 Lea x 1fcLk INTR F F LSB O OOOOOOO 1178 1314 15 16 17 18 _ 5Q DS005671 13 FIGURE 4 Block Diagram After the 1 is clocked through the 8 bit shift register which completes the SAR search it appears as the input to the D type latch LATCH 1 As soon as this 1 is output from the shift register the AND gate G2 causes the new digital word to transfer to the TRI STATE output latches When LATCH 1 is subsequently enabled the Q output makes a high to low transition which causes the INTR F F to set An inverting buffer then supplies the INTR input signal Note that this SET control of the INTR F F remains low for 8 of the external clock periods as the internal clocks run at 1 of the frequency of the external clock If the data output is conti
47. ro reference plus 12 LSB where the LSB is cal culated for the desired analog span 1 LSB analog span 256 is applied to pin 6 and the zero reference voltage at pin 7 should then be adjusted to just obtain the 00e to 01 yex code transition The full scale adjustment should then be made with the proper Vin voltage applied by forcing a voltage to the Vin input which is given by VMAx Yun 2 Vin fs adj Vmax 1 5 56 where Vuax the high end of the analog input range and Vuin the low end the offset zero of the analog range Both are ground referenced The Vrer 2 or Voc voltage is then adjusted to provide a code change from FE gy to FFyex This completes the adjustment procedure 2 6 Clocking Option The clock for the A D can be derived from the CPU clock or an external RC can be added to provide self clocking The CLK IN pin 4 makes use of a Schmitt trigger as shown in Figure 8 www national com 22 Functional Description Continued DS005671 17 a 1 1 RC R 10 kQ fcLk FIGURE 8 Self Clocking the A D Heavy capacitive or DC loading of the clock R pin should be avoided as this will disturb normal converter operation Loads less than 50 pF such as driving up to 7 A D converter clock inputs from a single clock R pin of 1 converter are allowed For larger clock line loading a CMOS or low power TTL buffer or PNP input logic should be used to minimize the loading on the clock
48. s decoding is still required to generate the appropriate CS for the con verter lt is important to note that in systems where the A D con verter is 1 of 8 or less I O mapped devices no address decoding circuitry is necessary Each of the 8 address bits to A7 can be directly used as CS inputs for each device 4 1 2 INS8048 Interface The INS8048 interface technique with the ADCO0801 series see Figure 13 is simpler than the 8080A CPU interface There are 24 lines and three test input lines in the 8048 With these extra I O lines available one of the lines bit 0 of port 1 is used as the chip select signal to the A D thus eliminating the use of an external address decoder Bus control signals RD WR and INT of the 8048 are tied directly to the A D The 16 converted data words are stored at on chip RAM locations from 20 to 2F Hex The RD and WR signals are generated by reading from and writing into a dummy address respectively A sample interface program is shown below 27 www national com 508090V r08090V 08090V 208090V 108090V ADC0801 ADC0802 ADC0803 ADC0804 ADC0805 Functional Description Continued INS8048 ANALOG INPUT 0 0801 DS005671 21 FIGURE 13 INS8048 Interface SAMPLE PROGRAM FOR Figure 13 INS8048 INTERFACE 04 10 JMP ORG 04 50 JMP ORG 99 FE ANL 81 MOVX 89 01 START ORL B8 20 MOV B9 FF MOV BA 10 MOV 25FF AGAIN MOV 99 FE ANL 91 MOVX 05 EN
49. subroutine the voltage at V increases or decreases as required to make the differential output voltage equal to zero This is accomplished by ensuring that the voltage at the output of A1 is approximately 2 5V so that a logic 1 5V on 33 www national com 508090V r08090V 08090V 208090V 108090V ADC0801 ADC0802 ADC0803 ADC0804 ADC0805 Functional Description Continued any output of Port B will source current into node Vy thus raising the voltage at V and making the output differential more negative Conversely a logic 0 OV will pull current out of node Vx and decrease the voltage causing the differ ential output to become more positive For the resistor val ues shown Vx can move 12 mV with a resolution of 50 pV which will null the offset error term to 14 LSB of full scale for AVIN 2 Ving 25V FROM OUTPUT PORT C FIGURE 16 Note 26 R2 49 5 R1 Note 27 Switches are LMC13334 CMOS analog switches the ADC0801 It is important that the voltage levels that drive the auto zero resistors be constant Also for symmetry a logic swing of OV to 5V is convenient To achieve this a CMOS buffer is used for the logic output signals of Port B and this CMOS package is powered with a stable 5V source Buffer amplifier A1 is necessary so that it can source or sink the D A output current 5Vpc 4 FROM OUTPUT E PORT BRUFFER az FIGURE 16 A sie O 793k nets ADJ 156M BT 1k 3 16 M
50. tem The total allowable input offset voltage error for this preamp is only 50 uV for 14 LSB error This would obviously require very precise amplifiers The expression for the differ ential output voltage of the preamp is 2 2 Vo Vin Vin 1 Rt US SIGNAL GAIN 2R2 Vos Vos Voss IxRx 1 rm DC ERROR TERM where ly is the current through resistor Rx All of the offset error terms can be cancelled by making tlxRx Vos Voss Vosa This is the principle of this auto zeroing scheme The INS8080A uses the 3 I O ports of an INS8255 Progra mable Peripheral Interface PPI to control the auto zeroing and input data from the ADCO801 as shown in Figure 19 The PPI is programmed for basic operation mode 0 with Port A being an input port and Ports B and C being output ports Two bits of Port C are used to alternately open or close the 2 switches at the input of the preamp Switch SW1 is closed to force the preamp s differential input to be zero during the zeroing subroutine and then opened and SW2 is then closed for conversion of the actual differential input signal Using 2 switches in this manner eliminates concern for the ON resistance of the switches as they must conduct only the input bias current of the input amplifiers Output Port B is used as a successive approximation regis ter by the 8080 and the binary scaled resistors in series with each output bit create a D A converter During the zeroing
51. tents of A D at port ADDRinC register If CARRY is not set increment C register to point 3 to next A D then test next bit in status word Read data from interrupting A D and invert the data Store the data Store A D identifier A D port ADDR Test next bit instatus word Re establishall registers as they were before the interrupt Return to original program 0 005671 39 www national com 508090VW 08090W 08090V 208090V 108090V ADC0801 ADC0802 ADC0803 ADC0804 ADC0805 Physical Dimensions inches millimeters unless otherwise noted 0 496 0 512 12 598 13 005 20 19 18 17 16 15 14 13 12 11 A 0 394 0 419 LEAD 1 IDENT Y 0 010 max 0 254 0 291 0 299 7 391 7 595 0010 0029 0 093 0 104 0 254 0 737 gt 2 362 2 642 8 MAX TYP 0 004 0 012_ ALL LEADS 0 102 0 305 SEATING Ad 7 1 A PLANE 0 004 TT 0 009 0 013 DADA 0 050 0 014 0 020 0 102 0 016 0 050 E TYP 0 229 0 330 ALL LEAD TIPS ze 0 406 1 270 36 A 0 366 0 508 TYP ALL LEADS TYP ALL LEADS TYP 0 008 10 203 M20B REV F SO Package M Order Number ADCO802LCWM or ADCO804LCWM NS Package Number M20B 1 013 1 040 E 0 092 X 0 030 25 73 26 42 2 337 X 0 762 0 032 0 005 MAX DP 0 813 0 127 0 260 0 005 io PIN NO 1 IDENT 260
52. w national com 2 Absolute Maximum Ratings notes 1 2 If Military Aerospace specified devices are required please contact the National Semiconductor Sales Office Distributors for availability and specifications Infrared 15 seconds 220 C Storage Temperature Range 65 C to 4150 C Package Dissipation at T4225 C 875 mW ESD Susceptibility Note 10 800V Supply Voltage Vcc Note 3 Voltage Logic Control Inputs At Other Input and Outputs Lead Temp Soldering 10 seconds Dual In Line Package plastic Dual In Line Package ceramic Surface Mount Package Vapor Phase 60 seconds Electrical Characteristics Tu 1 lt lt 40 CXTA 485 C 40 C lt T lt 85 C 0 C lt T lt 70 C 0 C lt TA lt 70 C d Operating Ratings notes 1 2 0 3V to 18V Temperature Range 0 3V to 0 3 ADCO804LCJ ADC0801 02 03 05LCN 260 C ADC0804LCN 300 C ADC0802 04LCWM Range of 215 C The following specifications apply for 5 Voc Tmn lt Ta lt Tmax and fc 42640 kHz unless otherwise specified 4 5 to 6 3 Voc Parameter Conditions Min Typ Max Units ADC0801 Total Adjusted Error Note 8 With Full Scale Adj LSB ADC0802 Total Unadjusted Error Note 8 LSB ADC0803 Total Adjusted Error Note 8 With Full Scale Adj LSB See Section 2 5 2 ADC0804 Total Unadjusted Error Note 8 Veaer 2 2 500 Voc LSB ADC0805 Total Unadjusted Error Note 8
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NATIONAL SEMICONDUCTOR ADC0801/ADC0802/ADC0803/ADC0804/ADC0805 handbook