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ANALOG DEVICES AD8325 handbook3

1. 34 Vout 6148 MAX GAIN C 31 C 10pF TOKO 6170 0070 1 1 28 T C 20pF z 1 R 750 lt 50 Vin 25 Vee TOKO617DB A0070 22 19 1 100 FREQUENCY MHz TPC 1 Basic Test Circuit TPC 4 AC Response for Various Cap Loads N I x m z gt a 8 E 1 a z 0 42 3 8 o 10 20 30 40 50 60 70 80 0 8 16 24 32 40 48 56 64 72 80 GAIN CONTROL Decimal GAIN CONTROL Decimal TPC 2 Gain Error vs Gain Control TPC 5 Output Referred Noise vs Gain Control 40 0 790 TXEN 0 30 Vin 31dBmV 20 20 MAX GAIN 10 46D o 40 8 0 2 gt o 2 10 23D 2 o 60 20 o 500 MIN GAIN 30 80 40 50 100 0 1 1 10 100 1000 0 1 1 10 100 1000 FREQUENCY MHz FREQUENCY MHz TPC 3 AC Response TPC 6 Isolation in Transmit Disable Mode vs Frequency REV 5 AD8325 6248 MAX GAIN 6148 MAX GAIN DISTORTION dBc 5 15 25 35 45 55 65 FUNDAMENTAL FREQUENCY MHz TPC 7 Second Order Harmonic Distortion vs Frequency for Various Output Levels Vour 62dBmV MAX GAIN Vour 61dBmV MAX GAIN
2. DISTORTION dBc FUNDAMENTAL FREQUENCY MHz TPC 8 Third Order Harmonic Distortion vs Frequency for Various Output Levels 50 Fo 42MHz 55 Vour 61dBmV MAX GAIN HD3 8 60 5 5 65 a o 8 70 75 HD2 80 10 20 30 40 50 60 70 80 GAIN CONTROL Dec Code TPC 9 Harmonic Distortion vs Gain Control 100 180 170 160 e TXEN 0 150 9 TXEN 1 lt LILLI 140 TOKO 61708 40070 a 1 1 0 1pF 130 Zin 1650 750 120 0 1pF GND 110 1 10 FREQUENCY MHz TPC 10 Input Impedance vs Frequency 1 lt a ul a 1 10 FREQUENCY MHz TPC 11 Output Impedance vs Frequency 10 CHPWR 12 3dBm 20 ACP UP 54 024 ACP LOW 53 79dB 30 40 50 60 70 80 100 co C11 eti 110 CENTER 21MHz 75kHz DIV SPAN 750kHz TPC 12 Adjacent Channel Power REV A AD8325 APPLICATIONS General Application The AD8325 is primarily intended for use as the upstream power amplifier PA in DOCSIS Data Over Cable Service Interface Specifications certified cable modems and CATV set top boxes Upstream data is modulated in QPSK or QAM format and done with DSP or a dedicated QPSK QAM
3. 2 steel internal tooth lockwasher ADS 30 5 2 P1 hardware 2 2 STAINLESS STEEL hex machine nut ADS 30 7 6 P1 hardware NOTES PULSE Diplexer part T 2 DO NOT INSTAL 3 0 R12 SMA s TXEN CLK L SDATA 28 Lead Thin Shrink Small Outline Package TSSOP RU 28 Hz P13 TP22 OUTLINE DIMENSIONS Dimensions shown in millimeters 7 elo 8 0 65 Bse 1 20 MAX 0 15 3 0 30 COPLANARITY 0 19 211 SEATING 0 10 PLANE 6 40 BSC 0 75 09 0 60 0 45 COMPLIANT TO JEDEC STANDARDS 153 Revision History Location Page 6 05 Data Sheet Changed from REV 0 to REV Changes ORDERING GUIDE 4 16 REV A A 02439 0 6 05
4. 75 output impedance This eliminates the need for external matching resistors needed in typical video or video filter ter mination requirements SPI Programming and Gain Adjustment Gain programming of the AD8325 is accomplished using a serial peripheral interface SPI and three digital control lines DATEN SDATA and CLK To change the gain eight bits of data are streamed into the serial shift register through the SDATA port The SDATA load sequence begins with a falling edge on the DATEN pin thus activating the CLK line With the line activated data on the SDATA line is clocked into the serial shift register Most Significant Bit MSB first on the rising edge of each CLK pulse Because only a 7 bit shift register is used the MSB of the 8 bit word is a don t care bit and is shifted out of the register on the eighth clock pulse A rising edge on the DATEN line latches the contents of the shift register into the attenuator core resulting in a well controlled change in the output signal level The serial interface timing for the AD8325 is shown in Figures 2 and 3 The programmable gain range of the AD8325 is 29 45 dB to 30 dB and scales 0 7526 dB per least significant bit LSB Because the AD8325 was characterized REV A with a transformer the stated gain values already take into account the losses associated with the transformer The gain transfer function is as follows Ay 30 0 dB 0 7526 dB 79 CODE fo
5. X M2 gt RM2 e Enable SLEEP Mode Figure 8 Screen Display of Windows Based Control Software REV A 11 AD8325 10 gt gt gt 821 71620 4 22 al TPIT 23 Ais Onn 13 um dic ello 1981 R TP1 a CLK 12 PWR GND 12 p22 0 4 mu 0 ANALOG DEVICES WILMINGTON MFG AD8325 EVAL BOARD 152 Q TP12 E E 001758 Figure 9 Evaluation Board Assembly Component Side REV A AD8325 e e i J 88 TTITIIII I o e LI E O B B Mt La be r gt a r lt lt Figure 10 Evaluation Board Layout Component Side REV A 13 AD8325 2 gt gt lt gt lt gt lt Figure 11 Evaluation Board Solder Side 14 REV A AD8325 ele ING TIVLSNI LON OG ING o ING 00 2 0 aayo ING 0241 Figure 12 Evaluation Board Schematic uMdofni 32 0 0 81 ING 91H ING toyol 1013 93 184 5 184 5 i ese 1 1 N lt a 7 15 REV AD8325 EVALUATION BOARD BILL
6. should also be ensure proper grounding of all internal nodes The differential input and output traces should be kept as short and symmetrical as possible In addition the input and output traces should be kept far apart in order to minimize coupling crosstalk through the board Following these guidelines will improve the overall performance of the AD8325 in all applications Initial Power Up When the 5 V supply is first applied to the Vcc pins of the AD8325 the gain setting of the amplifier is indeterminate Therefore as power is first applied to the amplifier the TXEN pin should be held low Logic 0 thus preventing forward signal transmission After power has been applied to the amplifier the gain can be set to the desired level by following the procedure in the SPI Programming and Gain Adjustment section The TXEN pin can then be brought from Logic 0 to 1 enabling forward signal transmission at the desired gain level Between Burst Operation The asynchronous TXEN pin is used to place the AD8325 into Between Burst mode while maintaining a differential output impedance of 75 Q Applying a Logic 0 to the TXEN pin acti vates the on chip reverse amplifier providing a 74 reduction in consumed power The supply current is reduced from approxi mately 133 mA to approximately 35 mA In this mode of operation between burst noise is minimized and the amplifier can no longer transmit in the upstream direction In addition to th
7. 0 2560 Ksywsec Noise and DOCSIS At minimum gain the AD8325 s output noise spectral density is 10 nV VHz measured at 10 MHz DOCSIS Table 4 8 Spurious Emissions in 5 MHz to 42 MHz specifies the output noise for various symbol rates The calculated noise power in dBmV for 160 18 20 log ez x160 kHz H60 2 48 dBmV Comparing the computed noise power of 48 dBmV to the 8 dBmV signal yields 56 dBc which meets the required level of 53 dBc set forth in DOCSIS Table 4 8 As the AD8325 s gain is increased from this minimum value the output signal increases at a faster rate than the noise resulting in a signal to noise ratio that improves with gain In transmit disable mode the output noise spectral density computed over 160 Ksymsgconp 18 1 0 nV VHz or 68 dBmV REV A ADJACENT CHANNEL SYMBOL RATE Overshoot on PC Printer Ports The data lines on some PC parallel printer ports have excessive overshoot that may cause communications problems when pre sented to the CLK pin of the AD8325 TP6 on the evaluation board The evaluation board was designed to accommodate a series resistor and shunt capacitor R2 and C5 to filter the CLK signal if required Transformer and Diplexer A 1 1 transformer is needed to couple the differential outputs of the AD8325 to the cable while maintaining a proper impedance match The specified transformer is avai
8. 0 Differential Input Figure 7 Option 2 If a differential signal source is available it may be applied directly to both the and Vw input ports of the evaluation board In this case 0 Oi chip resistors should be installed at locations R16 through R19 and R14 R15 and R20 should be left open The equation at the end of the preceding paragraph can be used to compute the correct value for R13 for any desired differential input impedance For differential input impedances of 75 Of or 150 Q the value of R13 will be 78 7 165 respectively DIFF T1 DIFFERENTIAL INPUT OPTION 1 Vint R13 AD8325 1 DIFFERENTIAL INPUT OPTION 2 Figure 7 Differential Input Termination Options 10 Installing the Visual Basic Control Software To install the CABDRIVE_25 evaluation board control soft ware close all Windows applications and then run SETUP EXE located on Disk 1 of the AD8325 Evaluation Software Follow the on screen instructions and insert Disk 2 when prompted to do so Enter the path of the directory into which the software will be installed and select the button in the upper left corner to complete the installation Running the Software To invoke the control software go to START gt PROGRAMS gt CABDRIVE 205 or select the AD8325 EXE icon from the directory containing the software Controlling the Gain Attenuation of the AD8325 The slide bar controls the AD8325 s g
9. ANALOG DEVICES 9 V CATV Line Driver Fine Step Output Power Control AD8325 FEATURES Supports DOCSIS Standard for Reverse Path Transmission Gain Programmable in 0 75 dB Steps Over a 59 45 dB Range Low Distortion at 61 dBmV Output 57 dBc SFDR at 21 MHz 55 dBc SFDR at 42 MHz Output Noise Level 48 dBmV 160 kHz Maintains 75 Output Impedance Transmit Enable and Transmit Disable Modes Upper Bandwidth 100 MHz Full Gain Range 5 V Supply Operation Supports SPI Interfaces APPLICATIONS Gain Programmable Line Driver DOCSIS High Speed Data Modems Interactive Cable Set Top Boxes PC Plug in Cable Modems General Purpose Digitally Controlled Variable Gain Block The 40832945 igitially c ga C fier optimized for coaxial line driving applications such as cable modems that are designed to the MCNS DOCSIS upstream standard An 8 bit serial word determines the desired output gain over a 59 45 dB range resulting in gain changes of 0 7526 dB LSB The AD8325 comprises a digitally controlled variable attenuator of 0 dB to 59 45 dB which is preceded by a low noise fixed gain buffer and is followed by a low distortion high power ampli fier The AD8325 accepts a differential or single ended input signal The output is specified for driving a 75 4 such as coaxial cable Distortion performance 57 dBc is achieved with an output level up to 61 dBmV at 21 MHz bandwidth A key performance and cost advantage of the AD8325
10. MA 02062 9106 U S A Tel 781 329 4700 www analog com Fax 781 461 3113 2005 Analog Devices Inc All rights reserved 106325 5 0 NS 25 C Vs 5 V 75 Vy differential 31 dBmV Voy measured through 1 1 transformer with an insertion loss of 0 5 dB 10 MHz unless otherwise noted Parameter Conditions Min Typ Max Unit INPUT CHARACTERISTICS Specified AC Voltage Output 61 dBmV Max Gain 31 dBmV Noise Figure Max Gain f 10 MHz 13 8 dB Input Resistance Single Ended Input 800 Differential Input 1600 9 Input Capacitance 2 pF GAIN CONTROL INTERFACE Gain Range 58 45 59 45 60 45 dB Maximum Gain Gain Code 79 Dec 29 2 30 0 30 8 dB Minimum Gain Gain Code 0 Dec 30 25 29 45 28 65 dB Gain Scaling Factor 0 7526 dB LSB OUTPUT CHARACTERISTICS Bandwidth 3 dB All Gain Codes 100 MHz Bandwidth Roll Off f 65 MHz 1 6 dB Bandwidth Peaking f 65 MHz 0 dB Output Noise Spectral Density Max Gain f 10 MHz 33 dBmV 160 kHz Min Gain f 10 MHz 48 dBmV 160 kHz Transmit Disable Mode f 10 MHz 68 dBmV in 160 kHz 1 dB Compression Point Max Gain f 10 MHz 18 5 dBm Differential Output Impedance Transmit Enable and Transmit Disable Modes 75 520 Q0 OVERALL PERFORMANCE Second Order Harmonic Distortion 7 61 Gain 70 dBc 6f dBmV i 7 dBc 6UdBmV 0 dBc Third Order m rti Az 61 dBc f 42 MHz Vour 61 dBmV M
11. OF MATERIALS AD8325 Evaluation Board Rev Single Ended to Differential Input Revised February 21 2001 Qty Description Vendor Ref Desc 10 25 V D size tantalum chip capacitor ADS 4 7 2 C12 1 000 pF 50 V 1206 ceramic chip capacitor ADS 4 5 20 C5 0 1 uF 50 1206 size ceramic chip capacitor ADS 4 5 18 C15 C16 0 1 25 0603 size ceramic chip capacitor ADS 4 12 8 C1 C3 7 11 1 0 5 1 8 W 1206 size chip resistor ADS 3 18 88 R1 R3 R8 R14 R15 R20 51 1 01 1 8 W 1206 size chip resistor ADS 3 18 99 R13 Yellow Test Point ADS 12 18 32 TP23 TP24 White Test Point ADS 12 18 42 1 8 Red Test Point ADS 12 18 43 TP9 Black Test Point ADS 12 18 44 10 12 GND NNN FN O0 b2O nf KF ON Centronics type 36 pin Right Angle Connector ADS 12 3 50 Pl Terminal Block 2 Pos Green ED1973 ND ADS 12 19 13 1 SMA End launch Jack JOHNSON 142 0701 801 ADS 12 1 31 Vint CABLE 0 1 1 Transformer TOKO 617DB A0070 TOKO T1 T3 PULSE Diplexer PULSE 72 AD8325 TSSOP UPSTREAM Cable Driver ADI AD8325XRU_ 71 AD8325 REV B Evaluation PC board NC Evaluation PC board 84 40 1 4 inch STAINLESS panhead machine screw ADS 30 1 1 84 40 13 4 inch long aluminum round stand off ADS 30 16 3 2 56 8 8 inch STAINLESS panhead machine screw ADS 30 1 17 P1 hardware 2 steel flat washer ADS 30 6 6 P1 hardware
12. ain attenuation which is displayed in dB and in V V The gain scales at 0 7526 dB per LSB with the valid codes being from decimal 0 to 79 The gain code i e position of the slide bar is displayed in decimal binary and hexadecimal see Figure 8 Transmit Enable Transmit Disable and Sleep The Transmit Enable and Transmit Disable buttons select the mode of operation of the AD8325 by controlling the logic level on the asynchronous TXEN pin The Transmit Enable button applies a Logic 1 to the TXEN pin putting the AD8325 in forward transmit mode The Transmit Disable button applies a Logic 0 to the TXEN pin selecting reverse mode where the Transrai called Pogyer U 2 0 chronous SLEEP pin putting the AD8325 into SLEEP mode Memory Section The MEMORY section of the software provides a convenient way to alternate between two gain settings The gt 1 but ton stores the current value of the gain slide bar into memory while the RM1 button recalls the stored value returning the gain slide bar to that level The X gt M2 and RM2 buttons work in the same manner REV AD8325 EVALUATION BOARD FEATURES AND OPERATION AD8325 08325 Upstream Cable Driver Evaluation Board Controller Rev 2 AIN Transmit Disable 50 00 dB Transmit Enable 51 62 v v T9 decimal code Memory ww BDIT coni AE ar Hex code
13. ax Gain 55 dBc f 65 MHz Vour 61 dBmV Max Gain 54 dBc Adjacent Channel Power Adjacent Channel Width Transmit Channel 53 8 dBc Width 160 Gain Linearity Error f 10 MHz Code to Code 0 3 dB Output Settling Due to Gain Change Min to Max Gain 60 ns Due to Input Change Max Gain 31 dBmV 30 ns Isolation in Transmit Disable Mode Max Gain TXEN 0 V f 42 MHz 33 dBc Vin 31 dBmV POWER CONTROL Transmit Enable Settling Time Toy Max Gain Vy 0 V 300 ns Transmit Disable Settling Time Torr Max Gain Vw 0 V 40 ns Between Burst Transients Equivalent Output 31 dBmV 3 mV Equivalent Output 61 dBmV 50 mV p p POWER SUPPLY Operating Range 4 75 5 5 25 Quiescent Current Transmit Enable Mode TXEN 1 123 133 140 mA Transmit Disable Mode TXEN 0 30 35 10 mA Sleep Mode 2 4 7 mA OPERATING TEMPERATURE 40 85 RANGE NOTES 617DB A0070 used for above specifications MACOM ETC 1 IT 15 be substituted Between Burst Transients measured at the output of a 42 MHz diplexer Specifications subject to change without notice REV AD8325 LOGIC INPUTS TTL CMOS Compatible Logic DATEN 50 SLEEP Vec 5 V Full Temperature Range Parameter Min Typ Max Unit Logic 1 Voltage 2 1 5 0 Logic 0 Voltage 0 0 8 Logic 1 Current Vig 5 V CLK SDATA DATEN 0 20 nA Logi
14. c 0 Current 0 V CLK SDATA DATEN 600 100 nA Logic 1 Current 5 TXEN 50 190 uA Logic 0 Current Vwi 0 V TXEN 250 30 uA Logic 1 Current 5 V SLEEP 50 190 uA Logic 0 Current Vwi 0 V SLEEP 250 30 uA TIMING REQUIREMENTS Full Temperature Range Vec 5 V T 4 ns 8 MHz unless otherwise noted Parameter Min Typ Max Unit Clock Pulsewidth 16 0 ns Clock Period 32 0 ns Setup Time SDATA vs Clock Tps 5 0 ns Setup Time DATEN vs Clock 15 0 ns Hold Time SDATA vs Clock 5 0 ns Hold Time DATEN vs Clock 3 0 ns Input Rise and Fall Times SDATA DATEN Clock Tp Tp 10 ns CLK JU 8 CLOCK DATEN CYCLES Mn TRANSFER G1 GAIN TRANSFER G2 TXEN ANALOG OUTPUT SIGNAL AMPLITUDE p p VALID DATA WORD G2 Figure 2 Serial Interface Timing SDATA MSB VALID DATA BIT MSB 2 CLK Figure 3 SDATA Timing REV A AD8325 ABSOLUTE MAXIMUM RATINGS PIN CONFIGURATION Supply Voltage Pins 5 9 10 19 20 29 21 ias e uet ens 6V Input Voltages 8 295 26 0 5 V Pins 1 2 2 0 7 RESP 0 8 V to 5 5 Internal Power Dissipation TSSOLD 0 9 W Operating Temperature Range 40 to 85 C Storage Temperature Range 65 to 150 C Lead Temperature Soldering 60 seconds 300 C Stresses ab
15. e TXEN pin the AD8325 also incorporates an asynchronous SLEEP pin which may be used to place the amplifier in a high output impedance state and further reduce the supply current to ximately 4 mA Logi 0 ASLEEP places the ifie A ning into or out of SLEEP m4 amplifte ef ig at the output compliant Between Burst operation for DOCSIS AD8325 TSSOP GND11 Vin Zin 1500 1650 4 617DB A0070 DIPLEXER 21 752 Figure 6 Typical Applications Circuit REV AD8325 Distortion Adjacent Channel Power and DOCSIS In order to deliver 58 dBmV of high fidelity output power required by DOCSIS the PA should be able to deliver about 61 dBmV in order to make up for losses associated with the transformer and diplexer TPC 7 and TPC 8 show the AD8325 second and third harmonic distortion performance versus fundamental frequency for various output power levels These figures are useful for determining the inband harmonic levels from 5 MHz to 65 MHz Harmonics higher in frequency will be sharply attenu ated by the low pass filter function of the diplexer Another measure of signal integrity is adjacent channel power or ACP DOCSIS section 4 2 9 1 1 states Spurious emissions from a transmitted carrier may occur in an adjacent channel that could be occupied by a carrier of the same or different symbol rates TPC 12 shows the measured ACP fo
16. ition inhibits the data latch holds the previous gain state and simultaneously enables the register for serial data load 2 SDATA Serial Data Input This digital input allows for an 8 bit serial gain word to be loaded into the internal register with the MSB Most Significant Bit first 3 CLK Clock Input The clock port controls the serial attenuator data transfer rate to the 8 bit master slave register A Logic 0 to 1 transition latches the data bit and a 1 to 0 transfers the data bit to the slave This requires the input serial data word to be valid at or before this clock transition 4 8 11 12 GND Common External Ground Reference 13 16 17 18 22 24 28 5 9 10 19 Common Positive External Supply Voltage A 0 1 uF capacitor must decouple each pin 20 23 27 6 TXEN Logic 0 disables transmission Logic 1 enables transmission 7 SLEEP Low Power Sleep Mode Logic 0 enables Sleep mode where goes to 400 and supply current is reduced to 4 mA Logic 1 enables normal operation 14 OUT Negative Output Signal 15 OUT Positive Output Signal 21 BYP Internal Bypass This pin must be externally ac coupled 0 1 UF cap 25 Noninverting Input DC biased to approximately 2 Should be ac coupled with a 0 1 uF capacitor 26 Inverting Input DC biased to approximately 2 Should be ac coupled with a 0 1 capacitor 4 REV A Typical Performance Characteristics AD8325
17. lable from TOKO Part 617DB A0070 however MA COM part ETC 1 1T 15 can also be used The evaluation board is equipped with the TOKO transformer but is also designed to accept the MA COM transformer The PULSE diplexer included on the evaluation board provides a high order low pass filter function typically used in the upstream path The ability of the PULSE diplexer to achieve DOCSIS compliance is neither expressed nor implied by Analog Devices Inc Data on the diplexer can be obtained from PULSE AD8325 Differential Inputs The AD8325 EVAL evaluation board may be driven with a differential signal in one of two ways A transformer may be used to convert a single ended signal to differential or a differ ential signal source may be used Figure 7 and the following paragraphs describe each of these methods Single Ended to Differential Input Figure 7 Option 1 A TOKO 617DB A0070 1 1 transformer is preinstalled in the location of the evaluation board Install 0 chip resistors at R14 R15 and R20 and leave R16 through R19 open For 50 differential input impedance install a 51 1 resistor at R13 For 75 differential input impedance use a 78 7 resistor In this configuration the input signal must be applied to the Vin port of the evaluation board For input impedances other than 50 75 Q the correct value for can be calculated using the following equation Desired Input Impedance 13 160
18. modula tor The amplifier receives its input signal from the QPSK QAM modulator or from a DAC In either case the signal must be low pass filtered before being applied to the amplifier Because the distance from the cable modem to the central office will vary with each subscriber the AD8325 must be capable of varying its output power by applying gain or attenuation to ensure that all signals arriving at the central office are of the same amplitude The upstream signal path contains components such as a trans former and diplexer that will result in some amount of power loss Therefore the amplifier must be capable of providing enough power into a 75 Qiload to overcome these losses without sacri ficing the integrity of the output signal Operational Description The AD8325 is composed of four analog functions in the power up or forward mode The input amplifier preamp can be used single endedly or differentially If the input is used in the differ ential configuration it is imperative that the input signals are 180 degrees out of phase and of equal amplitudes This will ensure proper gain accuracy and harmonic performance The preamp preamp and vernier gain blocks are differential to improve the PSRR and linearity A differential current is fed from the DAC into the output stage which amplifies these currents to the appropriate levels necessary to drive a 75 Qload The output stage utilizes negative feedback to implement a differential
19. ntial output pins and are also biased to a dc level of approximately 2 Therefore the outputs should be ac coupled before being applied to the load This is accomplished with a 1 1 transformer as seen in the typical applications circuit of Figure 6 The transformer also converts the output signal from differential to single ended while maintaining a proper impedance match to the line The differential output impedance of the AD8325 is internally maintained at 75 regardless of whether the amplifier is in transmit enable mode TXEN 1 or transmit disable mode TXEN 0 If the output signal is being evaluated on standard 50 test equipment 75 50 QU pad must be used to provide the test circuit with the correct impedance match Power Supply Decoupling Grounding and Layout Considerations Careful attention to printed circuit board layout details will prevent problems due to associated board parasitics Proper RF design techniques are mandatory The 5 V supply power should be delivered to each of the Vcc pins via a low impedance power bus to ensure that each pin is at the same potential The power bus should be decoupled to ground with a 10 uF tantalum capacitor located in close proximity to the AD8325 In addition to the 10 capacitor each pin should be individually decoupled to ground with a 0 1 ceramic chip capacitor located as close to the pin as possible The pin labeled BYP Pin 21
20. ove those listed under Absolute Maximum Ratings may cause perma nent damage to the device This is a stress rating only functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied Exposure to absolute maximum rating conditions for extended periods may affect device reliability ORDERING GUIDE Model Temperature Range Package Description Oya Package Option AD8325ARU 40 to 85 C 28 Lead TSSOP 67 7 C W RU 28 AD8325ARU REEL 40 to 85 C 28 Lead TSSOP 67 7 C W RU 28 AD8325ARUZ 40 to 85 C 28 Lead TSSOP 67 7 C W RU 28 AD8325ARUZ REEI 40 C to 85 C 28 Lead TSSOP 67 7 C W RU 28 AD8325 EVAL Evaluation Board lThermal Resistance measured on SEMI standard 4 layer board 7 Pb free part CAUTION ESD electrostatic discharge sensitive ING accumulate omth est ej 222225 S the AD8325 SD devices subject d to gy el ctro d MT ESD SENSITIVE DEVICE recommended to avoid performance degradation or loss of functionality PIN FUNCTION DESCRIPTIONS Pin No Mnemonic Description 1 DATEN Data Enable Low Input This port controls the 8 bit parallel data latch and shift register A Logic 0 to 1 transition transfers the latched data to the attenuator core updates the gain and simulta neously inhibits serial data transfer into the register A 1 to 0 trans
21. r 0 CODE x 1 9 where Ay is the gain in dB and CODE is the decimal equivalent of the 8 bit word Valid gain codes are from 0 to 79 Figure 4 shows the gain char acteristics of the AD8325 for all possible values in an 8 bit word Note that maximum gain is achieved at Code 79 From Code 80 through 127 the 5 25 dB of attenuation from the ver nier stage is being applied over every eight codes resulting in the sawtooth characteristic at the top of the gain range Because the eighth bit is a don t care bit the characteristic for codes 0 through 127 repeats from Codes 128 through 255 30 25 20 15 10 GAIN dB Figure 4 Gain vs Gain Code Input Bias Impedance and Termination Vi and inputs have a dc bias level of approximately Vcc 2 therefore the input signal should be ac coupled The differential input impedance is approximately 1600 O while the single ended input impedance is 800 Q If the AD8325 is being operated in a single ended input configuration with a desired input impedance of 75 Q the and inputs should be terminated as shown in Figure 5 If an input impedance other than 75 is desired the values of and R2 in Figure 5 be calculated using the following equations Zm UR1 800 R2 MZ yw RI1 Zin 750 R1 82 50 B 2 Figure 5 Single Ended Input Termination AD8325 Output Bias Impedance and Termination The differe
22. r a 16 QAM 61 dBmV signal taken at the output of the AD8325 evaluation board see Figure 12 for evaluation board schematic The transmit channel width and adjacent channel width in TPC 12 correspond to symbol rates of 160 Table I shows the ACP results for the AD8325 for all conditions in DOCSIS Table 4 7 Adjacent Channel Spurious Emissions Evaluation Board Features and Operation The AD8325 evaluation board Part AD8325 EVAL and control software can be used to control the AD8325 upstream cable driver via the parallel port of a PC A standard printer cable connected between the parallel port and the evaluation board is used to feed all the necessary data to the AD8325 by means of the Windows based Microsoft Visual Basic control software This package provides a means of evaluating the amplifier by providing a convenient way to program the gain attenuation as well as offering easy control of the amplifiers asynchronous TXEN and SLEEP pins With this evaluation kit the AD8325 can be evaluated with either a single ended or differ ential input configuration The amplifier can also be evaluated with or without the PULSE diplexer in the output signal path To remove the diplexer from the signal path leave R6 and R8 open and install a 0 CX chip resistor at R7 A schematic of the evalua tion board is provided in Figure 12 Table I ACP Performance for All DOCSIS Conditions All Values in dBc TRANSMIT 128
23. results from the ability to maintain a constant 75 Q output impedance during Transmit Enable and Transmit Disable conditions In addition this device has a sleep mode function that reduces the quiescent current to 4mA The AD8325 is packaged in a low cost 28 lead TSSOP operates from a single 5 V supply and has an operational temperature range of 40 C to 85 C REV A Information furnished by Analog Devices is believed to be accurate and reliable However no responsibility is assumed by Analog Devices for its use nor for any infringements of patents or other rights of third parties that may result from its use No license is granted by implication or otherwise under any patent or patent rights of Analog Devices Trademarks and registered trademarks are the property of their respective owners FUNCTIONAL BLOCK DIAGRAM 7 PINS BYP AD8325 Vour ATTENUATION POWER CORE AMP Vour 8 DECODE Zin SINGLE 8000 8 POWER DOWN 8 SHIFT ai REGISTER O DATEN DATA CLK 11 5 TXEN SLEEP 50 Vout 62dBmV MAX GAIN 52 61dBmv MAX GAIN 54 m 5 1 2 56 o 58 o a 60 Vout 60dBmV GAIN 62 59dBmV MAX GAIN 64 5 15 25 35 45 55 65 FUNDAMENTAL FREQUENCY MHz Figure 1 Worst Harmonic Distortion vs Gain Control One Technology Way P O Box 9106 Norwood

ANALOG DEVICES AD8325 handbook3

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