NEC PD17P203A 17P204 4-BIT SINGLE-CHIP MICROCONTROLLER WITH STATIC RAM AND 3-CHANNEL TIMER FOR INFRARED REMOTE CONTROLLER
Contents
1. uPD17P203A 17P204 AC PROGRAMMING CHARACTERISTICS 25 6 00 25 VPP 12 5 0 3 V Conditions Address Setup TimeNete 2 ys MDOJ MD1 Setup Time vs Data Setup Time vs MDOJ Address Hold TimeNete 2 ys Data Hold Time vs MDOT ton MDO 7 5 Data Output Float Delay Time tor Ver Setup Time vs tvps Setup Time vs tvps Initial Program Pulse Width tew Additional Program Pulse Width topw Setup Time vs MD1T twos MDO Data Output Delay Time tov MDO MD1 Vi MD1 Hold Time vs MD1 Recovery Time vs MDOJ tir gt 50 us Program Counter Reset Time tPcR CLK Input High Low Level Width fx Initial Mode Set Time t Setup Time vs MD1 Hold Time vs MD14 MD3 Setup Time vs MDOJ When data is read from program memory AddressNete 2 _ Data Output Delay Time When data is read from program memory AddressNote 2 Data Output Hold Time When data is read from program memory Hold Time vs When data is read from program memory Data Output Float Delay Time When data is read from program memory Reset Setup Time Notes 1 These symbols are the corresponding uPD27C256 maintenance product symbols 2 The internal2. 35 De 6 53335533 34 05 PP FW WwW GNDo 7 DURER 33 GND4 8 338888 32 Da BS 9 amp 31 MDs 10 30 29 MD 28 27 GNDs 24 25 26 1 O O0 0 0 00 0 0 a d 9 Fa z z Z 0 gt 4 5 Caution Those enclosed in parentheses indicate the processing of the pins not used in PROM programming mode L Ground these pins through a resistor 470 Open Do not connect anything to these pins CLK PROM clock input 0 mode selection 00 07 PROM data Power supply GND GNDo GNDs Ground Program power supply BLOCK DIAGRAM POAo POA POA2 POBo MDO POB i MD1 POB2 MD2 POB3 MD3 POCo DA 05 POC2 D6 POC3 D7 PODo DO POD D1 002 02 PODs D3 P1Ao P1As OOOO OOOO OOOO 1 PTB TM1OUT P1B3 TM2OUT P1OySCK 1 50 O H 1 2 51 1 uPD17P203A 17P204 RAM 336 x 4 bits One Time PROM 4096 x 16 bits uPD17P203A 7936 x 16 bits uPD17P204 Program Counter Stack 5 x 12 bits uPD17P203A 7 x 18 bits uPD17P204 Power GNDo Supply O GND Circuit GND2 Remote Control Re
3. Main clock oscillation frequency Subclock oscillation frequency CAPACITANCE Ta 25 C 0 V Tc wn Input capacitance 18 Cin INT RESET pins pF Other than INT RESET pins 10 DC CHARACTERISTICS VxRAM V 20 to 75 fx 4 MHz 32 kHz High Level Input Voltage Conditions RESET INT pins uPD17P203A 17 204 Other than RESET INT pins Low Level Input Voltage RESET INT pins 2 Other than RESET INT pins High Level Input Current lin2 TMOIN lina lins P1A P1C Vin 23V Low Level Input Current lii INT lita TMOIN liL w o pull up resistors 0 w pull up resistors liLe POA POB Vi 20V w o pull up resistors 0 V w pull up resistors li POC POD P1A P1C 20V w o pull up resistors 0 V w pull up resistors High Level Output Current loni POA POB 2 7 2 7 lona LED 2 7 lous
4. CMPOUT 2 7 V Low Level Output Current lot POA POB P1C 0 3 V 2 0 3 V 0 3 V 0 3 V 1015 LEDWDOUT 0 3 V love CMPOUT 0 3 V Vrer Output Voltage VREF C 0 1 uF R 82 Supply Current 1501 1502 mode Generates both XT and X Generates XT only 1504 HALT mode Generates both XT and X Generates XT only XRAM Supply Current IxRAM1 Operation mode Vxram 3 V IxRAM2 HALT mode Vxram 3 V 25 19 20 XRAM LOW SUPPLY VOLTAGE DATA HOLDING CHARACTERISTICS Ta 20 to 75 C VXRAMDR Data Holding Voltage VXRAMDR DC PROGRAMMING CHARACTERISTICS 25 6 00 25 Ver 12 5 0 3 High Level Input Voltage Conditions Other than CLK uPD17P203A 17 204 CLK Low Level Input Voltage Other than CLK CLK Input Leakage Current Vin Vit or High Level Output Voltage lou 1 mA Low Level Output Voltage lo 1 6 mA Voo Supply Current Supply Current Cautions 1 Vrp must not exceed 13 5 V including the overshoot 2 Apply Voo before Vpr and disconnect it after Vpr
5. low RESET INT RESET INT 13 uPD17P203A 17 204 2 DIFFERENCES BETWEEN MASK ROM PRODUCTS AND ONE TIME PROM PRODUCTS The uPD17P203A and uPD17203 are identical in the CPU functions and internal hardware peripherals except for that the 17 204 is provided with a PROM which can be written by the user in the place of the mask ROM of the uPD17204 The only differences between the two microcontrollers are therefore the program memory and mask option The relation between the uPD17P204 and uPD17204 is the same as the relation between the uPD17P203A and 17203 Note thatthe uPD17P203A and uPD17P204is slightly different from the 1720 and 17204 respectively in electrical characteristics such as supply voltage and supply current The following shows the differences between 17 20 and uPD17203A uPD17P204 and uPD17204 For the CPU functions and internal hardware peripherals of the uPD17203A 17 204 therefore refer to the Data Sheet of the wPD17203A 17204 adc EL 17 203 001 uPD17P203A 002 uPD17P203A 003 1 1720 One time PROM Mask ROM Program memory 0000H 0FFFH 0000H 0FFFH 4096x16 bits 4096x16 bits Pull up resistor of RESET pin Not provided Pull up resistor of POA and POB pins Not provided On request Provided Provided Main clock oscillator circuit mask option Subclock oscillator circuit Not provided Provide
6. APPENDIX MICROCONTROLLERS FOR LEARNING REMOTE CONTROLLER 25 APPENDIX B DEVELOPMENT 0 85 0202 nnne nnne nene 26 1 PIN FUNCTIONS 1 1 NORMAL OPERATION MODE Function Outputs NRZ signal in synchronization with infrared remote controller signal Remains low while remote control carrier is output uPD17P203A 17P204 Output Format CMOS push pull 1 2 At Reset High level output Outputs active high infrared remote control signal CMOS push pull Low level output Supplies power to XRAM Positive power Connect 4 MHz ceramic oscillator for main clock oscillation Oscillation stop Ground Inputs low active system reset signal While this pin remains low level oscillation of main clock stops Pull up resistor can also be connected by mask option uPD17P203A 001 and wPD17P204 001 only Outputs signal for detecting overrun This pin outputs a low level when an overflow in the watchdog timer or an overflow underflow in the stack is detected Connect this pin to the RESET pin N ch open drain High impedance Connect 32 kHz crystal oscillator across these pins When option not using subclock is selected main clock is divided and is supplied to watch timer Oscillation Outputs signal from voltage regulator for subclock oscillator circuit Connect external 0 1 capacitor GNDs Ground GND Ground of o
7. PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note Strong electric field when exposed to a MOS device can cause destruction of the gate oxide and ultimately degrade the device operation Steps must be taken to stop generation of static electricity as much as possible and quickly dissipate it once when it has occurred Environmental control must be adequate When it is dry humidifier should be used It is recommended to avoid using insulators that easily build static electricity Semiconductor devices must be stored and transported in an anti static container static shielding bag or conductive material All test and measurement tools including work bench and floor should be grounded The operator should be grounded using wrist strap Semiconductor devices must not be touched with bare hands Similar precautions need to be taken for PW boards with semiconductor devices on it 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note No connection for CMOS device inputs be cause of malfunction If no connection is provided to the input pins it is possible that an internal input level may be generated due to noise etc hence causing malfunction CMOS devices behave differently than Bipolar or NMOS devices Inputlevels of CMOS devices must be fixed high or low by using a pull up or pull down circuitry Each unused pin should be connected to or GND with a resistor if itis considered to have a possibility of being an output pin handlin
8. address is incremented by 1 at the third falling edge of CLK with four clocks constituting as one cycle The internal address is not connected to any pin 21 uPD17P203A 17 204 PROGRAM MEMORY WRITE TIMING Hi Z Hi Z Hid Hi Z Hi Z poor H eae Gar P Qc tos tov tor topw 1 tRES DO D1 D2 5 03 22 uPD17P203A 17P204 5 PACKAGE DRAWINGS 52 PIN PLASTIC C114 A B detail of lead end 22 i i ITEM MILLIMETERS INCHES Each lead centerline is located within 0 20 mm 0 008 inch of A 17 2 0 2 0 677 0 008 its true position T P at maximum material condition B 14 040 2 0 551 0 009 0 009 14 0 0 2 0 551 5 508 D 17 2 0 2 0 677 0 008 1 0 0 039 1 0 0 039 0 004 H 0 40 0 10 0 016 5 005 0 20 0 008 J 1 0 0 039 K 1 6 0 2 0 063 0 008 0 009 L 0 8 0 2 0 031 5 008 0 10 0 004 M 0 154505 0 0067 0 003 0 10 0 004 2 7 0 106 0 125 0 075 0 005 0 003 5 5 5 5 3 0 0 119 S52GC 100 3BH 2 23 uPD17P203A 17 204 6 RECOMMENDED SOLDERING CONDITIONS Soldering must be performed under the following conditions For details of recommended cond
9. device Note number of days the device can be stored after the dry pack was opened under storage conditions of 25 C and 65 RH max Caution not use two or more soldering methods in combination except the pin partial heating method 24 uPD17P203A 17P204 APPENDIX A MICROCONTROLLERS FOR LEARNING REMOTE CONTROLLER ROM Capacity 4096 x 16 bits mask ROM 4096 x 16 bits one time PROM 7936 x 16 bits mask ROM 7936 x 16 bits one time PROM RAM Capacity 336 x 4 bits Static RAM Capacity 4096 x 4 bits 2048 x 4 bits Carrier Generator for Infrared Remote Controller Provided Receiver Preamplifier for Infrared Remote Controller Provided Ports 28 External Interrupt INT 1 Timer 8 bit timer 3 channels 4 channels Watch timer 1 channel Watchdog Timer Provided WDOUT output Serial Interface 1 channel Stack 5 levels interrupt nesting levels 7 levels interrupt nesting levels Standby Function STOP and HALT modes Main System Instruction Execution Clock 4 us at 4 MHz 2 2 to 5 5V 2 9 to 5 5 VNete 2 2 to 5 5V Von 2 9 to 5 5 VNete Time supply voltage 20 to 75 Sub System Clock 488 us at 32 768 kHz 2 0 to 5 5 V Package 52 pin plastic OFP Note The supply voltage varies depending o
10. 11 2 GNDo 7 GNDas 588900 8 88238238 O Oh WDOUT 9 eee eae O POBs 10 XTour O O GNDs O O C Oe X9 O C 0 Q 0 QO Or Q Q 2253225332248 Os O90 C O gt gt 5 lt 5 AMPIN Operational amplifier input RESET Reset input AMPOUT Operational amplifier output SCK Serial clock input output Comparator input Sl Serial data input CMPOUT Comparator output 50 Serial data output GNDo GNDs Ground TMOIN Timer 0 input INT External interrupt input TMOOUT Timer 0 output LED Remote controller transmission TM1OUT Timer 1 output output indicator TM20UT Timer 2 output POAo POA3 I O port Power supply POBo POBs I O port OB VREG Voltage regulator output POCo POCs port OC VREF Reference voltage output PODo PODs port OD VXRAM StaticRAM XRAM power supply P1Ao P1As port 1A WDOUT Overrun detection output P1Bo P1Bs I O port 1B XOUT Main clock oscillation use P1Co P1Cs port 1C XTout Subclock oscillation use REM Remote controller transmission output uPD17P203A 17P204 2 PROM programming mode OQ 000000000000 52 51 50 49 48 45 44 43 42 41 40 1 39 D2 2 38 Di GNDO 3 37 Do 4 36 Dr 338383 CLK O 5
11. 7204 On request mask option 17 20 and uPD17P204 are different from uPD17203A and 17204 respectively the power supply voltage and the operating ambient temperature Therefore use uPD17P203A and uPD17P204 only for the system evaluation This document explains 17 204 as typical product where no specification is made The information in this document is subject to change without notice Document No 1C 2851A D No 8303 Date Published June 1995 P Printed in Japan The mark shows major revised points Corporation 1992 ORDERING INFORMATION Part Number Package LuPD17P203AGC 001 3BH LPD17P203AGC 002 3BH LuPD17P203AGC 003 3BH 17 204 001 17 204 002 17 204 003 52 pin plastic OFP 14 x 14 mm 52 pin plastic OFP 14 x 14 mm 52 pin plastic OFP 14 x 14 mm 52 pin plastic OFP 14 x 14 mm 52 pin plastic OFP 14 x 14 mm 52 pin plastic OFP 14 x 14 mm uPD17P203A 17P204 uPD17P203A 17 204 CONFIGURATION VIEW 1 Normal operation mode O PTBs TM2OUT O P1B2 TM10UT O O 1 2 9 O 1 50 O P1Co SCK P1Bo P1Ao C PODs 1219 LEDO 1 O 2 O POD 3 O PODo O 4 BEEEES Xin 5 33353555 555559 cup 411
12. DATA SHEET MOS INTEGRATED CIRCUIT uPD17P203A 17P204 4 BIT SINGLE CHIP MICROCONTROLLER WITH STATIC RAM AND 3 CHANNEL TIMER FOR INFRARED REMOTE CONTROLLER DESCRIPTION uPD17P203A and uPD17P204 are variations uPD17203A and uPD17204 respectively and are equipped with a one time PROM instead of an internal mask ROM 17 20 and uPD17P204 are suitable for evaluating a program when developing uPD17203A and uPD17204 systems respectively because the program can be written by the user When reading this document also refer to the 17203 and 17204 Data Sheets FEATURES 17K architecture General purpose register format Pin compatible except for PROM programming function uPD17P203A with uPD17203A LPD17P204 with uPD17204 Internal one time PROM 4096 16 bits 17 203 7936 x 16 bits uPD17P204 Static 16 Kbits wPD17P203A 8 Kbits uPD17P204 Power supply voltage 2 9 to 5 5 V at Ta 20 to 75 C fx 4MHz 2 0 to 5 5 V at TA 20 to 75 C fxr 32kHz The features of each product is shown in the following table Pull up resistor of RESET pin Pull up resistor of POA and POB pins Main clock oscillator circuit Subclock oscillator circuit uPD17P203A 001 uPD17P204 001 Provided uPD17P203A 002 17 204 002 Not provided Provided uPD17P203A 003 uPD17P204 003 Not provided Not provided Provided uPD17203A uPD1
13. DO0 MD3 Selects operation mode 00 07 Inputs and outputs 8 bit data 3 1 OPERATION MODE FOR WRITING READING AND VERIFICATION OF PROGRAM MEMORY If 6 is applied to the and 12 5 V to the Ver pin after uPD17P204 has been placed in the reset status for a fixed time 5V RESET OV uPD17P204 enters program memory write read or verify mode The MDO to pins are used to set the operation modes listed in the following table Leave the pins not used for program memory writing reading or Operating Mode Specification verification open or ground through pull down resistors Operating Mode Program memory address 0 clear mode Write mode Read verify mode x LorH Program inhibit mode 15 uPD17P203A 17 204 16 3 2 PROGRAM MEMORY WRITE PROCEDURE The program memory write procedure is as follows High speed program memory write is possible 1 Ground the unused pins through pull down resistors The CLK pin must be low 2 Supply 5 V to the pin The Ver pin must be low 3 After waiting for 10 microseconds supply 5 V to the VPP pin 4 Operate the MDO to MD3 pins to set program memory address 0 clear mode 5 Supply 6 V to the Voo pin 12 5 V to the Vr pin 6 Set program inhibit mode 7 Write data in 1 millisecond write mode 8 Set program inhibit mode 9 Set verify mode If data has been written connectly proceed to s
14. MOS push pull 37 to 40 Do to Ds 1 3 PIN CIRCUITS This section shows the I O circuits of the 17 204 pins in simplified schematic diagrams 1 0 lt lt D 5 J Pull up resistor Nete P ch e O Output N ch disable Input buffer Note 017 20 001 002 and uPD17P204 001 002 only uPD17P203A 17 204 2 POCo D4 POC3 D7 PODo DO PODs D3 Data N ch Output disable Input buffer 3 1 P1Bo P1B3 TM20UT Pull up resistor P ch Data Data Output disable Input buffer 10 uPD17P203A 17P204 4 P1Co SCK P1Cs Data Pul up P ch resistor VDD Data Output P ch Output N ch disable Input buffer 5 RESET Pull up resistorNete Input buffer Note 4PD17P203A 001 and uPD17P204 001 only 11 uPD17P203A 17 204 1 4 PROCESSING UNUSED PINS The following are recommended to process unused pins Table 1 1 Processing of Unused Pins Recommended Connection INT TMOIN Connect to GND Input Connect each to Voo through resistor Output Open high level output PODo PODs Input Connect each pin to GND thro
15. S17203 AS17203 is a device file for 1720 and 17P203A and it is used in combination with an assembler commonly used for the 17K series AS17K PC 9800 series 5 2HD 55 10 517203 3 5 2HD 55 13 17203 1 5 2HC 78104 17203 3 5 2HC 157813 517203 Device file 517204 517204 is a device file for 17204 17P204 and it is used in combination with an assembler for the 17K series 517 PC 9800 series 5 2HD 55 10 517204 3 5 2HD 5 13 17204 1 5 2HC 57810 517204 3 5 2HC uS7B13AS17204 Support software SIMPLEHOST SIMPLEHOST is a software package that enables man machine interface on the Windows when a program is developed by using an in circuit emulator and a personal computer PC 9800 series IBM PC AT Remark corresponding OS versions are as follows Version Ver 3 30 to Ver 5 00ANote Ver 3 1 to 5 0 Ver 3 0 to Ver 3 1 Note Ver 5 00 5 00A of MS DOS and Ver 5 0 of PC DOS have a task swap function but this function cannot be used with this software Windows 5 2HD uS5A10IE17K 3 5 2HD 5 13 17 5 2HC uS7B101E17K 3 5 2HC uS7B13l1E17K 28 uPD17P203A 17P204 uPD17P203A 17P204 NOTES FOR CMOS DEVICES 1
16. ceiver O AMPOUT O REM O LED Interrupt Controller O INTAV ee XRAM RESET O WDOUT 4096 x 4 bits uPD17P203A 2048 x 4 bits uPD17P204 Watch Timer CPU Clock Clock Stop Xin CLK Main clock CPU Clock XTin Subclock XTour uPD17P203A 17P204 1 PIN FUNCTIONS 0 0 0 0 2 4 7 1 1 NORMAL OPERATION 7 1 2 PROGRAMMING MODE 9 13 PINI O CIRCULTS etit 9 1 4 PROCESSING OF UNUSED 12 15 NOTES ON USING RESET AND INT PINS enne 13 2 DIFFERENCES BETWEEN MASK ROM PRODUCTS AND ONE TIME PROM PRODUCTS M 14 3 ONE TIME PROM PROGRAM MEMORY WRITING READING AND VERIFICATION ET 15 3 1 OPERATION MODE FOR WRITING READING AND VERIFICATION OF PROGRAM 15 3 2 PROGRAM MEMORY WRITE 16 3 3 PROGRAM MEMORY READ PROCEDURE 17 4 ELECTRICAL SPECIFICATIONS in 18 b PACKAGE DRAWINGS 252025 Pre 23 6 RECOMMENDED SOLDERING 8 4 4 4 0 010 24
17. ch be set in input or POC output mode in 4 bit units t N ch open drain POCs GND4 Ground PODo Constitute 4 bit I O port which can be set in input or to output mode in 4 bit units N ch open drain PODs P1Ao Constitute 4 bit I O port which can be set in input or to output mode in bitwise Pull up registor can be N ch open drain P1As connected through program P1Bo Port 1B or timer output P1B1 1 1 TMOOUT 4 bit I O port EE ue Input 1 2 Can be set in input output mode in bitwise N ch open drain 1 1 TM10UT Pull up resistor can be connected through program P1B3 TMOOUT TM20UT TM20UT Timer output Port 1C or serial interface P1Co P1Cs 1 4 bit I O port 1 1 5 0 Can be set in input output mode bitwise Input P1C2 SI SCK SO SI CMOS push pull P1C3 SCK serial clock I O SO serial clock data output SI serial clock data input Caution For A standard products note that standby mode is released when one or more of POC and POD pins goes high in standby mode uPD17P203A 17 204 12 PROGRAMMING MODE Function Output Format At Reset Ground Positive power Address updating clock input Supplies program voltage Apply 12 5V to this pin 28to 31 MDo to MDs Selects PROM programming mode 32 34 to D7 10 36 8 bit data C
18. d pin PROM program pins Provided Not provided P ly volt 2 2 to 5 5 V E Y Vonage 2 9 to 5 5 V at 4MHz Note i Ta 20 to 75 at 4MHz Package 52 pin plastic OFP im omes uPD17P204 001 uPD17P204 002 1 17 204 003 1 17204 One time PROM Mask ROM Program memory 0000H 1EFFH 0000H 1EFFH 7936x16 bits 7936x16 bits Pull up resistor of RESET pin Not provided Pull up resistor of POA and POB pins Not provided On request Provided Provided Main clock oscillator circuit mask option Subclock oscillator circuit Not provided Provided pin PROM program pins Provided Not provided P 2 2 to 5 5 V 2 9 to 5 5 V at 4MHz Note Pp TA 20 to 75 at 4MHz Package 52 pin plastic OFP Note For details on the power supply voltage refer to 4 ELECRICAL SPECIFICATIONS 14 uPD17P203A 17 204 3 ONE TIME PROGRAM MEMORY WRITING READING AND VERIFICATION The program memory of 4096 x 16 bits uPD17P203A and 7936 x 16 bits uPD17P204 one time PROM provided The following table lists the pins to be used In PROM mode no address input pin is used the CLK pin for this PROM writing reading or verification Instead the address is updated by the clock for input from Pin Name Function Applies program voltage Inputs address update clock M
19. ectronic equipment and industrial robots Special Transportation equipment automobiles trains ships etc traffic control systems anti disaster systems anti crime systems safety equipment and medical equipment not specifically designed for life support Specific Aircrafts aerospace equipment submersible repeaters nuclear reactor control systems life support systems or medical equipment for life support etc The quality grade of NEC devices in Standard unless otherwise specified in NEC s Data Sheets or Data Books If customers intend to use NEC devices for applications other than those specified for Standard quality grade they should contact NEC Sales Representative in advance Anti radioactive design is not implemented in this product 4 94 11
20. g related to the unused pins must be judged device by device and related specifications governing the devices 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Note Power on does not necessarily define initial status of MOS device Production process of MOS does not define the initial operation status of the device Immediately after the power source is turned ON the devices with reset function have not yet been initialized Hence power on does not guarantee out pin levels settings or contents of registers Device is not initialized until the reset signal is received Reset operation must be executed immedi ately after power on for devices having reset function 29 uPD17P203A 17 204 SIMPLEHOST is trademark of NEC Corporation MS DOS and Windows are trademarks of Microsoft Corporation PC AT and PC DOS are trademarks of IBM Corporation The export of this product from Japan is regulated by the Japanese government To export this product may be prohibited without governmental license the need for which must be judged by the customer The export or re export of this product from a country other than Japan may also be prohibited without a license from that country Please call an NEC sales representative No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Corporation NEC Corporation assumes no responsibility for any errors which
21. itions for surface mounting referto information document Semiconductor device mounting technology manual IEI 1207 For other soldering methods please consult with NEC personnel Table 6 1 Soldering Conditions of Surface Mount Type LPD17P203AGC 001 3BH 52 pin plastic QFP 14 x 14 mm LPD17P203AGC 002 3BH 52 pin plastic QFP 14 x 14 mm LPD17P203AGC 003 3BH 52 pin plastic QFP 14 x 14 mm LPD17P204GC 001 3BH 52 pin plastic QFP 14 x 14 mm LPD17P204GC 002 3BH 52 pin plastic QFP 14 x 14 mm LPD17P204GC 003 3BH 52 pin plastic QFP 14 x 14 mm Soldering Method Soldering Conditions Package peak temperature 235 C Time 30 seconds max 210 C min Number of times 2 max Days 7 daysNete after that prebaking is necessary for 20 hours at 125 C Infrared reflow Caution IR35 207 2 1 Start second reflow after device temperature which has risen because of first reflow has returned to room temperature 2 Do not clean flux with water after first reflow Package peak temperature 215 C Time 40 seconds max 200 C min Number of times 2 max Days 7 daysNete after that prebaking is necessary for 20 hours at 125 C Caution VP15 207 2 1 Start second reflow after device temperature which has risen because of first reflow has returned to room temperature 2 Do not clean flux with water after first reflow Pin part heating Pin temperature 300 C max Time 3 seconds max per side of
22. may appear in this document NEC Corporation does not assume any liability for infringement of patents copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device No license either express implied or otherwise is granted under any patents copyrights or other intellectual property rights of NEC Corporation or others While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices the possibility of defects cannot be eliminated entirely To minimize risks of damage or injury to persons or property arising from a defect in an NEC semiconductor device customer must incorporate sufficient safety measures in its design such as redundancy fire containment and anti failure features NEC devices are classified into the following three quality grades Standard Special and Specific The Specific quality grade applies only to devices developed based on a customer designated quality assurance program for a specific application The recommended applications of a device depend on its quality grade as indicated below Customers must check the quality grade of each device before using it in a particular application Standard Computers office equipment communications equipment test and measurement equipment audio and visual equipment home electronic appliances machine tools personal el
23. n the operating ambient temperature For details refer to 4 ELECTRICAL SPECIFICATIONS 25 uPD17P203A 17 204 26 APPENDIX DEVELOPMENT TOOLS The following tools are readily available for uPD17P203A and uPD17P204 program development Hardware Name Outline The IE 17K IE 17K ET and EMU 17 are in circuit emulators that can be commonly used with the 17K series products The IE 17K and IE 17K ET are connected to the host machine which is a PC 9800 In circuit emulators series product or IBM via RS 232 C The EMU 17K is inserted into an IE 17K expansion slot of a PC 9800 series product IE 17K ETNete 1 When these in circuit emulators are used in combination with a system evaluation EMU 17KNote 2 board SE board dedicated to each model of the device they operate as the emulator dedicated to that model A more sophisticated debugging environment can be created by using the man machine interface software SIMPLEHOST M The EMU 17K has a function that allows you to check the contents of the data memory real time The SE 17204 is an SE board for the uPD17203A 17P203A 17204 and 17P204 SE board SE 17204 It may be used alone to evaluated a system or in combination with an in circuit emulator for debugging The EP 17203GC is an emulation probe for the uPD17203A 17P203A 17204 17P204 It connects an SE board and the user system When used with the EV 9200G 52 this probe connects the SE b
24. oard and the target system Emulation Probe EP 17203GC Conversion socket The EV 9200G 52 connects the EP 17203GC and the target system EV 9200G 52Note 3 PROM programmer The AF9703 AF9704 AF9705 and AF9706 are PROM programmers that can AF 9703Note 4 AF 9704Nete program the uPD17P203A and 17P204 When connected with programmer adapter AF 9705Note 4 9706 4 AF 9808A this PROM programmer can program the uPD17P203A and 17P204 Program adapter The AF 9808A is an adapter for programming the 17 20 and 17P204GC AF 9808BNete 4 and is used in combination with the AF 9703 AF 9704 AF 9705 and AF 9706 Notes 1 Low cost model external power supply type 2 This is a product from I C Corp For details consult 3 One EV 9200G 52 is supplied with the EP 17203GC Five EV 9200G 52s are optionally available as a set 4 These are products from Ando Electric For details consult Ando Electric Software 17K series assembler AS17K Outline Machine AS17K is an assembler that can be used in common with the 17K series products When developing the program of the 17 20 and 17P204 AS17K is used in combination with a device file AS17203 AS17204 PC 9800 series uPD17P203A 17 204 MS DOS M 5 2DH Order Code uS5A10AS17K 3 5 2HD uS5A13AS17K IBM PC AT 5 2HC uS7B10AS17K 3 5 2HC uS7B13AS17K Device file A
25. ow Hi Z Hi Z E MDO MD1 ws fT 17 4 ELECTRICAL SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS Supply voltage 25 Conditions uPD17P203A 17 204 Ratings 0 3 to 47 0 Input voltage 0 3 to Voo 0 3 High level output current REM pin Peak value Effective valueNote 1 pin except for REM pin Peak value Effective valueNote Total except for REM pin Peak value Effective valueNote Low level output current 1 pin Peak value Effective valueNote Total Peak value Effective valueNote Operating ambient temperature 20 to 75 Storage temperature Note Effective value Peak value x Duty Caution 40 to 125 Even if one of the parameters exceeds its absolute maximum rating even momentarily the quality of the product may be degraded The absolute maximum rating therefore specifies the upper or lower limit of the value at which the product can be used without physical damages Be sure not to exceed or fall below this value when using the product RECOMMENDED OPERATING RANGE Ta 20 to 75 Supply voltage Conditions When the system clock is fx 4 MHz Ta 20 to 55 C When the system clock is fx 4 MHz When the system clock is fx 6 MHz Ta 20 to 50 C When the system clock is fXT 32 kHz
26. peration amplifier AMPIN Inverted input of operational amplifier Input GND2 Ground of operational amplifier AMPOUT Output of operational amplifier Output VREF Outputs reference voltage of 1 2Vop Connect external 0 1 uF capacitor CMPIN Non inverted input of comparator Output of this comparator can be obtained from CMPOUT Remark GNDs Ground of operational amplifier GND GNDs are the ground pins of the operational amplifier Keep all these pins at the same potential to stabilize the operation of the operational amplifier uPD17P203A 17 204 2 2 Function Output Format At Reset Comparator output Externally connect CMPOUT CMPOUT and TMOIN when using microcontroller as teaching remote controller Clock input to timer 0 Input clock is sampled by internal clock and then input to envelope signal generator circuit as well as to timer 0 By using timer O with timer 1 frequency of clock input to this pin can be measured INT External interrupt signal input pin Constitute 4 bit I O port which be set in input or to output mode in 4 bit units Pull up resistor can be connected by mask option 17 20 001 002 and 17 204 001 002 only When one or more of these pins goes low in standby mode standby mode CMOS push pull to is released POCo Constitute 4 bit I O port whi
27. tep 10 If data has not yet been written repeat steps 7 to 9 10 Write additional data for the number of times data was written X in steps 7 to 9 times 1 milliseconds 11 Set program inhibit mode 12 Supply a pulse to the CLK pin four times to update the program memory address by 1 13 Repeat steps 7 to 12 to the last address 14 Set program memory address 0 clear mode 15 Change the voltages of Voo and VPP pins to 5 V 16 Turn off the power supply Steps 2 to 12 are illustrated below X time repetition Reset Write Verif Additional Address ij y T data write increment Bj X D1 N a J M TT MM uPD17P203A 17 204 33 PROGRAM MEMORY READ PROCEDURE 1 Ground the unused pins through pull down resistors The CLK pin must be low 2 Supply 5 V to the Vpp pin The Ver pin must be low 3 After waiting for 10 microseconds supply 5 V to the pin 4 Operate the MDO to MD3 pins to set program memory address 0 clear mode 5 Supply 6 V to the Vpp and 12 5 V to the VPP pin 6 Set program inhibit mode 7 Set verify mode Data of each address is sequentially output each time a clock pulse is input to the CLK pin four times 8 Set program inhibit mode 9 Set program memory address 0 clear mode 10 Change the voltages and Vr pins to 5 V 11 Turn off the power supply Steps 2 to 9 are illustrated bel
28. ugh resistor P1Ao P1As 1 1 Output Open low level output 1 1 Input Connect each pin to GND through resistor Ouput Open LED Open REM Open WDOUT Connect to GND XiN Xour Connect to XTour Connect to AMPIN Connect to GND or AMPOUT AMPOUT CMPOUT Open CMPIN Connect to GND VREF Open 12 uPD17P203A 17P204 15 NOTES ON USING RESET AND INT PINS NORMAL OPERATION MODE ONLY In addition to the functions shown in 1 PIN FUNCTIONS the RESET and INT pins also have a function to set a test mode for IC testing in which the internal operations of the 17 204 are tested When a voltage higher than is applied to either of these pins the test mode is set This means that even during normal operation the uPD17P204 be set in the test mode if a noise exceeding is applied For example if the wiring length of the RESET or INT pin is too long noise superimposed on the wiring line of the pin may cause the above problem Therefore keep the wiring length of these pins as short as possible to suppress the noise otherwise take noise preventive measures as shown below by using external components Connect diode with low Vr between Connect capacitor between and RESET INT pin and RESET INT pin Diode with
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NEC PD17P203A 17P204 4 BIT SINGLE CHIP MICROCONTROLLER WITH STATIC RAM AND 3 CHANNEL TIMER FOR INFRA