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ANALOG DEVICES AD9230-11 English products handbook Rev 0

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1. Input Resistance Differential Full 16 20 24 Input Capacitance Full 4 pF LOGIC INPUTS Logic 1 Voltage Full 0 8 x AVDD V Logic 0 Voltage Full 0 2 x AVDD V Logic 1 Input Current SDIO Full 0 Logic 0 Input Current 5010 Full 60 Logic 1 Input Current SCLK PWDN CSB RESET Full 55 Logic 0 Input Current SCLK PWDN CSB RESET Full 0 Input Capacitance 25 C 4 pF LOGIC OUTPUTS Differential Output Voltage Full 247 454 mV Vos Output Offset Voltage Full 1 125 1 375 V Output Coding Twos complement gray code or offset binary default 1 See the AN 835 Application Note Understanding High Speed ADC Testing and Evaluation for a complete set of definitions and an explanation of how these tests were completed 2 LVDS Rrermination 100 Rev 0 Page 5 of 28 AD9230 11 SWITCHING SPECIFICATIONS AVDD 1 8 DRVDD 1 8 V Tum 40 C Tmax 85 C 1 0 dBFS full scale 1 25 V DCS enabled unless otherwise noted Table 4 Parameter Temp Min Typ Max Unit CONVERSION RATE Maximum Conversion Rate Full 200 MSPS Minimum Conversion Rate Full 40 MSPS PULSE WIDTH CLK Pulse Width High Full 2 25 2 5 ns CLK Pulse Width Low ta Full 2 25 2 5 ns OUTPUT LVDS SDR MODE Data Propagation Delay Full 3 8 ns Rise Time tr 2096 to 80 25 C 0 2 ns Fall Time tr 20 to 80 25 C 0 2 ns DCO Propagation Delay Full 3 9 ns
2. Differential Input Voltage Range Full 0 98 1 25 1 5 V p p Input Common Mode Voltage Full 1 4 V Input Resistance Differential Full 4 3 Input Capacitance 25 C 2 pF POWER SUPPLY AVDD Full 1 7 1 8 1 9 V DRVDD Full 1 7 1 8 1 9 V Supply Currents lavo Full 152 164 mA Iprvop SDR Full 55 58 mA Ipavopp DDR Mode Full 36 mA Power Dissipation Full SDR Full 373 400 mW DDR Mode Full 338 mW 1 See the AN 835 Application Note Understanding High Speed ADC Testing and Evaluation for a complete set of definitions and an explanation of how these tests were completed The input range is programmable through the SPI and the range specified reflects the nominal values of each setting See the Memory Map section 3 aypp and lorvon are measured with a 1 dBFS 10 3 MHz sine input at rated sample rate 4 Single data rate mode this is the default mode of the AD9230 11 5 Double data rate mode user programmable feature See the Memory Map section Rev 0 Page 3 of 28 AD9230 11 AC SPECIFICATIONS AVDD 1 8 V DRVDD 1 8 V 40 C Tmax 85 C fin 1 0 dBES full scale 1 25 V DCS enabled unless otherwise noted Table 2 Parameter Temp Min Typ Max Unit SNR fin 10 MHz 25 C 62 4 62 9 dB Full 62 2 dB fin 70 MHz 25 C 62 2 62 5 dB Full 62 0 dB fin 170 MHz 25 C 61 8 dB SINAD fin 10 MHz 25 C 62 3 62 8 dB Full 62 1 dB fin 70 MHz 25 C
3. 1011 unused 1100 unused Format determined by output_mode ain_config 0 0 0 0 0 Analog CML 0 0x00 input enable disable 1 1 0 off 0 off default default 0x14 output_mode 0 0 0 Output DDR Output Data format select 0x00 enable invert 00 offset binary 0 enabled 1 default enable 0 0 off 01 twos default disabled default complement 1 default 10 gray code disable 0x15 output_adjust 0 0 0 0 LVDS LVDS fine adjust 0x00 course 001 3 50 mA adjust 010 3 25 0 011 3 00 mA 3 5 100 2 75 mA default 101 2 50 mA 1 110 2 25 2 0 111 2 00 16 output_phase Output 0 0 0 0 0 0 0x03 clock polarity 1 inverted 0 normal default Rev 0 Page 23 of 28 AD9230 11 Default Addr Bit7 Bit 0 Value Notes Hex Register Name MSB Bit 6 Bit 5 Bit4 Bit3 Bit 2 Bit 1 LSB Hex Comments 0x17 flex_output_delay Output 0 0 Output clock delay 0 delay 00000 0 1 ns enable 00001 0 2 ns 0 00010 0 3 ns enable 1 11101 3 0 ns disable 11110 3 1 ns 11111 3 2 ns 0x18 flex_vref 0 0 0 Input voltage range setting 0 10000 0 98 V 10001 1 00 V 10010 1 02 V 10011 1 04 V 11111 1 23 V 00000 1 25 V 00001 1 27 V 01110 1 48 V 01111 1 50 V 0x2A ovr_config 0 0 0 0 0 0 OR OR 0x01 position enable DDR 1 mode default only 0 off O Pin 9 Pin
4. The length of the output data lines and loads placed on them should be minimized to reduce transients within the AD9230 11 These transients can degrade the dynamic performance of the converter The AD9230 11 also provides data clock output DCO intended for capturing the data in an external register The data outputs are valid on the rising edge of DCO The lowest typical conversion rate of the AD9230 11 is 40 MSPS At clock rates below 1 MSPS the AD9230 11 assumes the standby mode RBIAS The AD9230 11 requires the user to place a 10 resistor between the RBIAS pin and ground This resister should have a 196 tolerance and is used to set the master current reference ofthe ADC core CONFIGURATION USING THE SPI The AD9230 11 SPI allows the user to configure the converter for specific functions or operations through a structured register space inside the ADC This gives the user added flexibility to customize device operation depending on the application Addresses are accessed programmed or readback serially in 1 byte words Each byte may be further divided down into fields which are documented in the Memory Map section There are three pins that define the serial port interface SPI to this particular ADC They are the SCLK DFS SDIO DCS and CSB pins The SCLK DFS serial clock is used to synchronize the read and write data presented to the ADC The SDIO DCS serial data input output is a dual purpose pin that allows data to
5. 0 should be considered reserved and have a 0 written into their registers during power up DEFAULT VALUES Coming out of reset critical registers are preloaded with default values These values are indicated in Table 13 Other registers do not have default values and retain the previous value when exiting reset LOGIC LEVELS An explanation of logic level terminology follows bit is set is synonymous with bit is set to Logic 1 or writing Logic 1 for the bit Similarly clear a bit is synonymous with bit is set to Logic 0 or writing Logic 0 for the bit TRANSFER REGISTER MAP Address 0x08 to Address 0x18 are shadowed Writes to these addresses do not affect part operation until a transfer command is issued by writing 0x01 to Address OxFF setting the transfer bit This allows these registers to be updated internally and simultaneously when the transfer bit is set The internal update takes place when the transfer bit is set and the bit autoclears Addr Hex Register Name Bit7 MSB Bit 6 Bit 5 Bit4 Bit 3 Default Value Hex Notes Bit 2 Bit 1 Comments Chip Configuration Registers Soft 1 reset 0x00 LSB first chip port config 0 Soft reset LSB first The nibbles should be mirrored by the user so that LSB or MSB first mode registers correctly regardless of shift mode 0x18 0x01 chip_id 8 bit chip ID Bits 7 0 AD92
6. 10 1 2 Pin 21 Pin 22 Rev 0 Page 24 of 28 AD9230 11 OUTLINE DIMENSIONS PIN 1 INDICATOR INDICATOR 4 45 TER 50 sa BOTTOM VIEW 4 15 5 0 30 MIN 1 00 12 MAX 0 80 MAX 0 85 0 65 0 80 0 05 FOR PROPER CONNECTION 8 Y 0 02 NOM THE EXPOSED PAD REFER TO SEATING 0 50 Bsc COPLANARITY FUNCTION DESCRIPTIONS PLANE 0 20 REF 0 08 SECTION OF THIS DATA SHEET lt COMPLIANT JEDEC STANDARDS MO 220 VLLD 2 8 Figure 34 56 Lead Lead Frame Chip Scale Package LFCSP VO 8mm x 8 mm Body Very Thin Quad CP 56 2 Dimensions shown in millimeters ORDERING GUIDE Model Temperature Range Package Description Package Option AD9230BCPZ1 1 200 40 to 85 C 56 Lead Lead Frame Chip Scale Package LFCSP_VQ CP 56 2 AD92301 1 200EBZ LVDS Evaluation Board 17 RoHS Compliant Part Rev 0 Page 25 of 28 AD9230 11 NOTES Rev 0 Page 26 of 28 AD9230 11 NOTES Rev 0 Page 27 of 28 AD9230 11 NOTES 2008 Analog Devices Inc All rights reserved Trademarks and ANALOG registered trademarks are the property of their respective owners D07101 0 10 08 0 DEVICES www analog com Rev 0 Page 28 of 28
7. be sent and read from the internal ADC memory map registers The CSB pin is an active low control that enables or disables the read and write cycles see Table 9 Rev 0 Page 19 of 28 AD9230 11 Table 9 Serial Port Interface Pins Mnemonic Function SCLK SCLK serial clock is the serial shift clock in SCLK is used to synchronize serial interface reads and writes SDIO SDIO serial data input output is a dual purpose pin The typical role for this pin is an input and output depending on the instruction being sent and the relative position in the timing frame CSB CSB chip select bar is an active low control that gates the read and write cycles RESET Master Device Reset When asserted device assumes default settings Active low The falling edge of CSB in conjunction with the rising edge of the SCLK determines the start of the framing An example of the serial timing and its definitions can be found in Figure 33 and Table 11 During an instruction phase a 16 bit instruction is transmitted Data then follows the instruction phase and is determined by the W0 and W1 bits which is 1 or more bytes of data All data is composed of 8 bit words The first bit of each individual byte of serial data indicates whether this is a read or write command This allows the serial data input output SDIO pin to change direction from an input to an output Data can be sent in MSB or in LSB first mode MSB first is defaul
8. each stage are combined into a final 11 bit result in the digital correction logic The pipelined architecture permits the first stage to operate on a new input sample while the remaining stages operate on preceding samples Sampling occurs on the rising edge of the clock Each stage of the pipeline excluding the last consists of a low resolution flash ADC connected to a switched capacitor DAC and interstage residue amplifier MDAC The residue amplifier magnifies the difference between the reconstructed DAC output and the flash input for the next stage in the pipeline One bit of redundancy is used in each stage to facilitate digital correction of flash errors The last stage simply consists of a flash ADC The input stage contains a buffered differential SHA that can be ac or dc coupled The output staging block aligns the data carries out the error correction and passes the data to the out put buffers The output buffers are powered from a separate supply allowing adjustment of the output voltage swing During power down the output buffers go into a high impedance state ANALOG INPUT AND VOLTAGE REFERENCE The analog input to the AD9230 11 is a differential buffer For best dynamic performance the source impedances driving VIN and VIN should be matched such that common mode settling errors are symmetrical The analog input is optimized to provide superior wideband performance and requires that the analog inputs be driven diffe
9. to AGND 0 3V to 43 9 V Environmental Storage Temperature Range 65 C to 125 C Operating Temperature Range 40 C to 85 C Lead Temperature 300 C Soldering 10 sec Junction Temperature 150 C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device This is a stress rating only functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied Exposure to absolute maximum rating conditions for extended periods may affect device reliability THERMAL RESISTANCE The exposed paddle must be soldered to the ground plane for the LFCSP package Soldering the exposed paddle to the customer board increases the reliability of the solder joints maximizing the thermal capability of the package Table 6 Package Type Osc Unit 56 Lead LFCSP CP 56 2 30 4 2 9 C W Typical and are specified for a 4 layer board in still air Airflow increases heat dissipation effectively reducing In addition metal that is in direct contact with the package leads reduces the ESD CAUTION ESD electrostatic discharge sensitive device Charged devices and circuit boards can discharge without detection Although this product features patented or proprietary protection circuitry damage may occur on devices subjected to high energy ESD Therefore pro
10. to AVDD which disables the serial port interface Table 10 Mode Selection Mnemonic ExternalVoltage Configuration SDIO DCS AVDD Duty cycle stabilizer enabled AGND Duty cycle stabilizer disabled SCLK DFS AVDD Twos complement enabled AGND Offset binary enabled tps 1 tek 07101 027 Figure 33 Serial Port Interface Timing Diagram Rev 0 Page 20 of 28 Table 11 Serial Timing Definitions AD9230 11 Parameter Timing minimum ns Description tos 5 Setup time between the data and the rising edge of SCLK 2 Hold time between the data and the rising edge of SCLK tak 40 Period of the clock ts 5 Setup time between CSB and SCLK 2 Hold time between CSB and SCLK tui 16 Minimum period that SCLK should be in a logic high state tio 16 Minimum period that SCLK should be in a logic low state 500 1 Minimum time for the SDIO pin to switch from an input to an output relative to the SCLK falling edge not shown in Figure 33 tpis 5 5 Minimum time for the SDIO pin to switch from an output to an input relative to the SCLK rising edge not shown in Figure 33 Table 12 Output Data Format Offset Binary Output Mode Twos Complement Mode Input V Condition V D10 to DO D10 to DO OR VIN VIN lt 0 62 0000 0000 000 1000 0000 000 1 VIN VIN 0 62 0000 0000 000 1000 0000 000 0 VIN VIN 0 0000 0000 000 0000 0000 000 0 VIN V
11. 2 OR Overrange True Output Bit 1 AGND and DRGND should be tied to a common quiet ground plane Rev 0 Page 10 of 28 ano an 15454 aano 12 gt gt lt lt 2008583393333 D2 D8 1 PIN 4 02 08 2 INDICATOR D3 D9 3 D3 D9 4 MSB D4 D10 5 MSB D4 D10 6 DRVDD AD9230 11 DRGND 8 TOP VIEW OR 9 Not to Scale OR 10 DNC 11 DNC 12 DNC 13 DNC 14 e 9t e RRRSERSKESREK ooooooTT7oaaoomr ZZzzzzzweyzaoueu gt 09 y zz 99 NOTES 1 DNC DO NOT CONNECT 2 PIN 0 EXPOSED PADDLE AGND Figure 5 Double Data Rate Mode Pin Configuration Table 8 Double Data Rate Mode Pin Function Descriptions 07101 005 AD9230 11 Pin No Mnemonic Description 30 32 to 34 37 to 39 AVDD 1 8 V Analog Supply 41 to 43 46 7 24 47 DRVDD 1 8 V Digital Output Supply 0 AGND Analog Ground The exposed paddle should be connected to the analog ground 8 23 48 DRGND Digital Output Ground 35 VIN Analog Input Input True 36 VIN Analog Input Complement 40 CML Common Mode Output Pin Enabled through the SPI this pin provides a reference for the optimized internal bias voltage for VIN VIN 44 CLK Clock Input Input True 45 CLK Clock Input Complement 31 RBIAS Set Pin for Chip Bias Current Place 196 10 kO resistor termin
12. 30 11 Ox0C Read only Default is unique chip ID different for each device This is a read only register 0x02 chip grade 0 0 0 Speed grade 112 200 MSPS Read only Child ID used to differentiate graded devices Transfer Register OxFF device update 0 SW transfer 0x00 Synchronously transfers data from the master shift register to the slave Rev 0 Page 22 of 28 AD9230 11 Default Addr Bit7 Bit 0 Value Notes Hex Register Name MSB Bit 6 Bit5 Bit 4 Bit 3 Bit 2 Bit 1 LSB Hex Comments ADC Functions 0x08 modes 0 0 PWDN 0 0 Internal power down mode 0x00 Determines various 0 full 000 normal power up default generic modes of default 001 full power down chip operation 1 010 standby standby 011 normal power up Note external PWDN pin overrides this setting 0x09 clock 0 0 0 0 0 0 0 Duty 0x01 cycle stabilizer 0 disabled 1 enabled default OxOD test io 0 0 Reset Reset Output test mode 0x00 When this register PN23 PN9 gen 0000 off default is set the test data gen 1 0001 midscale short is placed on the 1 0 off 0010 FS short output pins in 0 off default 0011 FS short place of normal default 0100 checker board output data 0101 PN 23 sequence 01102 PN9 0111 one zero word toggle 1000 unused 1001 unused 1010 unused
13. 62 0 62 3 dB Full 61 8 dB fin 170 MHz 25 C 61 5 dB EFFECTIVE NUMBER OF BITS ENOB fin 10 MHz 25 C 10 3 Bits fin 70 MHz 25 C 10 2 Bits fin 170 MHz 25 C 10 1 Bits WORST HARMONIC SECOND OR THIRD fin 10 MHz 25 C 86 77 dBc Full 77 dBc fin 70 MHz 25 C 79 77 dBc Full 76 dBc fin 170 MHz 25 C 76 dBc WORST OTHER SFDR EXCLUDING SECOND AND THIRD fin 10 MHz 25 C 88 84 dBc Full 79 dBc fin 70 MHz 25 C 84 82 dBc Full 81 dBc fin 170 MHz 25 C 82 dBc ANALOG INPUT BANDWIDTH 25 C 700 MHz 1 All ac specifications tested by driving CLK and CLK differentially See the AN 835 Application Note Understanding High Speed ADC Testing and Evaluation for a complete set of definitions and an explanation of how these tests were completed Rev 0 Page 4 of 28 DIGITAL SPECIFICATIONS AD9230 11 AVDD 1 8 V DRVDD 1 8 V Tum 40 C Tmax 85 C 1 0 dBFS full scale 1 25 V DCS enabled unless otherwise noted Table 3 Parameter Temp Min Typ Max Unit CLOCK INPUTS Logic Compliance Full CMOS LVDS LVPECL Internal Common Mode Bias Full 1 2 V Differential Input Voltage Full 0 2 6 Vp p Input Voltage Range Full AGND 0 3 AVDD 1 6 V Input Common Mode Range Full 1 1 AVDD V High Level Input Voltage Full 1 2 3 6 V Low Level Input Voltage Vii Full 0 0 8 V High Level Input Current liu Full 10 10 Low Level Input Current li Full 10 10
14. ANALOG 11 Bit 200 MSPS DEVICES 1 8 V Analog to Digital Converter AD9230 11 FEATURES FUNCTIONAL BLOCK DIAGRAM RBIAS PWDN AGND AVDD SNR 62 5 dBFS fin up to 70 MHz 200 MSPS ENOB of 10 2 fin up to 70 MHz 200 MSPS 1 0 dBFS SFDR 77 dBc f n up to 70 MHz 200 MSPS 1 0 dBFS AD9230 11 Excellent linearity D DRVDD DRGND DNL 0 15 LSB typical INL 0 5 LSB typical omur n LVDS at 200 MSPS ANSI 644 levels D10 700 MHz full power analog bandwidth GLOCK On chip reference no external decoupling required oR Integrated input buffer and track and hold amplifier Low power dissipation 373 mW 200 MSPS LVDS SDR mode T EB 328 mW 200 MSPS LVDS DDR mode RESET SCLK SDIO CSB 5 Programmable input voltage range Figure 1 1 0 V to 1 5 V 1 25 V nominal 1 8 V analog and digital supply operation Selectable output data format offset binary twos complement gray code Clock duty cycle stabilizer Integrated data capture clock APPLICATIONS Wireless and wired broadband communications Cable reverse path Communications test equipment Radar and satellite subsystems Power amplifier linearization GENERAL DESCRIPTION PRODUCT HIGHLIGHTS The AD9230 11 is an 11 bit monolithic sampling analog to 1 High Performance Maintains 62 5 dBFS SNR digital converter ADC optimized for high performance 200 MSPS with a 70 MHz input low power and ease of use The product opera
15. Data to DCO Skew tskew Full 0 3 0 1 0 5 ns Latency Full 6 Cycles OUTPUT LVDS DDR MODE Data Propagation Delay tpo Full 3 8 ns Rise Time tr 20 to 80 25 C 0 2 ns Fall Time tr 20 to 80 25 C 0 2 ns DCO Propagation Delay Full 3 9 ns Data to DCO Skew tskew Full 0 5 0 1 0 3 ns Latency Full 6 Cycles APERTURE UNCERTAINTY JITTER ts 25 C 0 2 ps rms See Figure 2 2 See Figure 3 Rev 0 Page 6 of 28 AD9230 11 TIMING DIAGRAMS N 1 gt ta N 4 VIN CLK CLK DCO DCO Dx Dx 5 VIN ter CLK CLK DCO 05 05 NO NO NO NO NO N 7 DATA DATA DATA DATA DATA D5 04 010 D10 D10 D10 N 7 N 4 N 3 D4 D10 5 6MSBs 8 51585 Figure 3 Double Data Rate Mode Rev 0 Page 7 of 28 AD9230 11 ABSOLUTE MAXIMUM RATINGS Table 5 Parameter Rating Electrical AVDD to AGND 0 3V to 2 0V DRVDD to DRGND 0 3V to 2 0V AGND to DRGND 0 3 V to 40 3 V AVDD to DRVDD 2 0V to 2 0V 00 00 through D10 D10 0 3 V to DRVDD 0 3 V to DRGND DCO DCO DRGND OR OR to 0 3V to DRVDD 0 3V 0 3V to DRVDD 0 3 V CLK to AGND 0 3V to 43 9 V CLK to AGND 0 3V to 43 9 V VIN to AGND 0 3V to AVDD 0 2V VIN to AGND 0 3V to AVDD 0 2V SDIO DCS to DGND 0 3 V to DRVDD 0 3V PWDN to AGND 0 3V to 43 9 V CSB to AGND 0 3V to 43 9 V SCLK DFS
16. IN 0 62 1111 1111 111 0111 1111 111 0 VIN VIN gt 0 62 0 5 LSB 11111111 111 01111111 111 1 Rev 0 Page 21 of 28 AD9230 11 MEMORY MAP READING THE MEMORY MAP TABLE Each row in the memory map table has eight address locations The memory map is roughly divided into three sections chip configuration register map Address 0x00 to Address 0x02 transfer register map Address OxFF and ADC functions map Address 0x08 to Address 0x2A The Addr Hex column of the memory map indicates the register address in hexadecimal and the Default Value Hex column shows the default hexadecimal value that is already written into the register The Bit 7 MSB column is the start of the default hexadecimal value given For example Hexadecimal Address 0x09 the clock register has a hexadecimal default value of 0x01 This means Bit 7 0 Bit 6 0 Bit 5 0 Bit 4 0 Bit 3 0 Bit 2 0 Bit 1 0 and Bit 0 1 or 0000 0001 in binary The default value enables the duty cycle stabilizer Overwriting this default so that Bit 0 0 disables the duty cycle stabilizer For more information on this and other functions consult the AN 877 Application Note Interfacing to High Speed ADCs via SPI at www analog com Table 13 Memory Map Register RESERVED LOCATIONS Undefined memory locations should not be written to other than their default values suggested in this data sheet Addresses that have values marked as
17. K Clock Input Complement 31 RBIAS Set Pin for Chip Bias Current Place 1 10 kO resistor terminated to ground Nominally 0 5 V 28 RESET CMOS Compatible Chip Reset Active Low 25 SDIO DCS Serial Port Interface SPI Data Input Output Serial Port Mode Duty Cycle Stabilizer Select External Pin Mode 26 SCLK DFS Serial Port Interface Clock Serial Port Mode Data Format Select Pin External Pin Mode 27 CSB Serial Port Chip Select Active Low 29 PWDN Chip Power Down 49 DCO Data Clock Output Complement 50 DCO Data Clock Output Input True 51 52 DNC Do No Connect 53 DO LSB DO Complement Output Bit LSB 54 DO LSB DO True Output Bit LSB 55 D1 D1 Complement Output Bit 56 01 D1 True Output Bit 1 D2 D2 Complement Output Bit 2 D2 D2 True Output Bit Rev 0 Page 9 of 28 AD9230 11 Pin No Mnemonic Description 3 D3 D3 Complement Output Bit 4 D3 D3 True Output Bit 5 D4 D4 Complement Output Bit 6 D4 D4 True Output Bit 9 D5 D5 Complement Output Bit 10 D5 D5 True Output Bit 11 D6 D6 Complement Output Bit 12 D6 D6 True Output Bit 13 D7 D7 Complement Output Bit 14 D7 D77 True Output Bit 15 D8 D8 Complement Output Bit 16 D8 D8 True Output Bit 17 D9 D9 Complement Output Bit 18 D9 D9 True Output Bit 19 D10 MSB D10 Complement Output Bit MSB 20 010 MSB D10 True Output Bit MSB 21 OR Overrange Complement Output Bit 2
18. PS 70 3 MHz Figure 10 SNR SFDR vs Input Amplitude 140 3 MHz 200MSPS 170 3MHz 1 0dBFS SNR 61 3dB ENOB 10 1 BITS SFDR 73dBc a a 2 m u a lt 2 0 a 8 40 30 20 10 0 10 20 30 40 50 60 70 80 90 5 FREQUENCY MHz E TEMPERATURE C E Figure 8 64k Point Single Tone FFT 170 MSPS 140 3 MHz Figure 11 Offset vs Temperature Rev 0 Page 13 of 28 AD9230 11 1 0 0 2 DNL LSB e INL LSB b b 55 N 1 o 0 512 1024 1536 2048 OUTPUT CODE 512 1024 1536 2048 OUTPUT CODE Figure 12 DNL Figure 14 INL 07101 034 2 5 2 0 07101 013 TEMPERATURE C Figure 13 Gain vs Temperature Rev 0 Page 14 of 28 07101 033 AD9230 11 EQUIVALENT CIRCUITS AVDD AVDD 25kO CSB 07101 006 07101 009 Figure 18 Equivalent CSB Input Circuit DRVDD V v Dx Dx v V Figure 16 Analog Inputs 1 4 V Figure 19 LVDS Outputs Dx Dx OR OR DCO DCO AVDD DRVDD SCLK DFS 25 RESET PWDN ik SDIO DCS 25kQ Figure 17 Equivalent SCLK DFS RESET PWDN Input Circuit Figure 20 Equivalent SDIO DCS Input Circuit Rev 0 Page 15 of 28 AD9230 11 THEORY OF OPERATION The AD9230 11 architecture consists of a front end sample and hold amplifier SHA followed by a pipelined switched capacitor ADC The quantized outputs from
19. Using the SPI section for more details on using this feature The duty cycle stabilizer uses a delay locked loop DLL to create the nonsampling edge As a result any changes to the sampling frequency require approximately eight clock cycles to allow the DLL to acquire and lock to the new rate Rev 0 Page 17 of 28 AD9230 11 Clock Jitter Considerations High speed high resolution ADCs are sensitive to the quality of the clock input The degradation in SNR at a given input frequency fa due only to aperture jitter 5 can be calculated by SNR Degradation 20 x logio 1 2 x fa x tj In this equation the rms aperture jitter represents the root mean square of all jitter sources including the clock input analog input signal and ADC aperture jitter specifications IF undersampling applications are particularly sensitive to jitter see Figure 29 Treat the clock as an analog signal in cases where aperture jitter may affect the dynamic range of the AD9230 11 Power supplies for clock drivers should be separated from the ADC output driver supplies to avoid modulating the clock signal with digital noise Low jitter crystal controlled oscillators make the best clock sources If the clock is generated from another type of source by gating dividing or other methods it should be retimed by the original clock at the last step Refer to the AN 501 Application Note and the AN 756 Application Note for more in depth information about
20. ated to ground Nominally 0 5 V 28 RESET CMOS Compatible Chip Reset Active Low 25 SDIO DCS Serial Port Interface SPI Data Input Output Serial Port Mode Duty Cycle Stabilizer Select External Pin Mode 26 SCLK DFS Serial Port Interface Clock Serial Port Mode Data Format Select Pin External Pin Mode 27 CSB Serial Port Chip Select Active Low 29 PWDN Chip Power Down 49 DCO Data Clock Output Complement 50 DCO Data Clock Output Input True 51 ND D5 ND D5 Complement Output Bit 52 ND D5 ND D5 True Output Bit 53 D0 D6 LSB D0 D6 Complement Output Bit LSB 54 06 LSB 00 06 True Output Bit LSB 55 D1 D7 D1 D7 Complement Output Bit 56 D1 D7 D1 D7 True Output Bit 1 D2 D8 D2 D8 Complement Output Bit 2 D2 D8 D2 D8 True Output Bit Rev 0 Page 11 of 28 AD9230 11 Pin No Mnemonic Description 3 D3 D9 D3 D9 Complement Output Bit 4 D3 D9 D3 D9 True Output Bit 5 D4 D10 MSB D4 D10 Complement Output Bit MSB 6 D4 D10 MSB D4 D10 True Output Bit MSB 9 OR OR Complement Output Bit This pin is disabled if Pin 21 is reconfigured through the SPI to be OR 10 OR OR True Output Bit This pin is disabled if Pin 22 is reconfigured through the SPI to be OR 11 to 20 DNC Do Not Connect 21 DNC OR Do Not Connect This pin can be reconfigured as the Overrange Complement Output Bit through the serial port register 22 DNC OR Do Not Connect This pin can be reconfigured as
21. ations where frequencies in the 70 MHz to 100 MHz range are being sampled For these applications differen tial transformer coupling is the recommended input configuration The signal characteristics must be considered when selecting a transformer Most RF transformers saturate at frequencies below a few megahertz and excessive signal power can also cause core saturation leading to distortion In any configuration the value of the shunt capacitor C is dependent on the input frequency and may need to be reduced or removed 07101 015 Figure 22 Differential Transformer Coupled Configuration As an alternative to using a transformer coupled input at frequen cies in the second Nyquist zone the AD8352 differential driver can be used see Figure 23 0 1pF y 07101 016 Figure 23 Differential Input Configuration Using the AD8352 Rev 0 Page 16 of 28 CLOCK INPUT CONSIDERATIONS For optimum performance the AD9230 11 sample clock inputs CLK and CLK should be clocked with a differential signal This signal is typically ac coupled into the CLK pin and the CLK pin via a transformer or capacitors These pins are biased internally and require no additional bias Figure 24 shows a preferred method for clocking the AD9230 11 The low jitter clock source is converted from single ended to differential using an RF transformer The back to back Schottky diodes across the secondary transformer limit clock excursions into
22. ble However no responsibility is assumed by Analog Devices for its use nor for any infringements of patents or other rights of third parties that may result fromits use Specifications subject to change without notice No One Technology Way P O Box 9106 Norwood MA 02062 9106 U S A license is granted by implication or otherwise under any patent or patent rights of Analog Devices Tel 781 329 4700 www analog com Trademarks and registered trademarks are the property of their respective owners Fax 781 461 3113 2008 Analog Devices Inc All rights reserved AD9230 11 TABLE OF CONTENTS Features 8 aS LU LR uer 1 Applications 1 Functional Block Diagram sse 1 General Description oett o e RE A IDEE 1 Product Highlights 1 REVISION 2 Specificatioli i esie tilii atero rediens 3 DE Specifications 3 AC Specifications ettet vete I ORDRE I ires 4 Digital Specifications 5 Switching Specifications 6 Timing 1 7 Absolute Maximum Ratings eerte 8 Thermal Resistance 8 ESD Caution 8 Pin Configurations and Function Descriptions 9 Typical Performance Characteristics 13 Equivalent Circuits eee te tete eee iad 15 REVISION HISTORY 10 08 Revision 0 Initial Ve
23. e configured to drive 12 pairs of LVDS outputs at the same rate as the input clock signal single data rate or SDR mode or six pairs of LVDS outputs at 2x the rate of the input clock signal double data rate or DDR mode SDR is the default mode the device can be reconfigured for DDR by setting Bit 3 in Register 14 see Table 13 Out of Range OR An out of range condition exists when the analog input voltage is beyond the input range of the ADC OR is a digital output that is updated along with the data output corresponding to the particular sampled input voltage Thus OR has the same pipeline latency as the digital data OR is low when the analog input voltage is within the analog input range and high when the analog input voltage exceeds the input range as shown in Figure 32 OR remains high until the analog input returns to within the input range and another conversion is completed By logically AND ing OR with the MSB and its complement over range high or underrange low conditions can be detected AD9230 11 OR DATA OUTPUTS TES ENES 1 1111 1111 OR 1111 1111 0 1111 1111 FS 1 2 LSB 0 0000 0000 0 0000 0000 1 0000 0000 FS FS 1 2 LSB FS 1 2LSB Figure 32 OR Relation to Input Voltage and Output Data TIMING The AD9230 11 provides latched data outputs with a pipeline delay of seven clock cycles Data outputs are available one propagation delay trp after the rising edge of the clock signal
24. jitter performance as it relates to ADCs visit www analog com 130 RMS CLOCK JITTER REQUIREMENT 120 110 100 90 80 SNR dB 70 60 50 40 30 1 10 100 1000 ANALOG INPUT FREQUENCY MHz 07101 022 Figure 29 Ideal SNR vs Input Frequency and Jitter POWER DISSIPATION AND POWER DOWN MODE The power dissipated by the AD9230 11 is proportional to its sample rate The digital power dissipation does not vary much because it is determined primarily by the DRVDD supply and bias current of the LVDS output drivers By asserting PWDN Pin 29 high the AD9230 11 is placed in standby mode or full power down mode as determined by the contents of Register 0x08 Reasserting the PWDN pin low returns the AD9230 11 to its normal operational mode An additional standby mode is supported by means of varying the clock input When the clock rate falls below 20 MHz the AD9230 11 assumes a standby state In this case the biasing network and internal reference remain on but digital circuitry is powered down Upon reactivating the clock the AD9230 11 resumes normal operation after allowing for the pipeline latency DIGITAL OUTPUTS Digital Outputs and Timing The AD9230 11 differential outputs conform to the ANSI 644 LVDS standard on default power up This can be changed to a low power reduced signal option similar to the IEEE 1596 3 standard using the SPI This LVDS standard can further reduce the overall power dis
25. nches 14 12 300 E 10 _ 200 z z 100 8 ul 100 6 9 ui 200 54 300 400 5 500 0 e 3 2 1 0 1 2 3 0 0 2 40 8 TIME ns TIME ps Figure 30 Data Eye for LVDS Outputs ANSI Mode with Trace Lengths Less than 24 Inches on Standard FR 4 Rev 0 Page 18 of 28 600 12 400 N VOLTAGE mV 200 TIE JITTER HISTOGRAM Hits o 400 0 3 2 1 0 4 2 3 100 0 TIME ns TIME ps 600 o 07101 024 Figure 31 Data Eye for LVDS Outputs in ANSI Mode with Trace Lengths Greater than 24 Inches on Standard FR 4 The format of the output data is offset binary by default An example of the output coding format can be found in Table 12 If it is desired to change the output data format to twos comple ment see the Configuration Using the SPI section An output clock signal is provided to assist in capturing data from the AD9230 11 The DCO is used to clock the output data and is equal to the sampling clock CLK rate In single data rate mode SDR data is clocked out of the AD9230 11 and must be captured on the rising edge of the DCO In double data rate mode DDR data is clocked out of the AD9230 11 and must be captured on the rising and falling edges of the DCO See the timing diagrams shown in Figure 2 and Figure 3 for more information Output Data Rate and Pinout Configuration The output data of the AD9230 11 can b
26. per ESD precautions should be taken to avoid performance degradation or loss of functionality Rev 0 Page 8 of 28 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS 54 LSB 53 D0 LSB 56 D1 55 D1 52 DNC 51 DNC 50 DCO 49 DCO H 48 DRGND 47 DRVDD 46 AVDD 45 CLK 44 CLK 43 AVDD D2 1 02 2 INDICATOR D3 3 D3 4 D4 5 D4 6 VEA AD9230 11 DRGND 8 TOP VIEW D5 9 Not to Scale D5 10 D6 11 06 12 D7 13 D7 14 A0 XO sf 10 OR co v7 NON 4d5d dd5go ogoaoont BRB S SSSR KS ul rro v am an o 00 NOTES 1 DNC DO NOT CONNECT 2 PIN 0 EXPOSED PADDLE AGND AVDD AVDD CML AVDD AVDD AVDD VIN VIN AVDD AVDD AVDD RBIAS AVDD PWDN Figure 4 Single Data Rate Mode Pin Configuration Table 7 Single Data Rate Mode Pin Function Descriptions 07101 004 AD9230 11 Pin No Mnemonic Description 30 32 to 34 37 to 39 41 to AVDD 1 8 V Analog Supply 43 46 7 24 47 DRVDD 1 8 V Digital Output Supply 0 AGND Analog Ground The exposed paddle should be connected to the analog ground 8 23 48 DRGND Digital Output Ground 35 VIN Analog Input True 36 VIN Analog Input Complement 40 CML Common Mode Output Pin Enabled through the SPI this pin provides a reference for the optimized internal bias voltage for VIN VIN 44 CLK Clock Input True 45 CL
27. rentially SNR and SINAD performance degrades significantly if the analog input is driven with a single ended signal A wideband transformer such as Mini Circuits ADT1 1WT provide the differential analog inputs for applications that require a single ended to differential conversion Both analog inputs are self biased by an on chip resistor divider to a nominal 1 4 V An internal differential voltage reference creates positive and negative reference voltages that define the 1 25 V p p fixed span of the ADC core This internal voltage reference can be adjusted by means of SPI control See the Configuration Using the SPI section ANALOG INPUT Cp ANALOG INPUT 0 1pF Differential Input Configurations Optimum performance is achieved while driving the AD9230 11 in a differential input configuration For baseband applications the AD8138 differential driver provides excellent performance and a flexible interface to the ADC The output common mode voltage of the AD8138 is easily set to AVDD 2 0 5 V and the driver can be configured in a Sallen Key filter topology to provide band limiting of the input signal 1V A 49 90 07101 014 Figure 21 Differential Input Configuration Using the AD8138 At input frequencies in the second Nyquist zone and above the performance of most amplifiers may not be adequate to achieve the true performance of the AD9230 11 This is especially true in IF undersampling applic
28. rsion Operation ze a Ren 16 Analog Input and Voltage Reference 16 Clock Input Considerations see 17 Power Dissipation and Power Down Mode 18 Digital QUtp ts ttt ye ete umts 18 19 eite eC HERE HON PR 19 Configuration Using the SPI see 19 Hardware Interfaces 20 Configuration Without the SPI sse 20 Memory eR RENE S 22 Reading the Memory Map Table sss 22 Reserved Locations eee tete i S kae 22 Default Values 2222 Logic Leyels sore op YS 22 Transfer Register Map etr et eR 22 Outline Dimensions enciende NU en P 25 Ordering Guide SUR tt 25 Rev 0 Page 2 of 28 AD9230 11 SPECIFICATIONS DC SPECIFICATIONS AVDD 1 8 V DRVDD 1 8 V Tum 40 C Tmax 85 C fix 1 0 dBFS full scale 1 25 V DCS enabled unless otherwise noted Table 1 Parameter Temp Min Typ Max Unit RESOLUTION 11 Bits ACCURACY No Missing Codes Full Guaranteed Offset Error 25 C 4 2 mV Full 12 12 mV Gain Error 25 C 0 89 FS Full 2 2 43 FS Differential Nonlinearity DNL 25 C 0 15 LSB Full 0 4 0 4 LSB Integral Nonlinearity INL 25 C 0 5 LSB Full 0 5 0 5 LSB TEMPERATURE DRIFT Offset Error Full uV C Gain Error Full 0 019 C ANALOG INPUTS VIN
29. sipation of the device which reduces the power by 39 mW See the Memory Map section for more information The LVDS driver current is derived on chip and sets the output current at each output equal to a nominal 3 5 mA 100 differential termination resistor placed at the LVDS receiver inputs results in a nominal 350 mV swing at the receiver The AD9230 11 LVDS outputs facilitate interfacing with LVDS receivers in custom ASICs and FPGAs that have LVDS capability for superior switching performance in noisy environments Single point to point net topologies are recommended with a 100 termination resistor placed as close to the receiver as possible No far end receiver termination and poor differential trace routing may result in timing errors It is recommended that the trace length is no longer than 24 inches and that the differential output traces are kept close together and at equal lengths An example of the LVDS output using the ANSI standard default data eye and a time interval error TIE jitter histogram with trace lengths less than 24 inches on regular FR 4 material is shown in Figure 30 Figure 31 shows an example of when the trace lengths exceed 24 inches on regular FR 4 material Notice that the TTE jitter histogram reflects the decrease of the data eye opening as the edge deviates from the ideal position It is up to the user to determine if the waveforms meet the timing budget ofthe design when the trace lengths exceed 24 i
30. t on power up and can be changed by changing the configuration register For more information about this feature and others see the AN 877 Application Note Interfacing to High Speed ADCS via SPI at www analog com CSB SCLK DON T CARE wo wom ow m ple mm HARDWARE INTERFACE The pins described in Table 9 comprise the physical interface between the user s programming device and the serial port of the AD9230 11 All serial pins are inputs which is an open drain output and should be tied to an external pull up or pull down resistor suggested value of 10 kQ This interface is flexible enough to be controlled by either PROMS or PIC microcontrollers as well This provides the user with an alternate method to program the ADC other than using an SPI controller If the user chooses not to use the SPI interface some pins serve a dual function and are associated with a specific function when strapped externally to AVDD or ground during device power on The Configuration Without the SPI section describes the strappable functions supported on the AD9230 11 CONFIGURATION WITHOUT THE SPI In applications that do not interface to the SPI control registers the SDIO DCS and SCLK DFS pins can alternately serve as standalone CMOS compatible control pins When the device is powered up it is assumed that the user intends to use the pins as static control lines for the duty cycle stabilizer In this mode the CSB pin should be connected
31. t supply is AVDD 1 8 V this input is designed to withstand input voltages up to 3 3 V as shown in Figure 28 making the selection of the drive logic voltage very flexible AD9510 AD9511 AD9512 AD9513 AD9514 AD9515 OPTIONAL 1000 CLK ADC AD9230 11 07101 020 500 RESISTOR IS OPTIONAL Figure 27 Single Ended 1 8 V CMOS Sample Clock AD9510 AD9511 AD9512 AD9513 AD9514 AD9515 0 1yF OPTIONAL 500 1000 CMOS DRIVER CLK ADC AD9230 11 500 RESISTOR IS OPTIONAL Figure 28 Single Ended 3 3 V CMOS Sample Clock 07101 021 Clock Duty Cycle Considerations Typical high speed ADCs use both clock edges to generate a variety of internal timing signals As a result these ADCs may be sensitive to clock duty cycle Commonly a 596 tolerance is required on the clock duty cycle to maintain dynamic performance characteristics The AD9230 11 contains a duty cycle stabilizer DCS that retimes the nonsampling edge providing an internal clock signal with a nominal 5096 duty cycle This allows a wide range of clock input duty cycles without affecting the perform ance of the AD9230 11 When the DCS is on noise and distortion performance are nearly flat for a wide range of duty cycles However some applications may require the DCS function to be off If so keep in mind that the dynamic range performance can be affected when operated in this mode See the Configuration
32. tes at up to a 2 Low Power Consumes only 373 mW Q 200 MSPS 200 MSPS conversion rate and is optimized for outstanding 3 Ease of Use LVDS output data and output clock signal dynamic performance in wideband carrier and broadband allow interface to current FPGA technology The on chip systems All necessary functions including a track and hold reference and sample and hold provide flexibility in T H amplifier and voltage reference are included on the system design Use of a single 1 8 V supply simplifies chip to provide a complete signal conversion solution system power supply design 4 Serial Port Control Standard serial port interface SPI supports various product functions such as data formatting disabling the clock duty cycle stabilizer power down gain adjust and output test pattern generation 5 Pin Compatible Family 10 bit and 12 bit pin compatible family offered as AD9211 and AD9230 The ADC requires a 1 8 V analog voltage supply and a differential clock for full performance operation The digital outputs are LVDS ANSI 644 compatible and support twos complement offset binary format or Gray code A data clock output is available for proper output data timing Fabricated on an advanced CMOS process the AD9230 11 is available in a 56 lead lead frame chip scale package specified over the industrial temperature range 40 C to 85 Rev 0 Information furnished by Analog Devices is believed to be accurate and relia
33. the AD9230 11 to approximately 0 8 V p p differential This helps prevent the large voltage swings of the clock from feeding through to other portions of the AD9230 11 and preserves the fast rise and fall times of the signal which are critical to low jitter performance MINI CIRCUITS ADT1 1WT 1 1Z 0 1pF CF CLOCK ks INPUT fon 1000 0 1pF F 0 1 SCHOTTKY DIODES HSM2812 07101 017 Figure 24 Transformer Coupled Differential Clock If a low jitter clock is available another option is to ac couple a differential PECL signal to the sample clock input pins as shown in Figure 25 The AD9510 AD9511 AD9512 AD9513 AD9514 AD9515 family of clock drivers offers excellent jitter performance AD9510 AD9511 AD9512 AD9513 AD9514 AD9515 CLOCK INPUT CLK ADC AD9230 11 07101 018 500 RESISTORS ARE OPTIONAL Figure 25 Differential PECL Sample Clock AD9510 AD9511 AD9512 AD9513 AD9514 AD9515 0 1pF 0 1pF CLOCK o INPUT CLOCK g INPUT 500 RESISTORS ARE OPTIONAL Figure 26 Differential LVDS Sample Clock 07101 019 AD9230 11 In some applications it is acceptable to drive the sample clock inputs with a single ended CMOS signal In such applications CLK should be directly driven from a CMOS gate and the CLK pin should be bypassed to ground with a 0 1 capacitor in parallel with a 39 kO resistor see Figure 27 Although the CLK input circui
34. the Overrange True Output Bit through the serial port register 1 AGND and DRGND should be tied to a common quiet ground plane Rev 0 Page 12 of 28 AD9230 11 TYPICAL PERFORMANCE CHARACTERISTICS AVDD 1 8 V DRVDD 1 8 V rated sample rate DCS enabled T4 25 C 1 25 V differential input AIN 1 dBFS unless otherwise noted 200MSPS 10 3MHz 1 0dBFS SNR 62 9dB SNR dB 85 C ENOB 10 3 BITS SFDR 86dBc a amp z FDR dBc 25 C ul x 4 SFDR dBc 40 C S E 5 d 2 SNR dB 25 100 120 LLL BRL LU me 10 20 30 40 50 60 70 80 90 1008 0 50 100 150 200 250 300 350 400 4508 FREQUENCY MHz E ANALOG INPUT FREQUENCY MHz E Figure 6 64k Point Single Tone FFT 200 MSPS 10 3 MHz Figure 9 Single Tone SNR SFDR vs Input Frequency fin with 1 25 V p p Full Scale 200 MSPS 0 200MSPS SFDR dBFS 70 3MHz 1 0dBFS TAL 20 SNR 62 5dB ENOB 10 2 BITS SFDR 77dBc 5 SNR dBFS E 60 J A 5 o 80 4 n o 7 400 SFDR dBc SNR dB 120 140 5 0 10 20 30 40 50 60 70 80 90 100 90 80 70 60 50 40 30 20 10 0 8 FREQUENCY MHz AMPLITUDE dBFS E Figure 7 64k Point Single Tone FFT 200 MS

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