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Guangzhou zhouli microcontroller LPC2468 device user manual

1. 30 19 DMACCxDestAddr 30 19 DMACCO0DestAddr 0xFFE0 4104 DMACC1DestAddr 0xFFE0 4124 31 0 DestAddr DMA 0x0000 0000 30 9 3 DMACCOLLI 0xFFE0 4108 DMACCI1LLI 0xFFE0 4128 DMACCxLLI LD LLI 0 LLI DMA DMA DMA 30 20 DMACCxLLI
2. 25 4 i an PWM0 amp PWM1 amp PC 32 PC R W 0 0xE001 4010 0xE001 8010 PR PR PWMOPC PWMIPC TC 1 PC MCR MCR R W 0 OxE001 4014 0xE001 8014 TC PWMOMCR PWMIMCR MRO 0 MR0 MCR R W 0 0xE001 4018 0xE001 8018 TC TC TC PC PWMOMRO PWMIMRO MR0 TC PWM PWM1 MRI 1 MR1 MCR R W 0 0xE001 401C 0xE001 801C TC TC TC PC PWMOMR1 PWMIM
3. ARM7TDMI S 2 CHAIN RANGE 256 32 ARM7TDMI S ARM7TDMI S
4. 30 18 DMACCxSrcAddr 2 2 2 2 K 30 18 DMACCOSrcAddr 0xFFE0 4100 DMACC1SrcAddr 0xFFE0 4120 31 0 SrcAddr DMA 0x0000 0000 Rev 1 0 Date 2007 01 30 Guangzhou ZLGMCU Development Co Ltd 210 30 DMA GPDMA 30 9 2 DMACCODestAddr OxFFEO 4104 DMACC1DestAddr 0xFFE0 4124 2 DMACCxDestAddr DMA
5. 3 000 3 CAP K 23 7 T O 1 2 3 CCR 0xE000 4028 0xE000 8020 0xE007 0028 0xE007 4028 0 CAPORE CAPn 0 CAPn 0 0 1 TC 0 CRO 1 CAPOFE CAPn 0 CAPn 0 1 0 TC 0 CR0 2 CAPOI CAPn 0 CAPn 0 CR0 0 3 CAP1RE CAPn 1 CAPn 1 0 1 TC 0 CR1 4 CAP1FE CAPn 1 CAPn 1 1 0 TC 0 CR1 5 CAPII CAPn 1 CAPn 1 CR1 0 6 CAP2RE CAPn
6. TE Rev 1 0 Date 2007 01 30 Guangzhou ZLGMCU Development Co Ltd 159 26 ADC 26 5 3 A D AD0 9 9 3 AD0 Rev 1 0 Date 2007 01 30 Guangzhou ZLGMCU Development Co Ltd 160 27 DAC 27 DAC 27 1 10 e e HERR e 27 2 K 27 1 DAC 27 1 D A AOUT DACR
7. Rev 1 0 Date 2007 01 30 Guangzhou ZLGMCU Development Co Ltd 216 30 DMA GPDMA 0x 200 0x E00 Ox0A 0x0B 0x0C 0x0D 0x0E OxOF 0x10 0x11 30 3 LLI LLI 0x20000 0x0A200 0x0AE00 e 0x0A200 e e 1 32 e 3072 0xC00 e 16 e LLI 0x20010 LLI 0x20010 e 0x0B200 e e 1 32 e 3072 0xC00 e 16 e LLI 0x20020
8. 6 00000 5 00001 32 00100 32 00101 0 32 0 01000 0 32 0 01001 0 32 0 01010 0 32 0 01011 0 9 0 01100 0 8 0 01101 1 32 1 10000 1 32 1 10001 1 32 1 10010 1 32 1 10011 Date 2007 01 30 223 Rev 1 0 Guangzhou ZLGMCU Development Co Ltd 31 EmbeddedICE 31 2 1 9 1 10100
9. e PWM PWM PWM e PWM e PWM e I E PWM e 32 32 3 32
10. ISP INVALID_COMMAND ASCI ISP ISP CMD_SUCCESS ISP RAM 29 4 ISP ISP U lt gt 29 5 B lt gt lt gt 29 6 A lt gt 29 8 RAM W lt gt lt gt 29 9 R lt gt lt gt 29 10 P lt gt lt gt 29 11 RAM Flash C lt Flash gt lt RAM gt lt gt 29 12 G lt gt lt gt 29 13 E lt gt lt
11. 1 0 Unused 0 NA 2 PWMSEL2 PWM2 0 1 0 3 PWMSEL3 1 PWM3 PWMSEL2 0 4 PWMSEL4 1 PWM4 PWMSEL2 0 5 PWMSEL5 1 PWM5 PWMSEL2 0 6 PWMSEL6 1 PWM6 PWMSEL2 0 8 7 1 NA 9 PWMENAI1 PWMI1 0 0 PWM 1 PWM 10 PWMENA2 PWM2 PWMENA1 0 11 PWMENA3 PWMG3 PWMENA1 0 12 PWMENA4 PWM4 PWMENA1 0 13 PWMENA5 PWM5 PWMENA1 0 14 PWMENA6 PWM6 PWMENA1 0 31 15 Unused 0 NA Rev 1 0 Date 2007 01 30 Guangzhou ZLGMCU Development Co Ltd 153 PWM 4
12. SPI SPI SPI SPI SPI SPI SPEN e SPIIO H e SPI SPI e e SPI SPI IO CMOS IO H SPI VO SSEL SPI 18 4 2
13. SSPn SSELO 1 LO SSEL FS CS Rev 1 0 Date 2007 01 30 Guangzhou ZLGMCU Development Co Ltd 57 19 SSP0 1 19 1 A SPI SSI Microwire MISO SSPn DR M SIM ee s MISO0 1 VO MISO SSPn DX S SO S SSPn FS SSEL
14. RealMonitor 33 3 RealMonitor app_IRQDispatchO RealMonitor rm_irqhandler2 Rev 1 0 Date 2007 01 30 Guangzhou ZLGMCU Development Co Ltd 232 33 RealMonitor e app_IRQHandler0 RealMonitor irq RealMonitor RM_UNDEF_HANDLER RM_PREFETCHABORT_HANDLER RM_DATAABORT_HANDLER RealMonitor
15. Ili 17 4 UARTI1 17 4 APB CPU UART1 UART1 U1RX RXD1 UART1 RX CUIRSR RXD1 UIRSR UART1 RX FIFO CPU UART1 U1Tx CPU UART1 TX FIFO UITHR UART1 TX U1TSR U1THR TXD1 UART1 UIBRG UART1 TX U1BRG APB PCLK U1DLL U1DLM UART1 TX 16 NBAUDOUT Modem UIMCR UIMSR Modem UARTI1 handshaking
16. 1 0 1 NA 2 AAC 0 3 SIC PC 0 4 1 NA 5 STAC 0 6 I2ENC PC 0 7 1 NA AAC 1 PCONSET AA 0 SIC EC 1 DCONSET SI 0 STAC 1 F DPCONSET STA 0 I2ENC PC 1 2CONSET DEN 0 21 7 3 2C I2C O 1 2 STAT 0xE001 C004 0xE005 C004 0xE008 0004 FA PC FC PC 21 7 KC
17. K 28 12 6 Clk1 28 1 0 59 6 0 59 5 0 23 CH 5 1 28 29 30 31 3 0 6 9 1 365 EK 366 HJE 4 1 12 12 0 4095 2843 SEC 6 b 0 59 R W 0xE002 4020 MIN 6 0 59 R W OxE002 4024 HOUR 5 shr 0 23 R W OxE002 4028 DOM 5 W CH 1 28 29 30 31 R W 0xE002 402C DOW 3 WHA 0 6 H R W OxE002 4030 DOY 9 CE WEA 12365 CHEX 366 U R W OxE002 4034 MONTH 4 1 12 R W 0xE002 4038 YEAR 12 0 4095 R W 0xE002 403C 1 28 4 4 1 RTC 2 0 0 RTC
18. 8 Packet 3 0 Packet 7 4 EXTIN 0 TRACECLK A E EE PIPESTAT 2 0 LU TRACESYNC A H EE TRACEPKT 3 0 EE 32 5 ETM 29 32 3 ARM ARM IHI 0014E 32 3 ETM ETM ETM R W 000 0000 ETM RO 000 0001 WO 000 0010
19. UART1 RBR FIFO 0 1 4 BD RXD1 0 0 RXD1 1 U1LSR UL1FCR 0 UART1 RBR FIFO 0 o 1 5 FRX THRE UARTI THR THRE U1THR 1 0 UITHR 1 UITHR 6 UITHR U1TSR TEMT UITSR UITHR 1 TEMT TEMT 0 UITHR U1TSR
20. boot C 0 1073774592 512 lt CR gt lt LF gt RAM 0x4000 8000 512 Flash 0 29 8 8 lt gt lt gt 29 13 ISP G Flash RAM T Thumb A CHAT ARM CMD_SUCCESS ADDR_ERROR ADDR_NOT_MAPPED CMD_LOCKED PARAM _ERROR CODE_READ_PROTECTION_ENABLED RAM Flash ISP G 0 A lt CR gt lt LF gt ARM 0x0000 0000 29 8 9 lt gt lt gt 29 14 ISP E Rev 1 0 Dat
21. e ws_sel 1 TS e FIFO FIFO 0 Rev 1 0 Date 2007 01 30 Guangzhou ZLGMCU Development Co Ltd 121 22 FS 22 3 221 I I2SRX_CLK
22. 29 30 IAP 0 CMD_SUCCESS 1 INVALID_ COMMAND 2 SRC_ADDR_ERROR 3 DST_ADDR_ ERROR 4 SRC_ADDR_NOT_MAPPED 5 DST _ADDR_NOT_MAPPED Z 6 COUNT_ERROR 4 7 INVALID_SECTOR 8 SECTOR_NOT_BLANK KJET 9 SECTOR_NOT_PREPARED_ FOR_WRITE_OPERATION 10 COMPARE_ERROR 11 BUSY Flash 29 10 JTAG Flash Flash RAM I AP RAM Flash Rev 1 0 Date 2007 01 30 Guangzhou Z
23. Rev 1 0 Date 2007 01 30 Guangzhou ZLGMCU Development Co Ltd 45 17 UART 1 ER 17 20 UART1 UITER 0xE001 0030 6 0 1 NA 7 TXEN 1 THR 1 TXD 0 THR TX FIFO TX CTS XOFF F DC3 XON DC1 Tx CTS XON DC1
24. GPDMA 1 DMACIntStatus 2 2 DMACIntTCStatus 3 4 DMACIntTCCIr 1 DMACIntErrClr 1 LIT x 30 13 GPDMA ART 4 GPDMA Rev 1 0 Date 2007 01 30 Guangzhou ZLGMCU Development Co Ltd 218 30 DMA GPDMA I
25. 3 0 UnLSR UnLSR 3 0 FE UnFCR 0 Rx UARTn RBR FIFO 0 1 4 RXDn 0 BD 0 RXDn 1 UnLSR UnFCR 0 UARTn RBR FIFO 0 1 5 UARTn THR THRE UnTHR 1 0 UnTHR
26. NC RTC 28 1 ILR 2 R W 0xE002 4000 CTC 15 RO 0xE002 4004 CCR 4 R W 0xE002 4008 CIR 8 R W 0xE002 400C AMR 8 R W 0xE002 4010 CTIME0 32 0 RO 0xE002 4014 CTIMEI 32 1 RO 0xE002 4018 CTIME2 32 2 RO 0xE002 401C SEC 6 R W 0xE002 4020 MIN 6 R W 0xE002 4024 Rev 1 0 Date 2007 01 30 Guangzhou ZLGMCU Development Co Ltd 164 28 RTC RAM G G lle e e
27. PCLK CAP CTCR 3 2 rH LI CAP CAP CTCR 1 0 CAP PCLK 2 CAP PCLK 1 4 CAP
28. 5 0 0 59 NA 7 6 1 NA 13 8 0 59 NA 15 14 1 NA 20 16 0 23 NA 23 21 1 NA 26 24 K 0 6 NA 31 27 1 NA 28 4 3 2 1 CTIME1 0xE002 4018 1 T 28 10 1 CCTIME1 0xE002 4018 4 0 CH 1 28 29 30 31 NA 7 5 1
29. SSPn amp CRO 0 R W 0 SSPOCR0 0xE006 8000 SSP1CR0 0xE003 0000 CRI 1 R W 0 SSPOCR1 0xE006 8004 SSP1CR1 0xE003 0004 DR FIFO R W 0 SSPODR 0xE006 8008 FIFO SSP1DR 0xE003 0008 SR RO 0 SSP0SR 0xE006 800C SSP1SR 0xE003 000C CPSR R W 0 SSPOCPSR 0xE006 8010 SSP1CPSR 0xE003 0010 IMSC R W 0 SSPOIMSC 0xE006 8014 SSP1IMSC 0xE003 0014 RIS R W 0 SSPORIS 0xE006 8018 SSP1RIS 0xE003 0018 MIS R W 0 SSPOMIS 0xE006 801C SSP1MIS 0xE003 001C ICR SSPICR FESE ATTA o R W NA SSPOICR 0xE006 8020 SSP1ICR 0xE003 0020 DMACR DMA R W 0 SSPODMACR 0xE006 8024 SSP1DMACR 0xE003 0024 1 Rev 1 0 Date 2007 01 30 Guangzhou ZLGMCU Development Co Ltd 64 O 19 5 1 SSPn
30. DMA muted 32 Cchunk 32 I2S FIFO muted FIFO 32 22 2 Rev 1 0 Date 2007 01 30 Guangzhou ZLGMCU Development Co Ltd 126
31. Rev 1 0 Date 2007 01 30 Guangzhou ZLGMCU Development Co Ltd 211 30 DMA GPDMA 30 21 DMACC0Control 0xFFE0 410C DMACC1Control 0xFFE0 412C 11 0 TransferSize GPDMA 0 GPDMA 14 12 SBSize 0 DMACBREQ 17 15 DBsize
32. 1 8V z Rev 1 0 Date 2007 01 30 Guangzhou ZLGMCU Development Co Ltd 163 28 RTC RAM 28 3 RTC CLK32k PRESCALER 28 1 RTC 28 4 RTC 4 8 miscellaneous 28 4 2 8 28 4 4 8 28 5 RTC 28 1
33. 18 6 6 SPI SPTSR 0xE002 0014 SPI 1 18 9 SPI SPTSR 0xE002 0014 2 0 1 NA 3 ABRT 0 4 MODF 0 5 ROVR 0 6 WCOL 0 7 SPIF SPI 0 18 6 7 SPI SOSPINT 0xE002 001C SPIO 18 40 SPI SOSPINT 0xE002 001C
34. Flash boot 2 2 0 GB 8k BOOT BLOCK OXIFEP PFEF FLASH 2 0GB 8kB BOOT BLOCK H Wr Je 0x7FFF E000 0x0007 FFFF 8k BOOT BLOCK 0x0007 E000 BOOT BLOCK 0 0 GB 0x0000 0000 29 1 29 4 1 1 ARM 0x0000 0014 Wr In sr 259 IJ 2 O boot boot Flash pj lt 0 signature 0x0000 0000 Flash signature 0 0
35. 0xE007 C030 6 0 1 NA 7 TXEN 1 THR 1 TxD 0 JA THR TX FIFO XOFF DC3 XON DC1 16 4 UART0 UART2 UART3 16 2 APB CPU UART UARTn UnRx RXDn UARTn RX CUnRSR RXDn UnRSR UARTn RX FIFO UARTn UnTx CPU FIFO CUnTHR 4
36. 15 1 NA 28 4 2 3 CCR 0xE002 4008 4 Rev 1 0 Date 2007 01 30 Guangzhou ZLGMCU Development Co Ltd 166 28 RTC RAM 28 5 CCR 0xE002 4008 0 CLKEN 1 0 NA 1 CTCRST CTC 1 CCR 1 0 NA 3 2 CTTEST 0 NA 4 CLKSRC 0 CTC NA NXP
37. 8 16 18 3 SPI 18 1 SPI 4 8 3 SCK SSEL CPHA 0 MOSI MISO CPHA 1 MOSI MISO CPOL 0 1 SSEL CPHA 0 SSEL CPHA 1 Rev 1 0 Date 2007 01 30 Guangzhou ZLGMCU Development Co Ltd 48 18 SPI SSEL CPHA 0 CPHA 1 18 1 SPI CPHA 0 CPHA 1 18 1
38. 28 3 ILR 0xE002 4000 0 RTCCIF 1 1 NC 1 RTCALF 1 1 NC 2 RTSSF 1 CISS NC 7 2 1 NA 28 4 2 2 CTCR 0xE002 4004 CCR 0 CTC 28 4 CTCR 0xE002 4004 14 0 CTC 32 768 RTC NA 32 768 28 8 1
39. e CPSM 1 CPSM 20 14 MCICommand Rev 1 0 Date 2007 01 30 Guangzhou ZLGMCU Development Co Ltd 82 20 SD MMC 20 14 MCICommand 0xE008 C00C 5 0 CmdIndex 0 6 Response CPSM 0 7 LongRsp CPSM 136 0 8 Interrupt CPSM 0 9 Pending CPSM CmdPend 0 10 Enable CPSM 0 3 MCLK 2 PCLK 20 15 20 15
40. ISP Flash Go Unlock Rev 1 0 Date 2007 01 30 Guangzhou ZLGMCU Development Co Ltd 177 29 Flash ISP Unlock 29 8 ISP 29 4 2 ISP ASCI CR LF lt CR gt lt LF gt ISP lt CR gt lt LF gt ASCH UU 29 4 2 1 ISP _0 _1 _n lt CR gt lt LF gt
41. SD I2S TAT 0x40 0x48 0x38 AA 1 0x68 0x78 0xB0 20 18 0x10 PC SLA W ED AT 21 8 3 21 12 I2ADR I2CON T 21 15 I2C0ADR 12C1ADR i 6 5 4 3 2 1 0 7 GC 7 PC LSB GC EC 0x00 Rev 1 0 Date 2007 01 30 Guangzhou ZLGMCU Development Co Ltd 1
42. TCK nTRST nTRST EmbeddedICE RTCK JTAG ARM7TDMI S Multi ICE ARM Multi ICE 72 ARM DAI 0072A 31 5 JTAG JTAG DBGEN DBGEN 0 JTAG 31 6 EmbeddedICE 16 ARM ARM7TDMI S rev 4 ARM DDI 0234A DBGEN 1 JTAG i 31 2 ARM7TDMI S 31 2 EmbeddedICE
43. 2 0 SubSecSel SubSecSel H NC 000 16 32 768 kHz 488 001 32 32 768 kHz 977 010 64 32 768 kHz 1 95 011 128 32 768 kHz 3 9 ZPR E 100 256 32 768 kHz 7 8 ZPM E 101 512 32 768 kHz 15 6 110 1024 32 768 kHz 31 25 lll 2048 32 768 kHz 62 5 6 3 Unused
44. GPDMA pack IRIRI Cunpack 30 3 1 8 GPDMA AHB endian Rev 1 0 Date 2007 01 30 Guangzhou ZLGMCU Development Co Ltd 198 30 DMA GPDMA GPDMA 16 32 32 30 1 j 30 1
45. RTCX1 2 RTC APB PCLK RTCX1 2 32 kHz 1 RTC m RTC RTC epg EL nir B WRF PCLK RTC PCLK RTC PLL APB RTC RTC PCLK RTCX RTCX1 2 32 kHz RTC APB PCLK RTC R
46. 1 1 IC 1 SDA PC PC SCL sm o H ITF Ho PC 1 PC _21 8 1 1 2 9 OT IW 1 2 3 4 SCL 1 2 SDA PC 1 T C 3 PC PC SDA
47. 1 5 0x24 I2CONSET STA AA 2 0x08 I2CONCLR SI 3 4 5 21 9 9 5 0x80 ACK 1 DAT 2 1 5 3 5 0x0C DPCONCLR SI AA 4 5 6 7 0x04 I2CONSET AA 0x08 I2CONCLR SI L 8 21 9 9 6 0x88 1 5 0x04 I2CONSET AA 2 0x08 I2CONCLR SI 3 Rev 1 0 Date 2007 01 30 Guangzhou ZLGMCU Development Co Ltd 118 21 ec Eco sc1 2C2 21 9 9 7 0x90
48. 689 12 F4 http www zlgmcu com m A o 8 30 11 50 FF 1 30 5 30 8 30 11 50 E mail hk www zlgmcu com E mail 86 020 22644358 22644359 22644360 22644361 zlgmcu support zlgmcu com 689 12 F4 510630 020 38730972 38730976 38730916 38730917 38730977 020 38730925 http www zlgmcu com 203 204 020 87578634 87569917 020 87578842 113 A FE 1207 1208 010 62536178 62536179 82628073 010 82614433 217 502 0571 28139611 28139612 28139613 28139615 28139616 28139618
49. DMACRawIntTCStatus DMACRawInt ErrorStatus HrH r5E W Z Ja DMACIntTCStatus DMACIntErrorStatus DMA DMACIntStatus DMACIntTCStatus DMACIntErrorStatus DMACIntTCClear the DMACIntErrClr 30 12 1 DMA 1 DMACIntStatus 2 DMACIntTCStatus 3 DMACIntErrorStatus 4 5 DMACIntTCCIr 1 DMACIntErrClr 1 30 12 2 GPDMA
50. PC 7 7 LSB GC 0x00 21 6 3 7 I2ADR 7 8 0x00 21 6 4 2DAT 8 IDAT MSB f 7 ID AT MAB Date 2007 01 30 DD AT ID AT Rev 1 0 Guangzhou ZLGMCU Development Co Ltd 94 21 ec Eco sc1 2C2 l ee 21 6 5
51. 1 6 21 9 10 2 0xB0 R W ACK ACK STA DDD AT 0x24 I2CONSET STA AA 0x08 DCONCLR SI 1 o O e G N Rev 1 0 Date 2007 01 30 Guangzhou ZLGMCU Development Co Ltd 119 21 lC Eco sc1 2C2 21 9 10 3 0xB8 ACK ACK DDD AT 0x04 DCONSET AA 0x08 DCONCLR SI 1 21 9 10 4 0xC0 1 0x04 I2CONSET AA 2 0x08 I2CONCLR SI 3
52. 17 3 1 UART1 U1RBR 0xE001 0000 DLAB 0 UIRBR UART1 RX FIFO LSB bit0 WJ MSB 0 8 UIRBR UILCR DLAB 0 UIRBR jani HT PE FE BI RBR FIFO RBR 2 E UILSR U1RBR 17 3 UART1 U1RBR 0xE001 0000 DLAB 0 7 0 RBR UART UART1 RX FIFO 3 H KFT 17 3 2 UART1 U1THR 0xE001 0000 DLAB 0 UITHR UART1 TX FI
53. F o 31 2 1 NA 24 5 24 1 PCLK WDCLK Y WDFEED RIJID IRJA hH E RTC pclk j wdclk RC WDCLKSEL WDMOD O gt gt 24 1 Rev 1 0 Date 2007 01 30 Guangzhou ZLGMCU Development Co Ltd 142 25 PWM0 PWMI1 25 1 25 PWMO PWM e PWM PWM PWM PWM0 PWMI1 e e 7 6 3 PWM
54. 0 0 32 2007 01 30 Rev 1 0 Guangzhou ZLGMCU Development Co Ltd 202 30 DMA GPDMA 30 6 1 GPDMA GPDMA DMACConfiguration DMA 30 8 13 DMACConfiguration 0xFFE0 4030 30 6 2 GPDMA GPDMA DMACEnbldChns DMA 30 6 4 DMA e DMACConfiguration DMA GPDMA 30 9 6
55. 25 2 PWM LPC2400 PWM PCLR 7 4 PWM 1 PWM 3 AJEA PWM 3 PWM MR0 PWM PWM PWM PWM
56. ISP ISP IRC PLL 14 748MHz CCLK ISP 29 9 8 ISP 29 4 1 Boot Flash 8kB Flash 0x0007 E000 F boot boot 0x7FFF E000 Flash boot ISP IAP RAM T RAM Flash boot boot 64 0x0000 0000 Rev 1 0 Date 2007 01 30 Guangzhou ZLGMCU Development Co Ltd 176 29 Flash
57. WDRESET 1 0 WDINT WDRESET WDEN 1 WDINT WDEN WDRESET WDTOF WDINT VIC Rev 1 0 Date 2007 01 30 Guangzhou ZLGMCU De
58. 28 1 HOUR 5 R W 0xE002 4028 DOM 5 HH CH R W 0xE002 402C DOW 3 R W 0xE002 4030 DOY 9 HH CE R W 0xE002 4034 MONTH 4 R W 0xE002 4038 YEAR 12 R W 0xE002 403C a 8 en AP an ALSEC 6 R W 0xE002 4060 ALMIN 6 R W 0xE002 4064 ALHOUR 5 R W 0xE002 4068 ALDOM 5 R W 0xE002 406C ALDOW 3 R W 0xE002 4070 ALDOY 9 R W 0xE002 4074 ALMON 4 R W 0xE002 4078 ALYEAR 12 R W 0xE002 407C PREINT 13 R W 0 0xE002 4080 PREFRAC 15 R W 0 0xE002 4084 1 RTC RTC 28 4 1 RTC LR CHR AMR
59. 0 9 8 MATn 0 0 1 3 EM3 3 TC MR3 0 11 10 1 MATn 0 0 1 5 4 EMCO 0 0 23 9 00 7 6 EMC1 1 1 23 9 00 9 8 EMC2 2 2 23 9 00 11 10 EMC3 3 3 K 23 9 00 15 12 1 NA 23 9 EMRI 11 10 EMR 9 8 o P 00 01
60. WDMOD WDMOD WDEN WDEN WDFEED 0xAA WDFEED 0x55 APB PCLK K 24 5 WDFEED 0xE000 0008 7 0 Wu 0xXAA 0x55 NA 24 4 4 WDTV 0xE000 000C WDTYV 32 6 WDCLK
61. VALUE 1024X VREF VssA VREF D A Jan E Vonavy Vss VSSA 27 3 DACR 0xE006 C000 5 0 D A K 27 2 D A DACR 0xE006 C000 5 0 1 NA 15 6 VALUE Aout 0 VALUE 1024 XVREF VssA 16 BIAS 0 DAC 1xs 700pA 0 1 DAC 2 Shs 3504A 31 17
62. 0 DMACBREQ 20 18 SWidth AHB 0 23 21 DWidth AHB 0 y CT lt Ho 25 24 1 NA 26 SI 0 27 DI
63. 0 IntErClr0 1 0 IntErrorStatus0 1 IntErClrl 1 1 IntErrorStatus1l 312 1 NA 30 8 6 DMACRawlntTCStatus 0xFFE0 4014 DMACRawIntTCStatus DMA 1 30 9 DMACRawIntTCStatus 30 9 DMACRawlntTCStatus 0xFFE0 4014 0 RawIntCStatus0 0 1 RawIntTCStatusl 1 31 2 1 NA 30 8 7 DMACRawlntErrorStatus 0xFFE0 4018 DMACRawIntErrorStatus
64. 29 8 7 RAM Flash lt Flash gt lt RAM gt lt gt cc 186 20 8 9 lt 3S lt Se un SSSR NS u uu a Q Du ata 187 29 8 9 lt gt lt gt a anna nn 187 29 8 10 lt gt lt gt 188 29 8 11 ID 0 188 590 Boot 189 29 8 13 lt 1 gt lt 2 gt lt gt 189 29 8 14 ISP 0 189 D VN A E 190 29 9 1 192 29 9 2 RAM Flash i 192 29 9 3 nn 193 29 9 4 De E a 193 20 9 5 a ID E a qu u Sun E E A AE 194 29 9 6 Boot 194 29 9 7 lt 1 gt lt 2 gt lt gt 194 29 9 8 EA HISP rn od 195 29 9 OTAPI SO r E A E E 195 29 10 JTAG FLASH nE A O ire eae ae o E aeae aa Er a ani iaa 195 30 DMA GPDMA csc 196 jO T 30 2 EI 9 DIV VN I E a 30 JR 30 3 1 GPDMA a aaaaannnsssnnsssnnnsssnannsnsnasssnasssnanssssasasa 303 TAN 30 3 1 2 198 30 3 1 3 DMA 30 3 1 4 198 303 5 PR K ron na a AA a R An 3031 6AHBEI
65. MCIDATO 20 SD MMC EB _ 20 6 CRC K 20 6 CRC 010 101 CRC 20 4 3 11 K 20 7 20 5 12 MCIStatus 0xE008 C034 20 7 TxFifoFull FIFO TxFifoEmpty FIFO TxFifoHalfEmpty FIFO TxDataAvlbl FIFO TxUnderrun FIFO RxFifoFull FIFO RxFifoEmpty FIFO RxFifoHalfFull FIFO RxDataAvlbl FIFO RxOverrun FIFO DataBlockEnd StartBitErr
66. UIIR ABEOInt UIER ABEOIntEn HMH K 5 U1ACR ABTOIntClr ABEOIntEn DIVADDVAL 0 E DIVADDVAL gt 0 UART1 Rx UIFDR UIDLM U1DLL U1ACR UARTI1 PCLK A SUARTI w lt x PCLK Eyki 2 ERA E iy EARR 12 17 3 15 AT UART1 ULIACR U1DLL U1DLM A a ASCII A 0x41
67. 0 PCAPn 0 0 0 1 PCAPn 0 TC CRO 1 PCAPn 0 0 0 1 PCAPn 0 TC HERA CRO 2 R PCAPn 0 0 0 1 PCAPn 0 CRO 3 PCAPn 1 0 0 1 PCAPn 1 TC CR1 4 PCAPn 1 0 0 1 PCAPn 1 TC HERA CR1 5 R PCAPn 1 0 0 1 PCAPn 1 CRI 31 6 I 1 NA 1 PWM0 25 5 6 PWM PWMOPCR 0xE001 404C PWM1PCR 0xE001 804C PWM PMW 25 10 25 10 PWM PWMOPCR 0xE001 404C PWM1PCR 0xE001 804C
68. 26 4 1 A D ADOCR 0xE003 4000 A D A D A D A D A D 26 3 A D ADOCR 0xE003 4000 7 0 SEL AD0 7 0 AD0 0 0x01 AD0 0 7 AD0 7 0x01 Rev 1 0 Date 2007 01 30 Guangzhou ZLGMCU Development Co Ltd 156 f UsT 26 ADC
69. 31 2 EmbeddedICE EmbeddedICE EmbeddedICE ARM7TDMI S JTAG 31 3 ARM7TDMI S JTAG ARM7TDMI S FAAA JTAG JTAG ARM7TDMI S EmbeddedICE 1248 EmbeddedICE ARM7TDMI S EmbeddedICE 12 2 1 ARM7TDMI S EmbeddedICE
70. e WDTC e WDMOD e WDFEED 0xAA 0x55 e 0x0000 0000 WDTOF WDTOF 2 PCLK WDCLK PCLK APB WDCLK clock domain WDMOD WDTC APB Rev 1 0 Date 2007 01 30 Guangzhou ZLGMCU Development Co Ltd 139 24 WDT WDCLK 3 WDCLK WDCLK WDCLK
71. DMACCxControl DMA 9 Rev 1 0 Date 2007 01 30 Guangzhou ZLGMCU Development Co Ltd 220 30 DMA GPDMA o bbb 1 GPDMA 2 TC 3 GPDMA LLI Rev 1 0 Date 2007 01 30 Guangzhou ZLGMCU Development Co Ltd 221 31 EmbeddedICE 31 EmbeddedICE 31 1 e e JTAG ARM7TDMI S e ARM7TDMI S e
72. PSTXRATE 22 12 I2SRXRATE 0xE008 8024 9 0 rx_rate DS 1 PCLK 10 0 PCLK PS 15 10 Unused 0 22 5 FS PS 8 16 32 TS FIFO FIFO o Crue 0 e 0 4 8 1 2 16 3 1 32 FIFO
73. 3 SPI SPIF SPIF SPI 4 SPI 5 SPI 6 2 SPI SPIF SPIF 18 4 4 SPI SPIF SPI SPIF ROVR SPI SPI SPI SPI
74. LSB LSB SSP SK 19 7 Microwire 19 4 3 1 Microwire CS SK Microwire CS SSP SK SK CS SK 19 8 SSP SK CS SSP SK 2 SK CS SK toi betu 2 tox HOLD SK 19 8 Microwire Date 2007 01 30 Rev 1 0 Guangzhou ZLGMCU Development Co Ltd 63 19 SSP0 1 19 5 SSP 19 2 19 2 SSP
75. 4 4 PC RSN AA SCL SDA 1 ZC 2 C 21 7 2 IC 12C 0 1 2 JCONCLR 0xE001 C018 0xE005 C018 0xE008 0018 I2CONCLR PCON I2CON C 1 TC 0 T Rev 1 0 Date 2007 01 30 Guangzhou ZLGMCU Development Co Ltd 98 21 lC Eco sc1 2C2 C ew Re l llg 21 6 C CI2C 0 1 2 JCONCLR 0xE001 C018 0xE005 C018 0xE008 0018
76. DPSM EEE WAIT S WAITR e DPSM EE WAIT S FIFO DPSM EE SEND e DPSM WAIT_R DPSM RECEIVE 20 4 3 7 DPSM MCICLK MCICLK DPSM 6 20 6 Rev 1 0 Date 2007 01 30 Guangzhou ZLGMCU Development Co Ltd 75 20 SD MMC FIFO CRC CRC k RxFIF0 CRC HRFIFO Ei 20 6 IDLE CFW MCIDAT 3 0 HLZ DPSM
77. PC STA STO ITC STO 21 8 10 SCL SDA 2C SDA SCL C SCL PC SCL SDA SCL 21 16 STA EC EC SDA SCL 2 PC SDA 0x08 SDA
78. PS SD SCK so qm OD SCK sp VEIN n 1 n i n 1l 1 224 FS Rev 1 0 Date 2007 01 30 Guangzhou ZLGMCU Development Co Ltd 122 22 FS 22 4 K 22 2 PS K 222 S I2SDAO TS R W 0xE008 8000 I2SDAI TS R W 0xE008 8004 I2STXFIFO FIFO 8X32 FIFO WO 0xE008 8008 I2SRXFIFO FIFO 8X32 FIFO RO 0xE008 800C I2SSTATE T
79. 0 UIRBR U1LSR 0 UART1 RBR FIFO 0 RDR AZI UILSRO 0 UIRBR 1 UIRBR 1 OE U1LSR UILSR 1 0 OE UARTI RSR UART1 RBR FIFO U1LSR 1 UART1 RBR FIFO UART1 RSR 0 1 UILSR 0 Pas UILSR 2 UIFCR 0 UART1 RBR FIFO 0 1 3 0 UILSR 0 FE U1LSR 3 UIFCR 0 W RX
80. Angel Angel Angel Multi ICE ARM EmbeddedICE Multi ICE RealMonitor Angel Multi ICE Multi ICE JTAG DCC Angel RealMonitor ROM RealMonitor 33 4
81. STO STO 1 PC STO 1 STO STO STO SI PC PC F8 AE SL SI EMET SCL SCL SI SI DCONCLR SIC 1 AA SCL SDA 1 2 I2ADR CGC EA a 3 Tc
82. MISO MOSI 1 2 SCK MOSI SCK SCK SSEL 1 2 SCK SCK SCK SSEL CPHA 0 SSEL SCK SSEL 19 4 2 5 CPOL 1 CPHA 1 SPI CPOL 1 CPHA 1 SPI 19 5
83. e GPDMA 8 E30 27 30 27 DMA GPDMA GPDMA GPDMA GPDMA GPDMA 30 13 1 DMA DMA 1 DMA 2 DMA 3 GPDMA DMA DMA GPDMA AHB 4
84. SCL PC CDAT E I2CONSET PC DPCONSET PC 1 DCONCLR C 1 21 6 9 5 PC 5 5 IC 26 21 7 PC 7
85. 20 2 0 1 1 Ta T CRC7 39 8 32 45 40 6 46 1 1 47 1 0 MCI CRC 48 20 3 136 20 4 20 4 CRC CMDI CRC 20 3 0 1 1 7 1 7 CRC7 1111111 39 8 32 45 40 6 46 1 0 47 1 0 K 20 4 0 1 1 127 1 127 CID Ek CSD CRC7 133 128 6 111111 134 1 1 135 1 0 6 48 136 20 5 5 TAT MCICommand 0xE008 C00C 20 5 20 5 12 0xE008 C034 Date 2007 01 30 KE MCIStatus 74 Rev 1 0 Guangzhou ZLGMCU Developm
86. 30 24 DMACC1Control 28 AHB HPROT 1 0 0 1 29 0 AMBA AHB HPROT 2 0 1 30 o AMBA 8 8 AHB HPROT 3 0 1 30 9 6 DMACCOConfiguration 0xFFE0 4110 DMACC1Configuration 0xFFE0 4130 2 DMACCxConfiguration 17
87. MR0 PWM PWM J pt 3 PWM MR0 Rev 1 0 Date 2007 01 30 Guangzhou ZLGMCU Development Co Ltd 143 25 PWMO PWM W C L V PWM PWM PWM PWM PWM 25 1 PWM PWM PWM0 PWM PWM1 PWM0 PWM
88. 14 JTAG EmbeddedICE IEEE 1149 1 1990 Rev 1 0 Date 2007 01 30 Guangzhou ZLGMCU Development Co Ltd 222 Ennn 31 EmbeddedICE 31 4 3 31 1 EmbeddedICE TMS TMS TAP TCK TMS TDI TMS TCK TDI TDO
89. FIFO RTS FIFO RTS1 UART RTS1 UART UART RTS1 UART RTS RTSen UARTI1 RTS1 RTS1 RTS1 RTS FIFO 8 NFE LK FIFO 4 RTS1 Date 2007 01 30 FIFO RTS1 RTS RTSen UARTI1 RTS RTSen UART1 type550 UIFCR 0x2
90. DMA LLI 0x20000 GPDMA LL LLI 0x20070 e 0x11200 e e 1 32 e 3072 0xC00 16 e LLI 0x0 LLI 0 DMA Rev 1 0 Date 2007 01 30 Guangzhou ZLGMCU Development Co Ltd 217 30 DMA GPDMA ARM 30 12 AHB LLI DMACCxControl DMACCxConfiguration
91. GPDMA 1 6 GPDMA 0 DMA GPDMA DMA DMA 7 DMA GPDMA FIFO 8 DMA 9 GPDMA 0 DMA GPDMA DMA DMACCxLLI 0 DMACCxSrcAddr DMACCxDestAddr DMACCxLLI DMACCxControl 2 DMACCxLLI 0 DMA 30 13 3 DMA DMA 1
92. ACK ACEK 1 IDAT 2 5 0x0C DCONCLR SI AA 3 21 9 9 8 0x98 1 5 0x04 I2CONSET AA 2 j 0x08 DPCONCLR SI 3 21 9 9 9 0xA0 1 0x04 I2CONSET KEM AA 2 0x08 I2CONCLR SI 3 21 9 10 21 9 10 1 0xA8 ACK ACK 1 IDD AT 2 j 0x04 I2CONSET REMM AA 3 5 0x08 I2CONCLR SI 4 5
93. m m 7 334 TA En aR A a A a ANS 233 33 REALMONITOR 4 237 4 QE aaa aaa wanaaqaswassauwasqwaqawawqayapawaaasayawqsawakasayasskawisasyasss 240 3 240 DA IAEA SA E 241 Rev 1 0 Date 2007 01 30 Guangzhou ZLGMCU Development Co Ltd XIII 16 1 e 16 FIFO e 550 TY 16 CUART 0 2 3 A 028 16 UART 0 2 3 e FIFO 1 4 8 14 FW e e autobaud BI e UART3 IDA 16 2 3 16 1 UARTO RXD0 RXD2 RXD3 TXD0 TXD2 TXD3 16 3 UART

Guangzhou zhouli microcontroller LPC2468 device user manual

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