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Almel ATmega128 ATmega128L programming Flash Manual

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1. cian ae SCL Bumus see tae ET See ene SCL SCL Figure 92 SCL SCL from master A SCL from master B SCL Bus Line 4 Rg Masters Start 7 Masters Start Counting Low Period Counting High Period SDA SDA SDA
2. Vcc GND AMEL z AMEL VO Figure 33 Figure 30 AVR Figure 33 PUOExn PUOVxn C i DDOExn DDOVxn PVOExn PVOVxn Pxn DATA BUS DIEOExn Gan DIEOVxn RESET lt SLEEP ii SYNCHRONIZER RPx clk yo Dixn lt AlOxn PUOExn Pxn PULL UP OVERRIDE ENABLE PUD PULLUP DISABLE PUOVxn Pxn PULL UP OVERRIDE VALUE WDx WRITE DDRx DDOExn Pxn DATA DIRECTION OVERRIDE ENABLE RDx READ DDRx DDOVxn Pxn DATA
3. AVR SREG Bit 7 6 5 4 3 2 1 0 R W R W R W R W R W R W R W R W 0 0 0 0 0 0 0 0 Bit 7 1 1 RETI SEI CLI Bit 6 T ELES BLD ABST AAT BST T BLD TT BitS H H BCD Bit 4 S S N V S N 2 V Bit 3 V 2 2 Bit 2 N
4. 168 AT mega12 8 memme 2467L AVR 05 04 BE ATmega128 2467L AVR 05 04 Figure 83 16 8 U2X 1 RxD REA 0 Figure 83 Fi PP et eee U2X 0 0 0 1 2 3 4 5 2 3 n On y o gt n gt n gt v Sample il U2X 1 0 1 RxD 1 0 8 9 10
5. Table 75 R D DS slow S 1 D S Sr fast D 1 S Sy D 5 10 S 16 S 8 Se Sr 8 Sr 4 Sm Sv 9 Sv 5 Row Ress Table 75 Table 76 Table 75 U2X 0 D
6. ADC ADC P 213 ADC P 210 BOD BODEN BOD P 44 BOD BOD
7. PC BLB02 BLB12 P 267 P 55 RESET E INTO 0 MCU MCUCR IVSEL Flash P 55 BOOTRST Flash P 255 RWW Read While Write 1
8. Flash 1 Boot Loader A MEL 261 AMEL Flash 2 P 263 o SPM Z RAMPZ X0000011 SPMCSR SPM R1 R0 Z PCPAGE Z EER RWW NRWW K JEFE NRWW CPU
9. 9 UCSZ 7 TXB8 1 fiz TXB8 1 TXB 0 9 1 UCSRA MPCM 2 UCSRA RXC 3 UDR WAS UCSRA MPCM MPCM 1 4 MPCM 1 5 MPCM
10. BYPASS AVR AVR RESET AVR AVR_RESET EXTEST EXTEST HS JTAG IR EXTEST SAMPLE PRELOAD SAMPLE PRELOAD AVR JTAG TAP JTAG JTAGEN MCUCSR JTD HAE JTAG JTAG TCK Bypass 236 AT mega12 8 mn rYs 2467L AVR 05 04 BE ATmega128
11. PWM PWM 8 Max TCNTO MAX Figure 40 TCNT0 PWM MRE PWM TCNT0 OCRO TCNTO Figure 40 PWM OCn Interrupt Flag Set OCRn Update TOVn Interrupt Flag Set lt 4 y Y Y Y YY Yy Z Y TCNTn Y y y Y Y OCn COMn1 0 2 OCn NG COMn1 0 3 Period 1 pl 2 3 BOTTOM T C TOV0 PWM OC0 PWM COM01 0 2 PWM COM01 0 3 PWM P 96Table 55 OCO OCRO0O TCNTO OCO
12. MCU CKSEL P 34 ATmega128 5 Vpo7 it MCU RESET MCU Veo7 MCU aes Pi 1 MCU P 235 IEEE 1149 1 JTAG Figure 22 DATA BUS MCU Control and Status Register MCUCSR LL LL LL 5E Ok PEN D Ol O LL Le ayo oje gt POR m Pull up Resistor vec Power On Reset Circuit BODEN Brown Out BODLEVEL Reset Circuit Pull up Resistor 9 EE SPIKE RESET Reset Circuit JTAG Reset Watchdog Register Timer Watchdog Oscillator Clock Generator
13. 1 0 AMEL z 1 O AMEL O Figure 30 I O Figure 30 1 0 DATA BUS SYNCHRONIZER WDx WRITE DDRx PUD PULLUP DISABLE RDx READ SLEEP Pos EP CONTROL WPx WRITE PORT clkyo VO CLOCK RRx READ PORTx REGISTER RPx READ PORTx PIN Note 1 WPx WDx RRx RPx RDx clkyo SLEEP PUD DDxn PORTxn PINxn P 81 l O DDxn DDRx PORTxn PORTx PINxn PINx DDxn DDxn 1 Pxn A PORTxn 1 PORTxn HS
14. SDA 184 AT mega12 8 mw rrr 2467L AVR 05 04 2467L AVR 05 04 Figure 93 SDA from Master A Master B START ATmega128 Master A loses D Aaa SDA SDA a SDA from Pos SDA Line Synchronized SCL Line 2 REPEATED START STOP REPEATED START STOP SLA R W AMEL a E oe E PLS LS 185 TWI Scl SDA
15. P 41 Flash and clk CPU Figure 18 Asynchronous Timer Counter AVR Clock Control Unit Clk easy Reset Logic Watchdog Timer Source clock Watchdog clock Clock Multiplexer Watchdog Oscillator Timer Counter External RC Crystal Low Frequency Calibrated RC Oscillator Oscillator External clock Oscillator Crystal Oscillator Oscillator CPU AVR CPU VO VO SPI USART lHMO VO TWI cko Flash Flash CPU
16. VO clk clk o 8 TCNTn MAX 1 MAX BOTTOM BOTTOM 1 TOVn Figure 70 CTC OCF2 140 ATmega128 eee 2467L AVR 05 04 BE ATmega128 2467L AVR 05 04 Figure 70 T C OCF2 fuk yo 8 clkjo clk clk 8 OCRn 1 OCRn 2 TCNTn OCRn OCRn 1 OCRn OCRn Value OCFn Figure 71 CTC OCF2 EM TCNT2 Figure 71 TIC CTC fk yo 8 clkjo clk clkyo 8 TCNTn CTC TOP BOTTOM BOTTOM 1 OCRn OCFn AMEL 141 8 TCCR2
17. SLA W TWDR TWDR TWDR SLA W TWCR TWI TWINT fv EE du KIER BE A TWINT 1 TWCR TWINT TWI TWINT 42 TWI 4 TWCR TWINT TWDR 5 TWSR ACK TWSR TWDR TWCR TW TWDR TWINT TWCR TWINT TWI TWINT 8S TWI 6
18. SYNCLOGIC PIN gt CONTROL gt XK Transmitter TX UDR Transmit CONTROL PARITY P Y GENERATOR 5 z PIN TRANSMIT SHIFT REGISTER S L TxD lt lt G Receiver gt CLOCK RX RECOVERY lt CONTROL a DATA PIN a RECEIVE SHIFT REGISTER RECOVERY lt CONTROL lt RxD i PARITY UDR Receive CHECKER lt Note P 2Figure 1 P 73Table 36 P75Table 39 USART USART XCK USART
19. BREAK OCD JTAG HT OCD JTAG PRIVATE0 8 JTAG OCD PRIVATE1 9 JTAG BA OCD PRIVATE2 A JTAG OCD PRIVATE3 B JTAG OCD 234 ATmega128 m s 2467L AVR 05 04 BE ATmega128 VO OCD OCD OCDR JTAG 2467L AVR 05 04 Bit 7 6 5 4 3 2 1 0 PMSBIDRD J J LSB ocpR R W R W R W R W R W R W R W R W 0 0 0 0 0 0 0 0 OCDR CPU IO IDRD By CPU i OCDR 7 OCDR MSB IDRD DRD MAS AVR
20. CPU CTC WGM01 0 2 OCRO TCNTO OCRO OCRO top A CTC Figure 38 TCNTO TCNT0 OCR0 TCNT0 8S Figure 38 CTC PSS FESS apie tase rr OCn Interrupt Flag Set TCNTn Period k 1 2 3 4 gt OCFO TOP TOP CTC TOP BOTTOM OCRO TCNTO OxFF 0x00 OCR0
21. Flash EEPROM Flash EEPROM Note 1 EESAVE EEPRPOM 1 4 XA1 XAO 10 2 BS1 BH 0 3 DATA 1000 0000 4 XTAL1 5 WR RDY BSY 6 RDY BSY Flash P 273Table 123 Flash Flash A Flash a 1 4 XA1 XAOBA 10 2 BS1 0 3 DATA 0001 0000 Flash 4 XTAL1 B
22. AVR TW TW 128 SCL SDA TWI Figure 86 TWI CC Device 1 Device 2 Device3 Device n R1 SDA 4 gt SCL 4 Table 86 TWI SCL Figure 86 TW TWI 0 TWI
23. S H kO fpc 2 ADC 220 ATmega128 eee 2467L AVR 05 04 ATmega128 Figure 113 Q lH ADCn MN 1 100 ka Ceh 14 pF Ne Vcc 2 EMI 1 2 Figure 114 AVCC LC Voc 3 A ADC CPU ADC 3 0
24. Table 20 1 BOD BODEN 2 ACSR ACBG 3 ADC 50 AT mega12 8 mn arF 2467L AVR 05 04 B ATmega128 2467L AVR 05 04 BOD ACBG ADC Table 20 Vou 1 15 1 23 1 40 V tac 40 70 hs Inc 10 HA 1 Mhz Vcc 5V Vcc P 53Table 22 WDR
25. UMSEL 1 XCK TxD XCK RxD 158 ATmega128 mas WA 2467L AVR 05 04 ______ JT T TT ATmega128 2467L AVR 05 04 Figure 81 XCK UCPOL 1 XCK E ERTER RxD TxD x E Sample UCPOL 0 XCK RxD TxD 7 7 Sample UCRSC UCPOL XCK Figure 81 UCPOL 0 XCK XCK UCPOL 1 XCK XCK A MEL 159 USART AMEL USART 30 1 5 6 7 8 9
26. TWCR TWSR 2 2 TWIN TWE 0 TWDR STA STO T A 2 08 START SLA W 0 0 1 X SLA W ACK s NOT ACK 10 START SLA W 0 0 1 X SLA W 0 0 1 x ACK NOT ACK SLA R SLA R 18 SLA W 0 0 1 X ACK NOT ACK ACK 1 0 1 x START TWDR OO 1 1 X STOP TWSTO TWDR 1 1 1 x STOP START TWSTO HS TWDR 2467L AVR 05 04 AMEL 195 AMEL Table 88 20 SLA W FH 0 0 X ACK NOT ACK NOT ACK 1 0 x START TWDR 0 1 X STOP TWSTO TWDR 1 1 X STOP START TWSTO TWDR 28
27. UBRR UCSRA MPCM USART CPU MPCM 5 8 9 9 RXB8 9 1
28. CKOPT 8 MHz CKOPT 16 MHz C1 C2 BX Table 8 Figure 19 C2 i XTAL2 i Si I XTAL1 e GND CKSEL3 1 Table 8 Table 8 CKOPT CKSEL3 1 MHz C1 C2 1 101 0 4 0 9 Z 1 110 0 9 3 0 12 pF 22 pF 1 111 3 0 8 0 12 pF 22 pF 0 101 110 111 1 0 12 pF 22 pF Note 1 Table 9 CKSELO SUT1 0
29. UDR 164 AT mega12 8 ms a rr 2467L AVR 05 04 B ATmega128 2467L AVR 05 04 RXC 8 UDR 0 USART USART_Receive SRRI sbis UCSRA RXC rjmp USART Receive MAE PRA RGR in ri UDR ret C REDE O unsigned char USART_Receive void GERRIE while UCSRA amp 1 lt lt RXC M PRH EE return UDR Note 1 X I O IO LDS STS SBRS SBR 5 CBR I O IN OUT SBIS CBI SB JE RXC AMEL SBRO r SBIC 165 9 AMEL 9 UCSZ 7 UDR 8
30. Tithe PWM MAX Figure 39 TCNT0 PWM PWM TCNTO OCRO TCNTO0 Figure 39 PWM OCRn Interrupt Flag Set OCRn Update FL EEE and TOVn Interrupt Flag Set TCNTn OCn COMn1 0 2 OCn COMn1 0 3 Period 2 3 le ale 5 ole 6 oe 7 gt Max T C A eR Tovo PWM OC0 PWM COM01 0 2 PWM 3 PWM P 95Table 54 OC0 PWM OC0 OCRO TCNTO LRN BW RAS MAX BA BOTTOM PWM
31. MCU P 84 CKSEL P 34 SM2 0 011 SLEEP TE MCU 0 ASSR A ASO BW 0 0 MCU REE TIMSK SREG AS0 0 MCU clkAsy SM2 0 110 S
32. C Voc C Vee f io Figure 160 0 1 1 0 MHz ACTIVE SUPPLY CURRENT vs FREQUENCY 0 1 1 0 MHz 5 5 V 5 0 V 4 5 V 4 0 V 3 3 V 2 7V 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 8 0 9 1 Frequency MHz A MEL 313 AMEL Figure 161 1 20 MHz ACTIVE SUPPLY CURRENT vs FREQUENCY 1 20 MHz Frequency MHz Figure 162 Vcc RC 1 MHz ACTIVE SUPPLY CURRENT vs Vcc INTERNAL RC OSCILLATOR 1 MHz 314 ATmega128 La ay 2467L AVR 05 04 ATmega128 Figure 163 Vcc RC 2 MHz ACTIVE SUPPLY CURRENT vs Vcc INTERNAL RC OSCILLATOR 2 MHz Figure 164 Vcc
33. 5 JTAG JTAGEN JTAG TDO Table 119 Ria BODLEVEL 7 BOD 1 BODEN 6 BOD 1 BOD SUT1 5 1 O SUTO 4 0 O CKSEL3 3 0 O CKSEL2 2 0 O CKSEL1 1 0 O CKSELO 0 1 O Notes 1 SUT1 0 P38Table 14 2 CKSEL3 0 RC 1 MHz P 34Table 6 1 LB1 EESAVE
34. Table 24 BOOTRST IVSEL 1 0 0000 0002 1 1 0000 Boot 0002 0 0 Boot 0002 0 1 Boot Boot 0002 Note Boot P 266Table 112 BOOTRST 1 0 ATmega128 ms 2467L AVR 05 04 BE ATmega128 2467L AVR 05 04 ATmega128 0000 0002 0004 0006 0008 000A 000C 000E 00 00 00 00 00 00 00 001E 0020 0022 0024 0026 0028 002A 002C 002E 0030 0032 0034 0036 0038 003A 003C 003E 0040 0042 0044 G PrP wan BN O 0046 0047 0048 0049 004A 004B jmp jmp jmp jmp jmp jmp jmp jmp jmp jmp jmp jmp jmp jmp jmp jmp jmp jmp jmp jmp jmp jmp jmp jmp jmp jmp jmp jmp jmp jmp jmp jmp jmp jmp jmp RESET ldir16 out ldi out sei lt instr gt RESET EXT_ EXT_ EXT_I EXT_I EXT_I EXT J J 3 3 3 3 3 O QO A WN EBE O EXT EXT_INT7 TIM2_COMP TIM2_OVF TIM1_CAPT TIM1_COMPA TIM1_COMPB TIM1_OVF TIMO_COMP TIMO_OVF SPI_STC USARTO_RXC USARTO_DRE USARTO_TXC
35. CAPR EN BAH PRM RRI BRA CPU CTC WGMn3 0 4 12 OCRnA 1CRn TCNTn OCRnA WGMn3 0 4 ICRn WGMn3 0 12 Nese Ss OCRnA ICRn TOP f CTC Figure 51 TCNTn TCNTn OCRnA ICRn TCNTn 5 Figure 51 CTC OCnA Interrupt Flag Set Or CFn Interrupt Flag Set f i TS Y Interrupt on TOP Y Y Y Y Y Y Y TCNTn A V gt E E ae COMnAt 0 1 Period k 1 gt lt 2 gt 3 4 4 gt OCFnA ICFn TOP TOP CTC
36. P 273 Flash 1 A 0000 0100 2 OE BS2 BS1 0 DATA 0 3 JOES BS2 BS1 1 DATA 0 278 ATmega128 LL a 2467L AVR 05 04 2467L AVR 05 04 ATmega128 4 OE BS1 0 BS2 1 DATA 0 5 38 OE 0 BS2 i 0 BS1 i 1 DATA 0 6 OE i 1 Figure 140 BS1 BS2 Fuse Low Byte Extended Fuse byte Lock bits Fuse high byte Flash A 0000 1000 B 00 02 OE BS1 0 DATA jS OE E 1 ONS Flash A 0000 1000
37. UDR 156 ATmega128 mars 2467L AVR 05 04 BE ATmega128 AVR USART AVR UART 2467L AVR 05 04 USART AVR UART USART FIFO FE DOR 9 RXB8 UDR a s Figure 79 USART DOR
38. Figure 125 P61V O Figure 124 Figure 125 A MEL 239 AMEL ID PINxn ID PORT DD PUExn PUD DDxn PORTxn Figure 125 Figure 124 ShiftDR To Next Cell EXTEST Vcc Y 3 Pullup Enable PUE gt 0 FF2 LD2 1 L ey G Output Control OC gt FF1 LD1 0 Q Zz Output Data OD 0 FFO LDO 0 0 Port Pin PXn 1 Q 1 Input Data ID lt A A A From Last Cell Cloc
39. 198 ATmega128 memm 2467L AVR 05 04 BE ATmega128 2467L AVR 05 04 Figure 99 MR Successfull reception SLA R A DATA from a slave receiver 08 Next transfer started with a repeated start condition Not acknowledge received after the slave address Arbitration lost in slave address or data byte Arbitration lost and addressed as slave 40 A DATA A p 50 58 Rs SLA Other master continues 48 gt Y a Other master Other master AorA continues A continues oa 38 38 To corresponding states in slave mode From master to slave From slave to master AIMEL r Any number of data bytes and their associated acknowledge bits This number contained in TWSR corresponds to a defined state of the Two wire Serial Bus The prescaler bits are zero or masked to zero MT 199 Table 89 AMEL TWCR TWSR 2 2 TWIN
40. 1 CBI SBI 1 O 1 CBI SBI 00 to 1F VO SRAM Flash LCD A D D A XMEM P 2Figure 1 P 68Table 27 P 72Table 33 P 79Table 45 Figure 11 Figure 11 Memory Configuration A Memory Configuration B 0x0000 0x0000 Internal memory Internal memory OxOFFF 0x1000 0x10FF 0x1100 Lower sector forea External Memory 0 60K x 8 External Memory 0 60K x 8 Upper sector OxFFFF OxFFFF Not
41. 1 2 3 4 1010 1100 0101 0011 XXXX XXXX xxxx Xxxx RESET 1010 1100 100x xxxx XXXX XXXX xxxx Xxxx BK EEPROM Flash 0010 H000 aaaa aaaa bbbb bbbb oooo 0000 a b H o 0100 H000 XXXX xxxx xbbb bbbb iii iiii b H i Eee 0100 1100 aaaa aaaa bxxx XXXX XXXX xxxx a b EEPROM 1010 0000 XXXX aaaa bbbb bbbb 00000000 EEPROM a b o EEPROM 1100 0000 xxxx aaaa bbbb bbbb ili iiii EEPROM a b o 0101 1000 0000 0000 XXXX XXXX xxoo 0000 0 1 JL P 268Table 115 1010 1100 111x XXXX XXXX XXXX 11 ii iii 0 P 268Table 115 0011 0000 XXXX XXXX xxxx xxbb 0000 0000 b o 1010 1100 1010 0000 XXXX XXXX ili iiii T 1
42. Write ACK SDA Read 1111 xxx 182 ATmega128 LLL 2467L AVR 05 04 B ATmega128 2467L AVR 05 04 Figure 89 Addr MSB Addr LSB R W CK XX X X SCL START TWI 9 8 1 START STOP 9 SCL SDA SDA NACK NACK MSB Figure 90 Data MSB DataLSB ACK Aggregate o
43. fok yo 2 5 130 ATmega128 mr s 2467L AVR 05 04 ATmega128 Figure 60 T C1 T C2 T C3 cK 10 BIT T C PRESCALER PSR321 T3 m T2 a Ti 5 CS30 CS20 CS10 CS31 CS21 CS11 CS32 CS22 CS12 TIMER COUNTER3 CLOCK SOURCE TIMER COUNTER2 CLOCK SOURCE TIMER COUNTER1 CLOCK SOURCE clk clkyy clk Note T3 T2 T1 Figure 59 IO SFIOR Bit 7 6 5 4 3 2 1 0 RAW R R R R W R W R W R W 0 0 0 0 0 0 0 0 Bit7 TSM T C RE TSM PSR0 PSR321 T C T C TSM Bit 0 PSR321 T C3 T C2 5 TIC1 T C3 T C2 T C1
44. ATmega128 XMEM 4 Table 4 ATmega128 ALE Tables 137 Tables 144 tu RL tary tpvrH XMEM XMEM P 308 Table 137 Table 144 Figure 156 Figure 159 XMEM XTAL1 XMEM Figure 13 SRWn1 0
45. P 228 ADC ADCL ADCH Bits 4 0 MUX4 0 226 AT mega12 8 eee 2467L AVR 05 04 2467L AVR 05 04 ATmega128 ADC Table 98 ADCSRA ADIF Table 98 AMEL MUX4 0 00000 ADCO 00001 ADC1 00010 ADC2 00011 ADC3 N A 00100 ADC4 00101 ADC5 00110 ADC6 00111 ADC7 01000 ADCO ADCO 10x 01001 ADC1 ADCO 10x 01010 ADCO ADCO 200x 01011 ADC1 ADCO 200x 01100 ADC2 ADC2 10x 01101 ADC3 ADC2 10x 01110 ADC2 ADC2 200x 01111 ADC3 ADC2 200x 10000 ADCO ADC1 1x 10001 ADC1 ADC1 1x 10010 N A ADC2 ADC1 1x 10011 ADC3 ADC1 1x 10100 ADC4 ADC1 1x 10101 ADC5 ADC1 1x 10110 ADC6 ADC1 1x 10111 ADC7 ADC1 1x 11000 ADCO ADC2 1x 11001 ADC1 ADC2 1x 11010 ADC2 ADC2 1x 11011 ADC3 ADC2 1x 11100 ADC4 ADC2 1x 11101 ADC5 ADC2 1x 11110 1 23V Vgc N A 11111 OV GND
46. ACK TWl CPU ACK Bits 7 0 TWD TWI A MEL 189 TWI TWAR TWI AMEL Bit 7 6 5 4 3 2 1 0 TWA6 TWA5 TWA4 TWA3 TWA2 TWA1 TWA0 TWGCE TWAR R W R W R W R W R W R W R W R W 1 1 1 1 1 1 1 0 TWAR 7 TWI TWAR TWAR LSB 0x00 Bits 7 1 TWA TWI Bit 0 TWGCE ERE TWI MCU TWI AVR TWI START TWI TW TWI
47. TCNT2 BOTTOM OC2 OC2 FOC2 OC2 134 AT mega12 8 memm 2467L AVR 05 04 BE ATmega128 2467L AVR 05 04 COM21 0 COM21 0 COM21 0 COM21 0 OC2 COM21 0 OC2 Figure 64 COM21 0 I O 1 O I O COM21 0 I O DDR PORT OC2 OC2 OC2 Figure 64 gt Waveform Generator x O IO olo z O I 5 a PORT lt lt f DDR clkyo COM21 0
48. TWCR TWI TWIE SREG TWINT TWE TWINT TWI TWINT 1 TWI TW TWSR TW TWCR TWCR TWDR TWI TWI Figure 95 TWI 190 ATmega128 msn 2467L AVR 05 04 BE ATmega128 Figure 95 TWI 1 Application 3 Check TWSR to see if START 5 Check TWSR to see if SLA W 7 Check TWSR to see if data 5 writes to TWCR was sent Application
49. 8 ATmega128 P 50 M103C WDTON 3 Table 21 0 ATmega103 P 54 AMEL s WDTCR AMEL Table 21 WDT WDT M103C WDTON WOT 1 2 0 2 Figure 28 WATCHDOG OSCILLATOR WATCHDOG PRESCALER Sololol l sil Sl STS Syere WATCHDOG RESET WDP1 WDP2 WDE MCU RESET Bit 7 6 5 4 3 2 1 0 WDCE WDE WDP2 WDP1 WDPO WD
50. Atmel ATmega128 270 ATmega128 memm 2467L AVR 05 04 BE ATmega128 2467L AVR 05 04 1 000 1E Atmel 2 001 97 128KB Flash 3 002 02 001 97 Armega128 ATmega128 RC 0x000 0x0001 0x0002 0x0003 1 2 4 8 MHz 1 MHz OSCCAL PE NL P 38 OSCCAL o A MEL 271 AMEL ATmega128 Flash EEPROM Ret 272 250 ns ATmega12
51. 4 MHz 0 Mtorer 0 0 16 MHz 10 tripv 325 3 0tc ci 50 ns 12 tanu RD 365 3 0tg ci 10 ns 15 tbvwH WR 375 3 0tcucu ns 16 twuwh WR 365 3 0tcucu 10 ns Table 140 4 5 5 5V SRWn1 1 SRWn0 1 4 MHz 0 Iter 0 0 16 MHz 10 terpy 325 3 0torc1 50 ns 12 tami RD 365 3 0tg ci 10 ns 14 twHDx WR 240 2 0to 1 10 ns 15 tbvwh WR 375 3 0tcucu ns 16 twuwh WR 365 3 0tcucu 10 ns Table 141 2 7 5 5V 4 MHz 0 tere 0 0 8 MHz 1 tau ALE 235 torcp 15 ns 2 ALE A 115 0 5tg 10 ns ALE 5 3a tax st ns ALE 5 5 3b tiiax LD ns 4 tvie ALE C 115 0 5tg
52. STOP TW SCL SDA Bit 3 TWWC TWI TWINT TWDR TWWC TWDR 188 ATmega128 memme 2467L AVR 05 04 BE ATmega128 TW TWSR TWI TWDR 2467L AVR 05 04 Bit 2 TWEN TWI TWEN TWI TWI TWEN 1 TWI MO SCL SDA TWI TWI Bit 1 Res 0 Bit 0 TWIE TWI SREG 1 TWIE TWINT 1 TWI Bit 7 6 5 4 3 2 1 0 TWS7 TWS6 TWS5 TWS4 TWS3 TWPS1 TWPS0 TWSR B S R R R R R R R W R W 1 1 1 1 1 0 0 0 Bits 7 3 TWS TWI 5 TW TWSR 5 2
53. 12V Figure 127 5V RSTT 12V RSTHV Figure 127 ShiftDR cell From system pin gt gt To system logic From ClockDR previous cell AVR RC RC Figure 128 RC 242 ATmega128 La ay 2467L AVR 05 04 ATmega128 Figure 128 XTAL1 TOSC1 XTAL2 TOSC2 ShiftDR Cell EXTEST Oscillator next Y 7 ShiftOR cell Re I ENABLE OUTPUT gt To System Logic i L FF1 D QD Q 0 D Q L i G From ClockDR UpdateDR Previous From ClockDR
54. LED Vcc Figure 29 P 299 Figure 29 IO Logic See Figure General Digital I O for Details Coin x n PORTB3 B 3 PORTxn VO P 81 0 VO PORTx DDRx PINx SFIOR PUD VO P 62 IO P 66
55. SBI CBI Bit 3 ADIE ADC ADIE SREG 1 ADC Bits 2 0 ADPS2 0 ADC XTAL ADC Table 99 ADC ADPS2 ADPS1 ADPS0 0 0 0 2 0 0 1 2 0 1 0 4 0 1 1 8 1 0 0 16 1 0 1 32 1 1 0 64 1 1 1 128 ATmega128 mmm 2467L AVR 05 04 BE ATmega128 ADC ADCL ADCH ADLAR 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R R R R R R R R R R R R R R R R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADLAR 1 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 i R R R R R R R R R R R R R R R R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADC 2 ADCL Z J ADC ADCH 8 ADCH ADCL ADCH ADMUX ADLAR MUXn
56. ce XTAL1 1 RESET 05 0 3 Voc Vv Viet XTAL1 0 5 0 1 Voce V Vito RESET 0 5 0 2 Voc V Vin ea AS EI 0 6 Veg Vec 0 5 V ViH1 XTAL1 0 7 Vec Vcc 0 5 V Vino RESET 0 85 Vo Voc 0 5 V V O lo 20 MA Vcc 5V 0 7 V ot A B C D E F G loL 10 MA Vec 3V 0 5 V V lop 20 mA Voc 5V 4 0 V Ori A B C D lop 10 MA Vec 3V 2 2 V Vcc 5 5V Me VO 1 Bi a0 Ha Vcc 5 5V 8 0 A IH O i Rest Reset 30 100 kQ Reen PEN 25 100 kQ Rey IO 33 122 kQ 299 2467L AVR 05 04 AMEL AMEL T 40 C 85 C Veg 2 7V 5 5V 4 MHz Vcc 3V ATmega128L i mA 8 MHz Vec 5V ATmega128 a ma RE 4 MHz Vec 3V TH Z Vcc Icc ATmega128L 8 MHz Voc 5V ATmega128 1 mA WDT Vcc 3V lt 25 40 A ae WDT Vcc 3V lt 10 25
57. UBRRnL 176 AT mega12 8 m FV 2467L AVR 05 04 BE ATmega128 Table 82 UBRR 0 5 FS P 170 Ero seme 100 Table 82 UBRR fose 1 0000 MHz fosc 1 8432 MHz fosc 2 0000 MHz U2X 0 U2X 1 U2X 0 U2X 1 U2X 0 U2X 1 bps UBRR UBRR UBRR UBRR UBRR UBRR 2400 25 0 2 51 0 2 47 0 0 95 0 0 51 0 2 103 0 2 4800 12 0 2 25 0 2 23 0 0 47 0 0 25 0 2 51 0 2 9600 6 7 0 12 0 2 11 0 0 23 0 0 12 0 2 25 0 2 14 4k 3 8 5 8 3 5 7 0 0 15 0 0 8 3 5 16 2 1 19 2k 2 8 5 6 7 0 5 0 0 11 0 0 6 7 0 12 0 2 28 8k 1 8 5 3 8 5 3 0 0 7 0 0 3 8 5 8 3 5 38 4k 1 18 6 2 8 5 2 0 0 5 0 0 2 8 5 6 7 0 57 6k 0 8 5 1 8 5 1 0 0 3 0 0 1 8 5 3 8 5 76 8k _ _ 1 18 6 1
58. ID 2467L AVR 05 04 Bypass Bypass TDI TDO Capture DR 0 Bypass Figure 122 Figure 122 MSB LSB Bit 31 28 27 12 1 1 0 sift 1D 4 bits 16 bits 11 bits 1 bit 4 A 0x0 B 0x1 16 ATmega128 JTAG Table 100 Table 100 AVR JTAG ATmega128 0x9702 ID 11 ATMEL JTAG ID Table 101 Table 101 ID JTAG ID Hex ATMEL 0x01F AVR JTAG HIGHZ ON AVR AVR AVR
59. REPEATED START STOP START START REPEATED START START START STOP SCL SDA Figure 88 START REPEATED START STOP START STOP START REPEATED START STOP TWI 9 7 1 READ WRITE 1 READ WRITE SCL ACK SDA ACK SDA STOP REPEATED START SLA R SLA W READ WRITE MSB 0000 000 ACK SDA
60. SRAM SRAM 1 2 3 2 3 4 5 7 9 5 R26 R31 Y Z 63 X Y Z 32 64 MO 4096 SRAM P 9 ATmega128 me 2467L AVR 05 04 2467L AVR 05 04 Figure 9 ATmega128 Memory Configuration A Data Memory 0100 Internal SRAM 4096 x 8 10FF 1100 External SRAM 0 64K x 8 Memory Configuration B 0000 001F 64 I O Registers 0020 005F 160 Ext I O Reg 0060 00FF Data Memory 32 Registers 0000 001F 64 I
61. Table 130 AVR JTAG JTAG Flash 2048 Flash 8 JTAG Update DR Shift DR Flash Shift DR Flash TCK Note JTAG PROG PAGELOAD AVR RFE JTAG AVR AVR JTAG JTAG Flash 2056 Flash Flash 8 8 JTAG HPA Capture DR Shift DR
62. 32 kHz ADC ADC CPU IO ADC AMEL s AMEL AVR Table 6 CKSEL3 0 1 1111 1010 1001 RC 1000 0101 RC 0100 0001 0000 Note 1 1 0 CPU CPU
63. OC2 1 0 H OC2 DDR OC2 DDR_OC2 OC2 COM21 0 P 142 8 COM21 0 CTC PWM COM21 0 0 OC2 PWM P 143Table 65 PWM P 143Table 66 PWM P 143Table 67 COM21 0 PWM FOC2 T C WGM21 0 COM21 0
64. 0 Bit 2 Res 0 Bits 1 0 TWPS TWI Table 87 TWI TWPS1 TWPSO 0 0 1 0 1 4 1 0 16 1 1 64 P 186 TWPS1 0 Bit 7 6 5 4 3 2 1 0 TWD7 TWD6 TWD5 TWD4 TWD3 TWD2 TWD1 TWDO TWDR R W R W R W R W R W R W R W R W 1 1 1 1 1 1 1 1 TWDR TWDR TWI TWINT TWINT TWDR TWDR MCU TWI TWDR
65. 5 93 20 106 67 6 67 6 8 3 0 6 94 12 105 79 5 79 5 88 2 5 7 94 81 105 11 5 11 5 19 2 0 8 95 36 104 58 4 58 4 54 2 0 9 95 81 104 14 4 14 4 19 1 5 10 96 17 103 78 3 78 3 83 1 5 170 ATmega128 mr s 2467L AVR 05 04 BE ATmega128 MPCM 2467L AVR 05 04 Table 76 U2X 1 D Rast 5 94 12 105 66 5 66 5 88 25 6 94 92 104 92 4 92 5 08 2 0 7 95 52 104 35 4 35 4 48 1 5 8 96 00 103 90 3 90 4 00 1 5 9 96 39 103 53 3 53 3 61 1 5 10 96 70 103 23 3 23 3 30 1 0 XTAL 2
66. ACSR ACD ADC SM2 0 001 SLEEP MCU CPU ADC 0 clkyo clkcpu clkr Ash ADC ADC AD ADC BOD 0 SPM EEPROM INT7 4 INT3 0 MCU ADC SM2 0 010 SLEEP MCU BOD INT7 4 INT3 0 MCU
67. TOP BOTTOM OCRnA ICRn TCNTn 0xFFFF 0x0000 OCRnA ICRn PWM OCRnA TOP WGMn3 0 15 OCRnA CTC OCnA COMnA1 0 1 OCnA DDR_OCnA 1 foco fok yo 2 OCRnA 0x0000 ko OCnA 2 N 1 OCRnA N 1 8 64 256 1024 TOVn MAX 0x0000 112 ATmega128 memm 2467L AVR 05 04 B ATmega128 PWM 2467L AVR 05 04 PWM WGMn3 0 5 6 7 14 3R 15 PWM
68. AD Ro ATmega103 F JTAG PF7 TDI PF5 TMS PF4 TCK Table 42 F PF7 ADC7 TDI ADC 7 RZ JTAG PF6 ADC6 TDO AD 6 JTAG PF5 ADC5 TMS ADC 5 JTAG PF4 ADC4 TCK ADC 4 JTAG PF3 ADC3 ADC 3 PF2 ADC2 ADC 2 PF1 ADC1 ADC 1 PFO ADCO ADC 0 TDI ADC7 F Bit 7 ADC7 7 TDI JTAG JTAG WO TDO ADC6 F Bit 6 ADC6 6 TDO JTAG JTAG
69. MCUCSR JTD JTD 1 reset JTD JTAG JTAG VO ISP JTAG JTAG LSB 4 16 JTAG OPCODE 16 TDI TDO TAP Run Test Idle JTAG Figure 146 286 ATmega128 eee 2467L AVR 05 04 AVR_RESET C PROG_ENABLE 4 PROG_COMMANDS 5 2467L AVR 05 04 ATmega128 Figure 146 Capture IR a E A E E EE E E kin TT Maw uuu wywasawakiwayuwasq
70. TWI MT TWI EEPROM MR EEPROM TWI SR S START Rs REPEATED START R SDA W SDA A BF A SDA AIBA A SDA Data 8 P STOP SLA Figure 97 Figure 103 TWINT TWSR 0 TWI TWI TWINT TWINT TWSR Table 88 Table 91 BA 0
71. AREF ADC AREF VREr AREF Veer AREF AREF AVCC 1 1V ADC P 306Table 136 AVCC ADC CPU VO ADC 1 ADC ADC 2 HEA ADC CPU ADC
72. ID ATmega128 IDCODE KATE TAP Test Logic Reset ID ATrmega128 IDCODE JTAG Update DR ID ATmega128 Rev G XDIV OSCCAL 1 XDIV XDIV 2 NOP 8 NOP 1 SREG Wiss 2 XDIV 3 8 NOP 4 SREG CLI te Par EBE S OUT XDIV temp NOP NOP NOP NOP NOP NOP NOP NOP
73. OC2 COM21 0 1 50 OCR2 0 foco clk Vo Zo X CTC OC2 PWM A MEL 137 2467L AVR 05 04 PWM AMEL PWM WGM21 0 1 PWM BOTTOM MAX MAX BOTTOM MAX TCNT2 OCR2 OC2 BOTTOM TCNT2 OCR2 OC2 PWM PWM 8 MAX TCNT2 MAX Fig
74. POR Voe Voc RESET Figure 23 MCU RESET Voc Veo 7 i For RESET ____ Nast TIME OUT INTERNAL RESET AMEL a 2467L AVR 05 04 AMEL Figure 24 MCU RESET TIME OUT Tour 1 I INTERNAL RESET RESET Table 19 Vrest EFA trour MCU Figure 25 Vcc RESET 1 1 lt trout TIME OUT I I I i INTERNAL oo O RESET ATmega128 BOD Brown out Detection Voc BODLEVEL BOD 2 7V BODL
75. T C T C TCCR2 CS22 0 P 130 3 2 1 8 T C Figure 62 Figure 62 TOVn DAIA BUS Int Req bottom top count TCNT2 1 1 direction clear AS TCNT2 clk T C top TCNT2 bottom TCNT2 0 clk7s clkr gt