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MICROCHIP MCP2515 Manual

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1. measured in TQ and is fixed at 2 TQ for the Microchip Register 5 1 CAN module Since PS2 also begins at the sample point and is the last segment in the bit time it is required that the PS2 minimum is not less than the IPT FIGURE 5 2 TQ AND THE BIT PERIOD tosc TBRPCLK Sync PropSeg PS1 PS2 BIT fixed Programmable Programmable Programmable TQ tTQ gt gt DS21801E page 38 2007 Microchip Technology Inc MCP2515 5 2 Synchronization To compensate for phase shifts between the oscillator frequencies of each of the nodes on the bus each CAN controller must be able to synchronize to the relevant signal edge of the incoming signal Synchronization is the process by which the DPLL function is implemented When an edge in the transmitted data is detected the logic will compare the location of the edge to the expected time SyncSeg The circuit will then adjust the values of PS1 and PS2 as necessary There are two mechanisms used for synchronization 1 Hard synchronization 2 Resynchronization 5 2 1 HARD SYNCHRONIZATION Hard synchronization is only performed when there is a recessive to dominant edge during a BUS IDLE condition indicating the start of a message After hard synchronization the bit time counters are restarted with S
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3. FIGURE 1 2 EXAMPLE SYSTEM IMPLEMENTATION Node Node Node Controller Controller Controller SPI SPI SPI MCP2515 MCP2515 MCP2515 TX RX TA x XCVR XCVR XCVR CANH gt 4 gt TABLE 1 1 PINOUT DESCRIPTION PDIP SOIC TSSOP T Name Pin Pin Type Description Alternate Pin Function TXCAN 1 1 O Transmit output pin to CAN bus RXCAN 2 Receive input pin from CAN bus CLKOUT 3 Clock output pin with programmable Start of Frame signal prescaler TXORTS 4 4 Transmit buffer request to send General purpose digital input 100 internal pull up to VDD 100 internal pull up to VDD TXIRTS 5 5 Transmit buffer TXB1 request to send General purpose digital input 100 internal pull up to VDD 100 internal pull up to TX2RTS 6 7 Transmit buffer TXB2 request to send General purpose digital input 100 internal pull up to VDD 100 internal pull up to OSC2 7 8 Oscillator output OSC1 8 9 Oscillator input External clock input Vss 9 10 P Ground reference for logic and I O pins RX1BF 10 11 Receive buffer RXB1 interrupt pin or General purpose digital output general purpose digital output RXOBF 11 12 Receive buffer RXBO interrupt or General purpose digital output general purpose digital output INT 12 13 O Interrupt output pin SCK 13 14 Clock input for SPI interface 5 14 16 Data input pin for S
4. Notes 1 Pin 1 visual index feature may vary but must be located within the hatched area 2 S Significant Characteristic 3 Dimensions D and E1 do not include mold flash or protrusions Mold flash or protrusions shall not exceed 010 per side 4 Dimensioning and tolerancing per ASME Y14 5M BSC Basic Dimension Theoretically exact value shown without tolerances Microchip Technology Drawing C04 007B DS21801E page 76 2007 Microchip Technology Inc MCP2515 18 Lead Plastic Small Outline 50 Wide 7 50 mm Body SOIC Note For the most current package drawings please see the Microchip Packaging Specification located at http www microchip com packaging A SA E1 LA NOTE 1 2222 123 e L A pes h T M x a 1 La Units MILLIMETERS Dimension Limits MIN NOM MAX Number of Pins N 18 Pitch e 1 27 BSC Overall Height A 2 65 Molded Package Thickness A2 2 05 Standoff A1 0 10 0 30 Overall Width E 10 30 BSC Molded Package Width E1 7 50 BSC Overall Length D 11 55 BSC Chamfer optional h 0 25 0 75 Foot Length L 0 40
5. Note This parameter is periodically sampled and not 100 tested TABLE 13 3 CAN INTERFACE AC CHARACTERISTICS Industrial 1 40 C to 85 C VDD 2 7V to 5 5V Extended TAMB 40 C to 125 C 4 5V to 5 5V CAN Interface AC Characteristics Param Sym Characteristic Min Max Units Conditions No TWF Wake up Noise Filter 100 ns TABLE 13 4 AC CHARACTERISTICS Industrial I TAMB 40 C to 85 VDD 2 7V to 5 5V Extended TAMB 40 C to 125 VDD 4 5V to 5 5V RESET AC Characteristics Param Sym Characteristic Min Max Units Conditions No trl RESET Pin Low Time 2 us 2007 Microchip Technology Inc DS21801E page 71 2515 TABLE 13 5 CLKOUT PIN AC CHARACTERISTICS 5 Industrial I TAMB 40 C to 85 VDD 2 7V to 5 5V GLKOUTRINAC DC Characterishes Extended 40 C to 125 VDD 4 5V to 5 5V Characteristic Min Max Units Conditions No thCLKOUT CLKOUT Pin High Time 15 ns Tosc 40 ns Note 1 tCLKOUT CLKOUT Pin Low Time 15 ns Tosc 40 ns Note 1 tCLKOUT CLKOUT Pin Rise Time 5 ns Measured from 0 3 to 0 7 Note 1 tcLKOUT CLKOUT Pin Fall Time 5 ns Measured from 0 7 VDD to 0 3 VDD Note 1 tgCLKOUT CLOCKOUT Propagation Delay 100 ns Note 1 15 thSOF Star
6. 2007 Microchip Technology Inc DS21801E page 63 MCP2515 Each status bit returned in this command may also be read by using the standard read command with the appropriate register address 12 9 RX Status Instruction The RX Status instruction Figure 12 9 is used to quickly determine which filter matched the message and message type standard extended remote After the command byte is sent the controller will return 8 bits of data that contain the status data If more clocks are sent after the 8 bits are transmitted the controller will continue to output the same status bits as long as the CS pin stays low and clocks are provided 12 10 Bit Modify Instruction The Bit Modify instruction provides a means for setting or clearing individual bits in specific status and control registers This command is not available for all registers See Section11 0 Register Map to The part is selected by lowering the CS pin and the Bit Modify command byte is then sent to the MCP2515 The command is followed by the address of the register the mask byte and finally the data byte The mask byte determines which bits in the register will be allowed to change A 1 in the mask byte will allow a bit in the register to change while a 0 will not The data byte determines what value the modified bits in the register will be changed to A 1 in the data byte will set the bit and a 0 will clear the
7. Set CANINTF RXOIF 1 Set RXBOCTRL FILHIT lt 0 gt according to which filter criteria CANINTE RXOIE 1 BFPCTRL BOBFM 1 and BF1CTRL BOBFE 1 Yes RXBOCTRL BUKT 1 Generate Overflow Error Set EFLG RX0OVR Yes a filter criteria for RXB1 Go to Start Meets Yes Generate Overflow Error Set EFLG RX10VR No CANINTE ERRIE 1 rupt on INT Go Stat Interrupt on INT Go t0 Start Generate RXBO 5 CANINTF RX1IF 0 Yes Move message into RXB1 Y Set CANINTF RX1IF 1 Y Set RXBOCTRL FILHIT 2 0 according to which filter criteria was met Yes Interrupt INT Set CANSTAT 3 0 accord RXB1 ing to which receive buffer the message was loaded into Set RXBFO Pin 0 BFPCTRL B1BFM 1 and BF1CTRL B1BFE 1 DS21801E page 26 2007 Microchip Technology Inc MCP2515 REGISTER 4 1 RXBOCTRL RECEIVE BUFFER 0 CONTROL ADDRESS 60h U 0 R W 0 R W 0 U 0 R 0 R W 0 R 0 R 0 1 RXMO RXRTR BUKT BUKT1 FILHITO bit 7 bit 0 Legend R Readable bit W Writable bit U Unimplemented bit read as 0 n Value at POR 1 Bit is set 0 Bit is cleared x Bit is unknown bit 7 Unimplemen
8. REGISTER 4 5 RXBnSIDL RECEIVE BUFFER n STANDARD IDENTIFIER LOW ADDRESS 62h 72h R x R x R x R x R x U 0 R x R x SID2 SID1 SIDO SRR IDE EID17 EID16 bit 7 bit 0 Legend R Readable bit W Writable bit U Unimplemented bit read as 0 n Value at POR 1 Bit is set 0 Bit is cleared x Bit is unknown bit 7 5 SID Standard Identifier bits lt 2 0 gt These bits contain the three least significant bits of the Standard Identifier for the received message bit 4 SRR Standard Frame Remote Transmit Request bit valid only if IDE bit 0 1 Standard Frame Remote Transmit Request Received 0 Standard Data Frame Received bit 3 IDE Extended Identifier Flag bit This bit indicates whether the received message was a Standard or an Extended Frame 1 Received message was an Extended Frame 0 Received message was a Standard Frame bit 2 Unimplemented Reads as 0 bit 1 0 EID Extended Identifier bits lt 17 16 gt These bits contain the two most significant bits of the Extended Identifier for the received message REGISTER 4 6 RXBnEID8 RECEIVE BUFFER n EXTENDED IDENTIFIER HIGH ADDRESS 63h 73h R x R x 21015 21014 21013 21012 EID11 EID10 EID9 EID8 bit 7 bit 0 Legend R Readable bit W Writable bit U Unimplemented bit read as 0 n Value at POR 1 Bit is set 0 Bit is cleared x Bit is unkno
9. 2515 5 DS21801E page 48 2007 Microchip Technology Inc MCP2515 7 0 INTERRUPTS The MCP2515 has eight sources of interrupts The CANINTE register contains the individual interrupt enable bits for each interrupt source The CANINTF register contains the corresponding interrupt flag bit for each interrupt source When an interrupt occurs the INT pin is driven low by the MCP2515 and will remain low until the interrupt is cleared by the MCU An interrupt can not be cleared if the respective condition still prevails It is recommended that the bit modify command be used to reset flag bits in the CANINTF register rather than normal write operations This is done to prevent unintentionally changing a flag that changes during the write command potentially causing an interrupt to be missed It should be noted that the CANINTF flags are read write and an interrupt can be generated by the MCU setting any of these bits provided the associated CANINTE bit is also set 7 1 Interrupt Code Bits The source of a pending interrupt is indicated in the CANSTAT ICOD interrupt code bits as indicated in Register 10 2 In the event that multiple interrupts occur the INT will remain low until all interrupts have been reset by the MCU The CANSTAT ICOD bits will reflect the code for the highest priority interrupt that is currently pending Interrupts are internally prioritized such that the lower the ICOD value the higher
10. DS21801E page 54 2007 Microchip Technology Inc MCP2515 9 0 RESET The MCP2515 differentiates between two resets 1 Hardware Reset Low on RESET pin 2 SPI Reset Reset via SPI command Both of these resets are functionally equivalent It is important to provide one of these two resets after power up to ensure that the logic and registers are in their default state A hardware reset can be achieved automatically by placing an RC on the RESET pin see Figure 9 1 The values must be such that the device is held in reset for a minimum of 2 us after VDD reaches Operating voltage as indicated in the electrical specification tRL FIGURE 9 1 RESET PIN CONFIGURATION EXAMPLE 1 AAA RESET I6 Note 1 The diode D helps discharge the capacitor quickly when VDD powers down 2 R1 1kQ to 10 will limit any current flowing into RESET from external capacitor C in the event of RESET pin breakdown due to Electrostatic Discharge ESD or Electrical Overstress EOS 2007 Microchip Technology Inc DS21801E page 55 MCP2515 NOTES DS21801E page 56 2007 Microchip Technology Inc MCP2515 10 0 MODES OF OPERATION The MCP2515 has five modes of operation These modes are 1 Configuration mode 2 Normal mode 3 Sleep mode 4 Listen only mode 5 Loopback mode The operational mode is selected the CANCTRL REQOP bits see R
11. 2007 Microchip Technology Inc MCP2515 4 5 3 FILHIT BITS Filter matches on received messages can be determined by the FILHIT bits in the associated RXBnCTRL register RXBOCTRL FILHITO for buffer 0 and RXB1CTRL FILHIT lt 2 0 gt for buffer 1 The three FILHIT bits for receive buffer 1 RXB1 are coded as follows 101 Acceptance Filter 5 RXF5 100 Acceptance Filter 4 RXF4 011 Acceptance Filter RXF3 010 Acceptance Filter 2 RXF2 001 Acceptance Filter 1 RXF1 000 Acceptance Filter 0 RXFO Note and 001 can only occur if the BUKT bit in RXBOCTRL is set allowing RXBO messages to roll over into RXB1 RXBOCTRL contains two copies of the BUKT bit and the FILHIT lt O gt bit The coding of the BUKT bit enables these three bits to be used similarly to the RXB1CTRL FILHIT bits and to distinguish a hit on filter RXFO and RXF1 in either or after roll over into RXB1 111 Acceptance Filter 1 RXB1 110 Acceptance Filter 0 RXB1 001 Acceptance Filter 1 RXBO 000 Acceptance Filter 0 RXBO Soe a ae FIGURE 4 5 If the BUKT bit is clear there are six codes corresponding to the six filters If the BUKT bit is set there are six codes corresponding to the six filters plus two additional codes corresponding to RXFO and RXF 1 filters that roll over into RXB1 4 5 4 MULTIPLE FILTER MATCHES If more than one acceptance filter matche
12. 1 27 Footprint L1 1 40 REF Foot Angle 0 8 Lead Thickness c 0 20 0 33 Lead Width b 0 31 0 51 Mold Draft Angle Top a 5 15 Mold Draft Angle Bottom 5 15 Notes 1 Pin 1 visual index feature may vary but must be located within the hatched area 2 Significant Characteristic 3 Dimensions D and E1 do not include mold flash or protrusions Mold flash or protrusions shall not exceed 0 15 mm per side 4 Dimensioning and tolerancing per ASME Y14 5M BSC Basic Dimension Theoretically exact value shown without tolerances REF Reference Dimension usually without tolerance for information purposes only Microchip Technology Drawing C04 051B 2007 Microchip Technology Inc DS21801E page 77 MCP2515 20 Lead Plastic Thin Shrink Small Outline ST 4 4 mm Body TSSOP Note For the most current package drawings please see the Microchip Packaging Specification located at http www microchip com packaging 1 1 1 12 b lt e i 1 i r A J L1 L Units MILLIMETERS Dimension Limits MIN NOM MAX Number o
13. Revision C November 2004 Section 9 0 RESET added Heading 12 1 added notebox Heading 12 6 Changed verbiage within paragraph in Section 12 0 SPI Interface Added Appendix A Revision History Revision B September 2003 Front page bullet Standby current typical Sleep Mode changed from 10 LA to 1 pA Added notebox for maximum frequency on CLK OUT in Section 8 2 CLKOUT Pin Section 12 0 SPI Interface Table 12 1 Changed supply voltage minimum to 2 7V Internal Capacitance Changed VDD condition to OV Standby Current Sleep mode Split specification into 40 C to 85 C and 40 C to 125 C Revision A May 2003 Original Relase of this Document 2007 Microchip Technology Inc DS21801E page 79 2515 5 DS21801E page 80 2007 Microchip Technology Inc MCP2515 PRODUCT IDENTIFICATION SYSTEM To order or obtain information e g on pricing or delivery refer to the factory or the listed sales office PARTNO X IXX Examples al a MCP2515 E P Extended Temperature Device Temperature Package 18LD PDIP package Range b MCP2515 I P Industrial Temperature 18LD PDIP package Device MCP2515 CAN Controller w SPI Interface MGP2515 E SO Extended Temperature MCP2515T CAN Controller w SPI Interface 18LD SOIC package Tape and Reel d MCP2515 I SO Industrial Temperature 18LD SOIC package e MCP2515T I S
14. loL 41 6 mA 4 5V High Level Output Voltage V TXCAN RXnBF Pins VDD 0 7 V 3 0 mA VDD 4 5V SO CLKOUT 0 5 V 400 pA VDD 4 5V INT 0 7 V 1 0 mA 4 5V Input Leakage Current ILI All I O except OSC1 and 1 1 JA CS RESET VoD TXnRTS pins VIN Vss to VDD OSC1 Pin 5 5 CINT Internal Capacitance 7 pF TAMB 25 C fc 1 0 MHz All Inputs and Outputs VDD Note 1 IDD Operating Current 10 mA VDD 5 5V 25 MHz FCLK 1 MHz SO Open 16 Standby Current Sleep mode 5 JA CS TXnRTS VDD Inputs tied to VDD or 55 40 85 8 JA CS TXnRTS Inputs tied to VDD or 55 40 C TO 125 Note 1 This parameter is periodically sampled and not 100 tested DS21801E page 70 2007 Microchip Technology Inc MCP2515 TABLE 13 2 OSCILLATOR TIMING CHARACTERISTICS p M z s Industrial 1 40 C to 85 C VDD 2 7V to 5 5V Note Oscillator Timing Gharacterlstics Extended 40 to 125 C 4 5V to 5 5V Param Sym Characteristic Min Max Units Conditions No Fosc Clock In Frequency 1 40 MHz 4 5V to 5 5V 1 25 MHz 2 7V to 5 5V Tosc Clock In Period 25 1000 ns 4 5V to 5 5V 40 1000 ns 2 7V to 5 5V TDUTY Duty Cycle 0 45 0 55 TOSH TOSH TOSL External Clock Input
15. 886 3 572 9526 Fax 886 3 572 6459 Taiwan Kaohsiung Tel 886 7 536 4818 Fax 886 7 536 4803 Taiwan Taipei Tel 886 2 2500 6610 Fax 886 2 2508 0102 Thailand Bangkok Tel 66 2 694 1351 Fax 66 2 694 1350 EUROPE Austria Wels Tel 43 7242 2244 39 Fax 43 7242 2244 393 Denmark Copenhagen Tel 45 4450 2828 Fax 45 4485 2829 France Paris Tel 33 1 69 53 63 20 Fax 33 1 69 30 90 79 Germany Munich Tel 49 89 627 144 0 Fax 49 89 627 144 44 Italy Milan Tel 39 0331 742611 Fax 39 0331 466781 Netherlands Drunen Tel 31 416 690399 Fax 31 416 690340 Spain Madrid Tel 34 91 708 08 90 Fax 34 91 708 08 91 UK Wokingham Tel 44 118 921 5869 Fax 44 118 921 5820 10 05 07 DS21801E page 84 2007 Microchip Technology Inc
16. ERROR FLAG ADDRESS 2Dh R W 0 R W 0 R 0 R 0 R 0 R 0 R 0 R 0 RX1OVR RXOOVR TXBO TXEP RXEP TXWAR RXWAR EWARN bit 7 bit 0 Legend R Readable bit W Writable bit U Unimplemented bit read as 0 n Value at POR T Bit is set 0 Bit is cleared x Bit is unknown bit 7 RX10VR Receive Buffer 1 Overflow Flag bit Set when a valid message is received for RXB1 and CANINTF RX1IF 1 Must be reset by MCU bit 6 RXOOVR Receive Buffer 0 Overflow Flag bit Set when a valid message is received for RXBO and CANINTF RXOIF 1 Must be reset by MCU bit 5 TXBO Bus Off Error Flag bit Bit set when TEC reaches 255 Reset after a successful bus recovery sequence bit 4 TXEP Transmit Error Passive Flag bit Set when TEC is equal to or greater than 128 Reset when TEC is less than 128 bit 3 RXEP Receive Error Passive Flag bit Set when REC is equal to or greater than 128 Reset when REC is less than 128 bit 2 TXWAR Transmit Error Warning Flag bit Set when TEC is equal to or greater than 96 Reset when TEC is less than 96 bit 1 RXWAR Receive Error Warning Flag bit Set when REC is equal to or greater than 96 Reset when REC is less than 96 bit 0 EWARN Error Warning Flag bit Set when TEC or REC is equal to or greater than 96 TXWAR or RXWAR 1 Reset when both REC and TEC are less than 96 2007 Microchip Technology Inc DS21801E page 47
17. Unimplemented bit read as 0 n Value at POR 1 Bit is set 0 Bit is cleared x Bit is unknown bit 7 5 SID Standard Identifier bits lt 2 0 gt bit 4 Unimplemented Reads as 0 bit 3 EXIDE Extended Identifier Enable bit 1 Message will transmit extended identifier 0 Message will transmit standard identifier bit 2 Unimplemented Reads as 0 bit 1 0 EID Extended Identifier bits lt 17 16 gt REGISTER 3 5 TXBnEID8 TRANSMIT BUFFER n EXTENDED IDENTIFIER HIGH ADDRESS 33h 43h 53h R W x R W x R W x R W x R W x R W x R W x R W x EID15 EID14 EID13 EID12 EID11 EID10 EID9 EID8 bit 7 bit 0 Legend R Readable bit W Writable bit U Unimplemented bit read as 0 n Value at POR 1 Bit is set 0 Bit is cleared x Bit is unknown bit 7 0 EID Extended Identifier bits lt 15 8 gt REGISTER 3 6 TXBnEIDO TRANSMIT BUFFER n EXTENDED IDENTIFIER LOW ADDRESS 34h 44h 54h R W x R W x R W x R W x R W x R W x R W x R W x EID7 EID6 EID5 EID4 EID3 EID2 EID1 EIDO bit 7 bit 0 Legend R Readable bit W Writable bit U Unimplemented bit read as 0 n Value at POR 1 Bit is set 0 Bit is cleared Bit is unknown bit 7 0 EID Extended Identifier bits lt 7 0 gt DS21801E page 20 2007 Microchip Technology Inc MCP2515 REGISTER 3 7 T
18. in TQ s of PS1 The SAM bit controls how many times the RXCAN pin is sampled Setting this bit to a 1 causes the bus to be sampled three times twice at 2 before the sample point and once at the normal sample point which is at the end of PS1 The value of the bus is determined to be the majority sampled If the SAM bit is set to a 0 the RXCAN pin is sampled only once at the sample point The BTLMODE bit controls how the length of PS2 is determined If this bit is set to a 1 the length of PS2 is determined by the PHSEG2 lt 2 0 gt bits of CNF3 see Section 5 5 3 CNF3 If the BTLMODE bit is set to a 0 the length of PS2 is greater than that of PS1 and the information processing time which is fixed at 2 To for the MCP2515 5 5 8 CNF3 The PHSEG2 lt 2 0 gt bits set the length of PS2 if the CNF2 BTLMODE bit is set to a 1 If the BTLMODE bit is set to a 0 the PHSEG2 lt 2 0 gt bits have no effect 2007 Microchip Technology Inc DS21801E page 41 2515 REGISTER 5 1 CNF1 CONFIGURATION 1 ADDRESS 2Ah R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 SJW1 SJWO BRP5 BRP4 BRP3 BRP2 BRP1 BRPO bit 7 bit 0 Legend R Readable bit W Writable bit U Unimplemented bit read as 0 n Value at POR 1 Bit is set 0 Bit is cleared x Bit is unknown bit 7 6 SJW Synchronization Jum
19. six consecutive recessive bits on the bus before attempting to rejoin bus communications The error delimiter consists of eight recessive bits and allows the bus nodes to restart bus communications cleanly after an error has occurred 2 5 Overload Frame An overload frame shown in Figure 2 5 has the same format as an active error frame An overload frame however can only be generated during an interframe space In this way an overload frame can be differenti ated from an error frame an error frame is sent during the transmission of a message The overload frame consists of two fields an overload flag followed by an overload delimiter The overload flag consists of six dominant bits followed by overload flags generated by other nodes and as for an active error flag giving a maximum of twelve dominant bits The overload delimiter consists of eight recessive bits An overload frame can be generated by a node as a result of two conditions 1 The node detects a dominant bit during the interframe space illegal condition Exception The dominant bit is detected during the third bit of IFS In this case the receivers will interpret this as a SOF 2 Due to internal conditions the node is not yet able to begin reception of the next message A node may generate a maximum of two sequential overload frames to delay the start of the next message Note Case 2 should never occur with the MCP2515 due to very short internal
20. 949 10 4 4 E 9L gt a 9 Le Sq JO ejoueH 2007 Microchip Technology Inc 2515 5 DS21801E page 14 2007 Microchip Technology Inc MCP2515 3 0 MESSAGE TRANSMISSION 3 1 Transmit Buffers The MCP2515 implements three transmit buffers Each of these buffers occupies 14 bytes of SRAM and are mapped into the device memory map The first byte TXBnCTRL is a control register associated with the message buffer The information in this register determines the conditions under which the message will be transmitted and indicates the status of the message transmission see Register 3 2 Five bytes are used to hold the standard and extended identifiers as well as other message arbitration information see Register 3 4 through Register 3 7 The last eight bytes are for the eight possible data bytes of the message to be transmitted see Register 3 8 At a minimum the TXBnSIDH TXBnSIDL and TXBnDLC registers must be loaded If data bytes are present in the message the TXBnDm registers must also be loaded If the message is to use extended identifiers the TXBnEIDm registers must also be loaded and the TXBnSIDL EXIDE bit set Prior to sending the message the MCU must initialize the CANINTE TXInE bit to enable or disable the generation of an interrupt when the message is sent Note The
21. Listen only Mode Listen only mode provides a means for the MCP2515 to receive all messages including messages with errors by configuring the RXBnCTRL RXM lt 1 0 gt bits This mode can be used for bus monitor applications or for detecting the baud rate in hot plugging situations For auto baud detection it is necessary that there are at least two other nodes that are communicating with each other The baud rate can be detected empirically by testing different values until valid messages are received Listen only mode is a silent mode meaning no messages will be transmitted while in this mode including error flags or acknowledge signals The filters and masks can be used to allow only particular messages to be loaded into the receive registers or the masks can be set to all zeros to allow a message with any identifier to pass The error counters are reset and deactivated in this state The Listen only mode is activated by setting the mode request bits in the CANCTRL register 2007 Microchip Technology Inc DS21801E page 57 MCP2515 10 4 Loopback Mode Loopback mode will allow internal transmission of messages from the transmit buffers to the receive buffers without actually transmitting messages on the CAN bus This mode can be used in system development and testing In this mode the ACK bit is ignored and the device will allow incoming messages from itself just as if they were coming from another node The L
22. PropSeg PS1 PS2 Associated with the NBT are the sample point Synchronization Jump Width SJW and Information Processing Time IPT which are explained later SYNCHRONIZATION SEGMENT The Synchronization Segment SyncSeg is the first segment in the NBT and is used to synchronize the nodes on the bus Bit edges are expected to occur within the SyncSeg This segment is fixed at 1 TQ FIGURE 5 1 CAN BIT TIME SEGMENTS SyncSeg PropSeg PhaseSeg1 PS1 PhaseSeg2 PS2 Sample Point Nominal Bit Time NBT tpit gt 2007 Microchip Technology Inc DS21801E page 37 MCP2515 PROPAGATION SEGMENT The Propagation Segment PropSeg exists 10 compensate for physical delays between nodes The propagation delay is defined as twice the sum of the signal s propagation time on the bus line including the delays associated with the bus driver The PropSeg is programmable from 1 8 TQ PHASE SEGMENT 1 PS1 AND PHASE SEGMENT 2 PS2 The two phase segments PS1 and PS2 are used to compensate for edge phase errors on the bus PS1 can be lengthened or PS2 shortened by resyncronization PS1 is programmable from 1 8 TQ and PS2 is programmable from 2 8 TQ SAMPLE POINT The sample point is the point in the bit time at which the logic level is read and interpreted The sample point is located at the end of PS1 The exception to this rule is if the sample mode is configu
23. bit provided that the mask for that bit is set to a 1 see Figure 12 7 FIGURE 12 1 BIT MODIFY Mask byte 010110101 Data byte 1 Previous O which registers allow the use of this Register olilolilolololi commana Contents Note Executing the Bit Modify command on Resulting registers that are not bit modifiable will Register 011111010 0 0 1 force the mask to FFh This will allow byte Contents writes to the registers not bit modify TABLE 12 1 SPI INSTRUCTION SET Instruction Name Instruction Format Description RESET 1100 0000 Resets internal registers to default state set Configuration mode READ 0000 0011 Read data from register beginning at selected address Read RX Buffer 1001 When reading a receive buffer reduces the overhead of a normal read command by placing the address pointer at one of four locations as indicated by n m Note The associated RX flag bit CANINTF RXnIF will be cleared after bringing CS high WRITE 0000 0010 Write data to register beginning at selected address Load TX Buffer 0100 When loading a transmit buffer reduces the overhead of a normal Write command by placing the address pointer at one of six locations as indicated by a b c RTS 1000 Onnn Instructs controller to begin message transmission sequence f
24. delays 2 6 Interframe Space The interframe space separates a preceding frame of any type from a subsequent data or remote frame The interframe space is composed of at least three recessive bits called the Intermission This allows nodes time for internal processing before the start of the next message frame After the intermission the bus line remains in the recessive state bus idle until the next transmission starts DS21801E page 8 2007 Microchip Technology Inc MCP2515 STANDARD DATA FRAME FIGURE 2 1 Bulynys 11g ui lt gt Buyers 5 gt g Jeynuep 01000 rn iid O 531 828 5 EBRES S op 58 awe ge D SL gt lt 8 gt lt 8 de oet v LE m o pu3 2i S pier 949 pier4 eieg 1 pjer4 lt yA gt 9r 8 gt 50 e Le 19 10 1equinu eieq DS21801E page 9 2007 Microchip Technology Inc MCP2515 EXTENDED DATA FRAME FIGURE 2 2
25. of the phase error is less than or equal to the programmed value of the SJW the effect of a resynchronization is the same as that of a hard synchronization 5 2 2 3 Positive Phase Error e 0 If the magnitude of the phase error is larger than the SJW and if the phase error is positive PS1 is lengthened by an amount equal to the SJW 5 2 2 4 Negative Phase Error e 0 If the magnitude of the phase error is larger than the resynchronization jump width and the phase error is negative PS2 is shortened by an amount equal to the SJW 5 2 8 SYNCHRONIZATION RULES 1 Only recessive to dominant edges will be used for synchronization 2 Only one synchronization within one bit time is allowed 3 An edge will be used for synchronization only if the value detected at the previous sample point previously read bus value differs from the bus value immediately after the edge 4 Atransmitting node will not resynchronize on a positive phase error e gt 0 5 If the absolute magnitude of the phase error is greater than the SJW the appropriate phase segment will adjust by an amount equal to the SJW 2007 Microchip Technology Inc DS21801E page 39 MCP2515 FIGURE 5 3 SYNCHRONIZING THE BIT TIME Input Signal e 0 PhaseSeg2 PS2 SyncSeg PropSeg PhaseSe
26. there is an error state warning flag bit EFLG EWARN which is set if at least one of the error counters equals or exceeds the error warning limit of 96 EWARN is reset if both error counters are less than the error warning limit 2007 Microchip Technology Inc DS21801E page 45 MCP2515 FIGURE 6 1 ERROR MODES STATE DIAGRAM RESET lt 127 Error Active TEC lt 127 128 occurrences of 11 consecutive REC gt 127 or recessive bits TEC gt 127 TEC gt 255 REGISTER 6 1 TRANSMIT ERROR COUNTER ADDRESS 1Ch 0 0 0 0 0 0 0 0 7 TEC6 TEC5 4 TEC2 bit 7 bit 0 Legend R Readable bit W Writable bit U Unimplemented bit read as 0 n Value at POR 1 Bit is set 0 Bit is cleared Bit is unknown bit 7 0 TEC Transmit Error Count bits lt 7 0 gt REGISTER 6 2 REC RECEIVER ERROR COUNTER ADDRESS 1Dh 0 0 0 0 0 0 0 0 7 REC6 REC5 REC4 REC3 REC2 REC1 RECO bit 7 bit 0 Legend R Readable bit W Writable bit U Unimplemented bit read as 0 n Value at POR 1 Bit is set 0 Bit is cleared Bit is unknown bit 7 0 REC Receive Error Count bits lt 7 0 gt DS21801E page 46 2007 Microchip Technology Inc MCP2515 REGISTER 6 3
27. unknown bit 7 0 REGISTER 4 11 SID Standard Identifier Filter bits lt 10 3 gt These bits hold the filter bits to be applied to bits lt 10 3 gt of the Standard Identifier portion of a received message RXFnSIDL FILTER n STANDARD IDENTIFIER LOW ADDRESS 01h 05h 09h 11h 15h 19h R W x R W x R W x U 0 R W x U 0 R W x R W x SID2 SID1 SIDO EXIDE EID17 EID16 bit 7 bit 0 Legend R Readable bit W Writable bit U Unimplemented bit read as 0 n Value at POR 1 Bit is set 0 Bit is cleared x Bit is unknown bit 7 5 bit 4 bit 3 bit 2 bit 1 0 SID Standard Identifier Filter bits lt 2 0 gt These bits hold the filter bits to be applied to bits lt 2 0 gt of the Standard Identifier portion of a received message Unimplemented Reads as 0 EXIDE Extended Identifier Enable bit 1 Filter is applied only to Extended Frames 0 Filter is applied only to Standard Frames Unimplemented Reads as 0 EID Extended Identifier Filter bits lt 17 16 gt These bits hold the filter bits to be applied to bits lt 17 16 gt of the Extended Identifier portion of a received message DS21801E page 34 2007 Microchip Technology Inc MCP2515 REGISTER 4 12 RXFnEID8 FILTER n EXTENDED IDENTIFIER HIGH ADDRESS 02h 06h 12h 16h 1Ah R W x R W x R W x R W x R W x R W x
28. using a DPLL that is configured to synchronize to the incoming data as well as provide the nominal timing for the transmitted data The DPLL breaks each bit time into multiple segments made up of minimal periods of time called the Time Quanta TQ Bus timing functions executed within the bit time frame such as synchronization to the local oscillator network transmission delay compensation and sample point positioning are defined by the programmable bit timing logic of the DPLL 5 1 The CAN Bit Time All devices on the CAN bus must use the same bit rate However all devices are not required to have the same master oscillator clock frequency For the different clock frequencies of the individual devices the bit rate has to be adjusted by appropriately setting the baud rate prescaler and number of time quanta in each segment The CAN bit time is made up of non overlapping segments Each of these segments are made up of integer units called Time Quanta TQ explained later in this data sheet The Nominal Bit Rate NBR is defined in the CAN specification as the number of bits per second transmitted by an ideal transmitter with no resynchronization It can be described with the equation EQUATION 5 1 1 NBR fhi gt Nominal Bit Time The Nominal Bit Time NBT tpi is made up of non overlapping segments Figure 5 1 Therefore the NBT is the summation of the following segments bit SyncSeg
29. well as status registers accessed via the SPI interface can also be used to determine when a valid message has been received Additionally there are three pins available to initiate immediate transmission of a message that has been loaded into one of the three transmit registers Use of these pins is optional as initiating message transmissions can also be accomplished by utilizing control registers accessed via the SPI interface 1 3 SPI Protocol Block The MCU interfaces to the device via the SPI interface Writing to and reading from all registers is accomplished using standard SPI read and write commands in addition to specialized SPI commands FIGURE 1 1 BLOCK DIAGRAM CAN Module T RXCAN TX and Buffers SPI Cs Protocol Interface SCK SPI Engine Masks and Filters Logic 4 SI Bus TXCAN SO Control Logic OSC1 mimi 0862 a 9 A n Generation INT CLKOUT 4 gt RXOBF gt RX1BF TXORTS Control TXIRTS and Interrupt TX2RTS Registers RESET 2007 Microchip Technology Inc DS21801E page 3 MCP2515
30. 1 3431 Australia Sydney Tel 61 2 9868 6733 Fax 61 2 9868 6755 China Beijing Tel 86 10 8528 2100 Fax 86 10 8528 2104 China Chengdu Tel 86 28 8665 5511 Fax 86 28 8665 7889 China Fuzhou Tel 86 591 8750 3506 Fax 86 591 8750 3521 China Hong Kong SAR Tel 852 2401 1200 Fax 852 2401 3431 China Nanjing Tel 86 25 8473 2460 Fax 86 25 8473 2470 China Qingdao Tel 86 532 8502 7355 Fax 86 532 8502 7205 China Shanghai Tel 86 21 5407 5533 Fax 86 21 5407 5066 China Shenyang Tel 86 24 2334 2829 Fax 86 24 2334 2393 China Shenzhen Tel 86 755 8203 2660 Fax 86 755 8203 1760 China Shunde Tel 86 757 2839 5507 Fax 86 757 2839 5571 China Wuhan Tel 86 27 5980 5300 Fax 86 27 5980 5118 China Xian Tel 86 29 8833 7252 Fax 86 29 8833 7256 ASIA PACIFIC India Bangalore Tel 91 80 4182 8400 Fax 91 80 4182 8422 India New Delhi Tel 91 11 4160 8631 Fax 91 11 4160 8632 India Pune Tel 91 20 2566 1512 Fax 91 20 2566 1513 Japan Yokohama Tel 81 45 471 6166 Fax 81 45 471 6122 Korea Daegu Tel 82 53 744 4301 Fax 82 53 744 4302 Korea Seoul Tel 82 2 554 7200 Fax 82 2 558 5932 or 82 2 558 5934 Malaysia Kuala Lumpur Tel 60 3 6201 9857 Fax 60 3 6201 9859 Malaysia Penang Tel 60 4 227 8870 Fax 60 4 227 4068 Philippines Manila Tel 63 2 634 9065 Fax 63 2 634 9069 Singapore Tel 65 6334 8870 Fax 65 6334 8850 Taiwan Hsin Chu Tel
31. 1 Interrupt bit O Unimplemented Read as 0 2007 Microchip Technology Inc DS21801E page 59 2515 5 DS21801E page 60 2007 Microchip Technology Inc MCP2515 11 0 REGISTER MAP reading and writing of data Some specific control and status registers allow individual bit modification using The register map for the MCP2515 is shown in the SPI Bit Modify command The registers that allow Table 11 1 Address locations for each register are this command are shown as shaded locations in determined by using the column higher order 4 bits Table 11 1 A summary of the MCP2515 control and row lower order 4 bits values The registers registers is shown in Table 11 2 have been arranged to optimize the sequential TABLE 11 1 CONTROLLER REGISTER MAP Lower Higher Order Address Bits Address Bits 0000 xxxx 0001 xxxx 0010 xxxx 0011 xxxx 0100 xxxx 0101 xxxx 0110 xxxx 0111 xxxx 0000 RXFOSIDH RXF3SIDH RXMOSIDH TXBOCTRL TXB1CTRL TXB2CTRL RXBOCTRL RXB1CTRL 000 RXFOSIDL RXF3SIDL RXMOSIDL TXBOSIDH TXB1SIDH TXB2SIDH RXBOSIDH RXB1SIDH 0010 RXFOEID8 RXF3EID8 RXMOEID8 TXBOSIDL TXB1SIDL TXB2SIDL RXBOSIDL RXB1SIDL 001 RXFOEIDO RXF3EIDO RXMOEIDO TXBOEID8 TXB1EID8 TXB2EID8 RXBOEID8 RXB1EID8 0100 RXF1SIDH RXF4SIDH RXM1SIDH TXBOEIDO TXB1EIDO TXB2EIDO RXBOEIDO RXB1EIDO 010 RXF1SIDL RXF4SIDL RXM1SIDL TXBODLC TXB1DLC TXB2DLC
32. 28 SOF wAKFL PHSEG22 PHSEG 1 PHSEG20 00 000 CNF2 29 BTLMODE SAM PHSEG12 PHSEG11 PHSEG10 PRSEG2 PRSEG1 PRSEGO 0000 0000 CNF1 2A SJW1 SJWO BRP5 BRP4 BRP3 BRP2 1 BRPO 0000 0000 CANINTE 28 MERRE WAKIE ERRIE TX2IE RXOIE 0000 0000 CANINTF 2 MERRF WAKIF ERRIF TXIIF TXOIF RXOIF 0000 0000 EFLG 2D RXIOVR RXOOVR TXBO TXEP RXEP TXWAR RXWAR EWARN 0000 0000 TXBOCTRL 30 ABTF MLOA TXERR TXREQ 1 000 0 00 TXBICTRL 40 ABTF MLOA TXERR TXREQ 1 TXPO 000 0 00 TXB2CTRL 50 ABTF MLOA TXERR TXREQ 1 TXPO 000 0 00 RXBOCTRL 60 E RXM1 RXMO RXRTR BUKT BUKT FILHITO 00 0000 RXBICTRL 70 RSM1 RXMO RXRTR FILHIT2 FILHIT1 FILHITO 00 0000 2007 Microchip Technology Inc DS21801E page 61 2515 5 DS21801E page 62 2007 Microchip Technology Inc MCP2515 12 0 SPI INTERFACE 12 1 Overview The MCP2515 is designed to interface directly with the Serial Peripheral Interface SPI port available on many microcontrollers and supports Mode 0 0 and Mode 1 1 Commands and data are sent to the device the 1 pin with data being clocked in on the rising edge of SCK Data is driven out by the MCP2515 on the SO line on the falling edge of SCK The CS pin must be held low while any
33. 5 gt gt DS21801E page 11 2007 Microchip Technology Inc 2515 ERROR FRAME FIGURE 2 4 10 eoeds 1 1 oo Jeyuuneq 10113 1013 0193 10113 9121 Jo eyeq lt 8 93 9 Buinis ig gt 4 10413 20 2 5 ubue 0 eed JOUER 9 omo g pem 2 E 8 gt gt lt 8 lt v LE d 4 5 pier PIE UONENIJJY 85N50 8 4 9 eL La peidnueiu gt 2007 Microchip Technology Inc DS21801E page 12 MCP2515 OVERLOAD FRAME FIGURE 2 5 dp LJO olo oo ofo 91214 4043 8 Le 9 gt 10 4043 10 eoedg 1 1 JO 9LUEJ 0 puJ La gt 4 DS21801E page 13 oe lo O8 o 5 5 e op 949 5 62 6 si 4 gt a LE gt Q owed o Jo pu3 z plats 5
34. BFPCTRL BxBFM bits these pins are active low and are mapped to the CANINTF RXnIF bit for each receive buffer When this bit goes high for one of the receive buffers indicating that a valid message has been loaded into the buffer the corresponding RXBnBF pin will go low When the CANINTF RXnIF bit is cleared by the MCU the corresponding interrupt pin will go to the logic high state until the next message is loaded into the receive buffer Normal SOF Signaling 4 START OF FRAME BIT M ID BIT Sample Point RXCAN mE gt Glitch Filtering 4 EXPECTED START OF FRAME BIT gt Expected Sample Point BUS IDLE RXCAN DS21801E page 24 2007 Microchip Technology Inc MCP2515 4 4 3 CONFIGURED AS DIGITAL OUTPUT TABLE 4 1 CONFIGURING RXNBF PINS When used as digital outputs the BFPCTRL BxBFM bit BnBFE BnBFM BnBFS Pin Status must be cleared and BFPCTRL BnBFE must be set for 0 X X Disabled high impedance the associated buffer In this mode the state of the pin is controlled by the BFPCTRL BnBFS bits Writing a 1 Receive buffer interrupt 1 1 X to the BnBFS bit will cause a high level to be driven on 1 0 0 Digital output 0 1 0 1 the associated buffer full pin while a 0 will cause the Digital output 1 pin to drive low When using the pins in this mode the state of the pin should be modified on
35. ION 4 1 Receive Message Buffering The MCP2515 includes two full receive buffers with multiple acceptance filters for each There is also a separate Message Assembly Buffer MAB that acts as a third receive buffer see Figure 4 2 4 1 1 MESSAGE ASSEMBLY BUFFER Of the three receive buffers the MAB is always committed to receiving the next message from the bus The MAB assembles all messages received These messages will be transferred to the RXBn buffers See Register 4 4 to Register 4 9 only if the acceptance filter criteria is met 4 1 2 RXBO AND RXB1 The remaining two receive buffers called RXBO and RXB1 can receive a complete message from the protocol engine via the MAB The MCU can access one buffer while the other buffer is available for message reception or for holding previously received message Note The entire contents of the MAB is moved into the receive buffer once a message is accepted This means that regardless of the type of identifier standard or extended and the number of data bytes received the entire receive buffer is overwritten with the contents Therefore the contents of all registers in the buffer must be assumed to have been modified when any message Is received 4 1 3 RECEIVE FLAGS INTERRUPTS When a message is moved into either of the receive buffers the appropriate CANINTF RXnIF bit is set This bit must be cleared by the MCU in order to allow a new message to be
36. LG register 1 Interrupt pending must be cleared by MCU to reset interrupt condition 0 No interrupt pending bit 4 TX2IF Transmit Buffer 2 Empty Interrupt Flag bit 1 Interrupt pending must be cleared by MCU to reset interrupt condition 0 No interrupt pending bit 3 TX1IF Transmit Buffer 1 Empty Interrupt Flag bit 1 Interrupt pending must be cleared by MCU to reset interrupt condition 0 No interrupt pending bit 2 TXOIF Transmit Buffer 0 Empty Interrupt Flag bit 1 Interrupt pending must be cleared by MCU to reset interrupt condition 0 No interrupt pending bit 1 RX1IF Receive Buffer 1 Full Interrupt bit 1 Interrupt pending must be cleared by MCU to reset interrupt condition 0 No interrupt pending bit 0 RXOIF Receive Buffer 0 Full Interrupt Flag bit 1 Interrupt pending must be cleared by MCU to reset interrupt condition 0 No interrupt pending 2007 Microchip Technology Inc DS21801E page 51 2515 5 DS21801E page 52 2007 Microchip Technology Inc MCP2515 8 0 OSCILLATOR The MCP2515 is designed to be operated with a crystal or ceramic resonator connected to the OSC1 and OSC2 pins The MCP2515 oscillator design requires the use of a parallel cut crystal Use of a series cut crystal may give a frequency out of the crystal manufacturers specifications A typical oscillator circuit is shown in Figure 8 1 The MCP2515 may also be driven by an external clock source co
37. MICROCHIP MCP2515 Stand Alone CAN Controller With SPI Interface Features Implements CAN V2 0B at 1 Mb s 0 8 byte length in the data field Standard and extended data and remote frames Receive buffers masks and filters Two receive buffers with prioritized message storage Six 29 bit filters Two 29 bit masks Data byte filtering on the first two data bytes applies to standard data frames Three transmit buffers with prioritizaton and abort features High speed SPI Interface 10 MHz SPI modes 0 0 and 1 1 One shot mode ensures message transmission is attempted only one time Clock out pin with programmable prescaler Can be used as a clock source for other device s Start of Frame SOF signal is available for monitoring the SOF signal Can be used for time slot based protocols and or bus diagnostics to detect early bus degredation Interrupt output pin with selectable enables Buffer Full output pins configurable as Interrupt output for each receive buffer General purpose output Request to Send RTS input pins individually configurable as Control pins to request transmission for each transmit buffer General purpose inputs Low power CMOS technology Operates from 2 7V 5 5V 5 mA active current typical 1 LA standby current typical Sleep mode Temperature ranges supported Industrial I 40 C to 85 C Extended E 40 C to 125 C D
38. O Tape and Reel Temperature 40 to 85 C Industrial Industrial Temperature Range 40 to 125 Extended 1810 SOIC package f MCP2515 1 ST Industrial Temperature Package Plastic DIP 300 mil Body 18 Lead 20LD TSSOP package SO Plastic SOIC 300 mil Body 18 Lead g MCP2515T I ST Tape and Reel ST TSSOP 4 4 mm Body 20 Lead Industrial Temperature 20LD TSSOP package 2007 Microchip Technology Inc DS21801E page 81 2515 5 DS21801E page 82 2007 Microchip Technology Inc Note the following details of the code protection feature on Microchip devices Microchip products meet the specification contained in their particular Microchip Data Sheet Microchip believes that its family of products is one of the most secure families of its kind on the market today when used in the intended manner and under normal conditions There are dishonest and possibly illegal methods used to breach the code protection feature All of these methods to our knowledge reguire using the Microchip products manner outside the operating specifications contained in Microchip s Data Sheets Most likely the person doing so is engaged in theft of intellectual property Microchip is willing to work with the customer who is concerned about the integrity of their code Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their
39. PI interface 50 15 17 Data output for SPI interface 5 16 18 Chip select input for SPI interface RESET 17 19 Active low device reset input VDD 18 20 P Positive supply for logic and pins NC m 6 15 No internal connection Note Type Identification Input Output P Power DS21801E page 4 2007 Microchip Technology Inc MCP2515 1 4 Transmit Receive Buffers Masks Filters The MCP2515 has three transmit and two receive buffers two acceptance masks one for each receive buffer and a total of six acceptance filters Figure 1 3 shows a block diagram of these buffers and their connection to the protocol engine FIGURE 1 3 CAN BUFFERS AND PROTOCOL ENGINE BLOCK DIAGRAM BUFFE RS Acceptance Mask RXM1 XZ Acceptance Filter RXF2 SZ _ Acceptance Mask Acceptance Filter RXF3 XZ ZS SZ 0 c Acceptance Filter Acceptance Filter e lt lt 5 RXFO RX4 o 0 0 SZ ZS SZ ZS t i Acceptance Filter Acceptance Filter RXF1 RXF5 R M R X Identifier A Identifier X Message B B Queue 0 B 1 Control Transmit Byte Seguencer Data Field Data Fi
40. Ps that filter on the first data byte e g DeviceNet 4 5 2 FILTER MATCHING The filter masks see Register 4 14 through Register 4 17 are used to determine which bits in the identifier are examined with the filters A truth table is shown in Table 4 2 that indicates how each bit in the identifier is compared to the masks and filters to deter mine if the message should be loaded into a receive buffer The mask essentially determines which bits to apply the acceptance filters to If any mask bit is set to a zero that bit will automatically be accepted regardless of the filter bit TABLE 4 2 FILTER MASK TRUTH TABLE Mask Bit Filter n identifier Reject bit bit n x X Accept o 0 0 1 Reject 1 1 0 Reject 1 1 Note X don t care As shown in the receive buffers block diagram Figure 4 2 acceptance filters RXFO and filter mask RXMO are associated with RXBO Filters RXF2 RXF3 RXF4 RXF5 and mask RXM1 are associated with RXB1 FIGURE 4 4 MASKS AND FILTERS APPLY TO CAN FRAMES Extended Frame ID10 IDO EID17 EIDO ha Masks and Filters apply to the entire 29 bit ID field gt Standard Data Frame 1010 100 Data Byte 0 Data Byte 1 4 11 bit ID Standard frame 9 q 16 bit data filtering gt The two MSb EID17 and EID16 mask and filter bits are not used DS21801E page 32
41. R W x R W x EID15 EID14 EID13 EID12 EID11 EID10 EID9 EID8 bit 7 bit 0 Legend R Readable bit W Writable bit U Unimplemented bit read as 0 n Value at POR 1 Bit is set 0 Bit is cleared x Bit is unknown bit 7 0 EID Extended Identifier bits lt 15 8 gt These bits hold the filter bits to be applied to bits lt 15 8 gt of the Extended Identifier portion of a received message REGISTER 4 13 RXFnEIDO FILTER n EXTENDED IDENTIFIER LOW ADDRESS 03h 07h OBh 13h 17h 1Bh R W x R W x R W x R W x R W x R W x R W x R W x EID7 EID6 EID5 EID4 EID3 EID2 EID1 EIDO bit 7 bit 0 Legend R Readable bit W Writable bit U Unimplemented bit read as 0 Value at POR 1 Bit is set 0 Bit is cleared Bit is unknown bit 7 0 EID Extended Identifier bits lt 7 0 gt These bits hold the filter bits to be applied to the bits lt 7 0 gt of the Extended Identifier portion of a received message REGISTER 4 14 RXMnSIDH MASK n STANDARD IDENTIFIER HIGH ADDRESS 20h 24h R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 51010 5109 5108 5107 5106 5105 5104 5103 bit 7 bit 0 Legend R Readable bit W Writable bit U Unimplemented bit read as 0 n Value at POR 1 Bit is set 0 Bit is cleared x Bit is unknown bit 7 0 SID Standard Identifier Mask bits lt 10 3 gt These bits hold the mas
42. RL CLKEN 1 1 CLKOUT pin enabled for SOF signal 0 CLKOUT pin enabled for clockout function If CANCTRL CLKEN 0 Bit is don t care bit 6 WAKFIL Wake up Filter bit 1 Wake up filter enabled 0 Wake up filter disabled bit 5 3 Unimplemented Reads as 0 bit 2 0 PHSEG2 PS2 Length bits lt 2 0 gt PHSEG2 1 x Ta Minimum valid setting for PS2 is 2 Ta 2007 Microchip Technology Inc DS21801E page 43 2515 5 DS21801E page 44 2007 Microchip Technology Inc MCP2515 6 0 ERROR DETECTION The CAN protocol provides sophisticated error detection mechanisms The following errors can be detected 6 1 CRC Error With the Cyclic Redundancy Check CRC the transmitter calculates special check bits for the bit sequence from the start of a frame until the end of the data field This CRC sequence is transmitted in the CRC Field The receiving node also calculates the CRC sequence using the same formula and performs a comparison to the received sequence If a mismatch is detected a CRC error has occurred and an error frame is generated The message is repeated 6 2 Acknowledge Error In the acknowledge field of a message the transmitter checks if the acknowledge slot which has been sent out as arecessive bit contains a dominant bit If not no other node has received the frame correctly An acknowledge error has occurred an error frame is generated and the message will have to be re
43. RXBODLC RXB1DLC 0110 RXF1EID8 RXF4EID8 RXM1EID8 TXBODO TXB1DO TXB2DO RXBODO RXB1D0 011 RXF1EIDO RXF4EIDO RXM1EIDO TXBOD1 TXB1D1 TXB2D1 RXBOD1 RXB1D1 000 RXF2SIDH RXF5SIDH CNF3 TXBOD2 TXB1D2 TXB2D2 RXBOD2 RXB1D2 00 RXF2SIDL RXF5SIDL CNF2 TXBOD3 TXB1D3 TXB2D3 RXBOD3 RXB1D3 010 RXF2EID8 RXF5EID8 CNF1 TXBOD4 TXB1D4 TXB2D4 RXBOD4 RXB1D4 01 RXF2EIDO RXF5EIDO CANINTE TXBOD5 TXB1D5 TXB2D5 RXBOD5 RXB1D5 100 BFPCTRL TEC CANINTF TXBOD6 TXB1D6 TXB2D6 RXBOD6 RXB1D6 110 TXRTSCTRL REC EFLG TXBOD7 TXB1D7 TXB2D7 RXBOD7 RXB1D7 110 CANSTAT CANSTAT CANSTAT CANSTAT CANSTAT CANSTAT CANSTAT CANSTAT 11 CANCTRL CANCTRL CANCTRL CANCTRL CANCTRL CANCTRL CANCTRL CANCTRL Note Shaded register locations indicate that these allow the user to manipulate individual bits using the Bit Modify command TABLE 11 2 CONTROL REGISTER SUMMARY rs Bit7 Bit 6 Bit5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0 BIBFS BOBFS BIBFE BOBFE B1BFM 00 0000 TXRTSCTRL B2RTS B1RTS BORTS B2RTSM B1RTSM BORTSM x000 CANSTAT xE OPMOD2 ICOD2 1 1 ICODO 100 000 CANCTRL xF 2 OSM CLKEN CLKPRE1 CLKPREO 1110 0111 TEC 1C Transmit Error Counter TEC 0000 0000 REC 1D Receive Error Counter REC 0000 0000 CNF3
44. RXM BITS The RXBnCTRL RXM bits set special receive modes Normally these bits are cleared to 00 to enable reception of all valid messages as determined by the appropriate acceptance filters In this case the determination of whether or not to receive standard or extended messages is determined by the RFXnSIDL EXIDE bit in the acceptance filter register If RXBnCTRL RXM bits are set to 01 or 10 the receiver will only accept messages with standard or extended identifiers respectively If an acceptance filter has the RFXnSIDL EXIDE bit set such that it does not correspond with the RXBnCTRL RXM mode that acceptance filter is rendered useless These two modes of RXBnCTRL RXM bits can be used in systems where it is known that only standard or extended messages will be on the bus If the RXBnCTRL RXM bits are set to 11 the buffer will receive all messages regardless of the values of the acceptance filters Also if a message has an error before the EOF that portion of the message assembled in the MAB before the error frame will be loaded into the buffer This mode has some value in debugging a CAN system and would not be used in an actual system environment 2007 Microchip Technology Inc DS21801E page 23 MCP2515 4 3 Start of Frame Signal If enabled the Start Of Frame signal is generated on the SOF pin at the beginning of each CAN message detected on the RXCAN pin The RXCAN pin monitors an idle bus for a recessiv
45. Setting the TXnRTS pin low for the particular transmit buffer s that are to be transmitted If transmission is initiated via the SPI interface the TXREQ bit can be set at the same time as the TXP priority bits When TXBnCTRL TXREQ is set the TXBnCTRL ABTF TXBnCTRL MLOA and TXBnCTRL TXERR bits will be cleared automatically Note Setting the TXBnCTRL TXREQ bit does not initiate a message transmission It merely flags a message buffer as being ready for transmission Transmission will start when the device detects that the bus is available Once the transmission has completed successfully the TXBnCTRL TXREQ bit will be cleared the CANINTF TXnIF bit will be set and an interrupt will be generated if the CANINTE TXnIE bit is set If the message transmission fails the TXBnCTRL TXREQ will remain set This indicates that the message is still pending for transmission and one of the following condition flags will be set If the message started to transmit but encoun tered an error condition the TXBnCTRL TXERR and the CANINTF MERRE bits will be set and an interrupt will be generated on the INT pin if the CANINTE MERRE bit is set f the message is lost arbitration at the TXBnCTRL MLOA bit will be set Note If One shot mode is enabled CANCTRL OSM the above conditions will still exist However the TXREQ bit will be cleared and the message will not attempt transmission a second time 3 4 One Sho
46. TXBnCTRL TXREQ bit must be clear indicating the transmit buffer is not pending transmission before writing to the transmit buffer 3 2 Transmit Priority Transmit priority is a prioritization within the MCP2515 of the pending transmittable messages This is independent from and not necessarily related to any prioritization implicit in the message arbitration scheme built into the CAN protocol Prior to sending the SOF the priority of all buffers that are queued for transmission is compared The transmit buffer with the highest priority will be sent first For example if transmit buffer 0 has a higher priority setting than transmit buffer 1 buffer 0 will be sent first If two buffers have the same priority setting the buffer with the highest buffer number will be sent first For example if transmit buffer 1 has the same priority setting as transmit buffer 0 buffer 1 will be sent first There are four levels of transmit priority TXBnCTRL TXP lt 1 0 gt for a particular message buffer is set to 11 that buffer has the highest possible priority If TXBnCTRL TXP lt 1 0 gt for a particular message buffer is 00 that buffer has the lowest possible priority 3 3 Initiating Transmission In order to initiate message transmission the TXBnCTRL TXREQ bit must be set for each buffer to be transmitted This can be accomplished by Writing to the register via the SPI write command Sending the SPI RTS command
47. V to VDD 1 0V Storage temperature ee ee ee es 65 C to 150 Ambient temp with power applied ie 65 C to 125 C Soldering temperature of leads 10 seconds 300 T Notice Stresses above those listed under Maximum Ratings may cause permanent damage to the device This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied Exposure to maximum rating conditions for extended periods may affect device reliability 2007 Microchip Technology Inc DS21801E page 69 2515 TABLE 13 1 CHARACTERISTICS DC Characteristics Industrial I TAMB 40 C to 85 VDD 2 7V to 5 5V Extended TAMB 40 C to 125 VDD 4 5V to 5 5V Characteristic Min Max Units Conditions Supply Voltage 2 7 5 5 V VRET Register Retention Voltage 24 V High Level Input Voltage RXCAN 2 1 V SCK CS SI TXnRTS Pins 0 7VpD VDD41 V 0501 0 85 V RESET 0 85 VDD V Low Level Input Voltage ViL RXCAN TXnRTS Pins 0 3 15 V SCK CS SI 0 3 0 4 V OSC1 Vss 3 VDD V RESET Vss 15 V Low Level Output Voltage VoL TXCAN 0 6 V IOL 46 0 mA VDD 4 5V RXnBF Pins 0 6 V oL 48 5 mA 4 5V SO CLKOUT 0 6 V IOL 2 1 mA VDD 4 5V INT 0 6
48. XBnDLC TRANSMIT BUFFER n DATA LENGTH CODE ADDRESS 35h 45h 55h R W x R W x R W x R W x R W x R W x R W x R W x DLC3 DLC2 DLC1 DLCO bit 7 bit 0 Legend R Readable bit W Writable bit U Unimplemented bit read as 0 n Value at POR 1 Bit is set 0 Bit is cleared x Bit is unknown bit 7 bit 6 bit 5 4 bit 3 0 REGISTER 3 8 Unimplemented Reads as 0 RTR Remote Transmission Request bit 1 Transmitted Message will be a Remote Transmit Request 0 Transmitted Message will be a Data Frame Unimplemented Reads as 0 DLC Data Length Code 3 0 bits Sets the number of data bytes to be transmitted 0 to 8 bytes Note TXBnDm TRANSMIT BUFFER DATA BYTE m ADDRESS 36h 3Dh 46h 4Dh 56h 5Dh It is possible to set the DLC to a value greater than 8 however only 8 bytes are transmitted R W x R W x R W x R W x R W x R W x R W x R W x TXBnDm7 TXBnDm6 TXBnDm5 TXBnDm4 TXBnDm3 TXBnDm2 TXBnDmi TXBnDmO bit 7 bit 0 Legend R Readable bit W Writable bit U Unimplemented bit read as 0 n Value at POR 1 Bit is set 0 Bit is cleared x Bit is unknown bit 7 0 TXBnDM7 TXBNDMO Transmit Buffer n Data Field Bytes m 2007 Microchip Technology Inc DS21801E page 21 2515 5 DS21801E page 22 2007 Microchip Technology Inc MCP2515 4 0 MESSAGE RECEPT
49. Y DNV ISO TS 16949 2002 Trademarks The Microchip name and logo the Microchip logo Accuron dsPIC KEELOQ KEELOQ logo microID MPLAB PIC PICmicro PICSTART PRO MATE rfPIC and SmartShunt are registered trademarks of Microchip Technology Incorporated in the U S A and other countries AmpLab FilterLab Linear Active Thermistor Migratable Memory MXDEV MXLAB SEEVAL SmartSensor and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U S A Analog for the Digital Age Application Maestro CodeGuard dsPICDEM dsPICDEM net dsPICworks dsSPEAK ECAN ECONOMONITOR FanSense FlexROM fuzzyLAB In Circuit Serial Programming ICSP ICEPIC Mindi MiWi MPASM MPLAB Certified logo MPLIB MPLINK PICkit PICDEM PICDEM net PICLAB PICtail PowerCal Powerlnfo PowerMate PowerTool REAL ICE rfLAB Select Mode Smart Serial SmartTel Total Endurance UNI O WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U S A and other countries SQTP is a service mark of Microchip Technology Incorporated in the U S A All other trademarks mentioned herein are property of their respective companies 2007 Microchip Technology Incorporated Printed in the U S A Rights Reserved gt Printed on recycled paper Microchip received ISO TS 16949 2002 certification for its worldwide headquarters design and wafer fabrication facilities in C
50. Y INSTRUCTION 0123456789101112131415161718192021 22 23 24 25 26 27 28 29 30 31 SCK r instruction address byte lt mask byte data byte si ef sj 4 2 AJ z e 5 21302 1 of 7 ej 51 4j 32 10 so high impedance Note Not all registers can be accessed with this command See the register map for a list of the registers that apply DS21801E page 66 2007 Microchip Technology Inc MCP2515 FIGURE 12 8 READ STATUS INSTRUCTION cs 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 SCK instruction SI ilo ilo 9 0 0 0 don t care repeat data out _ lt data high impedance SO 21 7 6 sla si 21140 CANINTF RXOIF CANINTFL RX1IF TXBOCNTRL TXREQ CANINTF TXOIF TXB1CNTRL TXREQ CANINTF TX1IF TXB2CNTRL TXREQ CANINTF TX2IF FIGURE 12 9 RX STATUS INSTRUCTION cs a s 100 1 ilo off don t care repeat H dataout dai
51. a high impedance so 7 6 5 4312 1047 6 54432 1 80 716 4 3 Msg Type Received 2 110 Filter Match 0 0 No RX message 0 0 Standard data frame 0 0 0 RXFO 1 Message in RXBO 1 Standard remote frame 0 0 1 1 1 0 in RXB1 1 0 Extended data frame 1101 RXF2 1 1 Messages in both buffers 1 1 Extended remote frame 01111 RXF3 CANINTF RXnIF bits mappedto The extended ID bit is mapped to 11010 RXF4 bits 7 and 6 bit 4 The RTR bit is mapped to 1 1 1 1 0 rollover to RXB1 Buffer 0 has higher priority therefore RXBO status is 1 1 1 RXF1 rollover to RXB1 reflected in bits 4 0 2007 Microchip Technology Inc DS21801E page 67 2515 FIGURE 12 10 SPI INPUT TIMING SO high impedance FIGURE 12 11 SPI OUTPUT TIMING 5 8 9 SCK ___ Mode 1 1 0 0 12 13 dcm so MSB out A A Y LSB out f SI dont care NENNEN DS21801E page 68 2007 Microchip Technology Inc MCP2515 13 0 ELECTRICAL CHARACTERISTICS 13 1 Absolute Maximum Ratings 1 MDD a Aries Ale es i ei ee ed vi dee rea 7 0V Allinputs arid Outputs VSS js ce Mase ties 0 6
52. a Field and is used to check the CRC field of incoming messages 1 5 3 ERROR MANAGEMENT LOGIC The Error Management Logic EML is responsible for the fault confinement of the CAN device Its two counters the Receive Error Counter REC and the Transmit Error Counter TEC are incremented and decremented by commands from the bit stream processor Based on the values of the error counters the CAN controller is set into the states error active error passive or bus off 1 5 4 BIT TIMING LOGIC The Bit Timing Logic BTL monitors the bus line input and handles the bus related bit timing according to the CAN protocol The BTL synchronizes on a recessive to dominant bus transition at Start of Frame hard syn chronization and on any further recessive to dominant bus line transition if the CAN controller itself does not transmit a dominant bit resynchronization The BTL also provides programmable time segments 10 compensate for the propagation delay time phase shifts and to define the position of the sample point within the bit time The programming of the BTL depends on the baud rate and external physical delay times FIGURE 1 4 CAN PROTOCOL ENGINE BLOCK DIAGRAM RX TX 9 Bit Timing Logic Transmit Logic Sample lt 2 0 gt Re
53. bit 1 Request abort of all pending transmit buffers 0 Terminate request to abort all transmissions bit 3 OSM One Shot Mode bit 1 Enabled Message will only attempt to transmit one time 0 Disabled Messages will reattempt transmission if required bit 2 CLKEN CLKOUT Pin Enable bit 1 CLKOUT pin enabled 0 CLKOUT pin disabled Pin is in high impedance state bit 1 0 CLKPRE CLKOUT Pin Prescaler bits lt 1 0 gt 00 FCLKOUT System Clock 1 01 FCLKOUT System Clock 2 10 FCLKOUT System Clock 4 11 FCLKOUT System Clock 8 DS21801E page 58 2007 Microchip Technology Inc MCP2515 REGISTER 10 2 CANSTAT CAN STATUS REGISTER ADDRESS XEh R 1 R 0 R 0 U 0 R 0 R 0 R 0 U 0 OPMOD2 OPMOD 1 OPMODO ICOD2 ICOD1 ICODO bit 7 bit 0 Legend Readable bit W Writable bit U Unimplemented bit read as 0 n Value at POR T Bit is set 0 Bit is cleared x Bit is unknown bit 7 5 OPMOD Operation Mode bits lt 2 0 gt 000 Device is in the Normal operation mode 001 2 Device is in Sleep mode 010 Device is in Loopback mode 011 Device is in Listen only mode 100 Device is in Configuration mode bit 4 Unimplemented Read as 0 bit 3 1 ICOD Interrupt Flag Code bits 2 0 000 Interrupt 001 Error Interrupt 010 Wake up Interrupt 011 TXBO Interrupt 100 TXB1 Interrupt 101 TXB2 Interrupt 110 RXBO Interrupt 1112 RXB
54. ceive Error Counter TEC StuffReg lt 5 0 gt E Transmit ErrPas ajorny Error Counter Decision BusOff BusMon Comparator op CRC lt 14 0 gt p Protocol FSM SOF Comparator Shift lt 14 0 gt Transmit lt 5 0 gt Receive lt 7 0 gt gt Receive lt 7 0 gt Transmit lt 7 0 gt RecData lt 7 0 gt TrmData lt 7 0 gt Interface to Standard Buffer Rec Trm Addr DS21801E page 6 2007 Microchip Technology Inc MCP2515 2 0 CAN MESSAGE FRAMES The MCP2515 supports standard data frames extended data frames and remote frames standard and extended as defined in the CAN 2 0B specification 2 1 Standard Data Frame The CAN standard data frame is shown in Figure 2 1 As with all other frames the frame begins with a Start Of Frame SOF bit which is of the dominant state and allows hard synchronization of all nodes The SOF is followed by the arbitration field consisting of 12 bits the 11 bit identifier and the Remote Transmission Request RTR bit The RTR bit is used to distinguish a data frame RTR bit dominant from a remote frame RTR bit recessive Following the arbitration field is the control field consisting of six bits The first bit of this field is the Identifier Extension IDE bit which must be dominant to specify a standard frame The following bit Reserved Bit Zero RBO is reserved and is defined as a dominant bit by the CAN protocol The remaining four bits of the
55. code Code protection does not mean that we are guaranteeing the product as unbreakable Code protection is constantly evolving We at Microchip are committed to continuously improving the code protection features of our products Attempts to break Microchip s code protection feature may violation of the Digital Millennium Copyright Act If such acts allow unauthorized access to your software or other copyrighted work you may have right to sue for relief under that Act Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates It is your responsibility to ensure that your application meets with your specifications MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED WRITTEN OR ORAL STATUTORY OR OTHERWISE RELATED TO THE INFORMATION INCLUDING BUT NOT LIMITED TO ITS CONDITION QUALITY PERFORMANCE MERCHANTABILITY OR FITNESS FOR PURPOSE Microchip disclaims all liability arising from this information and its use Use of Microchip devices in life support and or safety applications is entirely at the buyer s risk and the buyer agrees to defend indemnify and hold harmless Microchip from any and all damages claims suits or expenses resulting from such use No licenses are conveyed implicitly or otherwise under any Microchip intellectual property rights QUALITY MANAGEMENT SYSTEM CERTIFIED B
56. control field are the Data Length Code DLC which specifies the number of bytes of data 0 8 bytes contained in the message After the control field is the data field which contains any data bytes that are being sent and is of the length defined by the DLC 0 8 bytes The Cyclic Redundancy Check CRC field follows the data field and is used to detect transmission errors The CRC field consists of a 15 bit CRC sequence followed by the recessive CRC Delimiter bit The final field is the two bit Acknowledge field During the ACK Slot bit the transmitting node sends out a recessive bit Any node that has received an error free frame acknowledges the correct reception of the frame by sending back a dominant bit regardless of whether the node is configured to accept that specific message or not The recessive acknowledge delimiter completes the acknowledge field and may not be overwritten by a dominant bit 2 2 Extended Data Frame In the extended CAN data frame shown in Figure 2 2 the SOF bit is followed by the arbitration field which consists of 32 bits The first 11 bits are the Most Significant bits MSb Base ID of the 29 bit identifier These 11 bits are followed by the Substitute Remote Request SRR bit which is defined to be recessive The SRR bit is followed by the IDE bit which is recessive to denote an extended CAN frame It should be noted that if arbitration remains unresolved after transmissio
57. e however for a destination node to request data from the source To accomplish this the destination node sends a remote frame with an identifier that matches the identifier of the required data frame The appropriate data source node will then send a data frame in response to the remote frame request There are two differences between a remote frame shown in Figure 2 3 and a data frame First the RTR bit is at the recessive state and second there is no data field In the event of a data frame and a remote frame with the same identifier being transmitted at the same time the data frame wins arbitration due to the dominant RTR bit following the identifier In this way the node that transmitted the remote frame receives the desired data immediately 2 4 Error Frame An error frame is generated by any node that detects a bus error An error frame shown in Figure 2 4 consists of two fields an error flag field followed by an error delimiter field There are two types of error flag fields The type of error flag field sent depends upon the error status of the node that detects and generates the error flag field 2007 Microchip Technology Inc DS21801E page 7 MCP2515 2 4 1 ACTIVE ERRORS If an error active node detects a bus error the node interrupts transmission of the current message by generating an active error flag The active error flag is composed of six consecutive dominant bits This bit sequence actively vi
58. e to dominant edge If the dominant condition remains until the sample point the DSTEMP interprets this as a SOF and a SOF pulse is generated If the dominant condition does not remain until the sample point the DSTEMP interprets this as a glitch on the bus and no SOF signal is generated Figure 4 1 illustrates SOF signalling and glitch filtering As with One shot mode one use for SOF signaling is for TTCAN type systems In addition by monitoring both the RXCAN pin and the SOF pin a MCU can detect early physical bus problems by detecting small glitches before they affect the CAN communications 4 4 RXOBF and RX1BF Pins In addition to the INT pin which provides an interrupt signal to the MCU for many different conditions the receive buffer full pins RXOBF and RX1BF can be used to indicate that a valid message has been loaded into RXBO or RXB1 respectively The pins have three different configurations Register 4 1 1 Disabled 2 Buffer Full Interrupt 3 Digital Output FIGURE 4 1 START OF FRAME SIGNALING 4 4 1 DISABLED The RXBnBF pins can be disabled to the high impedance state by clearing BFPCTRL BnBFE 4 4 2 CONFIGURED AS BUFFER FULL The RXBnBF pins can be configured to act as either buffer full interrupt pins or as standard digital outputs Configuration and status of these pins is available via the BFPCTRL register Register 4 3 When set to operate in Interrupt mode by setting BFPCTRL BxBFE and
59. e3 can be found on the outer packaging for this package Note In the event the full Microchip part number cannot be marked on one line it will be carried over to the next line thus limiting the number of available characters for customer specific information 2007 Microchip Technology Inc DS21801E page 75 MCP2515 18 Lead Plastic Dual In Line P 300 mil Body PDIP Note For the most current package drawings please see the Microchip Packaging Specification located at http www microchip com packaging N 1 E1 U 1 2 3 E aa b e e Units INCHES Dimension Limits MIN NOM MAX Number of Pins N 18 Pitch e 100 BSC Top to Seating Plane A 210 Molded Package Thickness A2 115 130 195 Base to Seating Plane A1 015 Shoulder to Shoulder Width E 300 310 325 Molded Package Width E1 240 250 280 Overall Length D 880 900 920 Tip to Seating Plane L 115 130 150 Lead Thickness 008 010 014 Upper Lead Width b1 045 060 070 Lower Lead Width b 014 018 022 Overall Row Spacing 8 eB 430
60. egister locations can be read sequentially using this method The read operation is terminated by raising the CS pin Figure 12 2 12 4 Read RX Buffer Instruction The Read RX Buffer instruction Figure 12 3 provides a means to quickly address a receive buffer for reading This instruction reduces the SPI overhead by one byte the address byte The command byte actually has four possible values that determine the address pointer location Once the command byte is sent the controller clocks out the data at the address location the same as the Read instruction i e sequential reads are possible This instruction further reduces the SPI overhead by automatically clearing the associated receive flag CANINTF RXnIF when CS is raised at the end of the command 12 5 Write Instruction The Write instruction is started by lowering the CS pin The Write instruction is then sent to the MCP2515 followed by the address and at least one byte of data It is possible to write to sequential registers by continuing to clock in data bytes as long as CS is held low Data will actually be written to the register on the rising edge of the SCK line for the DO bit If the CS line is brought high before eight bits are loaded the write will be aborted for that data byte and previous bytes in the command will have been written Refer to the timing diagram in Figure 12 4 for a more detailed illustration of the byte write sequence 12 6 Load TX Buffer In
61. egister 10 1 When changing modes the mode will not actually change until all pending message transmissions are complete The requested mode must be verified by reading the CANSTAT OPMODE bits see Register 10 2 101 Configuration Mode The MCP2515 must be initialized before activation This is only possible if the device is in the Configuration mode Configuration mode is automatically selected after power up a reset or can be entered from any other mode by setting the CANTRL REQOP bits to 100 When Configuration mode is entered all error counters are cleared Configuration mode is the only mode where the following registers are modifiable CNF1 CNF2 CNF3 TXRTSCTRL Filter registers Mask registers 10 2 Sleep Mode The MCP2515 has an internal Sleep mode that is used to minimize the current consumption of the device The SPI interface remains active for reading even when the MCP2515 is in Sleep mode allowing access to all registers To enter Sleep mode the mode request bits are set in the CANCTRL register REQOP lt 2 0 gt The CANSTAT OPMODE bits indicate operation mode These bits should be read after sending the sleep command to the MCP2515 The MCP2515 is active and has not yet entered Sleep mode until these bits indicate that Sleep mode has been entered When in internal Sleep mode the wake up interrupt is still active if enabled This is done so that the MCU can also be placed into a Slee
62. eld Em E PROTOCOL Receive gt ENGINE a Counter TEC Transmit gt ErrPas NZ EE BusOff Transmit lt 7 0 gt Receive lt 7 0 gt lt pas Shift lt 14 0 gt Transmit lt 5 0 gt Receive lt 8 0 gt jy 4 Comparator Protocol Finite State SOF CRC lt 14 0 gt Machine Bit le Transmit imi Logic Timing Clock n Logic lt Generator TX RX Configuration Registers 2007 Microchip Technology Inc DS21801E page 5 MCP2515 1 5 CAN Protocol Engine The CAN protocol engine combines several functional blocks shown in Figure 1 4 and described below 1 5 1 PROTOCOL FINITE STATE MACHINE The heart of the engine is the Finite State Machine FSM The FSM is a sequencer that controls the sequential data stream between the TX RX shift register the CRC register and the bus line The FSM also controls the Error Management Logic EML and the parallel data stream between the TX RX shift registers and the buffers The FSM ensures that the processes of reception arbitration transmission and error signaling are performed according to the CAN protocol The automatic retransmission of messages on the bus line is also handled by the FSM 1 5 2 CYCLIC REDUNDANCY CHECK The Cyclic Redundancy Check register generates the Cyclic Redundancy Check CRC code which is transmitted after either the Control Field for messages with 0 data bytes or the Dat
63. er 1 0x76 80 7 6 5 43 2 10 Start at 100 FIGURE 12 4 BYTE WRITE INSTRUCTION Ee 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 e c H SCK r instruction address byte lt data byte a 00 00 UJE psy high impedance SO 2007 Microchip Technology Inc DS21801E page 65 MCP2515 FIGURE 12 5 LOAD TX BUFFER Address Points to Addr CS o o o TX buffer 0 Start at 0x31 TXBOSIDH 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 o o 1 TX buffer 0 Start at 0x36 Li peo _______ o 1 0 TX buffer 1 Start at 0x41 instruction gt data in TXB1SIDH 0 1 1 TX buffer 1 Start at 0 46 si 0 1 0 0 ofa b 76543 2 10 be 1 0 0 TX buffer 2 Start at 0x51 high impedance TXB2SIDH 0 1 1 TK buffer 2 Start 0 56 TXB2D0 FIGURE 12 6 REQUEST TO SEND RTS INSTRUCTION SCK instruction si Si 1 0 0 0 0 yx AT high impedance SO FIGURE 12 7 BIT MODIF
64. erved when the CLKOUT pin function is enabled disabled or the prescaler value is changed CRYSTAL CERAMIC RESONATOR OPERATION HRs 4 5 Co OSC2 Note 1 A series resistor RS may be required for AT strip cut crystals 2 The feedback resistor RF is typically in the range of 2 to 10 MQ FIGURE 8 2 EXTERNAL CLOCK SOURCE Clock from external system 1 Open gt 0562 0501 Note 1 resistor to ground may be used reduce system noise This may increase system current 2 Duty cycle restrictions must be observed see Table 12 1 2007 Microchip Technology Inc DS21801E page 53 MCP2515 FIGURE 8 3 EXTERNAL SERIES RESONANT CRYSTAL OSCILLATOR CIRCUIT 330 330 Other Devices 74AS04 74AS04 74AS04 MCP2510 rf oH 04 gt 0 1 mF XTAL Note 1 Duty cycle restrictions must be observed see Table 12 1 TABLE 8 1 CAPACITOR SELECTION FOR TABLE 8 2 CAPACITOR SELECTION FOR CERAMIC RESONATORS CRYSTAL OSCILLATOR Typical Capacitor Values Used Typical Capacitor Osc Crystal Val T Mode Freq 0 1 0562 Type Freq 2 SES HS 8 0 MHz 27 pF 27 pF E c2 16 0 MHz 22 pF 22 pF HS 4 MHz 27 pF 27 pF Capacitor values are for design guidance only 8 MHz 22 pF 22 pF These capacitors were tested with
65. escription Microchip Technology s MCP2515 is a stand alone Controller Area Network CAN controller that imple ments the CAN specification version 2 0B It is capable of transmitting and receiving both standard and extended data and remote frames The MCP2515 has two acceptance masks and six acceptance filters that are used to filter out unwanted messages thereby reducing the host MCUs overhead The MCP2515 interfaces with microcontrollers MCUs via an industry standard Serial Peripheral Interface SPI Package Types 18 Lead PDIP SOIC TXCAN 11 M 18 VDD RXCAN 12 17L RESET CLKOUT SOF 13 16105 LO TXORTSLJ4 5 15050 TXMIRTSI 5 A 1408 E TXORTSLI6 13 scK 0802 17 12 INT osci 18 119 RXOBF Vss 9 10 RX1BF 20 LEAD TSSOP TXCANC 20 2 19 CLKOUT SOFCH 18568 TXORTSCH4 1780 TXIRTSCI 5 5 1655 SI NCEH6 NA 155 NC 5 7 6 1455 SCK 05228 13 INT osc1c49 12 Vss c110 1155 RX1BF 2007 Microchip Technology Inc DS21801E page 1 2515 5 DS21801E page 2 2007 Microchip Technology Inc MCP2515 1 0 DEVICE OVERVIEW The MCP2515 is stand alone CAN controller developed to simplify applications that require interfacing with a CAN bus A simple block diagram of the MCP2515 is shown in Figu
66. essage did not lose arbitration while being sent bit 4 TXERR Transmission Error Detected bit 1 A bus error occurred while the message was being transmitted 0 No bus error occurred while the message was being transmitted bit 3 TXREQ Message Transmit Request bit 1 Buffer is currently pending transmission MCU sets this bit to request message be transmitted bit is automatically cleared when the message is sent 0 Buffer is not currently pending transmission MCU can clear this bit to request a message abort bit 2 Unimplemented Read as 0 bit 1 0 TXP Transmit Buffer Priority lt 1 0 gt bits 11 Highest Message Priority 10 High Intermediate Message Priority 01 Low Intermediate Message Priority 00 Lowest Message Priority DS21801E page 18 2007 Microchip Technology Inc MCP2515 REGISTER 3 2 TXRTSCTRL TXnRTS PIN CONTROL AND STATUS REGISTER ADDRESS 0Dh U 0 U 0 R x R x R x R W 0 R W 0 R W 0 B2RTS B1RTS BORTS B2RTSM B1RTSM BORTSM bit 7 bit 0 Legend R Readable bit W Writable bit U Unimplemented bit read as 0 n Value at POR 1 Bit is set 0 Bit is cleared x Bit is unknown bit 7 Unimplemented Read as 0 bit 6 Unimplemented Read as 0 bit 5 B2RTS TX2RTS Pin State bit Reads state of TX2RTS pin when in Digital Input mode Reads as 0 when pin is in Request to Send mode bi
67. f Pins N 20 Pitch e 0 65 BSC Overall Height A 1 20 Molded Package Thickness A2 0 80 1 00 1 05 Standoff A1 0 05 0 15 Overall Width E 6 40 BSC Molded Package Width E1 4 30 4 40 4 50 Molded Package Length D 6 40 6 50 6 60 Foot Length L 0 45 0 60 0 75 Footprint L1 1 00 REF Foot Angle 0 8 Lead Thickness c 0 09 0 20 Lead Width b 0 19 0 30 Notes 1 Pin 1 visual index feature may vary but must be located within the hatched area 2 Dimensions D and E1 do not include mold flash or protrusions Mold flash or protrusions shall not exceed 0 15 mm per side 3 Dimensioning and tolerancing per ASME Y14 5M BSC Basic Dimension Theoretically exact value shown without tolerances REF Reference Dimension usually without tolerance for information purposes only Microchip Technology Drawing C04 088B DS21801E page 78 2007 Microchip Technology Inc MCP2515 APPENDIX A REVISION HISTORY Revision E November 2007 Removed preliminary watermark Updated templates Updated register information Updated package outline drawings Revision D April 2005 Added Table 8 1 and Table 8 2 in Section 8 0 Oscillator Added note box following tables Changed address bits in column heading in Table 11 1 Section 11 0 Register Map Modified Section 14 0 Packaging Information to reflect pb free device markings Appendix A Revision History Rearranged order of importance
68. g1 PS1 SJW PS2 SJW PS1 Point Nominal Bit Time NBT No Resynchronization e 0 Input Signal e 0 v EN PhaseSeg2 PS2 SyncSeg PropSeg PhaseSeg1 PS1 gt SJW PS2 gt SJW PS1 M NE Sample vis Point 1 4 Nominal Bit Time NBT gt l 4 Actual Bit Time gt Resynchronization to Slower Transmitter gt 0 Input Signal lt 0 v 54 PhaseSeg2 PS2 SyncSeg PropSeg PhaseSeg1 PS1 SJW PS2 SJW PS1 Sample Point 1 lt Nominal Bit Time NBT Actual Bit Time Resynchronization to a Faster Transmitter e 0 HEEENNNEEEE ay DS21801E page 40 2007 Microchip Technology Inc MCP2515 5 3 Programming Time Segments Some requirements for programming of the time segments PropSeg PS1 gt PS2 PropSeg PS1 gt TDELAY e PS2 gt SJW For example assuming that a 125 kHz CAN baud rate with Fosc 20 MHz is desired Tosc 50ns choose BRP lt 5 0 gt 04h then Ta 500 ns To obtain 125 kHz the bit time must be 16 TQ Typically the sampling of the bit should take place at about 60 70 of the bit time depending on the system parameters Also
69. handler and Tempe Arizona Gresham Oregon and design centers in California and India The Company s quality system processes and procedures are for its PIC MCUs and dsPIC DSCs KEELOG code hopping devices Serial EEPROMs microperipherals nonvolatile memory and analog products In addition Microchip s quality system for the design and manufacture of development systems is 150 9001 2000 certified 2007 Microchip Technology Inc DS21801E page 83 MICROCHIP WORLDWIDE SALES AND SERVICE AMERICAS Corporate Office 2355 West Chandler Blvd Chandler AZ 85224 6199 Tel 480 792 7200 Fax 480 792 7277 Technical Support http support microchip com Web Address www microchip com Atlanta Duluth GA Tel 678 957 9614 Fax 678 957 1455 Boston Westborough MA Tel 774 760 0087 Fax 774 760 0088 Chicago Itasca IL Tel 630 285 0071 Fax 630 285 0075 Dallas Addison TX Tel 972 818 7423 Fax 972 818 2924 Detroit Farmington Hills MI Tel 248 538 2250 Fax 248 538 2260 Kokomo Kokomo IN Tel 765 864 8360 Fax 765 864 8387 Los Angeles Mission Viejo CA Tel 949 462 9523 Fax 949 462 9608 Santa Clara Santa Clara CA Tel 408 961 6444 Fax 408 961 6445 Toronto Mississauga Ontario Canada Tel 905 673 0699 Fax 905 673 6509 ASIA PACIFIC Asia Pacific Office Suites 3707 14 37th Floor Tower 6 The Gateway Harbour City Kowloon Hong Kong Tel 852 2401 1200 Fax 852 240
70. ip Technology Inc DS21801E page 49 2515 7 6 2 RECEIVER WARNING The REC has reached the MCU warning limit of 96 7 6 3 TRANSMITTER WARNING The TEC has reached the MCU warning limit of 96 7 6 4 RECEIVER ERROR PASSIVE The REC has exceeded the error passive limit of 127 and the device has gone to error passive state 7 6 5 TRANSMITTER ERROR PASSIVE The TEC has exceeded the error passive limit of 127 and the device has gone to error passive state 7 6 6 BUS OFF The TEC has exceeded 255 and the device has gone to bus off state 7 7 Interrupt Acknowledge Interrupts are directly associated with one or more sta tus flags in the CANINTF register Interrupts are pend ing as long as one of the flags is set Once an interrupt flag is set by the device the flag can not be reset by the MCU until the interrupt condition is removed REGISTER 7 1 CANINTE INTERRUPT ENABLE ADDRESS 2Bh R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 MERRE WAKIE ERRIE TX2IE TX1IE TXOIE RX1IE RXOIE bit 7 bit 0 Legend R Readable bit W Writable bit U Unimplemented bit read as 0 Value at POR T Bit is set 0 Bit is cleared x Bit is unknown bit 7 MERRE Message Error Interrupt Enable bit 1 Interrupt on error during message reception or transmission 0 Disabled bit 6 WAKIE Wakeup Interrupt Enable bit 1 Interrupt on CAN bus activity 0 Disabled bit 5 ERRIE Er
71. is unknown bit 7 Unimplemented Read as 0 bit 6 5 RXM Receive Buffer Operating Mode bits 11 Turn mask filters off receive any message 10 Receive only valid messages with extended identifiers that meet filter criteria 01 Receive only valid messages with standard identifiers that meet filter criteria 00 Receive all valid messages using either standard or extended identifiers that meet filter criteria bit 4 Unimplemented Read as 0 bit 3 RXRTR Received Remote Transfer Request bit 1 Remote Transfer Request Received 0 No Remote Transfer Request Received bit 2 0 FILHIT Filter Hit bits indicates which acceptance filter enabled reception of message 101 Acceptance Filter 5 RXF5 100 Acceptance Filter 4 RXF4 011 Acceptance Filter 3 RXF3 010 Acceptance Filter 2 RXF2 001 Acceptance Filter 1 RXF1 Only if BUKT bit set in RXBOCTRL 000 Acceptance Filter 0 RXFO Only if BUKT bit set in RXBOCTRL DS21801E page 28 2007 Microchip Technology Inc MCP2515 REGISTER 4 3 BFPCTRL RXnBF PIN CONTROL AND STATUS ADDRESS 0Ch U 0 U 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 B1BFS BOBFS B1BFE BOBFE B1BFM BOBFM bit 7 bit 0 Legend R Readable bit W Writable bit U Unimplemented bit read as 0 n Value at POR 1 Bit is set 0 Bit is cleared x Bit is unknown bit 7 Unimplemented Read as 0 bit 6 U
72. k bits to be applied to bits lt 10 3 gt of the Standard Identifier portion of a received message 2007 Microchip Technology Inc DS21801E page 35 MCP2515 REGISTER 4 15 RXMnSIDL MASK n STANDARD IDENTIFIER LOW ADDRESS 21h 25h R W 0 R W 0 R W 0 U 0 U 0 U 0 R W 0 R W 0 SID2 SID1 SIDO EID17 EID16 bit 7 bit 0 Legend R Readable bit W Writable bit U Unimplemented bit read as 0 n Value at POR 1 Bit is set 0 Bit is cleared x Bit is unknown bit 7 5 SID Standard Identifier Mask bits lt 2 0 gt These bits hold the mask bits to be applied to bits lt 2 0 gt of the Standard Identifier portion of a received message bit 4 2 Unimplemented Reads as 0 bit 1 0 EID Extended Identifier Mask bits lt 17 16 gt These bits hold the mask bits to be applied to bits lt 17 16 gt of the Extended Identifier portion of a received message REGISTER 4 16 RXMnEID8 MASK EXTENDED IDENTIFIER HIGH ADDRESS 22h 26h R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 EID15 EID14 EID13 EID12 EID11 EID10 EID9 EID8 bit 7 bit 0 Legend R Readable bit W Writable bit U Unimplemented bit read as 0 n Value at POR 1 Bit is set 0 Bit is cleared x Bit is unknown bit 7 0 REGISTER 4 17 EID Extended Identifier bits lt 15 8 gt These bits hold the filter bits to be applied
73. ly by using the Bit Modify SPI command to prevent glitches from occurring on either of the buffer full pins FIGURE 4 2 RECEIVE BUFFER BLOCK DIAGRAM Note Messages received in the MAB are intially applied to the mask and filters of RXBO In addition only one filter match occurs e g if the message matches both RXFO and RXF2 the match will be for RXFO and the message will be moved into Acceptance Filter RXF2 Acceptance Mask Acceptance Filter RXMO RXF3 4 U tt Acceptance Filter Acceptance Filter RXFO RXF4 5 v c Acceptance Filter Acceptance Filter e RXF1 RXF5 p aN aN t K Identifier M Identifier 2 x A B B B Data Field Data Field 2007 Microchip Technology Inc DS21801E page 25 MCP2515 FIGURE 4 3 RECEIVE FLOW FLOWCHART Generate Error Frame v Begin Loading Message into Message Assembly Buffer MAB Valid Message Received Meets Yes a filter criteria CANINTF RXOIF 0 for RXBO Determines if the receive register is empty and able to accept a new message Determines if RXBO can roll over into RXB1 if it is full Move message into RXBO
74. message in a specific message buffer by clearing the associated TXBnCTRL TXREQ bit In addition all pending messages can be requested to be aborted by setting the CANCTRL ABAT bit This bit MUST be reset typically after the TXREQ bits have been verified to be cleared to continue transmitting messages The CANCTRL ABTF flag will only be set if the abort was requested via the CANCTRL ABAT bit Aborting a message by resetting the TXREQ bit does NOT cause the ABTF bit to be set Note Messages that were transmitting when the abort was requested will continue to transmit If the message does not successfully complete transmission i e lost arbitration or was interrupted by an error frame it will then be aborted DS21801E page 16 2007 Microchip Technology Inc MCP2515 FIGURE 3 1 TRANSMIT MESSAGE FLOWCHART Start Are any TXBnCTRL TXREQ bits 1 2 Clear TXBnCTRL ABTF TXBnCTRL MLOA TXBnCTRL TXERR The message transmission sequence begins when the device determines that the TXBnCTRL TXREQ for any of the transmit registers has been set Clearing the TXxBnCTRL TXREQ bit while it is set or setting the CAN CTRL ABAT bit before the message has started transmission will abort the message Is CAN bus available to start transmission Yes Examine TXBnCTRL TXP lt 1 0 gt to Determine Highest Priority Mes
75. n of the first 11 bits of the identifier and one of the nodes involved in the arbitration is sending a standard CAN frame 11 bit identifier the standard CAN frame will win arbitration due to the assertion of a dominant IDE bit Also the SRR bit in an extended CAN frame must be recessive to allow the assertion of a dominant RTR bit by a node that is sending a standard CAN remote frame The SRR and IDE bits are followed by the remaining 18 bits of the identifier Extended ID and the remote transmission request bit To enable standard and extended frames to be sent across a shared network the 29 bit extended message identifier is split into 11 bit most significant and 18 bit least significant sections This split ensures that the IDE bit can remain at the same bit position in both the standard and extended frames Following the arbitration field is the six bit control field The first two bits of this field are reserved and must be dominant The remaining four bits of the control field are the DLC which specifies the number of data bytes contained in the message The remaining portion of the frame data field CRC field acknowledge field end of frame and intermis sion is constructed in the same way as a standard data frame see Section 2 1 Standard Data Frame 2 3 Remote Frame Normally data transmission is performed on an autonomous basis by the data source node e g a sensor sending out a data frame is possibl
76. nimplemented Read as 0 bit 5 B1BFS RX1BF Pin State bit Digital Output mode only Reads as 0 when RX1BF is configured as interrupt pin bit 4 BOBFS RXOBF Pin State bit Digital Output mode only Reads as 0 when RXOBF is configured as interrupt pin bit 3 B1BFE RX1BF Pin Function Enable bit 1 Pin function enabled operation mode determined by B1BFM bit 0 Pin function disabled pin goes to high impedance state bit 2 BOBFE RXOBF Pin Function Enable bit 1 Pin function enabled operation mode determined by BOBFM bit 0 Pin function disabled pin goes to high impedance state bit 1 B1BFM RX1BF Pin Operation Mode bit 1 is used as interrupt when valid message loaded into RXB1 0 Digital Output mode bit 0 BOBFM RXOBF Pin Operation Mode bit 1 Pin is used as interrupt when valid message loaded into RXBO 0 Digital Output mode REGISTER 4 4 RXBnSIDH RECEIVE BUFFER n STANDARD IDENTIFIER HIGH ADDRESS 61h 71h R x R x R x R x R x R x R x R x SID10 SID9 SID8 SID7 06 5105 5104 5103 bit 7 bit 0 Legend R Readable bit W Writable bit U Unimplemented bit read as 0 n Value at POR 1 Bit is set V Bit is cleared x Bit is unknown bit 7 0 SID Standard Identifier bits lt 10 3 gt These bits contain the eight most significant bits of the Standard Identifier for the received message 2007 Microchip Technology Inc DS21801E page 29 MCP2515
77. nnected to the OSC1 pin as shown in Figure 8 2 and Figure 8 3 8 1 Oscillator Startup Timer The MCP2515 utilizes an Oscillator Startup Timer OST that holds the MCP2515 in reset to ensure that the oscillator has stabilized before the internal state machine begins to operate The OST maintains reset for the first 128 OSC1 clock cycles after power up or a wake up from Sleep mode occurs It should be noted that no SPI protocol operations should be attempted until after the OST has expired FIGURE 8 1 8 2 CLKOUT Pin The CLKOUT pin is provided to the system designer for use as the main system clock or as a clock input for other devices in the system The CLKOUT has an inter nal prescaler which can divide Fosc by 1 2 4 and 8 The CLKOUT function is enabled and the prescaler is selected via the CANCNTRL register see Register 10 1 Note The maximum frequency on CLKOUT is specified as 25 MHz See Table 13 5 The CLKOUT pin will be active upon system reset and default to the slowest speed divide by 8 so that it can be used as the MCU clock When Sleep mode is requested the MCP2515 will drive sixteen additional clock cycles on the CLKOUT pin before entering Sleep mode The idle state of the CLKOUT pin in Sleep mode is low When the CLKOUT function is disabled CANCNTRL CLKEN 0 the CLKOUT pin is in a high impedance state The CLKOUT function is designed to ensure that thcLkouT ticLkour timings are pres
78. not 100 tested 2007 Microchip Technology Inc 0 21801 73 2515 5 DS21801E page 74 2007 Microchip Technology Inc MCP2515 14 0 PACKAGING INFORMATION 14 1 Package Marking In 18 Lead PDIP 300 mil formation pup pu Du ph ru e YYWWNNN XXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXX OA GA hA GA hA hy 18 Lead SOIC 300 mil hg hg hg XXXXXXXXXXXX XXXXXXXXXXXX XXXXXXXXXXXX e AN YYWWNNN 20 Lead TSSOP 4 4 mm XXXXXXXX XXXXXNNN o LAN YYWW Examp le gu gh p rh TE D MCP2515 I P e3 0434256 Lo Examp bd hd hd hg le ul L MCP2515 E SO AN 0434256 le MCP2515 5 256 AN 0434 Legend Customer specific information Year code last digit of calendar year Year code last 2 digits of calendar year Week code week of January 1 is week 01 Alphanumeric traceability code Pb free JEDEC designator for Matte Tin Sn This package is Pb free The Pb free designator
79. olates the bit stuffing rule All other stations recognize the resulting bit stuffing error and in turn generate error frames themselves called error echo flags The error flag field therefore consists of between six and twelve consecutive dominant bits generated by one or more nodes The error delimiter field eight recessive bits completes the error frame Upon completion of the error frame bus activity returns to normal and the interrupted node attempts to resend the aborted message Note Error echo flags typically occur when a localized disturbance causes one or more but not all nodes to send an error flag The remaining nodes generate error flags in response echo to the original error flag 2 4 2 PASSIVE ERRORS If an error passive node detects a bus error the node transmits an error passive flag followed by the error delimiter field The error passive flag consists of six consecutive recessive bits The error frame for an error passive node consists of 14 recessive bits From this it follows that unless the bus error is detected by an error active node or the transmitting node the message will continue transmission because the error passive flag does not interfere with the bus If the transmitting node generates an error passive flag it will cause other nodes to generate error frames due to the resulting bit stuffing violation After transmission of an error frame an error passive node must wait for
80. oopback mode is a silent mode meaning no messages will be transmitted while in this state including error flags or acknowledge signals The TXCAN pin will be in a recessive state The filters and masks can be used to allow only particular messages to be loaded into the receive registers The masks can be set to all zeros to provide a mode that accepts all messages The Loopback mode is activated by setting the mode request bits in the CANCTRL register 10 5 Normal Mode Normal mode is the standard operating mode of the MCP2515 In this mode the device actively monitors all bus messages and generates acknowledge bits error frames etc This is also the only mode in which the MCP2515 will transmit messages over the CAN bus REGISTER 10 1 CANCTRL CAN CONTROL REGISTER ADDRESS XFh R W 1 R W 0 R W 0 R W 0 R W 0 R W 1 R W 1 R W 1 REQOP2 REQOP1 REQOPO ABAT OSM CLKEN CLKPRE1 CLKPREO bit 7 bit 0 Legend R Readable bit W Writable bit U Unimplemented bit read as 0 n Value at POR 1 Bit is set 0 Bit is cleared x Bit is unknown bit 7 5 REQOP Request Operation Mode bits lt 2 0 gt 000 Set Normal Operation mode 001 Set Sleep mode 010 Set Loopback mode 011 Set Listen only mode 100 Set Configuration mode All other values for REQOP bits are invalid and should not be used On power up REQOP b 111 bit 4 ABAT Abort All Pending Transmissions
81. operation is performed Table 12 1 shows the instruction bytes for all operations Refer to Figure 12 10 and Figure 12 11 for detailed input and output timing diagrams for both Mode 0 0 and Mode 1 1 operation Note The MCP2515 expects the first byte after lowering CS to be the instruction command byte This implies that CS must be raised and then lowered again to invoke another command 12 2 Reset Instruction The Reset instruction can be used to re initialize the internal registers of the MCP2515 and set Configuration mode This command provides the same functionality via the SPI interface as the RESET pin The Reset instruction is a single byte instruction that requires selecting the device by pulling CS low sending the instruction byte and then raising CS It is highly recommended that the reset command be sent or the RESET pin be lowered as part of the power on initialization sequence 12 3 Read Instruction The Read instruction is started by lowering the CS pin The Read instruction is then sent to the MCP2515 followed by the 8 bit address A7 through AO Next the data stored in the register at the selected address will be shifted out on the SO pin The internal address pointer is automatically incremented to the next address once each byte of data is shifted out Therefore it is possible to read the next consecutive register address by continuing to pro vide clock pulses Any number of consecutive r
82. or Message any of the transmit buffers Request To Send 1000 Onnn Request to send for TXB2 Request to send for Request to send for TXB1 Read Status 1010 0000 Quick polling command that reads several status bits for transmit and receive functions RX Status 1011 0000 Quick polling command that indicates filter match and message type standard extended and or remote of received message Bit Modify 0000 0101 Allows the user to set or clear individual bits in a particular register Note Not all registers can be bit modified with this command Executing this command on registers that are not bit modifiable will force the mask to FFh See the register map in Section 11 0 Register Map for a list of the registers that apply DS21801E page 64 2007 Microchip Technology Inc MCP2515 FIGURE 12 2 READ INSTRUCTION 14 15 16 17 18 19 20 21 22 23 sx Turn n n instruction r address byte A SI 000 0 0 1 100 100000 care high impedance Gals 50 DONNE 0 FIGURE 12 3 READ RX BUFFER INSTRUCTION CS Address Points to Address 12 13 14 Receive Buffer 0 0x61 sx _JUUUUUUUUUUUUTUUL same 0 1 Receive Buffer 0 0 66 instruction gt Start at RXBODO SI 1 0 0 110 m don t care 1 Receive Buffer 1 0x71 Start at RXB1SIDH high impedance data out 1 1 Receive Buff
83. p Width Length bits lt 1 0 gt 11 Length 4xTa 10 Length 3xTa 01 Length 2xTa 00 Length 1xTa bit 5 0 BRP Baud Rate Prescaler bits lt 5 0 gt TQ 2 x BRP 1 Fosc REGISTER 5 2 CNF2 CONFIGURATION 1 ADDRESS 29h R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 BTLMODE SAM PHSEG12 PHSEG11 PHSEG10 PRSEG2 PRSEGI PRSEGO bit 7 bit 0 Legend R Readable bit W Writable bit U Unimplemented bit read as 0 n Value at POR T Bit is set 0 Bit is cleared x Bit is unknown bit 7 bit 6 bit 5 3 bit 2 0 BTLMODE PS2 Bit Time Length bit 1 Length of PS2 determined by PHSEG22 PHSEG20 bits of CNF3 0 Length of PS2 15 the greater of PS1 and IPT 2 SAM Sample Point Configuration bit 1 Bus line is sampled three times at the sample point 0 Bus line is sampled once at the sample point PHSEG1 PS1 Length bits lt 2 0 gt PHSEG1 1 x Ta PRSEG Propagation Segment Length bits lt 2 0 gt PRSEG 1 x DS21801E page 42 2007 Microchip Technology Inc MCP2515 REGISTER 5 3 CONFIGURATION 1 ADDRESS 28h R W 0 R W 0 U 0 U 0 U 0 R W 0 R W 0 R W 0 SOF WAKFIL PHSEG22 PHSEG21 PHSEG20 bit 7 bit 0 Legend R Readable bit W Writable bit U Unimplemented bit read as 0 n Value at POR 1 Bit is set 0 Bit is cleared x Bit is unknown bit 7 SOF Start of Frame signal bit If CANCT
84. p mode and use the MCP2515 to wake it up upon detecting activity on the bus When in Sleep mode the MCP2515 stops its internal oscillator The MCP2515 will wake up when bus activity occurs or when the MCU sets via the SPI interface the CANINTF WAKIF bit to generate a wake up attempt the CANINTE WAKIE bit must also be set in order for the wake up interrupt to occur The TXCAN pin will remain in the recessive state while the MCP2515 is in Sleep mode 10 2 1 WAKE UP FUNCTIONS The device will monitor the RXCAN pin for activity while it is in Sleep mode If the CANINTE WAKIE bit is set the device will wake up and generate an interrupt Since the internal oscillator is shut down while in Sleep mode it will take some amount of time for the oscillator to start up and the device to enable itself to receive messages This Oscillator Start up Timer OST is defined as 128 Tosc The device will ignore the message that caused the wake up from Sleep mode as well as any messages that occur while the device is waking up The device will wake up in Listen only mode The MCU must set Normal mode before the DSTEMP will be able to communicate on the bus The device can be programmed to apply a low pass filter function to the RXCAN input line while in internal Sleep mode This feature can be used to prevent the device from waking up due to short glitches on the CAN bus lines The CNF3 WAKFIL bit enables or disables the filter 10 3
85. peated 6 3 Form Error If a node detects a dominant bit in one of the four segments including end of frame interframe space acknowledge delimiter or CRC delimiter a form error has occurred and an error frame is generated The message is repeated 6 4 Bit Error A bit error occurs if a transmitter detects the opposite bit level to what it transmitted i e transmitted a dominant and detected a recessive or transmitted a recessive and detected a dominant Exception the case where the transmitter sends a recessive bit and a dominant bit is detected during the arbitration field and the acknowledge slot no bit error is generated because normal arbitration is occurring 6 5 Stuff Error If between the start of frame and the CRC delimiter six consecutive bits with the same polarity are detected the bit stuffing rule has been violated A stuff error occurs and an error frame is generated The message is repeated 6 6 Error States Detected errors are made known to all other nodes via error frames The transmission of the erroneous mes sage is aborted and the frame is repeated as soon as possible Furthermore each CAN node is in one of the three error states according to the value of the internal error counters 1 Error active 2 Error passive 3 Bus off transmitter only The error active state is the usual state where the node can transmit messages and active error frames made of dominant bits without any
86. r Interrupt When an error occurs during the transmission or reception of a message the message error flag CANINTF MERRF will be set and if the CANINTE MERRE bit is set an interrupt will be gener ated on the INT pin This is intended to be used to facilitate baud rate determination when used in conjunction with Listen only mode 7 5 Bus Activity Wakeup Interrupt When the MCP2515 is in Sleep mode and the bus activ ity wakeup interrupt is enabled CANINTE WAKIE 1 an interrupt will be generated on the INT pin and the CANINTF WAKIF bit will be set when activity is detected on the CAN bus This interrupt causes the MCP2515 to exit Sleep mode The interrupt is reset by clearing the WAKIF bit Note The MCP2515 wakes up into Listen only mode 7 6 Error Interrupt When the error interrupt is enabled CANINTE ERRIE 1 an interrupt is generated on the INT pin if an overflow condition occurs or if the error state of the transmitter or receiver has changed The Error Flag EFLG register will indicate one of the following conditions 7 6 1 RECEIVER OVERFLOW An overflow condition occurs when the MAB has assembled a valid receive message the message meets the criteria of the acceptance filters and the receive buffer associated with the filter is not available for loading of a new message The associated EFLG RXnOVR bit will be set to indicate the overflow condition This bit must be cleared by the MCU 2007 Microch
87. r of data bytes that were received REGISTER 4 9 RXBnDM RECEIVE BUFFER DATA BYTE ADDRESS 66h 6Dh 76h 7Dh R x R x R x R x R x R x R x R x RBnDm7 RBnDm6 RBnDm5 RBnDm4 RBnDm3 RBnDm2 RBnDm 1 RBnDmO bit 7 bit 0 Legend R Readable bit W Writable bit U Unimplemented bit read as 0 n Value at POR 1 Bit is set 0 Bit is cleared Bit is unknown bit 7 0 RBnDm7 RBnDm0 Receive Buffer n Data Field Bytes m Eight bytes containing the data bytes for the received message 2007 Microchip Technology Inc DS21801E page 31 MCP2515 4 5 Message Acceptance Filters and Masks The message acceptance filters and masks are used to determine if a message in the message assembly buffer should be loaded into either of the receive buffers see Figure 4 5 Once a valid message has been received into the MAB the identifier fields of the message are compared to the filter values If there is a match that message will be loaded into the appropriate receive buffer 4 5 1 DATA BYTE FILTERING When receiving standard data frames 11 bit identifier the DSTEMP automatically applies 16 bits of masks and filters normally associated with extended identifiers to the first 16 bits of the data field data bytes 0 and 1 Figure 4 4 illustrates how masks and filters apply to extended and standard data frames Data byte filtering reduces the load on the MCU when implementing Higher Layer Protocols HL
88. re 1 1 The device consists of three main blocks 1 The CAN module which includes the CAN protocol engine masks filters transmit and receive buffers 2 The control logic and registers that are used to configure the device and its operation 3 The SPI protocol block An example system implementation using the device is shown in Figure 1 2 1 1 CAN Module The CAN module handles all functions for receiving and transmitting messages on the CAN bus Messages are transmitted by first loading the appropriate message buffer and control registers Transmission is initiated by using control register bits via the SPI interface or by using the transmit enable pins Status and errors can be checked by reading the appropriate registers Any message detected on the CAN bus is checked for errors and then matched against the user defined filters to see if it should be moved into one of the two receive buffers 1 2 Control Logic The control logic block controls the setup and operation of the MCP2515 by interfacing to the other blocks in order to pass information and control Interrupt pins are provided to allow greater system flexibility There is one multi purpose interrupt pin as well as specific interrupt pins for each of the receive registers that can be used to indicate a valid message has been received and loaded into one of the receive buffers Use of the specific interrupt pins is optional The general purpose interrupt pin as
89. received into the buffer This bit provides a positive lockout to ensure that the MCU has finished with the message before the MCP2515 attempts to load a new message into the receive buffer If the CANINTE RXnlE bit is set an interrupt will be generated on the INT pin to indicate that a valid message has been received In addition the associated RXnBF pin will drive low if configured as a receive buffer full pin See Section 4 4 RXOBF and RX1BF Pins for details 4 2 Receive Priority the higher priority buffer has one mask and two message acceptance filters associated with it The received message is applied to the mask and filters for RXBO first RXB1 is the lower priority buffer with one mask and four acceptance filters associated with it In addition to the message being applied to the RBO mask and filters first the lower number of acceptance filters makes the match on RXBO more restrictive and implies a higher priority for that buffer When a message is received bits 3 0 of the RXBnCTRL register will indicate the acceptance filter number that enabled reception and whether the received message is a remote transfer request 4 2 1 ROLLOVER Additionally RXBOCTRL register can be configured such that if RXBO contains a valid message and another valid message is received an overflow error will not occur and the new message will be moved into RXB1 regardless of the acceptance criteria of RXB1 4 2 2
90. red to sample three times per bit In this case while the bit is still sampled at the end of PS1 two additional samples are taken at one half TQ intervals prior to the end of PS1 with the value of the bit being determined by a majority decision INFORMATION PROCESSING TIME The Information Processing Time IPT is the time required for the logic to determine the bit level of a sampled bit The IPT begins at the sample point is Therefore PS2 IPT 2TQ min SYNCHRONIZATION JUMP WIDTH The Synchronization Jump Width SJW adjusts the bit clock as necessary by 1 4 TQ as configured to maintain synchronization with the transmitted message Synchronization is covered in more detail later in this data sheet Time Quantum Each of the segments that make up a bit time are made up of integer units called Time Quanta TQ The length of each Time Quantum is based on the oscillator period tosc The base TQ equals twice the oscillator period Figure 5 2 shows how the bit period is derived from Tosc and TQ The TQ length equals one TQ clock period which is programmable using a programmable prescaler called the Baud Rate Prescaler BRP This is illustrated in the following equation EQUATION 5 2 _ 2 BRP 2 BRP Tosc OSC Where BRP equals the configuration as shown in
91. restrictions In the error passive state messages and passive error frames made of recessive bits may be transmitted The bus off state makes it temporarily impossible for the station to participate in the bus communication During this state messages can neither be received or transmitted Only transmitters can go bus off 6 7 Error Modes and Error Counters The MCP2515 contains two error counters the Receive Error Counter REC see Register 6 2 and the Transmit Error Counter TEC see Register 6 1 The values of both counters can be read by the MCU These counters are incremented decremented accordance with the CAN bus specification The MCP2515 is error active if both error counters are below the error passive limit of 128 It is error passive if at least one of the error counters equals or exceeds 128 It goes to bus off if the TEC exceeds the bus off limit of 255 The device remains in this state until the bus off recovery sequence is received The bus off recovery sequence consists of 128 occurrences and 11 consec utive recessive bits see Figure 6 1 The MCP2515 after going bus off will recover back to error active without any intervention by the MCU if the bus remains idle for 128 x 11 bit times If this is not desired the error interrupt service routine should address this The Current Error mode of the MCP2515 can be read by the MCU via the EFLG register see Register 6 3 Additionally
92. ror Interrupt Enable bit multiple sources in EFLG register 1 Interrupt on EFLG error condition change 0 Disabled bit 4 TX2IE Transmit Buffer 2 Empty Interrupt Enable bit 1 Interrupt on TXB2 becoming empty 0 Disabled bit 3 Transmit Buffer 1 Empty Interrupt Enable bit 1 Interrupt on TXB1 becoming empty 0 Disabled bit 2 TXOIE Transmit Buffer 0 Empty Interrupt Enable bit 1 Interrupt on TXBO becoming empty 0 Disabled bit 1 RX1IE Receive Buffer 1 Full Interrupt Enable bit 1 Interrupt when message received in RXB1 0 Disabled bit 0 RXOIE Receive Buffer 0 Full Interrupt Enable bit 1 Interrupt when message received in RXBO 0 Disabled DS21801E page 50 2007 Microchip Technology Inc MCP2515 REGISTER 7 2 CANINTF INTERRUPT FLAG ADDRESS 2Ch R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 MERRF WAKIF ERRIF TX2IF TXOIF RX1IF RXOIF bit 7 bit 0 Legend R Readable bit W Writable bit U Unimplemented bit read as 0 n Value at POR T Bit is set 0 Bit is cleared x Bit is unknown bit 7 MERRF Message Error Interrupt Flag bit 1 Interrupt pending must be cleared by MCU to reset interrupt condition 0 No interrupt pending bit 6 WAKIF Wakeup Interrupt Flag bit 1 Interrupt pending must be cleared by MCU to reset interrupt condition 0 No interrupt pending bit 5 ERRIF Error Interrupt Flag bit multiple sources in EF
93. s the FILHIT bits will encode the binary value of the lowest numbered filter that matched For example if filter RXF2 and filter RXF4 match FILHIT will be loaded with the value for RXF2 This essentially prioritizes the acceptance filters with a lower numbered filter having higher priority Messages are compared to filters in ascending order of filter number This also insures that the message will only be received into one buffer This implies that RXBO has a higher priority than RXB1 4 5 5 CONFIGURING THE MASKS AND FILTERS The mask and filter registers can only be modified when the MCP2515 is in Configuration mode see Section 10 0 Modes of Operation MESSAGE ACCEPTANCE MASK AND FILTER OPERATION Acceptance Filter Register Acceptance Mask Register RXFno RXMno P RxRqst RXFn 3D E RXMn gt Message Assembly Buffer Identifier 2007 Microchip Technology Inc DS21801E page 33 MCP2515 REGISTER 4 10 RXFnSIDH FILTER n STANDARD IDENTIFIER HIGH ADDRESS 00h 04h 08h 10h 14h 18h R W x R W x R W x R W x R W x R W x R W x R W x 51010 5109 5108 5107 5106 5105 5104 5103 bit 7 bit 0 Legend R Readable bit W Writable bit U Unimplemented bit read as 0 n Value at POR 1 Bit is set 0 Bit is cleared x Bit is
94. sage v Transmit Message was Message Transmitted Successfully Yes Clear TxBnCTRL TXREQ Yes Generate 1 Interrupt CANINTE TXnIE 1 gt 5 CANTINF TXnIF No The CANINTE TXnIE bit determines if an interrupt should be generated when a message is successfully XBnCTRL TXREQ 0 or CANCTRL ABAT 1 f Message Error Message error or Lost arbitration Lost Arbitration Set TxBnCTRL TXERR CANTINF MERRF 5 TxBNCTRL MLOA No 4 5 Interrupt transmitted GOTO START 2007 Microchip Technology Inc DS21801E page 17 MCP2515 REGISTER 3 1 TXBNCTRL TRANSMIT BUFFER n CONTROL REGISTER ADDRESS 30h 40h 50h U 0 0 0 0 R W 0 U 0 R W 0 R W 0 ABTF MLOA TXERR TXREQ 1 bit 7 bit 0 Legend R Readable bit W Writable bit U Unimplemented bit read as 0 n Value at POR 1 Bit is set 0 Bit is cleared x Bit is unknown bit 7 Unimplemented Read as 0 bit 6 ABTF Message Aborted Flag bit 1 Message was aborted 0 Message completed transmission successfully bit 5 MLOA Message Lost Arbitration bit 1 Message lost arbitration while being sent 0 M
95. struction The Load TX Buffer instruction Figure 12 5 eliminates the eight bit address required by a normal write command The eight bit instruction sets the address pointer to one of six addresses to quickly write to a transmit buffer that points to the ID or data address of any of the three transmit buffers 12 7 Request To Send RTS Instruction The RTS command can be used to initiate message transmission for one or more of the transmit buffers The MCP2515 is selected by lowering the CS pin The RTS command byte is then sent Shown in Figure 12 6 the last 3 bits of this command indicate which transmit buffer s are enabled to send This command will set the TxBnCTRL TXREQ bit for the respective buffer s Any or all of the last three bits can be set in a single command If the RTS command is sent with nnn 000 the command will be ignored 12 8 Read Status Instruction The Read Status instruction allows single instruction access to some of the often used status bits for message reception and transmission The MCP2515 is selected by lowering the cs pin and the read status command byte shown in Figure 12 8 is sent to the MCP2515 Once the command byte is sent the MCP2515 will return eight bits of data that contain the status If additional clocks are sent after the first eight bits are transmitted the MCP2515 will continue to output the status bits as long as the CS pin is held low and clocks are provided on SCK
96. t 4 B1RTS TX1RTX Pin State bit Reads state of TX1RTS pin when in Digital Input mode Reads as 0 when pin is in Request to Send mode bit 3 BORTS TXORTS Pin State bit Reads state of TXORTS pin when in Digital Input mode Reads as 0 when pin is in Request to Send mode bit 2 B2RTSM TX2RTS Pin mode bit 1 Pin is used to request message transmission of TXB2 buffer on falling edge 0 Digital input bit 1 B1RTSM TX1RTS Pin mode bit 1 Pin is used to request message transmission of TXB1 buffer on falling edge 0 Digital input bit 0 BORTSM TXORTS Pin mode bit 1 Pin is used to request message transmission of TXBO buffer on falling edge 0 Digital input REGISTER 3 3 TXBnSIDH TRANSMIT BUFFER n STANDARD IDENTIFIER HIGH ADDRESS 31h 41h 51h R W x R W x R W x R W x R W x R W x R W x R W x 51010 5109 5108 5107 5106 5105 5104 5103 bit 7 bit 0 Legend R Readable bit W Writable bit U Unimplemented bit read as 0 n Value at POR 1 Bit is set 0 Bit is cleared x Bit is unknown bit 7 0 SID Standard Identifier bits lt 10 3 gt 2007 Microchip Technology Inc DS21801E page 19 MCP2515 REGISTER 3 4 TXBnSIDL TRANSMIT BUFFER n STANDARD IDENTIFIER LOW ADDRESS 32h 42h 52h R W x R W x R W x R W x R W x R W x R W x R W x 102 5101 SIDO EKIDE 21017 21016 bit 7 bit 0 Legend R Readable bit W Writable bit U
97. t Mode One shot mode ensures that a message will only attempt to transmit one time Normally if a CAN message loses arbitration or is destroyed by an error frame the message is retransmitted With One shot mode enabled a message will only attempt to transmit one time regardless of arbitration loss or error frame One shot mode is required to maintain time slots in deterministic systems such as TTCAN 2007 Microchip Technology Inc DS21801E page 15 MCP2515 3 5 TXnRTS PINS The TXnRTS pins are input pins that can be configured as Request to send inputs which provides an alternative means of initiating the transmission of a message from any of the transmit buffers Standard digital inputs Configuration and control of these pins is accomplished using the TXRTSCTRL register see Register 3 3 The TXRTSCTRL register can only be modified when the MCP2515 is in Configuration mode see Section 10 0 Modes of Operation If configured to operate as a request to send pin the pin is mapped into the respective TXBnCTRL TXREQ bit for the transmit buffer The TXREQ bit is latched by the falling edge of the TXnRTS pin The TXnRTS pins are designed to allow them to be tied directly to the RXnBF pins to automatically initiate a message transmission when the RXnBF pin goes low The TXnRTS pins have internal pull up resistors of 100 nominal 3 6 Aborting Transmission The MCU can request to abort a
98. t Of Frame High Time 2 Tosc ns Note 1 16 tySOF Start Of Frame Propagation 2 Tosc ns Measured from CAN bit sample Delay 0 5 TQ point Device is a receiver CNF1 BRP lt 5 0 gt 0 Note 2 Note 1 All CLKOUT mode functionality and output frequency is tested at device frequency limits however CLKOUT prescaler is set to divide by one This parameter is periodically sampled and not 10096 tested 2 Design guidance only not tested FIGURE 13 1 START OF FRAME PIN AC CHARACTERISTICS 16 RXCAN sample point ma 1 I DS21801E page 72 2007 Microchip Technology Inc MCP2515 TABLE 13 6 SPI INTERFACE AC CHARACTERISTICS SPI Interface AC Characteristics Extended E 40 C 011280 45V to 58V eus Sym Characteristic Min Max Units Conditions FOLK Clock Freguency 10 MHz 1 Tess CS Setup Time 50 ns 2 TcsH CS Hold Time 50 ns 3 TcsD CS Disable Time 50 ns 4 Tsu Data Setup Time 10 ns 5 THD Data Hold Time 10 ns 6 TR CLK Rise Time 2 us Note 1 7 TF CLK Fall Time 2 us Note 1 8 THI Clock High Time 45 ns 9 TLO Clock Low Time 45 ns ns 10 TCLD Clock Delay Time 50 ns 11 TCLE Clock Enable Time 50 ns 12 Tv Output Valid from Clock Low 45 ns 13 THO Output Hold Time 0 ns 14 This Output Disable Time 100 ns Note 1 This parameter is
99. ted Read as 0 bit 6 5 RXM Receive Buffer Operating Mode bits 11 Turn mask filters off receive any message 10 Receive only valid messages with extended identifiers that meet filter criteria 01 Receive only valid messages with standard identifiers that meet filter criteria 00 Receive all valid messages using either standard or extended identifiers that meet filter bit 4 Unimplemented Read as 0 bit 3 RXRTR Received Remote Transfer Request bit 1 Remote Transfer Request Received 0 No Remote Transfer Request Received bit 2 BUKT Rollover Enable bit 1 RXBO message will rollover and be written to RXB1 if RXBO is full 0 Rollover disabled bit 1 BUKT1 Read only Copy of BUKT bit used internally by the MCP2515 bit 0 FILHIT Filter Hit bit indicates which acceptance filter enabled reception of message 1 Acceptance Filter 1 RXF1 0 Acceptance Filter 0 RXFO Note If a rollover RXBO to RXB1 occurs the FILHIT bit will reflect the filter that accepted the message that rolled over 2007 Microchip Technology Inc DS21801E page 27 MCP2515 REGISTER 4 2 RXB1CTRL RECEIVE BUFFER 1 CONTROL ADDRESS 70h U 0 R W 0 R W 0 U 0 R 0 R 0 R 0 R 0 1 RXMO RXRTR FILHIT2 FILHIT1 FILHITO bit 7 bit 0 Legend R Readable bit W Writable bit U Unimplemented bit read as 0 n Value at POR 1 Bit is set 0 Bit is cleared x Bit
100. the interrupt priority Once the highest priority interrupt condition has been cleared the code for the next highest priority interrupt that is pending if any will be reflected by the ICOD bits see Table 7 1 Only those interrupt sources that have their associated CANINTE enable bit set will be reflected in the ICOD bits TABLE 7 1 ICOD lt 2 0 gt DECODE ICOD lt 2 0 gt Boolean Expression 000 ERR WAK TXO TX1 TX2 RXO RX1 00 ERR 010 ERR WAK 01 ERR WAK TXO 100 ERR WAK TXO TX1 10 ERR WAK TXO TX1 TX2 110 ERR WAK TXO TX1 TX2 RXO 11 ERR WAK TXO TX1 TX2 RXO RX1 Note ERR is associated with CANINTE ERRIE 7 2 Transmit Interrupt When transmit interrupt is enabled CANINTE TXnIE 1 an interrupt will be generated on the INT pin once the associated transmit buffer becomes empty and is ready to be loaded with a new message The CANINTF TXnIF bit will be set to indicate the source of the interrupt The interrupt is cleared by clearing the TXnIF bit 7 3 Receive Interrupt When the receive interrupt is enabled CANINTE RXnIE 1 an interrupt will be generated on the INT pin once a message has been successfully received and loaded into the associated receive buffer This interrupt is activated immediately after receiving the EOF field The CANINTF RXnIF bit will be set to indicate the source of the interrupt The interrupt is cleared by clearing the RXnIF bit 7 4 Message Erro
101. the resonators 20 MHz 15 pF 15 pF application listed below for basic start up and operation These values are not optimized Different capacitor values may be required to produce acceptable oscillator operation The user should test the performance of the oscillator over the expected VDD and temperature range for the Capacitor values are for design guidance only mation See the notes following Table 8 2 for additional infor Resonators Used These capacitors were tested with the crystals listed below for basic start up and operation These values are not optimized Different capacitor values may be required to produce acceptable oscillator operation The user should test the performance of the oscillator over the expected and temperature range for the application See the notes following this Table for additional 4 0 MHz information 8 0 MHz Crystals Used 16 0 MHz 4 0 MHz 8 0 MHz 20 0 MHz Note 1 While higher capacitance increases the stability of the oscillator it also increases the start up time 2 Since each resonator crystal has its own characteristics the user should consult the resonator crystal manufacturer for appropriate values of external components 3 RS may be required to avoid overdriving crystals with low drive level specification 4 Always verify oscillator performance over the VDD and temperature range that is expected for the application
102. to bits lt 15 8 gt of the Extended Identifier portion of a received message RXMnEIDO MASK n EXTENDED IDENTIFIER LOW ADDRESS 23h 27h R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 R W 0 EID7 EID6 EID5 2104 EID3 EID2 EID1 EIDO bit 7 bit 0 Legend R Readable bit W Writable bit U Unimplemented bit read as 0 n Value at POR 1 Bit is set 0 Bit is cleared x Bit is unknown bit 7 0 EID Extended Identifier Mask bits lt 7 0 gt These bits hold the mask bits to be applied to the bits lt 7 0 gt of the Extended Identifier portion of a received message DS21801E page 36 2007 Microchip Technology Inc MCP2515 5 0 BIT TIMING All nodes on a given CAN bus must have the same nominal bit rate The CAN protocol uses Non Return to Zero NRZ coding which does not encode a clock within the data stream Therefore the receive clock must be recovered by the receiving nodes and synchronized to the transmitter s clock As oscillators and transmission times may vary from node to node the receiver must have some type of Phase Lock Loop PLL synchronized to data transmission edges to synchronize and maintain the receiver clock Since the data is NRZ coded it is necessary to include bit stuffing to insure that an edge occurs at least every six bit times to maintain the Digital Phase Lock Loop DPLL synchronization The bit timing of the MCP2515 is implemented
103. typically the TDELAY is 1 2 TQ SyncSeg 1 and PropSeg 2 So setting PS1 7 Ta would place the sample at 10 after the transition This would leave 6 for PS2 Since PS2 is 6 according to the rules SJW could be a maximum of 4 Ta However a large SJW is typically only necessary when the clock generation of the differ ent nodes is inaccurate or unstable such as using ceramic resonators So a SJW of 1 is usually enough 5 4 Oscillator Tolerance The bit timing requirements allow ceramic resonators to be used in applications with transmission rates of up to 125 kbit sec as a rule of thumb For the full bus speed range of the CAN protocol a quartz oscillator is required A maximum node to node oscillator variation of 1 796 is allowed 5 5 Bit Timing Configuration Registers The configuration registers CNF1 CNF2 control the bit timing for the CAN bus interface These registers can only be modified when the MCP2515 is in Configuration mode see Section 10 0 Modes of Operation 5 5 1 The BRP lt 5 0 gt bits control the baud rate prescaler These bits set the length of relative to the OSC1 input frequency with the minimum TQ length being 2Tosc when BRP lt 5 0 gt b000000 The SJW lt 1 0 gt bits select the SJW in terms of number of Tas 5 5 2 CNF2 The PRSEG lt 2 0 gt bits set the length in of the propagation segment The PHSEG1 lt 2 0 gt bits set the length
104. wn bit 7 0 EID Extended Identifier bits lt 15 8 gt These bits hold bits 15 through 8 of the Extended Identifier for the received message DS21801E page 30 2007 Microchip Technology Inc MCP2515 REGISTER 4 7 RXBnEIDO RECEIVE BUFFER n EXTENDED IDENTIFIER LOW ADDRESS 64h 74h R x R x R x R x R x R x R x R x EID7 EID6 EID5 2104 EID3 EID2 EID1 EIDO bit 7 bit 0 Legend R Readable bit W Writable bit U Unimplemented bit read as 0 n Value at POR 1 Bit is set 0 Bit is cleared x Bit is unknown bit 7 0 EID Extended Identifier bits lt 7 0 gt These bits hold the least significant eight bits of the Extended Identifier for the received message REGISTER 4 8 RXBnDLC RECEIVE BUFFER n DATA LENGHT CODE ADDRESS 65h 75h R x R x R x R x R x R x R x R x EID7 EID6 EID5 EID4 EID3 EID2 EID1 EIDO bit 7 bit 0 Legend R Readable bit W Writable bit U Unimplemented bit read as 0 n Value at POR 1 Bit is set 0 Bit is cleared Bit is unknown bit 7 Unimplemented Reads as 0 bit 6 RTR Extended Frame Remote Transmission Request bit valid only when RXBnSIDL IDE 1 1 Extended Frame Remote Transmit Request Received 0 Extended Data Frame Received bit 5 Reserved Bit 1 bit 4 RBO Reserved Bit 0 bit 3 0 DLC Data Length Code bits lt 3 0 gt Indicates numbe
105. yncSeg Hard synchronization forces the edge that has occurred to lie within the synchronization segment of the restarted bit time Due to the rules of synchronization if a hard synchronization occurs there will not be a resynchronization within that bit time 5 2 2 RESYNCHRONIZATION As a result of resynchronization PS1 may be lengthened or PS2 may be shortened The amount of lengthening or shortening of the phase buffer segments has an upper bound given by the Synchronization Jump Width SJW The value of the SJW will be added to PS1 or subtracted from PS2 see Figure 5 3 The SJW represents the loop filtering of the DPLL The SJW is programmable between 1 TQ and 4 TQ 5 2 2 1 Phase Errors The NRZ bit coding method does not encode a clock into the message Clocking information will only be derived from recessive to dominant transitions The property which states that only a fixed maximum number of successive bits have the same value bit stuffing ensures resynchronization to the bit stream during a frame The phase error of an edge is given by the position of the edge relative to SyncSeg measured in TQ The phase error is defined in magnitude of TQ as follows e 0ifthe edge lies within SYNCSEG gt 0 edge lies before the SAMPLE POINT TQ is added to PS1 e Oifthe edge lies after the SAMPLE POINT of the previous bit TQ is subtracted from PS2 5 2 2 2 No Phase Error e 0 If the magnitude

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