Cortex-M3 权威 Service Manual(1)(1)
Contents
1. 3 4 error fault2. Cortex M3 4GB 2 6 PRIMASK FAULTMASK time critical deadline 8 30 Cortex M3 OxFFFFFFFF OxE0000000 OxDFFFFFFF OxA0000000 Ox9FFFFFFF Ox60000000 Ox5FFFFFFF Ox40000000 Ox3FFFFFFF 0x20000000 Ox1FFFFFFF Ox00000000 CM3 512 svetom ove NVIC MPU yStem Leve MB 1lGB External Device 8051 8255 1GB External RAM 512MB Peripherals 512MB sRAM RAM
3. NVIC MPU PSP MSP 8 CONTROL CONTROL 0 0 43
4. USB ARM Cortex M3 Cortex 32 32 DSP CM3 CM3 32
5. rock song hotmail com QQ 9471202 9312500 bugs Y Dz LL 2008 07 02 Sy Cortex M3 ARM7TDMI ARM CPU
6. POP PUSH 1 2 PUSH POP SP Cortex M3 PUSH POP PUSH RO R13 R0 R13 long POP RO RO R13 C ortex M3 PUSH
7. PUSH POP PUSH RO R3 LR POP RO R3 PC POP PC PUSH LR LR LR PC LR LR PC PUSH R13 STMDB POP R13 LDMIA STMDB LDMIA 3 10 R0 R2
8. Cortex M3 17 2 Cortex M3 1 device aggregation 3 4 CM3 C C CM3 ARM7 ARM9 NXP philips TI Atmel OKI ST ARM 32
9. handler SCS s s MSR APSR fault CONTROL 0 CONTROL 0 handler handler CONTROL 0 handler CONTROLI O Exception Exception handler handler CONTROL 0 Code Exception Exception ed 3 7
10. ARRM7 ARMY CM3 Thumbj Thumb CM3 both 16 32 ARM7 ARM9 Cortex M3 ARMVv7 S Cortex M3 SN Thumb ARM ARM7 CM3 data crunching CM3 ARM Cortex M3
11. Pull CoreSight 6 4 35 4 Cortex M3 ETM DWT fault fault patch ITM 36 Cortex M3 j CM3 RO R15 RO R12 A a 3 Cortex M3 16 RO R7
12. 5 retarget fault region both 200 6 text SI E 7
13. 2 CONTROL 2 5 F MPU MPU Cortex M3 Interrupt Controller
14. 4 TCM 20 Cortex M3 1 1 1 ARM ARM7TDMI S v4T ARM920T v4T ARM926EJ S v5E DSP Jazelle ARM966HS v5E MPU DSP ARM1022E DSP ARM1136J F S DSP Jazelle Cortex M3 MPU NVIC Cortex R4F MPU DSP 2 Jazelle ARM Java 3 MMU MMU MMU safety critical MPU MPU MMU
15. Cortex M3 Cortex M3 SP 32 Sp 4 RO PUSH RO Occupied Occupied Memory Occupied Occupied Be Last pushed data lt SP EE Occupied 0x12345678 lt SP Stack growth POP SP SP 4 47 Cortex M3 3 Occupied POP RO Occupied Memo Occupied Occupied ord Occupied Occupied ht SP 0x12345678 Ht SP 0x12345678 RO RO Ox12345678 9 POP 9 Ph PUSH ISR CM3 SP Cortex M3 ISR SP
16. 2 Cortex M3 Cortex M3 UBFX BFI BFC CLz RBIT UDIV SDIV SEV WFE WFI MSR MBRS CM3 Thumb 2 C EE CM3 j E CM3 SIMD SETEND FIQ wDNP CM3 1 fault Cortex M3 2 2 N A NMI hard fault
17. 3 Cortex M3 2 100MHz i 2 2 CM3 CPIl MHz Cortex M3 240 CM3 P RO R3 R12 LR PSR PC
18. NVIC 240 NVIC 16 4 1 11 CM3 256 2 2 NMI fault fault fault MPU Abort N A N A pendable request 33 Cortex M3 16 IRQ 0 0 17 IRQ 1 1 255 IRQ 239 239 CM3 240 NMI Cortex M3 3 CM3
19. 7 ARM ARMv7 Cortex ARM ARM7TDMI ARMVv7 v4T AS ARM ARM7TDMI ARM 32 ARM ARM 21 Cortex M3 1 16 Thumb Thumb Thumb
20. 3 Cortex M3 Cortex M3 Cortex M3 CM3 ARM The Cortex M The ARMv7 M Architecture Application Level Reference Manual 2 3 Technical Reference Manual CM3 AMBA Specification 2 0 4 AMBA C ARM Application Note 179 Cortex M3 Embedded Software Development 7
21. E 1 PC Java 19 Cortex M3 R ARMv7 R gt M F Cortex v7 M jy 1 HH CARMVv7 M Cortex M3 M
22. Abort N A 3 IRQ 0 0 er 7 9 s CM3 handler handler CM3 WORD 32 handler NVIC 0 0 3 5 oo oa 45 Cortex M3 3 ram Ox48 Ox3FF IRQ 2 239 11 SVC NVIC 11x4 0x2C
23. 0 0 PRIMASK BASEPRI FAULTMASK 0S fault faults fault FAULTMASK os PRIMASK FAULTMASK BASEPRI MRS MSR MRS RO BASEPRI BASEPRI RO MRS RO FAULTMASK 41 Cortex M3 3 MRS RO PRIMASK 2 MSR BASEPRI RO R0 BASEPRI MSR FAULTMASK RO MSR PRIMASK RO0 3 CM3 CPS 4 CPSID PRIMASK 1 I PRIMASK 0 CPSID FF LTMASK 1 F LTIMASK 0 CPSIE CPSIE
24. 5 Cortex M3 CM3 Code D Code AE 5 SRAM RAM 31 Cortex M3 2 MPU Cortex M3
25. CM3 32 32 CM3 MPU Both Cortex M3 Cortex M3 Processor Core System 2 o_O 5 CE Register I Bank es Interrupts GO sz 8 Memory Interface Memory Protection Unit Instruction Bus Data Bus Debug Interface Memory System and Peripherals 2 1 Private Peripherals Optional Cortex M3 Cortex M3 RO R15 R13 SP
26. MPU MPU CONTROL SVC SVC CONTROL 28 Cortex M3 4
27. 0 MSP Cortex M3 PUSH POP PUSH POP 9 SP PUSH POP PUSH POP SP PUSH PUSH PUSH POP PUSH POP SpP RO X R1 Y R2 2Z
28. CM3 ETM ETM PC Cortex M3 1 Cortex M3 handler CTPIU TIPu fault CITM ITM DAP
29. 8051 CM3 8 16 32 32 8 16 Cortex M3 1
30. MRS MSR MSP SP_main 0S R13 SP CONTROL 3 1 LR PC s s Cortex M3 gt High Registers ey MSP PSP PSP SP_process MSP E E PUSH POP SP 38 Cortex M3 Lu PUSH POP
31. ISR pending reentry EG 7 Cortex M3 ISR ri gj BASEPRI
32. ARM M R Cortex R4 re V7 A Ap e g Col e g Col v7 plication rtex A8 V7 R Real Time rtex R4 M Microcontroller e g Cortex M3 ARMv7 M The ARMv7 M Architecture Application Level Reference Manual M3 Technical Reference Manual v7 M System Level ARM Cortex v7M CM3 E ARM 1990s ARM7TDMI T Thumb D CM3 JTAG Debugging M ICE 4
33. both LR R14 LR BL Branch and Link LR main BL functionl function1l PC function1 LR main Functionl functionl BX LR functionl LR PUSH PC LSB 0 LR LSB 0 ARM Thumb ARM ARM Thumb CM3 LSB R15 R15 PC CM3 PC 4
34. Acorn VLSI 1 1991 ARM TI NEC F ARM er J 3 FP ARM7TDMI ARMv5TE ARM9E ARM946E S ARMv5TE ARM11 ARM11 ARM1136J F S ARM1156T2 F S ARM1176JZ F S ARMv6 ARM F MCU
35. 1 R14 ARM RISC R15 Cortex M3 PSRs PRIMASK FAULTMASK BASEPRI CONTROL xPSR s PRIMASK FAULTMASK ig gt S BASEPRI CONTROL 2 3 Cortex M3 27 Cortex M3 2 2 1 PRIMASK NMI
36. A s 7 E 2 Cortex M3 24 Cortex M3 Cortex M3 32 32 CM3 AD 2 2 2 Cortex M3 8GB cache CM3 CM3 j x
37. ARM ARM ARM 8 ARM ARM p ARM ARM PDA 20 4 ARM SoC ARM IP P ARM ARM1176TZ F S ARM 1H ARM7TDMI ARMv4T T Thumb
38. Cortex M3 MOV RO R1 R1 RO MRS lt reg gt lt special reg gt C for i 0 i lt 3 i funcl if a gt b 1 4 hc 0x123 16 2 3 3 e g IRQ 3 3 3 mmed_12 12 4 bit 15 12 15 12 1 R 2 W 3 RW 3 4 R Wc 0 Cortex M3 1 Cortex M3 Technical Reference Manual TRM Cortex M3 WW www arm com documentation ARMProcessor_Cores index html 2 ARMv7 M Architecture Application Le
39. violated MPU fault fault MPU MPU MPU region region MPU Cortex M3 Thumb 2 32 16 ARM 32 ARM 16
40. 8 NVIC 8 LDM STM PUSH POP Cortex M3 0 19mW MHz WFE E CM3 E CM3
41. xPSR P NVIC Nested Vectored NVIC P CM3 ISR ARM Cortex M3
42. BL Fxl1 Fxl1 PUSH RO RO amp SP PUSH R1 Rl amp SP PUSH R2 R2 amp SP Exl RO R2 POP R2 R2 amp SP POP R1 R1 amp SP POP RO RO amp SP BX LR RO0 X R1 Y R2 z Fx1 R0 R2 46 Lu Cortex M3 3 10 PUSH POP PUSH POP PUSH RO R2 RO R2 PUSH R3 R5 R8 R12 R3 R5 R8 R12 POP POP RO R2 RO R2 POP R3 R5 R8 R12 R3 R5 R8 R12 PUSH POP
43. ARM 40 1 7 2008 05 10 2008 06 07 TF _ tk 28
44. 1 deadline 1 166 Ab P Cortex M3 Cortex Architecture Architecture Architecture v4 v4T V5MV5E v6 1 1 1 1 1 1 1 1 a 1 1 1 1 1 1 ss ARM 1136 1176 EE 1 ARM926 1156T 2 1 946 966 1 ARM7TDMI IntelXScale 920T 1 1 Examples Intel I StrongARM 1 2 ARM E A Cortex A8 Cortex M3 Architectu V7 ea Ef
45. 1 Thumb BLX Thumb 1 1 1 La 1 I Time 1 1 2 7 ARM7 Thumb 2 Cortex M3 ARM Thumb ARM ARM CM3 ARM both ARM Thumb 32 C
46. 3 CM3 cM3 CM3 8 16 CM3 CM3 240 CM3 CM3 ARM32 9 9 P FP MPU CM3 FThumb 2 s CM3 Ad Hoc
47. ISA Thumb 2 Thumb 2 16 Thumb Thumb 2 16 32 Thumb 22 Cortex M3 Thumb 2 Instruction Set 32 bit and 16 bit Cortex M3 Thumb Instructions 16 bit 1 4 Cortex M3 EE 32 ARM Thumb 2 Thumb Thumb 2 Cortex M3 FE Thumb 2 Cortex M3 F EN
48. ARM ARM Thumb 1 Thumb 1 3 1 Thumb 2 v7 v6 ARM and Thumb 2 Instruction Set Quick Reference Card ARM Thumb 2 Thumb Thumb 2 2003 Thumb both 16 32 The ARM Architecture Reference Manual ARMARM ARM v7 3 3 Corex M3 ARMv7 M ARMv7 M Architecture Application Level Reference Manual Ref2 Thumb 2
49. WE CPU 3 A Es R 3 Windows CE Windows Mobile FMMU A ARMv7 A tH Symbian 8 M Linux E
50. ARM7TDMI ARM Cortex M3 ARM 32 ARMV7 Thumb 2 Cortex M3 ARM Wayne Lyons Cortex M3 gt ARM Cortex M3 Cortex M3 Cortex M3 Cortex M3 Technical Reference Manual Cortex M3 TRM ARMv7 M ARMv7 M Application Lev
51. MSP PSP ISR ISR CONTROL 1 cM3 CONTROL 1 CONTROL 1 0 MSP Interrupt Interrupt Service J Exit Interrupt Routine ISR Event Main Program Stacking Unstacking 1 p gt I Time Thread Mode Handler Mode Thread Mode Use MSP 1 Use MSP 1 Use MSP 3 15 CONTROL 1 0 CONTROL 1 1 PSP MSP 10 handler MS PsP Interrupt Interrupt Service Exit Event Main l Program Stacking Unstacking p gt 1 Time Thread Mode Handler Mode Thread Mode Use PSP 1 Use MSP 1 Use PSP 3 16 CONTROL 1 0 4 MSP handler
52. assert NMI halting stepping profiling JTAG Cortex M3 ARM CoreSight ARM CPU DAP DP DPs CM3 DPs SWJ DP JTAG SW DP JTAG 3 DPs SWJ DP ARM CoreSignt JTAG DP
53. RMv6 SIMD v6 Thumb 2 ARMv6 ARM9E ARM926E S A ARMv6 ARMVv7 ARM 1 DSP FARMv6 ARMv6
54. PUSH POP PUSH PUSH POP subroutine_ 1 PUSH RO R7 R12 R14 POP RO R7 R12 R14 BX R14 SP R13 both MSP PSP R13 SP MRS MSR MSP SP_main PSP SP_process PUSH POP 4 0x4 0x8 0xc R13 0 0 Read As zero 39 CortecM3 NN 3 R14 R14 LR
55. Cortex M3 3 ISR vy A 1 p gt Time Handler 1 3 8 CONTROL 0 1 both SR vw 1 1 pp 1 p gt 1 Time Handler 1 3 9 CONTROL 0 CONTROL O Cortex M3 16 4 1 11 240 Ll 240 IRQ SVC SVC
56. j 4 ARM exception fault R14 R14 ARM 3 MMU cache 1
57. zigBee DO zz Heth CM3 fault handing fault 23 Cortex M3 CM3 ne 1 MPU Cortex M3 1 ARM 8 Chpt 1 2 Chpt 3 6 Chpt 7 9 Chpt 10 11 Chpt 12 14 Chpt 15 16 Chpt 17 20 s Cortex M3 Cortex M3 Cortex M3 Cortex M3 Cortex M3
58. CM3 VO C ARM 1 be ARM ARM ARM ARM ARM ARM 1990 Advanced RISC Machines Ltd 18 Cortex M3 ARM6 VLSI Sharp ST
59. CONTROL 3 3 Cortex M3 CONTROL CONTROL 0 0 1 Handler CONTROLI 1 Cortex M3 handler CONTROL 1 0 0 1 LR 2 5 CONTROLI O CONTROL MRS MSR MRS RO CONTROL MSR CONTROL RO Cortex M3 2 42 CortexcM3 3 handler handler 3 6
60. PSR IPSR PSR EPSR MRS MSR 3 PSRs 2 3 xPSR PSR 26 25 24 23 20 Exception Number ICIT 3 3 Cortex M3 xPSR Ou le el loon le ee 3 4 xPSR PRIMASK FAULTMASK BASEPRI 3 2 Cortex M3 S PRIMASK 1 1 fault 0 FAULTMASK 1 1 NMI fault 0 BASEPRI 9
61. i SysTick NVIC 16 32 NVIC NMI NMI NMI NMI 3 4 Cortex M3 NVIC fault fault F fault 44 Cortex M3 3 3 4 Cortex M3 hard fault 1 fault fault FAULTMASK
62. Ox1000 MOV RO PC RO 0x1004 PC LR CM3 PC LSB 0 PC PC LSB 1 Thumb 0 ARM CM3 fault Cortex M3 PSRs xPSR PRIMASK FAULTMASK BASEPRI CONTROL MSR MRS MRS lt gp_reg gt lt special_reg gt MSR lt special_ reg gt lt gp_reg gt 40 Cortex M3 Lu PSRs PSR PSR APSR
63. safety critical NMI NMI SLEEPING SLEEPDEEP WF1 8051 4 fault banked JTAG MPU 1 faults i
64. handler P 48 CorexM3 3 MRS RO MSP RO MSR MSP RO R0 MRS RO PSP RO MSR PSP RO R0 PSP OS STMDB LDMIA 0OS PSP CM3 32 0x0000 0000 MSP 0x0000 0004 PC LSB 1 MSP pn
65. Reset Address Address Address TT 1 0x00000000 0x00000004 Reset Vector 3 17 ARM ARM 0 0 CM3 0 MSP 32 49 dx Wu Cortex M3 3 MSP 0x20008000 0x20008000 0x20007FFC 0x20007FF8 0x20007C00 ooo00100 FMM lt Pes Vector Ox00000004 Ox00000000 3 18 MSP PC CM3 MSP 1
66. 0x20007C00 0x20007FFF MSP 0x20008000 MSP 2 CM3 Thumb LSB 1 3 18 0x101 0x100 0x100 MSP 1 NMI fault MSP MSP 10 20 ARM 19 GCC 50
67. BASEPRI 3 Cortex M3 handler mode handler thread mode Cortex M3 handler handler 2 4 Cortex M3 CM3
68. MCU ARM7 32 10 CM3 ARM7 cCM3 ARM Cortex M3 vs Cortex M3 MCU Cortex M3 CPU CM3 MCU CM3
69. 32 Thumb 2 RO R7 RO R7 32 R8 R12 R8 R12 16 Thumb 32 32 37 Cortex M3 gt Low Registers ee R13 MSP rs xPSR PRIMASK R13 PSP FAULTMASK BASEPRI R13 R13 CM3
70. 5 12 Cortex M3 6 13 Cortex M3 7 14 Cortex M3 8 15 Cortex M3 16 Cortex M3 1 ARM Cortex M3 ARM Thumb 2 ISA Cortex M3 ARM Cortex M3 2010 20G
71. CM3 Cortex M3 TPIU JTAG AAA DAP Cortex M3 Cortex M3 2 Cortex M3 Thumb 2 16 Thumb 32 ARM 34 Cortex M3 Thumb 2 Cortex M3
72. MemManage fault fault usage Fault SVCall PendSV SysTick ARMv7 M CM3 ARM 16 4 1 11 4 1 240 CM3 FIQ v7 ARM FHIQ CM3 unified assembler framework CM3 Thumb 2 ARMv7 M Thumb 2 CM3 Thumb A v6 EB
73. 5212MB Code ARM Cortex M3 2 Cc ee Cortex M3 CM3 lt RAM CM3 MPU
74. Cortex M3 Cortex M3 Joseph Yiu Cortex M3 ARM 4 zal Cortex M3 ARM 1 E FE 150 2
75. OS PC PSP PPB AMBA AHB ARM uk Fault CoreSight AHB JTAG
76. SP banked Low Registers R13 PSP LR R15 PC High Registers MSP PSP 26 Cortex M3 RO R12 2 16 Thumb RO R12 32 RO R7 32 Thumb 2 Banked R13 Cortex M3 banked MSP PSP 0 ri
77. Thumb ARM 32 NOP Thumb 16 thumb ARM ARM Thumb overhead ARM Thumb ce ARM 32 e g BX LR ARM 1 PR OO OO 1 1 1 Thumb a 16
78. el Architecture Reference Manual Soc Cortex M3 Cortex M3 ARM GNU ARM7TDMI Cortex M3 Cortex M3 ADK AHB AHB AP AMBA APB ARM ARM ASIC ATB BE8 CPI CPU DAP DSP DWT ETM FPB FSR HTM ICE IDE IRQ ISA ISR ITM JTAG JTAG DP LR LSB LSU MCU MMU MPU MSB MSP NMI NVIC
79. vel Reference Manual ARMyv7 M www arm com products CPUs ARM_Cortex M3_v7 html 3 CoreSight Technology System Design Guide CoreSigH11i www arm com documentation Trace_Debug index html 4 AMBA Specification 4MB4 www arm com products solutions AMBA_Spec html 5 AAPCS Procedure Call Standard for the ARM Architecture AAPCS 4RM 2 www arm com pdfs aapcs pdf 6 RVCT 3 0 Compiler and Library Guide RVCT 3 0 www arm com pdfs DUI0205G _rvct_compiler and_libraries_guide pdf 7 ARM Application Note 179 Cortex M3 Embedded Sofrware Development ARM Y WH 179 Cortex M3 www arm com documentation Application_Notes index html Pp Cortex M3 1 Cortex M3 2 Cortex M3 3 10 Cortex M3 4 Cortex M3
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