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ST LSM320DL Linear sensor module 3D accelerometer sensor 2D gyroscope sensor handbook

1. Table 40 FIFO SRC REG A register WTM OVRN FIFO EMPTY FSS4 FSS3 FSS2 FSS1 FSSO INT1 CFG A 30h Table 41 INT1 CFG REG A register AOI 6D ZHIE ZLIE YHIE YLIE XHIE XLIE ZUPE ZDOWNE YUPE YDOWNE XUPE XDOWNE Table 42 INT1 CFG REG A description AOI AND OR combination of interrupt events Default value 0 Refer to Table 43 eD 6 direction detection function enabled Default value 0 Refer to Table 43 ZHIE Enable interrupt generation on Z high event or on direction recognition Default ZUPE value O 0 disable interrupt request 1 enable interrupt request ZLIE Enable interrupt generation on Z low event or on direction recognition Default ZDOWNE value O 0 disable interrupt request 1 enable interrupt request YHIE Enable interrupt generation on Y high event or on direction recognition Default YUPE value 0 0 disable interrupt request 1 enable interrupt request YLIE Enable interrupt generation on Y low event or on direction recognition Default YDOWNE value 0 0 disable interrupt request 1 enable interrupt request XHIE Enable interrupt generation on X high event or on direction recognition Default XUPE value 0 0 disable interrupt request 1 enable interrupt request XLIE XDOWNE Enable interrupt generation on X low event or on direction recognition Default value 0 0 disable interrupt request 1 enable interrupt request Content of
2. 46 INT1 CFG G description 46 INT1 SRC Gregister aa rb te Ae rond ERE E ee Ee ged mad Lag dade 46 INT1 SRC G description ren 47 INT1 THS XH G register 47 INT1 THS XH G description 47 INT1 THS XL G register 47 INT1 THS XL G description 47 INT1 THS ZH G register 47 INT1 THS ZH G description 48 INT1 THS ZL G register 48 Doc ID 018845 Rev 1 ky LSM320DL List of tables Table 100 INT1_THS_ZL_G description 48 Table 101 INT1 DURATION G register 48 Table 102 INT1 DURATION G description 48 Table 103 LGA 28L 7 5 x 4 4 x 1 1 mechanical data 51 Table 104 Document revision history EE EE Ee Re te e 52 Doc ID 018845 Rev 1 7 53 List of figures LSM320DL List of figures Figure 1 Figure 2 Figure 3 Figure 4 Figure 5 Figure 6 Figure 7 Figure 8 Figure 9 Figure 10 Figure 11 Figure 12 Figure 13 Figure
3. 13 Table 5 Temperature sensor characteristics 14 Table 6 SPI slave timing values na auaa 15 Table 7 12C slave timing values 0 16 Table 8 Absolute maximum ratings 17 Table 9 PattliSt EE EE P EE Kad dades ade EE 20 Table 10 Serial interface pin description 22 Table 11 Serial interface pin description 22 Table 12 Transfer when master is writing one byte to slave 23 Table 13 Transfer when master is writing multiple bytes to slave 23 Table 14 Transfer when master is receiving reading one byte of data from slave 23 Table 15 Transfer when master is receiving reading multiple bytes of data from slave 23 Table 16 Linear acceleration SAD Read Write patterns llle eee 24 Table 17 Angular rate SAD Read Write patterns 24 Table 18 Register address map 28 Table 19 CTRL_REG1_A register 30 Table 20 CTRL REG1 A description 30 Table 21 Data rate configuration ee Ee EE ee tee 30 Table 22 CTRL
4. 1 This bit must be set to 0 for correct operation Table 32 CTRL REG6 description l2 CLICKen Click interrupt on INT2 Default value O I2 INT1 Interrupt 1 function enabled on INT2 Default 0 BOOT 12 Boot on INT2 H LACTIVE 0 interrupt active high 1 interrupt active low 7 7 REFERENCE DATACAPTURE_A 26h Table 33 REFERENCE A register Ref7 Ref6 Ref5 Ref4 Ref3 Ref2 Ref1 Ref0 Table 34 REFERENCE register description Ref 7 Ref0 Reference value for interrupt generation Default value 0 7 8 STATUS REG A 27h Table 35 STATUS REG A register ZYXOR ZOR YOR XOR ZYXDA ZDA YDA XDA Table 36 STATUS REG A register description ZYXOR X Y and Z axis data overrun Default value 0 0 no overrun has occurred 1 a new set of data has overwritten the previous ones ZOR Z axis data overrun Default value 0 0 no overrun has occurred 1 a new data for the Z axis has overwritten the previous one YOR Y axis data overrun Default value 0 0 no overrun has occurred 1 a new data for the Y axis has overwritten the previous one XOR X axis data overrun Default value 0 0 no overrun has occurred 1 a new data for the X axis has overwritten the previous one ZYXDA X Y and Z axis new data available Default value 0 0 a new set of data is not yet available 1 a new set of data is available
5. Figure 1 Block diagram Sensing Block Sensing Interface X Yr CHARGE CS AG N AMPLIFIER AN C SDA SDI A G a gt MUX A D gt Control SDO_A G TAK s gt converter Logic gt o INT1 A 9 ii O Y N INT2Z A x INT G x CHARGE as AMPLIFIER DEMODULATOR DRDY G gt Ze gt Q 7 A mE SCL_A G l LOWPASS gt L x MUX FILTER Z d x ANALOG CONDITIONING Feedback A E E p kai Le Pa Feedback AUTOMATIC priver 7 CONTROL sed VOLTAGE AS AMPLIFIER Driver A TRIMMING REFERENCE CIBUS CLOCK SON LOGIC HEESE PHASE INTERRUPT GEN CIRCUNS GENERATOR AM09273V1 OT Doc ID 018845 Rev 1 9 53 Block diagram and pin description LSM320DL 1 2 Figure 2 Pin description Pin connection DIRECTION OF DETECTABLE ACCELERATIONS DIRECTION OF DETECTABLE ANGULAR RATE lt O O _ 9 LT gt 9218 4 a 9 Aa ro nn 8 9Y aono 7 Ha 5 5 9 o C 00 0 202050 VddlO A 28 LSM320DL Res Res Vdd IO G VCONT BOTTOM VI EW SCL G GND Res Res Res Vdd INT G Res Res Res CS A Res Vdd AM09274V1 10 53 Table 2 Pin description Pin Name Function Accelerometer C serial data SDA 1 SDA SDI_A E SPI serial data input SDI 3 wire interface ser
6. 1 Value loaded at boot This value must not be changed Doc ID 018845 Rev 1 LSM320DL Registers description Table 67 CTRL REG2 G description HPM1 High pass filter mode selection Default value 00 HPMO Refer to Table 68 HPCF3 High pass filter cut off frequency selection HPCFO Refer to Table 69 Table 68 High pass filter mode configuration HPM1 HPMO High pass filter mode 0 0 Normal mode reset reading HP RESET FILTER 0 1 Reference signal for filtering 1 0 Normal mode 1 1 Autoreset an interrupt event Table 69 High pass filter cut off frequency configuration Hz HPCF 0 ODR 100 Hz ODR 200 Hz ODR 400 Hz ODR 800 Hz 0000 8 15 30 56 0001 4 8 15 30 0010 2 4 8 15 0011 1 2 4 8 0100 0 5 1 2 4 0101 0 2 0 5 1 2 0110 0 1 0 2 0 5 1 0111 0 05 0 1 0 2 0 5 1000 0 02 0 05 0 1 0 2 1001 0 01 0 02 0 05 0 1 7 20 CTRL REG3 G 22h Table 70 CTRL REG1 G register 11 Int1 I1 Boot H Lactive PP OD l2 DRDY l2 WTM I2 ORun 12 Empty Table 71 CTRL REG3 G description 11 Int1 Interrupt enable on INT1 pin Default value O 0 disable 1 enable I1 Boot Boot status available on INT1 Default value O 0 disable 1 enable H Lactive a Interrupt active configuration on INT1 Default value O 0 high 1 low Doc ID 018845 Rev 1 41 53 Registers desc
7. 1577 Doc ID 018845 Rev 1 45 53 Registers description LSM320DL 7 36 7 37 46 53 Table 88 FIFO SRC G register description WTM Watermark status 0 FIFO filling is lower than WTM level 1 FIFO filling is equal or higher than WTM level OVRN Overrun bit status 0 FIFO is not completely filled 1 FIFO is completely filled EMPTY FIFO empty bit 0 FIFO not empty 1 FIFO empty FSS4 FSS1 FIFO stored data level INT1_CFG_G 30h Table 89 INT1_CFG_G register AND OR LIR ZHIE ZLIE o o XHIE XLIE 1 This bit must be set to 0 for correct operation Table 90 INT1 CFG G description AND OR AND OR combination of interrupt events Default value 0 0 OR combination of interrupt events 1 AND combination of interrupt events LIR Latch interrupt request Default value 0 0 interrupt request not latched 1 interrupt request latched Cleared by reading INT1 SRC reg ZHIE Enable interrupt generation on Z high event Default value 0 0 disable interrupt request 1 enable interrupt request on measured accel value higher than preset threshold ZLIE Enable interrupt generation on Z low event Default value 0 0 disable interrupt request 1 enable interrupt request on measured accel value lower than preset threshold XHIE Enable interrupt generation on X high event Default value 0 0 disable interrupt
8. a Doc ID 018845 Rev 1 33 53 Registers description LSM320DL 7 9 7 10 7 11 7 12 34 53 Table 36 STATUS_REG_A register description continued ZDA Z axis new data available Default value 0 0 a new data for the Z axis is not yet available 1 a new data for the Z axis is available YDA Y axis new data available Default value 0 0 a new data for the Y axis is not yet available 1 a new data for the Y axis is available OUT X L A 28h OUT X H A 29h X axis acceleration data The value is expressed in 2 s complement OUT Y L A 2Ah OUT Y H A 2Bh Y axis acceleration data The value is expressed in 2 s complement OUT Z L A 2Ch OUT Z H A 2Dh Z axis acceleration data The value is expressed in 2 s complement FIFO CTRL REG A 2Eh Table 37 FIFO CTRL REG Ar register FM1 FMO TR FTH4 FTH3 FTH2 FTH1 FTHO Table 38 FIFO CTRL REG A register description FM1 FMO FIFO mode selection Default value 00 see Table 39 TR Trigger selection Default value 0 0 trigger event linked to trigger signal on INT1 1 trigger event linked to trigger signal on INT2 FTH4 0 Default value 0 Table 39 FIFO mode configuration FM1 FMO FIFO mode 0 0 Bypass mode 0 1 FIFO mode 1 0 Stream mode 1 1 Trigger mode Doc ID 018845 Rev 1 ky LSM320DL Registers description 7 13 7 14 a FIFO SRC REG A 2Fh
9. AY LSM320DL Linear sensor module 3D accelerometer sensor and 2D gyroscope sensor Features m Analog supply voltage 2 4 V to 3 6 V m Digital supply voltage IOs 1 8 V m Low power mode m Power down mode m 3independent acceleration channels and 2 angular rate channels pitch and yaw m 29 49 8 16g dynamically selectable full scale m 250 500 2000 dps dynamically selectable full scale Embedded temperature sensor m SPI I2C serial interface 16 bit data output Programmable interrupt generator for free fall and motion detection m ECOPACK RoHS and Green compliant Preliminary data LGA 28L 7 5 x 4 4 x 1 1 mm The various sensing elements are manufactured using specialized micromachining processes while the IC interfaces are realized using a CMOS technology that allows to design a dedicated circuit which is trimmed to better match the sensing element characteristics LSM320DL has a dynamic user selectable full scale acceleration range of 2g 4g 8 16g and angular rate of 250 500 2000 deg sec The accelerometer and gyroscope sensors can be either activated or put in low power power down mode separately for application optimized Applications power saving m GPS navigation systems The LSM320DL is available in a plastic land grid m Impact recognition and logging array LGA package m Gaming and virtual reality input devices Several years ago ST su
10. 1 X high event has occurred XL X low Default value 0 0 no interrupt 1 X low event has occurred Interrupt 1 source register Read only register Reading at this address clears the INT1_SRC IA bit and the interrupt signal on the INT 1 pin and allows the refreshment of data in the INT1 SRC register if the latched option is chosen INT1 THS A 32h Table 46 INT1 THS A register 0 THS6 THS5 THS4 THS3 THS2 THS1 THSO Table 47 INT1 THS A description THS6 THSO Interrupt 1 threshold Default value 000 0000 Doc ID 018845 Rev 1 y LSM320DL Registers description 7 17 7 18 7 19 INT1 DURATION A 33h Table 48 INT1 DURATION Aregister 0 D6 D5 D4 D3 D2 D1 DO Table 49 INT1 DURATION A description D6 DO Duration value Default value 000 0000 D6 DO bits set the minimum duration of the interrupt 1 event to be recognized Duration steps and maximum values depend on the ODR chosen CLICK CFG A 38h Table 50 CLICK CFG A register ZD ZS YD YS XD XS Table 51 ZD CLICK_CFG_A description Enable interrupt double CLICK on Z axis Default value 0 0 disable interrupt request 1 enable interrupt request on measured accel higher than preset threshold value ZS Enable interrupt single CLICK on Z axis Default value 0 0 disable interrupt request 1 enable interr
11. Reboot memory content Default value 0 0 normal mode 1 reboot memory content FIFO EN FIFO enable Default value 0 0 FIFO disable 1 FIFO enable HPen 42 53 High pass filter enable Default value 0 0 HPF disabled 1 HPF enabled see Figure 12 Doc ID 018845 Rev 1 LSM320DL Registers description Table 75 CTRL REGS G description continued INT1 Sel INT1 selection configuration Default value 0 INT1 Selo see Table 77 Out Sel1 Out selection configuration Default value 0 Out Selo see Table 76 Figure 12 INT1 Sel and Out Sel configuration block diagram Out Sel 1 0 gt 00 ue 1 gt 01 ng DataReg SP 1 FIFO LPF2 HE o ADC LPF1 e HPF 1 HPen INT1 Sel 1 0 10 ka dnterupt Interrup 01 generator po 7777777 AM09276V1 Table 76 Out Sel configuration setting Hpen OUT SEL1 OUT SELO Description Data in DataReg and FIFO are non high X 0 0 pass filtered Data in DataReg and FIFO are high pass X 0 1 filtered 0 1 Data in DataReg and FIFO are low pass filtered by LPF2 1 1 7 Data in DataReg and FIFO are high pass and low pass filtered by LPF2 Table 77 INT_SEL configuration setting Hpen INT_SEL1 INT_SEL2 Description x 0 0 Non high pass filtered data are used for interrupt generation x 0 1 High
12. for correct operation Table 63 CTRL REG1 G description DR1 DRO Output data rate selection Refer to Table 64 BW1 BWO Bandwidth selection Refer to Table 64 PD Power down mode enable Default value 0 0 power down mode 1 normal mode or sleep mode Zen Z axis enable Default value 1 0 Z axis disabled 1 Z axis enabled Xen X axis enable Default value 1 0 X axis disabled 1 X axis enabled DR 1 0 is used to set ODR selection BW 1 0 is used to set Bandwidth selection Table 64 shows all frequencies resulting in combination of DR BW bits Doc ID 018845 Rev 1 39 53 Registers description LSM320DL 7 25 40 53 Table 64 DR and BW configuration setting DR 1 0 BW 1 0 ODR Hz Cut off 00 00 100 12 5 00 01 100 25 00 10 100 25 00 11 100 25 01 00 200 12 5 01 01 200 25 01 10 200 50 01 11 200 70 10 00 400 20 10 01 400 25 10 10 400 50 10 11 400 110 11 00 800 30 11 01 800 35 11 10 800 50 11 11 800 110 Combination of PD Zen Xen are used to set the device in different modes power down normal sleep mode according to the following table Table 65 Power mode selection configuration Mode PD Zen Xen Power down 0 Sleep 1 0 0 Normal 1 CTRL REG2 G 21h Table 66 CTRL REG2 G register of o HPM1 HPM1 HPCF3 HPCF2 HPCF1 HPCFO
13. 0 Z axis disabled 1 Z axis enabled Yen Y axis enable Default value 1 0 Y axis disabled 1 Y axis enabled Xen X axis enable Default value 1 0 X axis disabled 1 X axis enabled ODR lt 3 0 gt is used to set power mode and ODR selection In Table 21 all the frequencies resulting in a combination of ODR 3 0 are reported Table 21 Data rate configuration ODR3 ODR2 ODR1 ODRO Power mode selection 0 0 0 0 Power down mode 0 0 0 1 Normal low power mode 1 Hz 0 0 1 0 Normal low power mode 10 Hz 0 0 1 1 Normal low power mode 25 Hz 0 1 0 0 Normal low power mode 50 Hz 0 1 0 1 Normal low power mode 100 Hz 0 1 1 0 Normal low power mode 200 Hz 0 1 1 1 Normal low power mode 400 Hz 1 0 0 0 Low power mode 1 620 kHz 1 0 0 1 Normal 1 344 kHz Low Power mode 5 376 kHz Doc ID 018845 Rev 1 y LSM320DL Registers description 7 2 7 3 CTRL REG2 A 21h Table 22 CTRL REG2 A register HPM1 HPMO HPCF2 HPCF1 FDS HPCLICK HPIS2 HPIS1 Table 23 CTRL REG2 A description HPM1 HPMO High pass filter mode selection Default value 00 Refer to Table 24 HPCF2 HPCF1 High pass filter cut off frequency selection Filtered data selection Default value 0 FDS 0 internal filter bypassed 1 data from internal filter sent to output register and FIFO HPCLICK High
14. 12C slave timing diagram d r REPEATED JK YU L CARE i tsu SP STOP SDA SCL gt e ER e thst twsctty tw scth trscL sc AM09238V1 d Measurement points are done at 0 2 Vdd IO and 0 8 Vdd IO for both ports a 16 53 Doc ID 018845 Rev 1 LSM320DL Module specifications 2 5 Absolute maximum ratings Stresses above those listed as absolute maximum ratings may cause permanent damage to the device This is a stress rating only and functional operation of the device under these conditions is not implied Exposure to maximum rating conditions for extended periods may affect device reliability Table 8 Absolute maximum ratings Symbol Ratings Maximum value Unit Vdd IO VO pins supply voltage 0 3 to 4 8 V Vin Input voltage on any control pin SCL SDA SDI 0 3 to Vdd IO 0 3 V 3000 g for 0 5 ms 10000 g for 0 1 ms 3000 g for 0 5 ms 10000 g for 0 1 ms Apow Acceleration any axis powered Vdd 3 V Aunp Acceleration any axis unpowered Top Operating temperature range 40 to 85 C TsrG Storage temperature range 40 to 125 C ESD Electrostatic discharge protection 2 HBM kV This is a mechanical shock sensitive device improper handling can cause permanent damage to the part This is an ESD sensitive device improper handling can cause permanent damage to AGS the part ky Doc ID 01884
15. Multiple read command is also available in 3 wire mode Doc ID 018845 Rev 1 27 53 Register mapping LSM320DL 6 Register mapping Table 18 below provides a listing of the 8 bit registers embedded in the device and the related addresses Table 18 Register address map Name Psa Type as ia Default Comment Hex Binary Reserved do not modify 001100xb 00 1F Reserved CTRL REG1 A 001100xb rw 20 010 0000 00000111 CTRL REG2 A 001100xb rw 21 010 0001 00000000 CTRL REG3 A 001100xb rw 22 010 0010 00000000 CTRL REG4 A 001100xb rw 23 010 0011 00000000 CTRL REG5 A 001100xb rw 24 010 0100 00000000 CTRL REG6 A 001100xb rw 25 010 0101 00000000 REFERENCE A 001100xb rw 26 010 0110 00000000 STATUS REG A 001100xb r 27 010 0111 00000000 OUT XLA 001100xb r 28 010 1000 output OUT XHA 001100xb r 29 010 1001 output OUT YLA 001100xb r 2A 010 1010 output OUTYHA 001100xb r 2B 010 1011 output OUTZLA 001100xb r 2C 010 1100 output OUTZHA 001100xb r 2D 010 1101 output FIFO CTRL REG 001100xb rw 2E 010 1110 00000000 FIFO SRC REG 001100xb r 2F 010 1111 INT1 CFG A 001100xb rw 30 011 0000 00000000 INT1 SOURCE A 001100xb r 31 011 0001 00000000 INT1 THS A 001100xb rw 32 011 0010 00000000 INT1 DURATION A 001100xb rw 33 011 0011 00000000 INT2 CFG A 001100xb rw 34 011 0100 00000000 INT2 SOURCE A 001100xb r 35 011 0101 00000000 INT2 THS A 001100xb rw 3
16. REG2 A register 31 Table 23 CTRL REG2 Adescription 31 Table 24 High pass filter mode configuration 31 Table 25 CTRL_REG3_A register 31 Table 26 CTRL REG3 A description 31 Table 27 CTRL REG4 A register 32 Table 28 CTRL REG4 A description 32 Table 29 CTRL REGS A register 32 Table 30 CTRL REGS A description 32 Table 31 CTRL REG6 A register 33 Table 32 CTRL REG6 description 33 Table 33 REFERENCE A register 33 Table 34 REFERENCE register description 33 Table 35 STATUS REG Aregister 33 Table 36 STATUS REG A register description 33 Table 37 FIFO CTRL_REG_A register 34 Table 38 FIFO CTRL REG A register description 34 Table 39 FIFO mode configurat
17. address i e it is not able to receive because it is performing some real time function the data line must be left HIGH by the slave The master can then abort the transfer A LOW to HIGH transition on the SDA line while the SCL line is HIGH is defined as a STOP condition Each data transfer must be terminated by the generation of a STOP SP condition In order to read multiple bytes it is necessary to assert the most significant bit of the sub address field In other words SUB 7 must be equal to 1 while SUB 6 0 represents the address of the first register to be read In the presented communication format MAK is Master Acknowledge and NMAK is No Master Acknowledge Default address The SDO SAO pad can be used to modify less significant bits of the device address If the SAO pad is connected to voltage supply LSb is 1 ex address 00110015 or else if the SAO pad is connected to ground the LSb value is 0 ex address 0011000b The slave address is completed with a Read Write bit If the bit is 1 Read a repeated START SR condition must be issued after the two sub address bytes if the bit is 0 Write the master transmits to the slave with direction unchanged Table 16 and Table 17 explain how the SAD Read Write bit pattern is composed listing all the possible configurations Linear acceleration address the default factory 7 bit slave address is 001100xb Table 16 Linear acceleration SAD Read Wr
18. and the ST logo are trademarks or registered trademarks of ST in various countries Information in this document supersedes and replaces all information previously supplied The ST logo is a registered trademark of STMicroelectronics All other names are the property of their respective owners 2011 STMicroelectronics All rights reserved STMicroelectronics group of companies Australia Belgium Brazil Canada China Czech Republic Finland France Germany Hong Kong India Israel Italy Japan Malaysia Malta Morocco Philippines Singapore Spain Sweden Switzerland United Kingdom United States of America www st com 1577 Doc ID 018845 Rev 1 53 53
19. occurred 1 a new data for the X axis has overwritten the previous one SF Doc ID 018845 Rev 1 LSM320DL Registers description Table 83 STATUS REG G description continued ZXDA X Z axis new data available Default value O 0 a new set of data is not yet available 1 a new set of data is available ZDA Z axis new data available Default value 0 0 a new data for the Z axis is not yet available 1 a new data for the Z axis is available XDA X axis new data available Default value 0 0 a new data for the X axis is not yet available 1 a new data for the X axis is available 7 32 OUT X L G 28h OUT X H G 29h X axis angular rate data The value is expressed as 2 s complement 733 OUT Z L G 2Ch OUT Z H G 2Dh Z axis angular rate data The value is expressed as 2 s complement 7 34 FIFO CTRL REG G 2Eh Table 84 REFERENCE G register FM2 FM1 FMO WTM4 WTM3 WTM2 WTM1 WTMO Table 85 REFERENCE G register description FM2 FMO FIFO mode selection Default value 00 see Table 86 WTM4 WTMO FIFO threshold Watermark level setting Table 86 FIFO mode configuration FM2 FM1 FMO FIFO mode 0 0 0 Bypass mode 0 0 1 FIFO mode 0 1 0 Stream mode 0 1 1 Stream to FIFO mode 1 0 0 Bypass to stream mode 7 85 FIFO SRC REG G 2Fh Table 87 FIFO SRC G register WTM OVRN EMPTY FSS4 FSS3 FSS2 FSS1 FSSO
20. output INT1 TSH XH G 110100xb rw 32 011 0010 00000000 INT1 TSH XL G 110100xb rw 33 011 0011 00000000 Reserved 110100xb rw 34 Reserved Reserved 110100xb rw 35 Reserved INT1 TSH ZH G 110100xb rw 36 011 0110 00000000 INT1 TSH ZL G 110100xb rw 37 011 0111 00000000 INT1 DURATION G 110100xb rw 38 011 1000 00000000 Registers marked as Heserved must not be changed The writing to those registers may cause permanent damage to the device The content of the registers that are loaded at boot should not be changed They contain the factory calibration values Their content is automatically restored when the device is powered up a Doc ID 018845 Rev 1 29 53 Registers description LSM320DL 7 7 1 30 53 Registers description The device contains a set of registers which are used to control its behavior and to retrieve acceleration angular rate and temperature data The registers address made of 7 bits is used to identify them and to write the data through serial interface CTRL_REG1_A 20h Table 19 CTRL REG1 A register ODR3 ODR2 ODR1 ODRO LPen Zen Yen Xen Table 20 CTRL REG1 A description ODR3 0 Data rate selection Default value 0 0000 power down Others refer to Table 21 Data rate configuration Low power mode enable Default value 0 LPen 0 normal mode 1 low power mode Zen Z axis enable Default value 1
21. pass filter enabled for CLICK function 0 filter bypassed 1 filter enabled HPIS2 High pass filter enabled for AOI function on interrupt 2 0 filter bypassed 1 filter enabled HPIS1 High pass filter enabled for AOI function on interrupt 1 0 filter bypassed 1 filter enabled Table 24 High pass filter mode configuration HPM1 HPMO High pass filter mode 0 0 Normal mode reset reading HP RESET FILTER 0 1 Reference signal for filtering 1 0 Normal mode 1 1 Autoreset on interrupt event CTRL REG3 A 22h Table 25 CTRL REG3 A register I1 CLICK I1 AOl1 o 11 DRDY1 I1 DRDY2 I1 WTM 11_OVERRUN 1 This bit must be set to 0 for correct operation Table 26 CTRL REG3 A description 11 CLICK CLICK interrupt on INT1 Default value O 0 disable 1 enable 11 AOI AOI1 interrupt on INT1 Default value 0 0 disable 1 enable Doc ID 018845 Rev 1 31 53 Registers description LSM320DL Table 26 CTRL REG3 A description continued 11 DRDY1 DRDY1 interrupt on INT1 Default value 0 0 disable 1 enable 11 DRDY2 DRDY2 interrupt on INT1 Default value 0 0 disable 1 enable 11 WTM FIFO Watermark interrupt on INT1 Default value O 0 disable 1 enable I1 OVERRUN FIFO Overrun interrup
22. pass filtered data are used for interrupt generation OT Doc ID 018845 Rev 1 43 53 Registers description LSM320DL 7 29 7 30 7 31 44 53 Table 77 INT SEL configuration setting continued Hpen INT_SEL1 INT_SEL2 Description 0 1 x Low pass filtered data are used for interrupt generation 1 1 High pass and low pass filtered data are x used for interrupt generation REFERENCE DATACAPTURE G 25h Table 78 REFERENCE G register Ref7 Ref6 Ref5 Ref4 Ref3 Ref2 Ref1 Ref0 Table 79 REFERENCE G register description Ref 7 Ref0 Reference value for interrupt generation Default value 0 OUT TEMP G 26h Table 80 OUT TEMP G register Temp7 Temp6 Temp5 Temp4 Temp3 Temp2 Temp1 TempO Table 81 OUT TEMP G register description Temp7 TempO Temperature data 1L SB deg 8 bit resolution The value is expressed as two s complement STATUS REG G 27h Table 82 STATUS REG G register ZXOR ZOR XOR ZXDA ZDA XDA Table 83 STATUS REG G description X Z axis data overrun Default value 0 ZXOR 0 no overrun has occurred 1 new data has overwritten the previous one before it was read ZOR Z axis data overrun Default value 0 0 no overrun has occurred 1 a new data for the Z axis has overwritten the previous one XOR X axis data overrun Default value 0 0 no overrun has
23. request 1 enable interrupt request on measured accel value higher than preset threshold XLIE Enable interrupt generation on X low event Default value 0 0 disable interrupt request 1 enable interrupt request on measured accel value lower than preset threshold Configuration register for interrupt source INT1 SRC G 31h Table 91 INT1 SRC G register 0 IA ZH ZL XH XL Doc ID 018845 Rev 1 7 LSM320DL Registers description Table 92 INT1 SRC G description JA Interrupt active Default value 0 0 no interrupt has been generated 1 one or more interrupts have been generated ZH Z high Default value 0 0 no interrupt 1 Z high event has occurred ZL Z low Default value 0 0 no interrupt 1 Z low event has occurred XH X high Default value 0 0 no interrupt 1 X high event has occurred XL X low Default value 0 0 no interrupt 1 X low event has occurred Interrupt source register Read only register Reading at this address clears the INT1 SRC IA bit and eventually the interrupt signal on the INT1 pin and allows the refreshment of data in the INT1_SRC register if the latched option is chosen 7 88 INT1 THS XH G 32h Table 93 INT1 THS XH G register THSX14 THSX13 THSX12 THSX11 THSX10 THSX9 THSX8 Table 94 INT1 THS XH G description THSX14 THSX9 Interrupt
24. 0 2 Vdd IO VOH High level output voltage 0 9 Vdd IO VOL Low level output voltage 0 1 Vdd IO V Top Operating temperature range 40 85 C 1 Typical specifications are not guaranteed 2 Sleep mode introduces a faster turn on time compared to power down mode ky Doc ID 018845 Rev 1 13 53 Module specifications LSM320DL 2 3 Temperature sensor characteristics Vdd 3 0 V T 25 C unless otherwise noted Table 5 Temperature sensor characteristics Symbol Parameter Test condition Min Typ Max Unit Temperature sensor TSDr output change vs 1 C digit temperature TODR Temperature refresh x 1 Hz rate Top Opereling 40 85 C temperature range 1 Typical specifications are not guaranteed b The product is factory calibrated at 3 0 V 14 53 Doc ID 018845 Rev 1 Ly LSM320DL Module specifications 2 4 Communication interface characteristics 2 4 1 SPI serial peripheral interface Subject to general operating conditions for Vdd and Top Table 6 SPI slave timing values Value Symbol Parameter Unit Min Max tc SPC SPI clock cycle 100 ns fc SPC SPI clock frequency 10 MHz tsu CS CS setup time 6 th CS CS hold time 8 tsu Sl SDI input setup time 5 th Sl SDI input hold time 15 ns tv SO SDO valid output time 50 th SO SDO output hold time 9 tdis SO SDO output disable time 50 1 Values are guaran
25. 0 6 T2 0 4 M 0 1 d 0 3 k 0 05 h 0 1 Figure 15 LGA 28L 7 5 x 4 4 x 1 1 package drawing E1 Pin 1 Indicator Di B TOP VIEW Seating Plane Doc ID 018845 Rev 1 51 53 Revision history LSM320DL 9 52 53 Revision history Table 104 Document revision history Date 18 May 2011 Revision 1 Initial release Changes Doc ID 018845 Rev 1 LSM320DL Please Read Carefully Information in this document is provided solely in connection with ST products STMicroelectronics NV and its subsidiaries ST reserve the right to make changes corrections modifications or improvements to this document and the products and services described herein at any time without notice All ST products are sold pursuant to ST s terms and conditions of sale Purchasers are solely responsible for the choice selection and use of the ST products and services described herein and ST assumes no liability whatsoever relating to the choice selection or use of the ST products and services described herein No license express or implied by estoppel or otherwise to any intellectual property rights is granted under this document If any part of this document refers to any third party products or services it s
26. 14 Figure 15 8 53 Block diagram ete e aueh ee awd des as bared PG ae Bek 9 Pin CONNECTION ss ER 10 SPI slave timing diagram 15 I2C slave timing diagram Ee EG Ge Ee ee ee ek ee ee ek ee ke I ke 16 LSM320DL electrical connection 20 Read and write protocol 25 SPI read protocol a EE EE eee 26 Multiple bytes SPI read protocol 2 bytes example 26 SPI write protocol 2 aede e edd REY ae GP RE wer duds 26 Multiple bytes SPI write protocol 2 bytes example 27 SPI read protocol in 3 wire mode 27 INT1 Sel and Out Sel configuration block diagram 43 Wait disabled 22 2500 sieeve eis eea a ER eem x eR dd Rae d rur ba EE oe KORE ni 49 Wait enabled N N N ee EEE r ep 49 LGA 28L 7 5 x 4 4 x 1 1 package drawing 51 Doc ID 018845 Rev 1 1577 LSM320DL Block diagram and pin description 1 1 1 Block diagram and pin description Block diagram
27. 5 Rev 1 17 53 Module specifications LSM320DL 2 6 2 6 1 2 6 2 18 53 Terminology Sensitivity Linear acceleration sensitivity can be determined for example by applying 1 g acceleration to the device As the sensor can measure DC accelerations this can be done easily by pointing the axis of interest towards the center of the Earth noting the output value rotating the sensor by 180 degrees pointing to the sky and noting the output value again By doing so 1 g acceleration is applied to the sensor Subtracting the larger output value from the smaller one and dividing the result by 2 leads to the actual sensitivity of the sensor This value changes very little over temperature and also very little over time The sensitivity tolerance describes the range of sensitivities of a large population of sensors Angular rate sensitivity describes the angular rate gain of the sensor and can be determined by applying a defined angular velocity to it This value changes very little over temperature and also very little over time Zero level Linear acceleration Zero g level offset TyOff describes the deviation of an actual output signal from the ideal output signal if no acceleration is present A sensor in a steady state on a horizontal surface measures 0 gin the X axis and O gin the Y axis whereas the Z axis measures 1 g The output is ideally in the middle of the dynamic range of the sensor content of OUT registers OOh data ex
28. 5 Rev 1 25 53 Digital interfaces LSM320DL 5 2 1 5 2 2 26 53 SPI read Figure 7 SPI read protocol CS SPC SAT UA UAV EV AP AUATOC LT STAT Ee RT SDI XX XXX XOX OI EN XIX MS AD5 AD4 AD3 AD2 AD1 ADO SDO CX XX X X X X2 DO7 DO6 DOS DO4 DO3 DO2 DO1 DOO The SPI Read command is performed with 16 clock pulses Multiple byte read command is performed adding blocks of 8 clock pulses at the previous one bit 0 READ bit The value is 1 bit 1 MS bit When 0 do not increment address when 1 increment address in multiple reading bit 2 7 address AD 5 0 This is the address field of the indexed register bit 8 15 data DO 7 0 read mode This is the data that is read from the device MSb first bit 16 data DO 8 Further data in multiple byte reading Figure 8 Multiple bytes SPI read protocol 2 bytes example CS spe VVVVVVVVVVVVVVVVVVVVVVVV so AOOOOOEDDODOOOOELOOOOOOE MS AD5 AD4 AD3 AD2 AD1 ADO soo XO XO OU X OO OX X DO7 DO6 DO5 DO4 DOS DO2 DO1 DOO DO1H01H01H01H01 D01009 Dos SPI write Figure 9 SPI write protocol CS y SPC VVVVVVVVVVVVVVVV PEE EE EE EE Um EE DI7 DI6 DIS DI4 DIS Dl2 DM DIO MS AD5 AD4 ADS AD2 AD1 ADO The SPI write command is performed with 16 clock pulses Multiple byte write command is performed adding
29. 6 011 0110 00000000 INT2 DURATION A 001100xb rw 37 011 0111 00000000 CLICK CFG A 001100xb rw 38 011 1000 00000000 CLICK SRC A 001100xb rw 39 011 1001 00000000 CLICK THS A 001100xb rw 3A 011 1010 00000000 TIME LIMIT A 001100xb rw 3B 011 1011 00000000 28 53 Doc ID 018845 Rev 1 ky LSM320DL Register mapping Table 18 Register address map continued Name Prien Type dicia is Default Comment Hex Binary TIME LATENCY A 001100xb rw 3C 011 1100 00000000 TIME WINDOW A 001100xb rw 3D 011 1101 00000000 Reserved do not modify 001100xb 3E 3F Reserved Reserved 110100xb 00 1E Reserved CTRL REG1 G 110100xb rw 20 010 0000 00000111 CTRL REG2 G 110100xb rw 21 010 0001 00000000 CTRL REGS G 110100xb rw 22 010 0010 00000000 CTRL REG4 G 110100xb rw 23 010 0011 00000000 CTRL REG5 G 110100xb rw 24 010 0100 00000000 REFERENCE G 110100xb rw 25 010 0101 00000000 OUT TEMP G 110100xb r 26 010 0110 output STATUS REG G 110100xb r 27 010 0111 output OUT XL G 110100xb r 28 010 1000 output OUT XH G 110100xb r 29 010 1001 output Reserved 110100xb r 2A Reserved Reserved 110100xb r 2B Reserved OUT ZLG 110100xb r 2C 010 1100 output OUT Z HG 110100xb r 2D 010 1101 output FIFO CTRL REG G 110100xb rw 2E 010 1110 00000000 FIFO SRC REG G 110100xb r 2F 010 1111 output INT1 CFG G 110100xb rw 30 011 0000 00000000 INT1 SRC G 110100xb r 31 011 0001
30. High pass filter cut off frequency configuration Hz 41 CTRL REG1 G register aaan 41 CTRL REG3 G description eres 41 CTRL REG4 G register 42 CTRL REG4 G description 42 CTRL REGS G register 42 CTRL REGS G description 42 Out Sel configuration setting 43 INT SEL configuration setting 43 REFERENCE G register 44 REFERENCE G register description 44 OUT TEMP G register 44 OUT TEMP G register description 44 STATUS REG G register 44 STATUS REG G description 44 REFERENCE G register 45 REFERENCE G register description 45 FIFO mode configuration 45 FIFO SRC G register 45 FIFO SRC G register description 46 INT1 CFG G register
31. ICK CLICK detection enable Sign CLICK CLICK Sign 0 positive detection 1 negative detection Z Z CLICK CLICK detection Default value 0 0 no interrupt 1 Z high event has occurred Y Y CLICK CLICK detection Default value 0 0 no interrupt 1 Y high event has occurred X X CLICK CLICK detection Default value 0 0 no interrupt 1 X high event has occurred CLICK_THS_A 3Ah Table 54 CLICK THS A register Ths6 Ths5 Ths4 Ths3 Ths2 Ths1 ThsO Table 55 CLICK SRC A description Ths6 ThsO CLICK CLICK threshold Default value 000 0000 TIME LIMIT A 3Bh Table 56 TIME LIMIT A register TLI6 TLI5 TLI4 TLIS TLI2 TLI TLIO Table 57 TIME LIMIT A description TLI7 TLIO CLICK CLICK time limit Default value 000 0000 TIME LATENCY A 3Ch Table 58 TIME LATENCY A register TLA7 TLA6 TLA5 TLA4 TLA3 TLA2 TLA1 TLAO Doc ID 018845 Rev 1 LSM320DL Registers description Table 59 TIME LATENCY A description TLAZ TLAO CLICK CLICK time latency Default value 000 0000 7 23 TIME WINDOW A 3Dh Table 60 TIME WINDOW A register TW7 TW6 TW5 TW4 TW3 TW2 TW1 TWO Table 61 TIME WINDOW A description TW7 TWO CLICK CLICK time window 7 24 CTRL REG1 G 20h Table 62 CTRL REG1 G register DR1 DRO BW1 BWO PD Zen o 1 Xen 1 This bit must be set to 0
32. a DER ES etre 41 7 27 CIAL need GOS sobere ene iocos p rec de 42 7 28 CTRL REG5 GOAN atico tede rere oc ene etl le een 42 7 29 REFERENCE DATACAPTURE G 25h 44 7 30 QUT TEMP 26h ouem EAST REEKS EES RO X SEU ERE ae 44 7 31 STATUS REG OG 27h isse Rhea Rm Rm RE UR DS ER RE 44 7 92 OUT X L G 28h OUT X G 20H 4r x REAKSIE ER 45 ky Doc ID 018845 Rev 1 3 53 Contents LSM320DL 733 OUTZ L G 2Ch OUT_Z_H_G 2Dh 45 7 34 FIFO_CTAL BEG GER 2444 erra dnd view NG Ge GE ER ees 45 7 35 FIFO SRC HEG 6 2Fh acsi y EER N EG EE eN SR ee Ed 45 7 36 INT1_CFG_G 30h ten naa e ED AG EE ee DEE DE roc 46 7 87 INT SS CAC EE OR N OE ONE OE 46 38 INTi THE XAG 32h 4 La Gana tap Exe Ru Ex RE RE EE PR REG 47 7 39 INT1_THS_XL_G 38h vce ANG nG a eh Ice teen eec EER 47 740 INT1 THS ZH G 36h 47 741 INT1 THS ZL G 37h sssssssss en 48 7 42 INT1 DURATION G 38h 48 8 Package information naaa NG NANGGAD AKA ET GA WAGE ceed wae 50 9 Revision history cpa asa nm n IRR N MERE DERE RE Re eee 52 4 53 Doc ID 018845 Rev 1 ky LSM320DL List of tables List of tables Table 1 Devic SUMMA cerci resan PG DAANAN a ed es eae eee a cedar dtes 1 Table 2 Pin descipol AA E 10 Table 3 Mechanical characteristics 12 Table 4 Electrical characteristics
33. blocks of 8 clock pulses at the previous one Doc ID 018845 Rev 1 OT LSM320DL Digital interfaces 5 2 3 bit 0 WRITE bit The value is 0 bit 1 MS bit When 0 do not increment address when 1 increment address in multiple writing bit 2 7 address AD 5 0 This is the address field of the indexed register bit 8 15 data DI 7 0 write mode This is the data that is written inside the device MSb first bit 16 data DI 8 Further data in multiple byte writing Figure 10 Multiple bytes SPI write protocol 2 bytes example CS spe MEEGEDEEL GEREG WO DEP Pe so X fj X X J X X X X XX X a X d OI x xA DI7 DI6 DIS DI4 DIS DI2 DI1 DIO DI15DI14DI113DI12DI11DI10DI9 Dis RW MS AD5 AD4 AD3 AD2 AD1 ADO SPI read in 3 wire mode 3 wire mode is entered by setting to 1 bit SIM SPI serial interface mode selection in CTRL REG4 Figure 11 SPI read protocol in 3 wire mode UB N Loc SPC ub X Wu uM uus SDI O XX XX XXX KX EE EE XX RW DO7 DO6 DOS DO4 DO3 DO2 DO1 DOO MS AD5 AD4 AD3 AD2 AD1 ADO The SPI read command is performed with 16 clock pulses bit 0 READ bit The value is 1 bit 1 MS bit When 0 do not increment address when 1 increment address in multiple reading bit 2 7 address AD 5 0 This is the address field of the indexed register bit 8 15 data DO 7 0 read mode This is the data that is read from the device MSb first
34. ccessfully pioneered the a Motion activated functions use of this package for accelerometers Today ST has the widest manufacturing capability and m Intelligent power saving for handheld devices strongest expertise in the world for production of m Vibration monitoring and compensation sensors in a plastic LGA package m Free fall detection m 6D orientation detection Table DEVICE summary m Order codes EE Package Packing Description 9 LSM320DL Tray The LSM320DL is a system in package featuring TEN a 3D digital accelerometer and a 2D digital LSM320DLTR as Tape gyroscope pee The ST modules family uses a robust and mature manufacturing process already used for the production of micromachined accelerometers May 2011 Doc ID 018845 Rev 1 1 53 This is preliminary information on a new product now in development or undergoing evaluation Details are subject to change without notice www st com Contents LSM320DL Contents 1 Block diagram and pin description 9 1 1 Block diagram s vce uad eR Een Na Kala ee HR eda Rag NG ese 9 1 2 PIN description sok habe skew RE XR neni atras nan rE DEENA ENEE rE Rv EA 10 2 Module specifications 12 2 1 Mechanical characteristics 12 2 2 Electrical characteristics 13 2 3 Temperature sensor characteristics 14 2 4 Co
35. cription 37 CLICK_CFG_A register 37 CLICK_CFG_A description 37 CLICK SRC A register 37 CLICK SRC A description 38 CLICK_THS_A register 38 CLICK SRC A description 38 TIME LIMIT A register se is ee cece ete sk I mh 38 TIME LIMIT A description 38 TIME LATENCY A register 38 TIME LATENCY A description 39 TIME WINDOW A register 39 TIME WINDOW A description 39 CTRL REG1 G register 39 CTRL REG1 G description 39 DR and BW configuration setting aaan aaa anaana aaa 40 Power mode selection configuration 40 CTRL REG2 G register 40 CTRL REG2 Gdescription 41 High pass filter mode configuration 41
36. erved connect to GND 24 Res Reserved connect to GND 25 GND 0 V power supply 26 VCONT PLL filter connection 27 Res Reserved connect to GND 28 VddlO A Accelerometer power supply for IO pins a Doc ID 018845 Rev 1 11 53 Module specifications LSM320DL 2 Module specifications 2 1 Mechanical characteristics Vdd 3V T 25 C unless otherwise noted Table 3 Mechanical characteristics Symbol Parameter Test conditions Min Typ Max Unit FS bit set to 00 2 0 Li lerati FS bit set to 01 4 0 LA FS inear acceleration T g measurement range FS bit set to 10 18 0 FS bit set to 11 16 0 FS bit set to 00 250 Angul t Gps ERU COR a FS bit set to 01 500 dps measurement range FS bit set to 10 2000 FS bit set to 00 1 i i FS bit set to 01 2 LA So Linear acceleration mgldigit sensitivity FS bit set to 10 4 FS bit set to 11 12 FS bit set to 00 8 75 x mdps G So Angular rate sensitivity FS bit set to 01 17 5 digit FS bit set to 10 70 Linear acceleration LA So sensitivity change vs FS bit set to 00 0 05 el C temperature G So Angular rate sensitivity From 40 to 85 C 2 change vs temperature LA Tyort Typical Zong level offset ES pit set to 00 60 mg accuracy G_TyOff Typical zero rate level FS bit set to 00 10 LSb La_TCoft 2819 9 level change vs Max delta from 25 C 0 5 mg C temperature Zero rate level change v
37. hall not be deemed a license grant by ST for the use of such third party products or services or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoever of such third party products or services or any intellectual property contained therein UNLESS OTHERWISE SET FORTH IN ST S TERMS AND CONDITIONS OF SALE ST DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY WITH RESPECT TO THE USE AND OR SALE OF ST PRODUCTS INCLUDING WITHOUT LIMITATION IMPLIED WARRANTIES OF MERCHANTABILITY FITNESS FOR A PARTICULAR PURPOSE AND THEIR EQUIVALENTS UNDER THE LAWS OF ANY JURISDICTION OR INFRINGEMENT OF ANY PATENT COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT UNLESS EXPRESSLY APPROVED IN WRITING BY AN AUTHORIZED ST REPRESENTATIVE ST PRODUCTS ARE NOT RECOMMENDED AUTHORIZED OR WARRANTED FOR USE IN MILITARY AIR CRAFT SPACE LIFE SAVING OR LIFE SUSTAINING APPLICATIONS NOR IN PRODUCTS OR SYSTEMS WHERE FAILURE OR MALFUNCTION MAY RESULT IN PERSONAL INJURY DEATH OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE ST PRODUCTS WHICH ARE NOT SPECIFIED AS AUTOMOTIVE GRADE MAY ONLY BE USED IN AUTOMOTIVE APPLICATIONS AT USER S OWN RISK Resale of ST products with provisions different from the statements and or technical features set forth in this document shall immediately void any warranty granted by ST for the ST product or service described herein and shall not create or extend in any manner whatsoever any liability of ST ST
38. ial data output SDO 2 Res Reserved connect to GND Accelerometer 3 SDO A SPI serial data output SDO I2C least significant bit of the device address SAO Accelerometer 4 SCL A IC serial clock SCL SPI serial port clock SPC 5 DRDY G Gyroscope data ready 6 INT1 A Accelerometer interrupt signal Gyroscope 7 SDO G SPI serial data output SDO I2C least significant bit of the device address SAO 8 INT2 A Accelerometer interrupt signal Gyroscope IC serial data SDA 9 SDA SDI_G E SPI serial data input SDI 3 wire interface serial data output SDO Doc ID 018845 Rev 1 a LSM320DL Block diagram and pin description Table 2 Pin description continued Pin Name Function Gyroscope 10 cs G SPI enable I2C SPI mode selection 1 SPI idle mode IC communication enabled 0 SPI communication mode IC disabled 11 Res Reserved connect to GND 12 VddlO G Gyroscope power supply for IO pins Gyroscope 13 SCL G IC serial clock SCL SPI serial port clock SPC 14 Res Reserved connect to GND 15 Vdd Power supply 16 Res Reserved connect to GND Accelerometer SPI enable mi E I2C SPI mode selection 1 SPI idle mode IC communication enabled 0 SPI communication mode I C disabled 18 Res Reserved connect to GND 19 Res Reserved connect to GND 20 Res Reserved connect to GND 21 INT G Gyroscope interrupt signal 22 Vdd Power supply 23 Res Res
39. inside the LSM320DL may be accessed through both the I2C and SPI serial interfaces The latter may be SW configured to operate either in 3 wire or 4 wire interface mode To select exploit the I2C interface CS line must be tied high i e connected to Vdd IO Table 10 Serial interface pin description Pin name Pin description CS Linear acceleration SPI enable 7 Linear acceleration I C SPI mode selection 1 C mode 0 SPI enabled cs G Angular Rate SPI enable T Angular Rate I C SPI mode selection 1 I C mode 0 SPI enabled SCL A I2C serial clock SCL SCL G SPI serial port clock SPC 12 ial data SDA SDA SDI_A G seria data S SDA SDI G SPI serial data input SDI 3 wire interface serial data output SDO SDO_A I2C less significant bit of the device address SAO SDO_G SPI serial data output SDO I2C serial interface The LSM320DL IC is a bus slave The IC is employed to write the data into the registers whose content can also be read back The relevant IC terminology is given in the table below Table 11 Serial interface pin description Term Description Transmitter The device which sends data to the bus Receiver The device which receives data from the bus Master The device which initiates a transfer generates clock signals and terminates a transfer Slave The device addressed by the master There are two signals associated with the IC bus the serial clock line SCL and
40. ion 34 Table 40 FIFO_SRC_REG_ A register 35 Table 41 INT1 CFG REG A register 35 Table 42 INT1 CFG REG A description 35 Table 43 Interrupt mode 280 35 Table 44 INT1 SRC A register 36 Table 45 INT1 SRC Adescription 36 Table 46 INT1_THS_A register 36 Table 47 INT1 THS A description 36 Table 48 INT1 DURATION _Aregister 37 ky Doc ID 018845 Rev 1 5 53 List of tables LSM320DL Table 49 Table 50 Table 51 Table 52 Table 53 Table 54 Table 55 Table 56 Table 57 Table 58 Table 59 Table 60 Table 61 Table 62 Table 63 Table 64 Table 65 Table 66 Table 67 Table 68 Table 69 Table 70 Table 71 Table 72 Table 73 Table 74 Table 75 Table 76 Table 77 Table 78 Table 79 Table 80 Table 81 Table 82 Table 83 Table 84 Table 85 Table 86 Table 87 Table 88 Table 89 Table 90 Table 91 Table 92 Table 93 Table 94 Table 95 Table 96 Table 97 Table 98 Table 99 6 53 INT1_DURATION_A des
41. it sub address SUB is transmitted the 7 LSb represent the actual register address while the MSB enables address auto increment If the MSb of the SUB field is 1 the SUB register address is automatically increased to allow multiple data read write Table 12 Transfer when master is writing one byte to slave Master ST SAD W SUB DATA SP Slave SAK SAK SAK Table 13 Transfer when master is writing multiple bytes to slave haw or sw eel Tom Tom Tw Slave SAK SAK SAK Table 14 Transfer when master is receiving reading one byte of data from slave Master ST SAD W SUB SR SAD TR NMAK SP Slave SAK SAK SAK DATA Transfer when master is receiving reading multiple bytes of data from slave me Ee 2e EE EE IE IE Slave SAK DATA DATA DATA Data are transmitted in byte format DATA Each data transfer contains 8 bits The number of bytes transferred per transfer is unlimited Data is transferred with the most significant bit MSb first If a receiver can t receive another complete byte of data until it has performed some other function it can hold the clock line SCL LOW to force the transmitter into a wait Doc ID 018845 Rev 1 23 53 Digital interfaces LSM320DL state Data transfer only continues when the receiver is ready for another byte and releases the data line If a slave receiver doesn t acknowledge the slave
42. ite patterns Command SAD 6 1 SAD 0 SAO R W SAD R W Read 001100 0 1 00110001 31h Write 001100 0 0 00110000 30h Read 001100 1 1 00110011 33h Write 001100 1 0 00110010 32h Angular rate sensor the default factory 7 bit slave address is 110100xb Table 17 Angular rate SAD Read Write patterns Command SAD 6 1 SAD 0 SAO R W SAD R W Read 110100 0 1 11010001 F1h Write 110100 0 0 11010000 FOh Read 110100 1 1 11010011 F3h Write 110100 1 0 11010010 F2h 24 53 Doc ID 018845 Rev 1 ky LSM320DL Digital interfaces 5 2 SPI bus interface The LSM320DL SPI is a bus slave The SPI allows to write and read the registers of the device The serial interface interacts with the outside world with 4 wires CS SPC SDI and SDO SPC SDI SDO are common Figure 6 Read and write protocol cs NN SPC IKATAYATA TAYA TA TATATATA YATA TATAY SDI X XX X C OCOCOCOX X XXX X XX DI7 DI6 DI5 DI4 DI3 DI2 DIT DIO MS AD5 AD4 AD3 AD2 AD1 ADO SDO CX YY XY YY YX DO7 DO6 DOS DO4 DO3 DO2 DO1 DOO CS is the serial port enable and it is controlled by the SPI master It goes low at the start of the transmission and returns to high at the end SPC is the serial port clock and it is controlled by the SPI master It is stopped high when CS is high no transmission SDI and SDO are respectively the serial port data input and out
43. mmunication interface characteristics 15 2 4 1 SPI serial peripheral interface 15 2 4 2 I2C inter IC control interface 16 2 5 Absolute maximum ratings 17 26 Terminology 10 62 este ti ieee er Ged AA 18 2 6 1 SerisitiVily 5 ida Nae as Su Vx Ra UE Ra ROLE Ed adu d daa 18 2 6 2 Zero level seasea siaa naani da eee 18 3 lg mc ain a a a a a aa a a 19 3 1 Factory calibration XX pana chive eee cond EX WEE EE DR EES DEE he Eg 19 4 Application hints uuu ax mn Rn RE MM ER RC RE ROS RR ER RR COR n 20 4 1 External capacitors oue EER IS WR WES NEE DER KATE BE RE OE N RE NR E 20 4 2 Soldering information 21 5 Digital Interfaces eese n i mn RE C RC me is je EE EE 22 5 1 I2C serial interface 22 5 1 1 I2C Op ration iue exa ER Re GE Roe Se ewe De n c ee Gee a 23 5 2 SPI DUS niere 22 Soe REKE RED OE ES Se ed a e MCA RR E 25 5 2 1 SPIGA MMOL 26 5 2 2 AAR ME ase eo t ded a ER EE EE oe dide d 26 5 2 3 SPI read in 3 wire mode 27 6 Register mapping sies ees tas cere cca HR DEE EED ME NE eR N ae 28 2 53 Doc ID 018845 Rev 1 OT LSM320DL Contents 7 Registers description 30 71 CTRL_REG1_A 20h EE agape RES BELA S DEE IRAE ER EE 30 72 CTRL_REG2_A 21h css EET se
44. ning processes while the IC interfaces are realized using a CMOS technology that allows to design a dedicated circuit which is trimmed to better match the sensing element characteristics The LSM320DL may also be configured to generate an inertial wake up and free fall interrupt signal according to a programmed acceleration event along the enabled axes Factory calibration The IC interface is factory calibrated for sensitivity and zero level The trimming values are stored inside the device by a non volatile memory Any time the device is turned on the trimming parameters are downloaded into the registers to be used during the normal operation This allows the user to use the device without further calibration Doc ID 018845 Rev 1 19 53 Application hints LSM320DL 4 4 1 20 53 Application hints Figure 5 LSM320DL electrical connection Reserved pins have to be connected to GND C5 Vdd IO Vdd IO DIRECTION OF o ka DETECTABLE mad 2 B Z ACCELERATIONS GND Ss o 5 o Z 02 By G 3 g N o2 P 9 2 p 9 obs pn 55 8 gt VddlO A LSM320DL DIRECTION OF Res DETECTABLE ci TOP VIEW VCONT ANGULAR RATE GND C2 R2 sou PPA sou sou Q z o D vso sou sou sou C3 amp Vdd T GND C4 Digi
45. pressed as 2 s complement number A deviation from the ideal value in this case is called Zero g offset Offset is to some extent a result of stress to the MEMS sensor and therefore the offset can slightly change after mounting the sensor onto a printed circuit board or exposing it to extensive mechanical stress The offset changes little over temperature see Zero g level change vs temperature The Zero g level tolerance TyOff describes the standard deviation of the range of Zero g levels of a population of sensors Angular rate zero rate level describes the actual output value if there is no angular rate present The zero rate level of precise MEMS sensors is to some extent a result of stress to the sensor and therefore zero rate level can slightly change after mounting the sensor onto a printed circuit board or after exposing it to extensive mechanical stress This value changes very little over temperature and also very little over time Doc ID 018845 Rev 1 ky LSM320DL Functionality 3 3 1 Functionality The LSM320DL is a system in package featuring a 3D digital accelerometer and a 2D digital gyroscope The complete device includes specific sensing elements and two IC interfaces able to measure both the acceleration and angular rate applied to the module and to provide a signal to the external world through an SPI I C serial interface The various sensing elements are manufactured using specialized micromachi
46. put Those lines are driven at the falling edge of SPC and should be captured at the rising edge of SPC Both the read register and write register commands are completed in 16 clock pulses or in multiples of 8 in case of multiple bytes read write Bit duration is the time between two falling edges of SPC The first bit bit O starts at the first falling edge of SPC after the falling edge of CS while the last bit bit 15 bit 23 starts at the last falling edge of SPC just before the rising edge of CS bit 0 RW bit When O the data DI 7 0 is written into the device When 1 the data DO 7 0 from the device is read In the latter case the chip drives SDO at the start of bit 8 bit 1 MS bit When 0 the address remains unchanged in multiple read write commands When 1 the address is auto incremented in multiple read write commands bit 2 7 address AD 5 0 This is the address field of the indexed register bit 8 15 data DI 7 0 write mode This is the data that is written into the device MSb first bit 8 15 data DO 7 0 read mode This is the data that is read from the device MSb first In multiple read write commands further blocks of 8 clock periods are added When the MS bit is 0 the address used to read write data remains the same for every block When the MS bit is 1 the address used to read write data is increased at every block The function and the behavior of SDI and SDO remain unchanged Doc ID 01884
47. rein ce N SEN aes OR WE 31 73 GIRL BEG A ZA esses RAS DE ae ED Roc dr GR DE b vd 31 T4 CTRL_REG4_A 23h izbeseeLereS95v8ad esha PD RE GR Sp Ed 32 75 CURL REGS AMIN Gees EERS BANE BEREG S AE I eate DO DIE 32 Lb GIRL REGS A 25h ska AR ER e Re DEAN EE DRR Gai RR KAY 33 7 7 REFERENCE DATACAPTURE A 26h 33 78 STATUS REGAIN sen ERGER eee ER DERE ER EE eg OSs bes 33 79 OUT XL A 28h OUT X H A 29h seks na EER Rn EE 34 7 10 OUI Y LA 2Ah QUT Y M 2BH ecu SEER REED ES ERE 34 7 11 OUT Z L A 2Ch OUT ZH A 2Dh 34 2 12 FHIFO ETAL BEG AGERY nai in did RA NAK AE Red 34 7 15 FIFO SRC REG NEN ius iier SE ER PRXTER PLE tees nied ae 35 7 44 INT1_CFG_A 30h consistere te eds RP DR EE EE RE eee 35 7 45 INTI SRCNGIN s eaaet tede ed Red ry Eat KABAN Rd 36 7 46 WNT TS AK RETIRO TTD 36 7 17 INTI DURATION A 33h iese ER EX EER ER RR EX AE RE DERE EER 37 TAS CLICK ORG A GERY 222 ABRA RAHE xt anis AANA dr etd 37 7 49 CLICK_SRC_A 39h KY ANA bcp Rr Wat DERDE DREW Rd 37 7 20 CLICK THS A GAN oueteboperpr NG WALA PANGA EDE PERIERE NE E 38 7 21 TIME LIMIT A SB est kas ei cheat E ESAE GS 38 2 02 TIME LATENCY A SChi uasa sued verae d RACE Se e 38 728 TIME WINDOW A 3Dh 2 ti seide xe IURE ae ER ES Wa RE pe ERES 39 7 24 CTRL_REG1_G 20h naaawa ha BANGA ANDENG DO DER we SE Reb pcs 39 7 25 CTRL_REG2_G 21h Os kart A RES Done post dfe dcs od 40 7 26 CTRL_REG3_G 22h fa east aite Ka da
48. ription LSM320DL Table 71 CTRL_REG3_G description continued PP_OD Push pull open drain Default value 0 0 push pull 1 open drain 2 DRDY Date ready on DRDY INT2 Default value O 0 disable 1 enable l2 WTM FIFO watermark interrupt on DRDY INT2 Default value 0 0 disable 1 enable l2 ORun FIFO overrun interrupt on DRDY INT2 Default value 0 0 disable 1 enable l2 Empty FIFO empty interrupt on DRDY INT2 Default value 0 0 disable 1 enable 7 27 CTRL REG4 G 23h Table 72 CTRL REG4 G register BDU BLE FS1 FSO o o SIM 1 This bit must be set to 0 for correct operation Table 73 CTRL REGA G description BDU Block data update Default value 0 reading 0 continuous update 1 output registers not updated until MSB and LSB BLE Big little endian data selection Default value 0 0 data LSB lower address 1 data MSB lower address FS1 FSO Full scale selection Default value 00 00 250 dps 01 500 dps 10 2000 dps 11 2000 dps SIM SPI serial interface mode selection Default value 0 0 4 wire interface 1 3 wire interface 7 28 CTRL REGS G 24h Table 74 CTRL REGS G register BOOT FIFO EN HPen INT1_Sel1 INT1 SelO Out Sel1 Out_Sel0 Table 75 CTRL_REG5_G description BOOT
49. s FS bit set to 00 G_TCOff 0 03 dps C temperature from 40 to 85 C du FS bit set to 00 An Acceleration noise density Normal mode ODR bit set to 220 ug Hz 1001 Rn Rate noise density FS bit set to 00 0 03 s Hz Top Operating temperature range 40 85 C a The product is factory calibrated at 3 V The operational power supply range is from 2 4 V to 3 6 V 12 53 Doc ID 018845 Rev 1 ky LSM320DL Module specifications 1 Typical specifications are not guaranteed 2 Verified by wafer level test and measurement of initial offset and sensitivity 3 Typical Zero g level offset value after MSL3 preconditioning 4 Offset can be eliminated by enabling the built in high pass filter 2 2 Electrical characteristics Vdd 2 3 V T 2 25 C unless otherwise noted Table 4 Electrical characteristics Symbol Parameter Test conditions Min Typ Max Unit Vdd Supply voltage 2 4 3 6 V Vdd IO Power supply for VO 1 71 Vdd 0 1 V imi ODR 50Hz 11 LA Idd LA current consumption in HA normal mode ODR 1Hz 2 LA current consumption in low LA IddLowP ODR 50Hz 6 HA power mode LA IddPdn LA current consumption in T 25C 0 5 HA power down mode G Idd AR current consumption in 6 mA normal mode t Giaasi SPY Lm 1 5 mA in sleep mode G IddPdn AR current consumption in T 25 C 5 HA power down mode VIH Digital high level input voltage 0 8 Vdd IO V VIL Digital low level input voltage
50. t on INT1 Default value O 0 disable 1 enable 7 4 CTRL REG4 A 23h Table 27 CTRL REGA A register o 1 BLE FS1 FSO HR o 1 o SIM 1 This bit must be set to 0 for correct operation Table 28 CTRL REG4 A description BLE Big little endian data selection Default value 0 0 data LSB lower address 1 data MSB Q lower address FS1 FSO Full scale selection default value 00 00 2G 01 4G 10 8G 11 16G HR High resolution output mode default value 0 0 high resolution disable 1 high resolution enable SIM SPI serial interface mode selection Default value 0 0 4 wire interface 1 3 wire interface 7 5 CTRL REG5 A 24h Table 29 CTRL REGS A register BOOT FIFO EN LR INT1 D4D INT1 o o 1 This bit must be set to 0 for correct operation Table 30 CTRL REGS A description BOOT Reboot memory content Default value 0 0 normal mode 1 reboot memory content FIFO EN FIFO enable Default value 0 0 FIFO disable 1 FIFO enable LIR_INT1 Latch interrupt request on INT1_SRC register with INT1_SRC register cleared by reading INT1_SRC itself Default value 0 0 interrupt request not latched 1 interrupt request latched D4D_INT1 4D enable 4D detection is enabled on INT1 when 6D bit on INT1_CFG is set to 1 32 53 Doc ID 018845 Rev 1 ky LSM320DL Registers description 7 6 CTRL REG6 A 25h Table 31 CTRL REG6 A register I2 CLICKen I2 INT1 ot BOOT 12 on H LACTIVE
51. t the selected data rate written into the duration counter register Doc ID 018845 Rev 1 1577 LSM320DL Registers description Figure 13 Wait disabled e Wait bit 0 gt Interrupt disabled as soon as condition is no more valid ex Rate value below threshold Rate t n Threshold Duration pe Ka Wait Disabled t n Interrupt AM07493V1 Figure 14 Wait enabled Wait bit 1 gt Interrupt disabled after duration sample sort of hysteresis dps PO SA AN AG AP ENE 0 ae TX 3 Rate rd Threshold Counter IN H Tab m PT N Ii i _ __ e Duration y ri Value Pod Has dq om t n Interrupt Wait Enabled Duration value is the same used to validate interrupt AM08594V1 ky Doc ID 018845 Rev 1 49 53 Package information LSM320DL 8 Package information In order to meet environmental requirements ST offers these devices in different grades of ECOPACK packages depending on their level of environmental compliance ECOPACK specifications grade definitions and product status are available at www st com ECOPACK is an ST trademark 50 53 Doc ID 018845 Rev 1 1577 LSM320DL Package information Table 103 LGA 28L 7 5 x 4 4 x 1 1 mechanical data mm Dim Min Typ Max Al 1 1 A2 0 855 A3 0 2 D1 4 25 4 4 4 55 E1 7 25 7 5 7 55 N1 0 3 L1 5 4 L2 1 8 P2 1 2 T1
52. tal signal from to signal controller Signals levels are defined by proper selection of Vdd 4 9 INI AM09275V1 Table 9 Part list Component Typical value C1 10 nF C2 470 nF C3 10 pF C4 100 nF C5 100 nF R2 10 kOhm External capacitors The device core is supplied through Vdd line Power supply decoupling capacitors C4 100 nF ceramic C3 10 pF Al should be placed as near as possible to the supply pin of the device common design practice All the voltage and ground supplies must be present at the same time to have proper behavior of the IC refer to Figure 5 The functionality of the device and the measured acceleration angular rate data is selectable and accessible through the SPI I C interface Doc ID 018845 Rev 1 ky LSM320DL Application hints 4 2 The functions the threshold and the timing of the two interrupt pins for each sensor can be completely programmed by the user though the SPI I C interface Soldering information The LGA package is compliant with the ECOPACK RoHS and Green standard It is qualified for soldering heat resistance according to JEDEC J STD 020D Leave Pin 1 Indicator unconnected during soldering Land pattern and soldering recommendations are available at www st com mems Doc ID 018845 Rev 1 21 53 Digital interfaces LSM320DL 5 5 1 22 53 Digital interfaces The registers embedded
53. teed at 10 MHz clock frequency for SPI with both 4 and 3 wires based on characterization results not tested in production Figure 3 SPI slave timing diagram cs 3 3 H tsuics te sec tics I AH tai s SO a z 3 When no communication is on going data on CS SPC SDI and SDO are driven by internal pull up resistors c Measurement points are done at 0 2 Vdd IO and 0 8 Vdd IO for both input and output ports ky Doc ID 018845 Rev 1 15 53 Module specifications LSM320DL 2 4 2 12C inter IC control interface Subject to general operating conditions for Vdd and Top Table 7 12C slave timing values PC standard mode PC fast mode 1 Symbol Parameter Unit Min Max Min Max f scL SCL clock frequency 0 100 0 400 KHz tw SCLL SCL clock low time 4 7 1 3 tw SCLH SCL clock high time 4 0 0 6 d tsu SDA SDA setup time 250 100 ns th SDA SDA data hold time 0 01 3 45 0 0 9 us t sDA tyscLy SDA and SCL rise time 1000 20 0 10 300 tyspa sci SDA and SCL fall time 300 20 0 10 300 is th ST START condition hold time 4 0 6 Wen b p condition 47 0 6 tsu SP STOP condition setup time 4 0 6 ue kes Bus free time between STOP 47 13 j and START condition 1 Data based on standard I C protocol requirement not tested in production 2 Cb total capacitance of one bus line in pF Figure4
54. the serial data line SDA The latter is a bidirectional line used for sending and receiving the data to from the interface Doc ID 018845 Rev 1 ky LSM320DL Digital interfaces 5 1 1 Table 15 I2C operation The transaction on the bus is started through a START ST signal A START condition is defined as a HIGH to LOW transition on the data line while the SCL line is held HIGH After this has been transmitted by the master the bus is considered busy The next byte of data transmitted after the start condition contains the address of the slave in the first 7 bits and the eighth bit tells whether the master is receiving data from the slave or transmitting data to the slave When an address is sent each device in the system compares the first seven bits after a start condition with its address If they match the device considers itself addressed by the master Data transfer with acknowledge is mandatory The transmitter must release the SDA line during the acknowledge pulse The receiver must then pull the data line LOW so that it remains stable low during the HIGH period of the acknowledge clock pulse A receiver which has been addressed is obliged to generate an acknowledge after each byte of data received The I C embedded inside the LSM320DL behaves as a slave device and the following protocol must be adhered to After the start condition ST a slave address is sent once a slave acknowledge SAK has been returned an 8 b
55. this register is loaded at boot Write operation at this address is possible only after system boot Table 43 Interrupt mode AOI 6D Interrupt mode 0 0 OR combination of interrupt events 0 1 6 direction movement recognition 1 0 AND combination of interrupt events 1 1 6 direction position recognition Difference between AOI 6D 01 and AOI 6D 11 Doc ID 018845 Rev 1 35 53 Registers description LSM320DL 7 15 7 16 36 53 AOI 6D 01 is movement recognition An interrupt is generated when orientation moves from unknown zone to known zone The interrupt signal stays for a duration ODR AOI 6D 11 is direction recognition An interrupt is generated when orientation is inside a known zone The interrupt signal stays until orientation is inside the zone INT1_SRC_A 31h Table 44 INT1 SRC A register 0 IA ZH ZL YH YL XH XL Table 45 INT1 SRC A description IA Interrupt active Default value 0 0 no interrupt has been generated 1 one or more interrupts have been generated ZH Z high Default value 0 0 no interrupt 1 Z high event has occurred ZL Z low Default value 0 0 no interrupt 1 Z low event has occurred YH Y high Default value 0 0 no interrupt 1 Y high event has occurred YL Y low Default value 0 0 no interrupt 1 Y low event has occurred XH X high Default value 0 0 no interrupt
56. threshold Default value 0000 0000 7 39 INT1 THS XL G 33h Table 95 INT1 THS XL G register Table 96 INT1 THS XL G description THSX7 THSXO Interrupt threshold Default value 0000 0000 740 INT1 THS ZH G 36h Table 97 INT1 THS ZH G register THSZ14 THSZ13 THSZ12 THSZ11 THSZ10 THSZ9 THSZ8 1577 Doc ID 018845 Rev 1 47 53 Registers description LSM320DL 7 4 7 42 48 53 Table 98 INT1 THS ZH G description THSZ14 THSZ9 Interrupt threshold Default value 0000 0000 INT1 THS ZL G 37h Table 99 INT1 THS ZL G register THSZ7 THSZ6 THSZ5 THSZ4 THSZ3 THSZ2 THSZ1 THSZO Table 100 INT1 THS ZL G description THSZ7 THSZO Interrupt threshold Default value 0000 0000 INT1 DURATION G 38h Table 101 INT1 DURATION G register WAIT D6 D5 D4 D3 D2 D1 DO Table 102 INT1_DURATION_G description WAIT WAIT enable Default value 0 0 disable 1 enable D6 DO Duration value Default value 000 0000 D6 DO bits set the minimum duration of the interrupt event to be recognized Duration steps and maximum values depend on the ODR chosen WAIT bit has the following meaning Wait 0 the interrupt falls immediately if signal crosses the selected threshold Wait 1 if signal crosses the selected threshold the interrupt falls only after the duration has counted a number of samples a
57. upt request on measured accel higher than preset threshold value YD Enable interrupt double CLICK on Y axis Default value 0 0 disable interrupt request 1 enable interrupt request on measured accel higher than preset threshold value YS Enable interrupt single CLICK on Y axis Default value 0 0 disable interrupt request 1 enable interrupt request on measured accel higher than preset threshold value XD Enable interrupt double CLICK on X axis Default value 0 0 disable interrupt request 1 enable interrupt request on measured accel higher than preset threshold value XS Enable interrupt single CLICK on X axis Default value 0 0 disable interrupt request 1 enable interrupt request on measured accel higher than preset threshold value CLICK SRC A 39h Table 52 IA CLICK SRC A register DCLICK SCLICK Sign Z Y X Doc ID 018845 Rev 1 37 53 Registers description LSM320DL 7 20 7 21 7 22 38 53 Table 53 CLICK SRC A description IA Interrupt active Default value 0 0 no interrupt has been generated 1 one or more interrupts have been generated DCLICK Double CLICK CLICK enable Default value 0 0 double CLICK CLICK detection dis able 1 double CLICK CLICK detection enable SCLICK Single CLICK CLICK enable Default value 0 0 single CLICK CLICK detection dis able 1 single CL

ST LSM320DL Linear sensor module 3D accelerometer sensor 2D gyroscope sensor handbook

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