ST LSM303DLM Sensor module: 3-axis accelerometer 3-axis magnetometer handbook
Contents
1. 15 Transfer when master is writingonebytetoslave 16 Transfer when master is writing multiple bytestoslave 16 Transfer when master is receiving reading one byte of data from slave 16 SAD and read write patterns 17 Transfer when master is receiving reading multiple bytes of data from slave 17 SAD and read write patterns 17 Register address map 000 Aaaa 19 CTRL REGI Aregister 21 CTRL_REG1_A description AI 21 Power mode and low power output data rate configurations 21 Normal mode output data rate configurations and low pass cut off frequencies 22 CTRL REG2 Aregister 22 CTRL REG2 A description 22 High pass filter mode configuration 23 High pass filter cut off frequency configuration 23 CTRL REG3 Aregister 23 CTRL REGS3 A description 23 Data signal on INT 1andINT2pad 24 CTRL REG4 Aregister 242. ka A3 hc Akce ja i El Y ud e EE 1 d n io 8192208 B Doc ID 018725 Rev 1 LSM303DLM Revision history 11 Revision history Table 68 Document revision history Date 11 Apr 2011 Revision 1 Initial release Changes Doc ID 018725 Rev 1 37 38 LSM303DLM Please Read Carefully Information in this document is provided solely in connection with ST products STMicroelectronics NV and its subsidiaries ST reserve the right to make changes corrections modifications or improvements to this document and the products and services described herein at any time without notice All ST products are sold pursuant to ST s terms and conditions of sale Purchasers are solely responsible for the choice selection and use of the ST products and services described herein and ST assumes no liability whatsoever relating to the choice selection or use of the ST products and services described herein No license express or implied by estoppel or otherwise to any intellectual property rights is granted under this document If any part of this document refers to any third party products or services it shall not be deemed a license grant by ST for the use of such third party products or services or any intellectual prope
3. GN1 0 Doc ID 018725 Rev 1 33 38 Register description LSM303DLM Table 58 Gain setting Sensor input Gain X Y and Gain Z GN2 GN1 GNO field range Z Output range Gauss LSB Gauss ILSB Gauss 0 0 1 1 3 1100 980 0 1 0 1 9 855 760 0 1 1 2 5 670 600 1 ii B ET p ihe OxF800 0x07FF uin 2048 2047 1 0 1 4 7 400 355 1 1 0 5 6 330 295 1 1 1 8 1 230 205 9 2 3 MR_REG_M 02h Table 59 MR REG o0 o o OM o0 o0 MD1 MDO 1 This bit must be set to 0 for correct working of the device Table 60 MR REG description Mode select bits These bits select the operation mode of this device refer to Table 61 MD1 0 Table 61 Magnetic sensor operating mode MD1 MDO Mode 0 0 Continuous conversion mode 0 1 Single conversion mode 1 0 Sleep mode Device is placed in sleep mode 1 1 Sleep mode Device is placed in sleep mode 9 2 4 OUT X H M 03 OUT X LH M 04h X axis magnetic field data The value is expressed as 2 s complement 9 2 5 OUT Z H M 05 OUT Z L M 06h Z axis magnetic field data The value is expressed as 2 s complement 9 2 6 OUT Y H M 07 OUT Y L M 08h Y axis magnetic field data The value is expressed as 2 s complement 34 38 Doc ID 018725 Rev 1 ky LSM303DLM Register description 9 2 7 9 2 8 9 2 9 SR_REG_M 09h Tab
4. Table 47 Interrupt mode configuration AOI 6D Interrupt mode 0 0 OR combination of interrupt events 0 1 6 direction movement recognition 1 0 AND combination of interrupt events 1 1 6 direction position recognition LK Doc ID 018725 Rev 1 31 38 Register description LSM303DLM 9 1 17 9 1 18 9 1 19 32 38 INT2_SRC_A 35h Table 48 INT2 SRC A register 0 IA ZH ZL YH YL XH XL Table 49 INT2_SRC_A description IA Interrupt active Default value 0 0 no interrupt has been generated 1 one or more interrupts have been generated ZH Z high Default value O 0 no interrupt 1 Z high event has occurred ZL Z low Default value O 0 no interrupt 1 Z low event has occurred YH Y high Default value O 0 no interrupt 1 Y high event has occurred YL Y low Default value O 0 no interrupt 1 Y low event has occurred XH X high Default value O 0 no interrupt 1 X high event has occurred XL X Low Default value O 0 no interrupt 1 X low event has occurred Interrupt 2 source register Read only register Reading at this address clears the INT2 SRC A IA bit and the interrupt signal on the INT 2 pin and allows the refreshing of data in the INT2 SRC A register if the latched option was chosen INT2 THS A 36h Table 50 INT2_THS register 0 THS6 THS5 THS4 THS
5. 0 disable interrupt request 1 enable interrupt request on measured accel value lower than preset threshold YHIE Enable interrupt generation on Y high event Default value O 0 disable interrupt request 1 enable interrupt request on measured accel value higher than preset threshold YLIE Enable interrupt generation on Y low event Default value O 0 disable interrupt request 1 enable interrupt request on measured accel value lower than preset threshold XHIE Enable interrupt generation on X high event Default value O 0 disable interrupt request 1 enable interrupt request on measured accel value higher than preset threshold XLIE Enable interrupt generation on X low event Default value O 0 disable interrupt request 1 enable interrupt request on measured accel value lower than preset threshold Configuration register for Interrupt 1 source Table 38 Interrupt 1 source configurations AOI 6D Interrupt mode 0 0 OR combination of interrupt events 0 1 6 direction movement recognition 1 0 AND combination of interrupt events 1 1 6 direction position recognition INT1 SRC A 31h Table 39 INT1 SRC register 0 IA ZH ZL YH YL XH XL Doc ID 018725 Rev 1 29 38 Register description LSM303DLM 9 1 14 9 1 15 30 38 Table 40 INT1_SRC_A description IA Interrupt active Defa
6. 17 LSM303DLM Sensor module 3 axis accelerometer and 3 axis magnetometer Features Analog supply voltage 2 16 V to 3 6 V Digital supply voltage lOs 1 8 V Power down mode 3 magnetic field channels and 3 acceleration channels W 1 3 to 8 1 gauss magnetic field full scale m 2 g 4 g 8 g dynamically selectable full scale m High performance g sensor m C serial interface m 2 independent programmable interrupt generators for free fall and motion detection m Accelerometer sleep to wakeup function m 6D orientation detection m ECOPACK RoHS and Green compliant Preliminary data e LGA 28L 5x5x1 0 mm The various sensing elements are manufactured by using specialized micromachining processes while the IC interfaces are realized using a CMOS technology that allows the design of a dedicated circuit which is trimmed to better match the sensing element characteristics The LSM303DLM has a linear acceleration full scale of x2 g 4 g x8 gand a magnetic field full scale of x1 3 1 9 x2 5 x4 0 4 7 5 6 8 1 gauss both fully selectable by the user The LSM303DLM includes an I C serial bus interface that supports standard mode 100 kHz Applications and fast mode 400 kHz The system can be configured to generate an interrupt signal by mH Compensated compass inertial wakeup free fall events as well as by the position of the device itself Thre
7. 1 interrupt request latched 12 CFG1 Data signal on INT 2 pad control bits Default value 00 I2 CFGO see Table 26 Latch interrupt request on INT1_SRC register with INT1 SRC register cleared by LIR1 reading INT1 SRC register Default value 0 0 interrupt request not latched 1 interrupt request latched I1 CFG1 Data signal on INT 1 pad control bits Default value 00 11_CFGO see Table 26 Table 26 Data signal on INT 1 and INT 2 pad 11 2 _CFG1 H 2 CFGO INT 1 2 Pad 0 Interrupt 1 2 source 1 Interrupt 1 source OR Interrupt 2 source 0 Data ready 1 Boot running 9 1 4 CTRL REGA A 23h Table 27 CTRL REGA A register BDU BLE FS1 FSO 0 0 o 1 This bit must be set to 0 for correct working of the device Table 28 CTRL_REG4_A description BDU Block data update Default value 0 0 continuos update 1 output registers not updated between MSB and LSB reading BLE Big little endian data selection Default value O 0 data LSB lower address 1 data MSB lower address FS1 FSO Full scale selection Default value 00 00 2 g 01 4 g 11 8 g The BDU bit is used to inhibit output register updates between the reading of the upper and lower register parts In default mode BDU 0 the lower and upper register parts are updated continuously If it is not certain whether to read faster than the output data rate it
8. Default value O BOOT 0 normal mode 1 reboot memory content High pass filter mode selection Default value 00 HPM1 HPM i i 00 normal mode others refer to Table 22 FDS Filtered data selection Default value 0 0 internal filter bypassed 1 data from internal filter sent to output register HPen2 High pass filter enabled for Interrupt 2 source Default value O 0 filter bypassed 1 filter enabled HPent High pass filter enabled for Interrupt 1 source Default value 0 0 filter bypassed 1 filter enabled HPCF1 High pass filter cut off frequency configuration Default value 00 HPCFO 00 HPc 8 01 HPc 16 10 HPc 32 11 HPc 64 The BOOT bit is used to refresh the content of internal registers stored in the Flash memory block At device power up the content of the Flash memory block is transferred to the internal registers related to trimming functions to permit good device behavior If for any 24 38 Doc ID 018725 Rev 1 ky LSM303DLM Register description reason the content of the trimming registers has changed it is sufficient to use this bit to restore the correct values When the BOOT bit is set to 1 the content of the internal Flash is copied to the corresponding internal registers and is used to calibrate the device These values are factory trimmed and are different for every accelerometer They permit good device behavior and normally do not have to be modified At the end of the boot process the BOOT bi
9. Electrical characteristics 9 2 3 Communication interface characteristics 10 2 3 1 Sensor 12C inter IC control interface 10 3 Absolute maximum ratings 11 4 Terminology 4 5 Ciba C e 9 ach HAE as P EG elk SUR PRSE dada ap Ka 12 4 1 Linear acceleration sensitivity 12 4 2 YA yo So NI 3k d n ER SER tiraba 12 213 Sleep to wakeup 12 5 Functionality IA de ce E GR RR ACA ae eee 13 5 1 Factory calibration senex ve rr HER X RR E RET HERR E EE E HENCE REG 13 6 Application hilit6 cc eeu xx une x Eu RR ERE AAA 14 6 1 Erternalcapacitors 14 62 Solderinginformation 15 6 3 High current wiringeffects 15 7 Digital interfaces 16 ry PC serial interface 16 7 1 1 e ostia ehe reris Kona pe at at nrw i hed evade 17 7 1 2 Linear acceleration digital interface 18 7 1 3 Magnetic field digital interface 18 8 Register mapping ooooooocoooco ee eee 20 9 Register description 22 2 38 Doc ID 018725 Rev 1 ky LSM303DLM Contents 9 1 Linear acceleration regist
10. acceleration digital interface For linear acceleration the default factory 7 bit slave address is 001100xb The SDO SAO pad can be used to modify the least significant bit of the device address If the SAO pad is connected to voltage supply the LSB is 1 address 0011001b otherwise if the SAO pad is connected to ground the LSB value is 0 address 0011000b This solution permits connecting and addressing two different accelerometers to the same IPC lines The slave address is completed with a read write bit If the bit is 1 read a repeated START SR condition must be issued after the two sub address bytes if the bit is 0 write the master transmits to the slave with the direction unchanged Table 12 explains how the SAD read write bit pattern is composed listing all the possible configurations Table 12 SAD and read write patterns Command SAD 6 1 SAD 0 SAO R W SAD R W Read 001100 0 1 00110001 31h Write 001100 0 0 00110000 30h Read 001100 1 1 00110011 33h Write 001100 1 0 00110010 32h In order to read multiple bytes it is necessary to assert the most significant bit of the sub address field In other words SUB 7 must be equal to 1 while SUB 6 0 represents the address of the first register to be read In the presented communication format MAK is master acknowledge and NMAK is no master acknowledge Transfer when master is receiving reading multiple bytes
11. ky LSM303DLM List of tables Table 49 Table 50 Table 51 Table 52 Table 53 Table 54 Table 55 Table 56 Table 57 Table 58 Table 59 Table 60 Table 61 Table 62 Table 63 Table 64 Table 65 Table 66 Table 67 Table 68 INT2 SRC Adescription 30 INT2 THSregister 30 INT2 THS description 3 22 22 entat di danii aad dhcp Eds RESTI 30 INT2 DURATION Aregister 31 INT2 DURATION A description 31 CRA REG Mregister 31 CRA REG Mdescription 31 Data rate configurations IA II eee 31 CRA REG register role ue Exch SER ae eas ca Ree dee idea Pees ds 31 Gain SE eis kt aad idu ened ERR dee ae oe OR ete DR B RR ROBUR a Che dhe 32 MR REG susi ieead bns ened aver esurire asina bbed e da 32 MR_REG description 32 Magnetic sensoroperatingmode 32 laca ET 33 SR register description 0 0 00 res 33 RARE GE IMs ore talon ME sue iM Mee EM MIL ees 33 IRB REG M ice fre rasrubessbu aia reads 33 IROAIREGEM mom 33 WHO AM I M iiie rad dust n eredi due ede eae Es 33 Revision history wi IA II m m err 35 Doc ID 018725 Rev 1 5 38 Block diagram
12. set to 00 2 0 LA FS d FS bit set to 01 24 0 g FS bit set to 11 8 0 GN bits set to 001 1 3 GN bits set to 010 1 9 GN bits set to 011 2 5 M FS Magnetic measurement range GN bits set to 100 4 0 gauss GN bits set to 101 4 7 GN bits set to 110 5 6 GN bits set to 111 8 1 FS bit set to 00 1 12 bit representation LA So Linear acceleration sensitivity ig d NM 2 mg digit FS bit setto 11 3 9 12 bit representation GN bits set to 001 X Y 1100 GN bits set to 001 Z 980 GN bits set to 010 X Y 855 GN bits set to 010 Z 760 GN bits set to 011 X Y 670 GN bits set to 011 Z 600 M GN Magnetic gain setting price ee eee ESB GN bits set to 100 Z 400 gauss GN bits set to 101 X Y 400 GN bits set to 101 Z 355 GN bits set to 110 X Y 330 GN bits set to 110 Z 295 GN bits set to 1110 X Y 230 GN bits set to 1112 Z 205 a The product is factory calibrated at 2 5 V The operational power supply range is from 2 16 V to 3 6 V ky Doc ID 018725 Rev 1 9 38 Module specifications LSM303DLM Table 3 Sensor characteristics continued Symbol Parameter Test conditions Min Typ Max Unit LA TCSo Linear acceleration sensitivity FS bit set to 00 40 01 oC change vs temperature Linear acceleration typical LA TyOff Zero g level offset FS bit set to 00 x60 mg accuracy 9 LA TCort Linear acceleration Zero glevel Vay gelta from 25 C 40 5 mg C chan
13. 1 output OUTZLA Table 12 r 2C 010 1100 output OUTZHA Table 12 r 2D 010 1101 output Reserved do not modify Table 12 2E 2F Reserved INT1 CFG A Table 12 rw 30 011 0000 00000000 INT1 SOURCE A Table 12 r 31 011 0001 00000000 INT1 THS A Table 12 rw 32 011 0010 00000000 INT1 DURATION A Table 12 rw 33 011 0011 00000000 INT2 CFG A Table 12 rw 34 011 0100 00000000 INT2 SOURCE A Table 12 r 35 011 0101 00000000 INT2 THS A Table 12 rw 36 011 0110 00000000 INT2 DURATION A Table 12 rw 37 011 0111 00000000 Reserved do not modify Table 12 38 3F Reserved CRA_REG_M Table 14 rw 00 00000000 00010000 CRB_REG_M Table 14 rw 01 00000001 00100000 MR_REG_M Table 14 rw 02 00000010 00000011 ky Doc ID 018725 Rev 1 21 38 Register mapping LSM303DLM Table 15 Register address map continued Name Sous Type sional Default Comment Hex Binary OUT_X_H_M Table 14 r 03 0000001 1 output OUT XLM Table 14 r 04 00000100 output OUT Y HM Table 14 r 07 00000101 output OUTYLM Table 14 r 08 000001 10 output OUTZHM Table 14 r 05 00000111 output OUT_Z LM Table 14 r 06 00001000 output SR REG Mg Table 14 r 09 00001001 00000000 IRA REG M Table 14 r OA 00001010 01001000 IRB REG M Table 14 r OB 00001011 00110100 IRC_REG_M Table 14 r 0C 00001100 00110011 Reserved do not modify Table 14 OD OE Reserved WHO AM I M Table 14 r OF 00001111 00111100 Who am ID Reserved do not modify
14. 3 THS2 THS1 THSO Table 51 INT2 THS description THS6 THSO Interrupt 1 threshold Default value 000 0000 INT2 DURATION A 37h Table 52 INT2 DURATION A register 0 D6 D5 D4 D3 D2 D1 DO Doc ID 018725 Rev 1 ky LSM303DLM Register description 9 2 9 2 1 9 2 2 Table 53 INT2 DURATION A description D6 DO Duration value Default value 000 0000 The D6 DO bits set the minimum duration of the Interrupt 2 event to be recognized Duration time steps and maximum values depend on the ODR chosen Magnetic field sensing register description CRA_REG_M 00h Table 54 CRA_REG_M register o o o DO2 DO1 DOO o o 1 This bit must be set to 0 for correct working of the device Table 55 CRA REG M description DO to DOO Data output rate bits These bits set the rate at which data is written to all three data output registers refer to Table 56 Default value 100 Table 56 Data rate configurations DO2 DO1 DOO Minimum data output rate Hz 0 0 0 0 75 0 0 1 1 5 0 1 0 3 0 0 1 1 75 1 0 0 15 1 0 1 30 1 1 0 75 1 1 1 220 CRB_REG_M 01h Table 57 CRA_REG register GN2 GN1 GNO o o o o o 1 This bit must be set to 0 for correct working of the device CRA REG description Gain configuration bits The gain configuration is common for all channels refer to Table 58
15. CTRL REGA4 A description 24 CTRL REGS A register comuna iaa AA a aa 25 CTRL REGS5 Adescription 25 Sleep to wakeup configuration 25 REFERENCE Aregister 25 REFERENCE A description 25 STATUS REG Aregister 26 STATUS_REG_A description 26 INT1i CFG Aregister 27 INT1_CFG_A description ii AA AAH m m me 27 Interrupt 1 source configurations 27 INT1 SRC register oooocccccco e rrr 28 INT1 SRC Adescription 28 INT1 THS registers needs tied ween a cee x cach ier domare Loads 28 INT1 THS description 28 INT1 DURATION Aregister 28 INT2 DURATION A description 29 INT2_CFG_A register 0 4 ceca eae Rez eee hn ac crm ee 29 INT2_CFG_A description 29 Interrupt mode configuration 2 0 RII III 29 INT2 SRC Aregister 30 Doc ID 018725 Rev 1
16. Internally not connected 6 Vdd Power supply 7 Reserved Connect to Vdd 8 Reserved Leave unconnected 9 Reserved Leave unconnected 10 Reserved Leave unconnected 11 Reserved Leave unconnected 12 SET2 S R capacitor connection C2 13 Reserved Leave unconnected 14 Reserved Leave unconnected 15 C1 Reserved capacitor connection C1 16 SET1 S R capacitor connection C2 17 Reserved Connect to GND 18 DRDY M Magnetic signal interface data ready 19 SDA M Magnetic signal interface 1 C serial data SDA q Doc ID 018725 Rev 1 7 38 Block diagram and pin description LSM303DLM 8 38 Table 2 Pin description continued Pins Name Function 20 SCL M Magnetic signal interface 12C serial clock SCL 21 NC Internally not connected 22 Vdd IO Signal interface power supply for I O pins 23 Reserved Connect to Vdd IO 24 SCL A Linear acceleration signal interface 1 C serial clock SCL 25 SDA A Linear acceleration signal interface 12C serial data SDA 26 INT1 Inertial Interrupt 1 27 INT2 Inertial Interrupt 2 28 Reserved Connect to GND Doc ID 018725 Rev 1 q LSM303DLM Module specifications 2 Module specifications 2 1 Sensor characteristics Vdd 2 5 V T 25 C unless otherwise noted 9 Table 3 Sensor characteristics Symbol Parameter Test conditions Min Typ Max Unit FS bit
17. T ZL M 06h 34 9 2 6 OUTYHM 07 O0UT Y LM 08h 34 9 2 7 SB HEG M O9h clicar aria XE ERI EE RE 34 9 2 8 IR REG M OAh OBh OCh 000 2 IRR 34 9 2 9 WHO AM I M OF sssssss IRR e 34 10 Package information 35 11 Revision history 36 KI Doc ID 018725 Rev 1 3 38 List of tables LSM303DLM List of tables Table 1 Table 2 Table 3 Table 4 Table 5 Table 6 Table 7 Table 8 Table 9 Table 10 Table 11 Table 12 Table 13 Table 14 Table 15 Table 16 Table 17 Table 18 Table 19 Table 20 Table 21 Table 22 Table 23 Table 24 Table 25 Table 26 Table 27 Table 28 Table 29 Table 30 Table 31 Table 32 Table 33 Table 34 Table 35 Table 36 Table 37 Table 38 Table 39 Table 40 Table 41 Table 42 Table 43 Table 44 Table 45 Table 46 Table 47 Table 48 4 38 Device SUMMA cocci n e dea ad ee ee a a a beds 1 PIN DSSCHptON cO 5 Sensor characteristics 7 Electrical characteristics 8 IC slave timing A Reid Pg Ra dde cA ee Ped 9 Absolute makimumratings 10 Serial interface pin description 15 Serial interface pin description
18. Table 14 10 3A Reserved 22 38 Registers marked as reserved must not be changed Writing to these registers may cause permanent damage to the device The content of the registers that are loaded at boot should not be changed They contain the factory calibrated values Their content is automatically restored when the device is powered up Doc ID 018725 Rev 1 q LSM303DLM Register description 9 9 1 Register description The device contains a set of registers which are used to control its behavior and to retrieve acceleration data The register address made up of 7 bits is used to identify them and to write the data through the serial interface Linear acceleration register description CTRL_REG1_A 20h Table 16 CTRL_REG1_A register PM2 PM1 PMO DR1 DRO Zen Yen Xen Table 17 CTRL REG1 A description Power mode selection Default value 000 PM2 PMO 000 power down others refer to Table 18 t lection Default value DR1 DRO Data rate selection Default value 00 00 50 Hz others refer to Table 19 Zh Z axis enable Default value 1 0 Z axis disabled 1 Z axis enabled Yen Y axis enable Default value 1 0 Y axis disabled 1 Y axis enabled Xen X axis enable Default value 1 0 X axis disabled 1 X axis enabled PM bits allow selection between power down and two operating active modes The device is in
19. a read write Table 9 Transfer when master is writing one byte to slave Master ST SAD W SUB DATA SP Slave SAK SAK SAK Table 10 Transfer when master is writing multiple bytes to slave vsej somn ove Dom os Tw Slave SAK SAK SAK Table 11 Transfer when master is receiving reading one byte of data from slave Master ST SAD W SUB SR SAD R NMAK SP Slave SAK SAK SAK DATA Data are transmitted in byte format DATA Each data transfer contains 8 bits The number of bytes transferred per transfer is unlimited Data is transferred with the most significant bit MSb first If a receiver cannot receive another complete byte of data until it has performed some other function it can hold the clock line SCL LOW to force the transmitter into a wait state Data transfer only continues when the receiver is ready for another byte and releases the data line If a slave receiver does not acknowledge the slave address i e it is not able to receive because it is performing a real time function the data line must be left HIGH by the slave The master can then abort the transfer A LOW to HIGH transition on the SDA line while the SCL line is HIGH is defined as a STOP condition Each data transfer must be terminated by the generation of a STOP SP condition Doc ID 018725 Rev 1 ky LSM303DLM Digital interfaces 7 1 2 Table 13 Master Linear
20. ance with the set reset capacitor C2 nominally 0 22 uF in capacitance The device core is supplied through the Vdd line Power supply decoupling capacitors C4 100 nF ceramic C3 10 pF Al should be placed as near as possible to the supply pin of the device common design practice All the voltage and ground supplies must be present at the same time to obtain proper behavior of the IC refer to Figure 4 The functionality of the device and the measured acceleration magnetic field data is selectable and accessible through the IC interface The functions the threshold and the timing of the two interrupt pins INT 1 and INT 2 can be completely programmed by the user through the 12C interface Doc ID 018725 Rev 1 15 38 Application hints LSM303DLM 6 2 6 3 16 38 Soldering information The LGA package is compliant with the ECOPACK RoHS and Green standard It is qualified for soldering heat resistance according to JEDEC J STD 020 Leave pin 1 indicator unconnected during soldering Land pattern and soldering recommendations are available at www st com High current wiring effects High current in the wiring and printed circuit traces can be the cause of errors in magnetic field measurements for compassing Conductor generated magnetic fields add to the Earth s magnetic field creating errors in compass heading computation Keep currents that are higher than 10 mA a few millimeters further away from the sens
21. and pin description LSM303DLM 1 Block diagram and pin description 1 1 Block diagram Figure 1 Block diagram Sensing Block Sensing Interface Nom pna xa Ye CHARGE E 5 AMPLIFIER 5 a 4 4 Ya E SDA A MUX EM SCL A xx Nm SDA_M Z ERES Y SCL M gt as A x INT1 X rm m CHARGE INT2 AMPLIFIER SS Z M ur 24 p MUX __ Zz y x L INTERRUPT GEN REFERENCE AI OFEBET BUILT IN CLOCK IESUS SET RESET CIRCUITS AMO09239V1 JI 6 38 Doc ID 018725 Rev 1 LSM303DLM Block diagram and pin description 1 2 Pin description Figure 2 Pin connection Zz 9 F 34 e PgSSEER DIRECTION OF DETECTABLE MAGNETIC FIELDS NC RES SCL M GND SDA M RES DRDY M LSM303DM SA0 A Bis BOTTOM VIEW ie SET1 VDD DIRECTION OF ci RES DETECTABLE ACCELERATIONS AMO6044v2 Table 2 Pin description Pin Name Function 1 Reserved Connect to GND 2 GND 0 V supply 3 Reserved Connect to GND 4 SAO A Linear acceleration signal C less significant bit of the device address SAO 5 NC
22. atings Maximum value Unit Vdd Supply voltage 0 3 to 4 8 V Vdd IO l O pins supply voltage 0 3 to 4 8 V Vin Input voltage on any control pin SCL SDA 0 3 to Vdd IO 0 3 V 3 000 for 0 5 ms g Apow Acceleration any axis powered Vdd 2 5 V 10 000 for 0 1 ms g 3 000 for 0 5 ms g AUNP Acceleration any axis unpowered 10 000 for 0 1 ms g Top Operating temperature range 40 to 85 C TsrG Storage temperature range 40 to 125 C This is a mechanical shock sensitive device improper handling can cause permanent damage to the part A This is an ESD sensitive device improper handling can cause permanent damage to AL the part Doc ID 018725 Rev 1 LSM303DLM Terminology 4 4 1 4 2 4 3 Terminology Linear acceleration sensitivity Linear acceleration sensitivity describes the gain of the accelerometer sensor and can be determined by applying 1 g acceleration to it As the sensor can measure DC accelerations this can be done easily by pointing the selected axis towards the ground noting the output value rotating the sensor 180 degrees pointing to the sky and noting the output value again By doing so a 1 g acceleration is applied to the sensor Subtracting the larger output value from the smaller one and dividing the result by 2 leads to the actual sensitivity of the sensor This value changes very little over temperature and over time The sensitivity tolerance describes the range of sensitivi
23. ction on the bus is started through a START ST signal A START condition is defined as a HIGH to LOW transition on the data line while the SCL line is held HIGH After this has been transmitted by the master the bus is considered busy The next byte of data transmitted after the start condition contains the address of the slave in the first 7 bits and the 8 bit tells whether the master is receiving data from the slave or transmitting data to the slave When an address is sent each device in the system compares the first seven bits after a start condition with its address If they match the device considers itself addressed by the master Data transfer with acknowledge is mandatory The transmitter must release the SDA line during the acknowledge pulse The receiver must then pull the data line LOW so that it remains stable low during the HIGH period of the acknowledge clock pulse A receiver which has been addressed is obliged to generate an acknowledge after each byte of data received The I C embedded inside the LSM303DLM behaves like a slave device and the following protocol must be adhered to After the start condition ST a slave address is sent Once a slave acknowledge SAK has been returned an 8 bit sub address SUB is transmitted the 7 LSBs represent the actual register address while the MSB enables address auto increment If the MSb of the SUB field is 1 the SUB register address is automatically increased to allow multiple dat
24. ddress 03 Logically the address pointer operation functions as shown below If address pointer 08 then the address pointer 03 Or else if address pointer gt 12 then the address pointer O Or else address pointer address pointer 1 The address pointer value itself cannot be read via the PC bus Any attempt to read an invalid address location returns 0 and any write to an invalid address location or an undefined bit within a valid address location is ignored by this device Doc ID 018725 Rev 1 ky LSM303DLM Register mapping 8 Register mapping Table 15 provides a listing of the 8 bit registers embedded in the device and the related addresses Table 15 Register address map Name bos Type inc Default Comment Hex Binary Reserved do not modify Table 12 00 1F Reserved CTRL_REG1_A Table 12 rw 20 010 0000 000001 11 CTRL REG2 A Table 12 rw 21 010 0001 00000000 CTRL REG3 A Table 12 rw 22 010 0010 00000000 CTRL REG4 A Table 12 rw 23 010 0011 00000000 CTRL REG5 A Table 12 rw 24 010 0100 00000000 HP FILTER RESET A Table 12 r 25 010 0101 Dummy register REFERENCE A Table 12 rw 26 010 0110 00000000 STATUS REG A Table 12 r 27 010 0111 00000000 OUT XLA Table 12 r 28 010 1000 output OUT XHA Table 12 r 29 010 1001 output OUT YLA Table 12 r 2A 010 1010 output OUTYHA Table 12 r 2B 010 101
25. e O 0 a new set of data is not yet available 1 a new set of data is available ZDA Z axis new data available Default value O 0 new data for the Z axis is not yet available 1 new data for the Z axis is available YDA Y axis new data available Default value O 0 new data for the Y axis is not yet available 1 new data for the Y axis is available XDA X axis new data available Default value O 0 new data for the X axis is not yet available 1 new data for the X axis is available 9 1 9 OUT X L A 28h OUT X H A 29h X axis acceleration data The value is expressed as 2 s complement 9 1 10 OUT Y L A 2Ah OUT Y H A 2Bh Y axis acceleration data The value is expressed as 2 s complement 9 1 11 OUT Z L A 2Ch OUT Z H A 2Dh Z axis acceleration data The value is expressed as 2 s complement 9 1 12 INT1 CFG A 30h Table 36 INT1_CFG_A register AOI 6D ZHIE ZLIE YHIE YLIE XHIE XLIE 28 38 Doc ID 018725 Rev 1 ky LSM303DLM Register description 9 1 13 q Table 37 INT1 CFG A description AO AND OR combination of interrupt events Default value O see Table 38 eD 6 direction detection function enable Default value O see Table 36 ZHIE Enable interrupt generation on Z high event Default value O 0 disable interrupt request 1 enable interrupt request on measured accel value higher than preset threshold ZLIE Enable interrupt generation on Z low event Default value O
26. er description 22 9414 COTRL REGI A 20h oueseirosusadancnsa darias errata i cada 22 9 1 2 CTRL_REG2_A 21h aas esee canvas osa Lcda d edd 23 9 1 3 OTHL HEGS A 22h wnmanwnnana 24 14 CTRL_REG4_A 23h ioc xkradeve ku add 25 915 CTRL_REG5_A 24h uta n ce Ra a 26 9 1 6 HP FILTER RESET A 25h 26 9 1 7 REFERENCE A 26h 00 ccc re 26 9 1 8 STATUS REG A 27h 0 000 cece cece eee e eee nee 27 9 1 9 OUT XL A 285 OUT K HA Z2Ih 27 9 1 10 OUT Y LA 2A4h OUT Y HA 2Bh 27 441 OUT Z LA Ch OUT Z HA DR 27 53 12 INT1_CFG_A GON wamamamaman 28 94498 INT SRC A lc 29 9 1 14 JINTi THBS A GOH ias iria isla idad 29 9 1 15 INT1 DURATION A 33h 29 5346 INT2_CFG_A 34h read a REFS 30 9 1 17 INTL SRC A S5h wnmamamamamamaman 3i 9 1 18 INTE THS A S6h orcas ss ia 31 9 1 19 INT2 DURATION A 37h 32 9 2 Magnetic field sensing register description 32 9 2 1 OBA REG MIDOH 2i eR E ERIDLP6RR Ea retarda 32 922 CRB REG M Olh wamanenaanwanu 32 O23 MR_REG_M 02h tes Ee dart iode ei dion mar ERE deri eid 33 924 OUTXH M 03 OUT X LH M O4dh 33 925 OUTZH M 05 OU
27. es and replaces all information previously supplied The ST logo is a registered trademark of STMicroelectronics All other names are the property of their respective owners O 2011 STMicroelectronics All rights reserved STMicroelectronics group of companies Australia Belgium Brazil Canada China Czech Republic Finland France Germany Hong Kong India Israel Italy Japan Malaysia Malta Morocco Philippines Singapore Spain Sweden Switzerland United Kingdom United States of America www st com 38 38 Doc ID 018725 Rev 1 ky
28. ge vs temperature field 0 F M_CAS Magnetic cross axis sensitivity nra n die odis 1 dini H applied 3 gauss gauss M EF Maximum exposed field No permitting effect on 10000 gauss zero reading M_R Magnetic resolution 5 mgauss Sensitivity starts to M DF _ Disturbing field degrade Use S R pulse to 20 gauss restore sensitivity Top Operating temperature range 40 85 C 1 Typical specifications are not guaranteed 2 Verified by wafer level test and measurement of initial offset and sensitivity 3 Typical Zero g level offset value after MSL3 preconditioning 4 Offset can be eliminated by enabling the built in high pass filter 2 2 Electrical characteristics Vdd 2 5 V T 25 C unless otherwise noted Table 4 Electrical characteristics Test 1 Symbol Parameter conditions Min Typ Max Unit Vdd Supply voltage 2 16 3 6 V Vdd IO Module power supply for I O 1 71 1 8 Vdd 0 1 V Idd Current consumption in normal 360 UA mode z IddPdn Current consumption in power 2 UA down mode Top Operating temperature range 40 85 C 1 Typical specifications are not guaranteed 2 Magnetic sensor setting ODR 7 5 Hz Accelerometer sensor ODR 50 Hz 10 38 Doc ID 018725 Rev 1 2 LSM303DLM Module specifications 2 3 Communication interface characteristics 2 3 1 Sensor 1 C inter IC control interface Subject to general operating conditi
29. is recommended to set BDU bit to 1 In this way after the reading of the lower upper register part the content of that output register is not updated until the upper lower part is read also This feature avoids reading LSB and MSB related to different samples 26 38 Doc ID 018725 Rev 1 ky LSM303DLM Register description 9 1 5 9 1 6 9 1 7 CTRL_REG5_A 24h Table 29 CTRL_REG5_A register 0 0 0 0 0 0 TurnOn1 TurnOnO Table 30 CTRL_REG5_A description TurnOn1 TurnOnO Turn on mode selection for sleep to wakeup function Default value 00 TurnOn bits are used for turning on the sleep to wakeup function Table 31 Sleep to wakeup configuration TurnOn1 TurnOnO Sleep to wakeup status 0 0 Sleep to wakeup function is disabled 1 1 Turned on the device is in low power mode ODR is defined in CTRL_REG1_A By setting the TurnOn 1 0 bits to 11 the sleep to wakeup function is enabled When an interrupt event occurs the device goes into normal mode increasing the ODR to the value defined in CTRL_REG1_A Although the device is in normal mode CTRL_REG1_A content is not automatically changed to normal mode configuration HP FILTER RESET A 25h Dummy register Reading at this address instantaneously zeroes the content of the internal high pass filter If the high pass filter is enabled all three axes are instantaneously set to 0 g Th
30. is makes it possible to surmount the settling time of the high pass filter REFERENCE A 26h Table 32 REFERENCE A register Ref7 Ref6 Ref5 Ref4 Ref3 Ref2 Ref1 RefO Table 33 REFERENCE A description Ref7 RefO Reference value for high pass filter Default value OOh This register sets the acceleration value taken as a reference for the high pass filter output When the filter is turned on at least one FDS HPen2 or HPen1 bit is equal to 1 and HPM bits are set to 01 filter out is generated taking this value as a reference Doc ID 018725 Rev 1 27 38 Register description LSM303DLM 9 1 8 STATUS_REG_A 27h Table 34 STATUS REG A register ZYXOR ZOR YOR XOR ZYXDA ZDA YDA XDA Table 35 STATUS REG A description ZYXOR X Y and Z axis data overrun Default value O 0 no overrun has occurred 1 new data has overwritten the previous one Z axis data overrun Default value O ZOR 0 no overrun has occurred 1 new data for the Z axis has overwritten the previous one Y axis data overrun Default value O YOR 0 no overrun has occurred 1 new data for the Y axis has overwritten the previous one X axis data overrun Default value O XOR 0 no overrun has occurred 1 new data for the X axis has overwritten the previous one ZYXDA X Y and Z axis new data available Default valu
31. le 45 INT2 CFG A register AOI 6D ZHIE ZLIE YHIE YLIE XHIE XLIE Table 46 INT2_CFG_A description AND OR combination of interrupt events Default value O AO see Table 47 6 direction detection function enable Default value O 9B see Table 47 Enable interrupt generation on Z high event Default value O ZHIE 0 disable interrupt request 1 enable interrupt request on measured accel value higher than preset threshold Enable interrupt generation on Z low event Default value O ZLIE 0 disable interrupt request 1 enable interrupt request on measured accel value lower than preset threshold Enable interrupt generation on Y high event Default value O YHIE 0 disable interrupt request 1 enable interrupt request on measured accel value higher than preset threshold Enable interrupt generation on Y low event Default value O YLIE 0 disable interrupt request 1 enable interrupt request on measured accel value lower than preset threshold Enable interrupt generation on X high event Default value O XHIE 0 disable interrupt request 1 enable interrupt request on measured accel value higher than preset threshold Enable interrupt generation on X low event Default value O XLIE 0 disable interrupt request 1 enable interrupt request on measured accel value lower than preset threshold Configuration register for Interrupt 2 source
32. le 62 SR register LOCK DRDY Table 63 SR register description LOCK Data output register lock Once a new set of measurements is available this bit is set when the first magnetic field data register has been read DRDY Data ready bit This bit is when a new set of measurements is available IR REG M 0Ah OBh OCh Table 64 IRA REG M 0 1 0 0 0 0 Table 65 IRB REG M 0 0 1 1 0 0 Table 66 RC REG M 0 0 1 1 1 1 WHO AM M 0F Table 67 WHO AMI M 0 0 1 1 0 0 Doc ID 018725 Rev 1 35 38 Package information LSM303DLM 10 36 38 Package information In order to meet environmental requirements ST offers these devices in different grades of ECOPACK packages depending on their level of environmental compliance ECOPACK specifications grade definitions and product status are available at www st com ECOPACK is an ST trademark Figure 5 LGA 28 mechanical data and package dimensions Dimensions mm Outline and Min Typ Max mechanical data A1 1 A2 0 785 A3 0 200 D1 4 850 5 000 5 150 E1 4 850 5 000 5 150 S xx L1 1 650 SN p XQ A L2 3 300 N1 0 550 M 0 040 0 100 0 160 T1 0 260 0 300 0 340 LGA 28 5x5x1 12 0 380 0 400 ipiis Land Grid Array Packages d 0 200 k 0 050 h 0 100 AJ 4 e kB
33. of data from slave SAD W SUB SR SAD R MAK MAK NMAK SP Slave SAK SAK SAK DATA DATA DATA 7 1 3 Magnetic field digital interface For magnetic sensors the default factory 7 bit slave address is 0011110xb The slave address is completed with a read write bit If the bit is 1 read a repeated START SR condition must be issued after the two sub address bytes if the bit is 0 write the master transmits to the slave with the direction unchanged Table 14 explains how the SAD is composed Table 14 SAD and read write patterns Command SAD 6 0 R W SAD R W Read 0011110 1 00111101 3Dh Write 0011110 0 00111100 3Ch Doc ID 018725 Rev 1 19 38 Digital interfaces LSM303DLM 20 38 Magnetic signal interface reading writing The interface uses an address pointer to indicate which register location is to be read from or written to These pointer locations are sent from the master to this slave device and succeed the 7 bit address plus 1 bit read write identifier To minimize communication between the master and magnetic digital interface of LSM303DLM the address pointer updates automatically without master intervention This automatic address pointer update has two additional features First when address 12 or higher is accessed the pointer updates to address 00 and secondly when address 08 is reached the pointer rolls back to a
34. ons for Vdd and top Table 5 BC slave timing values 12C standard mode 12C fast mode Symbol Parameter Unit Min Max Min Max f scL SCL clock frequency 0 100 0 400 KHz twscii SCL clock low time 4 7 1 3 us tw SCLH SCL clock high time 4 0 0 6 tsu SDA SDA setup time 250 100 ns th sDA SDA data hold time 0 01 3 45 0 01 0 9 us t spA t sci SDA and SCL rise time 1000 20 0 10 300 ns t spA sci SDA and SCL fall time 300 20 0 1040 300 thsT START condition hold time 4 0 6 Repeated START condition su SR setup time id 0 5 us tsu sP STOP condition setup time 4 0 6 t E Bus free time between STOP 47 13 w SP SR lang START condition i i 1 Data based on standard 1 C protocol requirement not tested in production 2 Cb total capacitance of one bus line in pF Figure3 12C slave timing diagram P r REPEATED TART SCL b Measurement points are done at 0 2 Vdd IO and 0 8 Vdd_l0O for both ports q Doc ID 018725 Rev 1 11 38 Absolute maximum ratings LSM303DLM 3 12 38 Absolute maximum ratings Stresses above those listed as absolute maximum ratings may cause permanent damage to the device This is a stress rating only and functional operation of the device under these conditions is not implied Exposure to maximum rating conditions for extended periods may affect device reliability Table 6 Absolute maximum ratings Symbol R
35. or IC Doc ID 018725 Rev 1 ky LSM303DLM Digital interfaces 7 Digital interfaces The registers embedded inside the LSM303DLM are accessible through two separate C serial interfaces one for the accelerometer core and the other for the magnetometer core The two interfaces can be connected together on the PCB Table 7 Serial interface pin description Pin name Pin description SCL_A IPC serial clock SCL for accelerometer SDA_A 12C serial data SDA for accelerometer SCL_M 12C serial clock SCL for magnetometer SDA_M 12C serial data SDA for magnetometer 7 1 12C serial interface The LSM303DLM I C is a bus slave The I C is employed to write the data into the registers whose content can also be read back The relevant 12C terminology is given in the table below Table 8 Serial interface pin description Term Description Transmitter The device which sends data to the bus Receiver The device which receives data from the bus Master The device which initiates a transfer generates clock signals and terminates a transfer Slave The device addressed by the master There are two signals associated with the I C bus the serial clock line SCL and the serial data line SDA The latter is a bidirectional line used for sending and receiving the data to from the interface ky Doc ID 018725 Rev 1 17 38 Digital interfaces LSM303DLM 7 1 1 18 38 12C operation The transa
36. power down mode when the PD bits are set to 000 default value after boot Table 18 shows all the possible power mode configurations and respective output data rates Output data in the low power modes are computed with a low pass filter cut off frequency defined by DR1 and DPO bits DR bits in normal mode operation select the data rate at which acceleration samples are produced In low power mode they define the output data resolution Table 19 shows all the possible configurations for the DR1 and DPO bits Table 18 Power mode and low power output data rate configurations PM2 PM1 PMO Power mode selection Output ORA Hz 0 0 0 Power down 0 0 1 Normal mode ODR 0 1 0 Low power 0 5 Doc ID 018725 Rev 1 23 38 Register description LSM303DLM Table 18 Power mode and low power output data rate configurations continued PM2 PM1 PMO Power mode selection Cutpiur aata rate He ODR p 0 1 1 Low power 1 1 0 0 Low power 2 1 0 1 Low power 5 1 1 0 Low power 10 Table 19 Normal mode output data rate configurations and low pass cut off frequencies Output data rate Hz Low pass filter cut off DRI pRO ODR frequency Hz 0 0 50 37 0 1 100 74 1 0 400 292 1 1 1000 780 9 1 2 CTRL REG2 A 21h Table 20 CTRL_REG2_A register BOOT HPM1 HPMO FDS HPen2 HPen1 HPCF1 HPCFO Table 24 CTRL REG2 A description Reboot memory content
37. rty contained therein or considered as a warranty covering the use in any manner whatsoever of such third party products or services or any intellectual property contained therein UNLESS OTHERWISE SET FORTH IN ST S TERMS AND CONDITIONS OF SALE ST DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY WITH RESPECT TO THE USE AND OR SALE OF ST PRODUCTS INCLUDING WITHOUT LIMITATION IMPLIED WARRANTIES OF MERCHANTABILITY FITNESS FOR A PARTICULAR PURPOSE AND THEIR EQUIVALENTS UNDER THE LAWS OF ANY JURISDICTION OR INFRINGEMENT OF ANY PATENT COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT UNLESS EXPRESSLY APPROVED IN WRITING BY AN AUTHORIZED ST REPRESENTATIVE ST PRODUCTS ARE NOT RECOMMENDED AUTHORIZED OR WARRANTED FOR USE IN MILITARY AIR CRAFT SPACE LIFE SAVING OR LIFE SUSTAINING APPLICATIONS NOR IN PRODUCTS OR SYSTEMS WHERE FAILURE OR MALFUNCTION MAY RESULT IN PERSONAL INJURY DEATH OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE ST PRODUCTS WHICH ARE NOT SPECIFIED AS AUTOMOTIVE GRADE MAY ONLY BE USED IN AUTOMOTIVE APPLICATIONS AT USER S OWN RISK Resale of ST products with provisions different from the statements and or technical features set forth in this document shall immediately void any warranty granted by ST for the ST product or service described herein and shall not create or extend in any manner whatsoever any liability of ST ST and the ST logo are trademarks or registered trademarks of ST in various countries Information in this document supersed
38. sholds and timing m Map rotation of interrupt generators are programmable on the W Position detection fly by the end user m Motion activated functions Magnetic and accelerometer parts can be m Free fall detection enabled or put into power down mode separately m intelligent power saving for handheld devices The LSM303DLM is available in a plastic land grid array package LGA and is guaranteed to m Display orientation operate over an extended temperature range from m Gaming and virtual reality input devices 40 to 85 C m Impact recognition and logging i m Table 1 Device summary m Vibration monitoring and compensation Temp ET Part number range Package Packing Description Wis 3 C The LSM303DLM is a system in package LSM303DLM Tray featuring a 3D digital linear acceleration sensor 40 to 85 LGA 28 Tape and and a 3D digital magnetic sensor LSM303DLMTR reel April 2011 Doc ID 018725 Rev 1 1 38 This is preliminary information on a new product now in development or undergoing evaluation Details are subject to change without notice www st com Contents LSM303DLM Contents 1 Block diagram and pin description 5 1 1 Block diagram s a uade een Perd ewe S eda Rag ve edes 5 1 2 Pin description s cvs y bie w kaw ERE Re EFERERREGEWEXREREERRERS 6 2 Module specifications 8 2 1 Sensor characteristics 8 2 2
39. t is again set to 0 Table 22 High pass filter mode configuration HPM1 HPMO High pass filter mode 0 0 Normal mode reset reading HP RESET FILTER 0 1 Reference signal for filtering 1 0 Normal mode reset reading HP RESET FILTER HPCF 1 0 These bits are used to configure the high pass filter cut off frequency fp which is given by _ 1 fs qs in 1 aic 2n The equation can be simplified to the following approximated equation f f gt 6 HPc Table 23 High pass filter cut off frequency configuration HPcoeff2 1 ft Hz ft Hz ft Hz ft Hz Data rate 50 Hz Data rate 100 Hz Data rate 400 Hz Data rate 1000 Hz 00 1 2 8 20 01 0 5 1 4 10 10 0 25 0 5 2 5 11 0 125 0 25 1 2 5 CTRL REG3 A 22h Table 24 CTRL_REG3_A register IHL PP OD LIR2 12 CFG1 I2 CFGO LIR1 M CFG1 1 CFGO Table 25 CTRL REGS3 A description IHL Interrupt active high low Default value 0 0 active high 1 active low PP OD Push pull open drain selection on interrupt pad Default value 0 7 0 push pull 1 open drain Doc ID 018725 Rev 1 25 38 Register description LSM303DLM Table 25 CTRL_REG3_A description continued Latch interrupt request on INT2_SRC register with INT2_SRC register cleared by LIR2 reading INT2_SRC itself Default value 0 0 interrupt request not latched
40. th free fall and wakeup can be used simultaneously on two different accelerometer interrupts Factory calibration The IC interface is factory calibrated for linear acceleration sensitivity LA_So and linear acceleration Zero g level LA_TyOff The trimming values are stored inside the device in non volatile memory When the device is turned on the trimming parameters are downloaded into the registers to be used during normal operation This allows the use of the device without further calibration Doc ID 018725 Rev 1 ky LSM303DLM Application hints 6 6 1 Application hints Figure 4 LSM303DLM electrical connection recommended for 12C fast mode Vdd IO Vdd IO Electrical connection a Rpu J Rpu 10kOhm z Vdd Q gt p C3 10uF x e e X 3 DIRECTIONS OF n a E A 0 oO we El al 0 w gt A al zz z o gu veo e Rpu Rpu 10kOhm E LSM303DLM DRDYM p gt TOP VIEW uy OF ACCELERATIONS 9 VDD Ct 4 74F N n o nn n W Ww W ul E W Lu c c c c a c c l C2 0 22uF id GND AMO9240V1 External capacitors The C1 and C2 external capacitors should have a low SR value ceramic type construction Reservoir capacitor C1 is nominally 4 7 uF in capacit
41. tically wake up as soon as the interrupt event has been detected increasing the output data rate and bandwidth With this feature the system may be efficiently switched from low power mode to full performance depending on user selectable positioning and acceleration events therefore ensuring power saving and flexibility Doc ID 018725 Rev 1 13 38 Functionality LSM303DLM 5 5 1 14 38 Functionality The LSM303DLM is a system in package featuring a 3D digital linear acceleration and 3D digital magnetic field detection sensor The system includes specific sensing elements and an IC interface capable of measuring both the linear acceleration and the magnetic field applied on it and to provide a signal to the external world through an C serial interface with separated digital output The sensing system is manufactured using specialized micromachining processes while the IC interfaces are realized using a CMOS technology that allows the design of a dedicated circuit which is trimmed to better match the sensing element characteristics The LSM303DLM features two data ready signals RDY which indicate when a new set of measured acceleration data and magnetic data are available therefore simplifying data synchronization in the digital system that uses the device The LSM303DLM may also be configured to generate an inertial wakeup and free fall interrupt signal according to a programmed acceleration event along the enabled axes Bo
42. ties of a large number of sensors Zero g level Zero g level Offset LA TyOff describes the deviation of an actual output signal from the ideal output signal if no linear acceleration is present A sensor in steady state on a horizontal surface measures 0 g on both the X and Y axes whereas the Z axis measures 1 g Ideally the output is in the middle of the dynamic range of the sensor content of OUT registers 00h data expressed as 2 s complement number A deviation from the ideal value in this case is called Zero g offset Offset is to some extent a result of stress to the MEMS sensor and therefore the offset can slightly change after mounting the sensor onto a printed circuit board or exposing it to extensive mechanical stress Offset changes little over temperature see Linear acceleration Zero g level change vs temperature LA TCOff in Table 3 The Zero g level tolerance TyOff describes the standard deviation of the range of Zero g levels of a group of sensors Sleep to wakeup The sleep to wakeup function in conjunction with low power mode allows further reduction of system power consumption and the development of new smart applications The LSM303DLM may be set to a low power operating mode characterized by lower data rate refreshing In this way the device even if sleeping continues sensing acceleration and generating interrupt requests When the sleep to wakeup function is activated the LSM303DLM is able to automa
43. ult value 0 0 no interrupt has been generated 1 one or more interrupts have been generated ZH Z high Default value O 0 no interrupt 1 Z high event has occurred ZL Z low Default value O 0 no interrupt 1 Z low event has occurred YH Y high Default value O 0 no interrupt 1 Y high event has occurred YL Y low Default value O 0 no interrupt 1 Y low event has occurred XH X high Default value O 0 no interrupt 1 X high event has occurred XL X low Default value O 0 no interrupt 1 X low event has occurred Interrupt 1 source register Read only register Reading at this address clears the INT1_SRC_A IA bit and the interrupt signal on the INT 1 pin and allows the refreshing of data in the INT1 SRC A register if the latched option was chosen INT1 THS A 32h Table 41 INT1 THS register 0 THS6 THS5 THS4 THS3 THS2 THS1 THSO Table 42 INT1 THS description THS6 THSO Interrupt 1 threshold Default value 000 0000 INT1_DURATION_A 33h Table 43 INT1 DURATION A register 0 D6 D5 D4 D3 D2 D1 DO Table 44 INT2 DURATION A description D6 DO Duration value Default value 000 0000 The D6 DO bits set the minimum duration of the Interrupt 2 event to be recognized Duration steps and maximum values depend on the ODR chosen Doc ID 018725 Rev 1 ky LSM303DLM Register description 9 1 16 INT2 CFG A 34h Tab
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