ST STE2007 96 x 68 Single Chip LCD Controller/Driver handbook
Contents
1. TEST RI TEST CL VLCD VLCD VLCD VLCD LCD SNS VDD CP VDD CP VDD VDD VDD VDD VDD VDD VDDI VDDI VDDI VDDI VDDI VDDI OSC IN IDA IDB BUFF SCLK SDOUT SDIN SDAOUT yss_cp VSS_CP VSS_CP VSS LCD VSS LCD VSS LCD TEST_CR TEST RR 6 62 5 2007 2 Driver Pin Description 2 Driver Pin Description 2 1 CPU Interface Pins Table 2 CPU Interface Logic PIN Signal Type Description Note 5 Reset Input When Low the ICS Chip Select Input communication port is enabled Must be connected to SDOUT 0 Serial Data Output SDAIN at Module Level SDAIN Serial Data Input I C Interface Data Input SCLK Serial Clock Input I C Interface Clock Must be left floating SDA_OUT 0 Bus Data Out when Interface is not is use SA1 2 Slave Address Cannot be left floating SAO Slave Address Cannot be left floating Must be connected to ID C 4 Line SPI Data Command Selector m is in 2 2 Power Supply Pins Table 3 Power Supply Pins PIN Signal Type Description Note VSS Power Analog amp Digital Grounds VSS LCD Power2. SCL o7 7 D7 DeX 54 D2 output Hz i COMMAND REV Figure 11 4 lines SPI Video Data Write Cycle Dic SCL ya MNT L ud 05 02 5 02 o1 7 7 DeX Hz DATA to VIDEO DATA to VIDEO 4 2 1 1 Data Command Transfer break If the Host processor generates an break condition CS Line HIGH before having received Bit DO while transferring a Data byte to the Frame Memory or a Command identifier or a command parameter the not complete received byte is discarded the communication is interrupted and the interface is forced in reset state When CS line becomes low again to start new communication session STE2007 is ready to receive the same byte interrupted re transmitted or a new command identifier Figure 12 4 lines SPI Data Transfer break condition ____ Break p LITE
3. MCU Data Tx Start D NC High 2 E D Y 23X Xo X High 2 D2X D1 A 180255 LCD Driver Data Tx Start MCU Data Tx Start 4 3 4 2 Bus interface is a fully complying I2C bus specification selectable to work in both Fast 400kHz Clock and High Speed Mode 3 4MHz This bus is intended for communication between different ICs It consists of two lines one bi directional for data signals SDA and one for clock signals SCL Both the SDA and SCL lines must be connected to a positive supply voltage via an active or passive pull up The following protocol has been defined 21 62 4 STE2007 22 62 Data transfer may be initiated only when the bus is not busy During data transfer the data line must remain stable whenever the clock line is high Changes in the data line while the clock line is high will be interpreted as a Start or Stop Data Transfer condition see below Accordingly the following bus conditions have been defined BUS not busy Both data and clock lines remain High Start Data Transfer A change in the state of the data line from High to Low while the clock is High define the START condition Stop Data Transfer A Change in the state of the data line from low to High while the clock signal is High defi
4. Table 51 F1 NLA NL3 NL2 NL1 NLO Function N row 0 0 0 0 0 N line inversion disabled default 0 function disabled 1 7 function enabled h 0 0 0 0 1 N line inversion enabled 2 0 0 0 1 0 N line inversion enabled 3 1 1 1 1 1 N line inversion enabled 32 The XOR function defines the polarity 8 23 Number of Lines as the result of the logical XOR between the N Line and the frame Multiplexing Rate setting command polarity Table 52 Number of Lines D C D7 D6 D5 D4 D3 D2 D1 DO Function 0 1 1 0 1 0 M2 M1 Command Identifier Data Field Table 53 Multiplexing Rate M2 M1 0 Function 0 0 0 68 Lines Default 0 0 1 65 Lines 0 1 0 49 Lines 0 1 1 33 Lines 1 0 0 33 Lines Partial Display 1 0 1 25 Lines Partial Display 1 1 0 17 Lines Partial Display 1 1 1 9 Lines Partial Display 54 62 5 2007 9 Chip Mechanical Drawing 9 Chip Mechanical Drawing Table 54 Mechanical Dimensions Parameter Dimensions Wafer Thickness 500 Die Size X x Y 5 92 mm x 1 29 mm Bumps Size on Columns and Segments Side 28um X 89 um X 15 Pad Size on Columns and Segments Side 35um X 96um Bumps Pitch on Columns and Segments Side 45um Bumps Size on Interfaces Side 55um 73um X 15 Pad Size on Interfaces Side 64 um X 82 um Bumps Pitch on Interfaces Side 72um Spacing be
5. Direction G SEG 0 4 6 89 o1 92 Output Area 9 Partial Display COM16 comas COM17 COM19 20 COM44 coma COME 27 28 29 COM30 COM31 coM33 COM33 COM35 COM36 COM37 conos 9 40 COM41 COMAZ cower COM44 COMTO 7 COM48 16 51 COMIS COM12 55 COM59 5 comes come comes comes OM 37 62 5 Display Data DDRAM STE2007 5 4 Command Parameters Default Configuration Table 17 STATUS After Power On After HW Reset After SW Reset Description Driver Status MCU TxData MCU TxData MCU TxData mode mode mode Power Saver Mode Power Saver Power Saver Power Saver Mode Mode Mode DISPLAY MODE All Pixel On All Pixel On All Pixel On INVERSION OFF OFF OFF Display OFF OFF OFF Frame Memory Random No Change No Change Page Address Columns A
6. XEN COMMAND PARAMETER 4 2 1 2 Data Command Transfer pause It is possible while transferring Frame Memory Data Commands or Command Parameters to insert a pause in data transmission ICS Line HIGH after 8 Bits Received When CS is forced high after a whole byte received the received byte is processed Then STE2007 is forced in a wait state ready to restart processing incoming data from the point where the communication has been paused 20 62 5 2007 4 4 2 2 If a new command identifier is transferred after pause condition the previous communication session is definitively closed Four are the possible conditions Command Pause Command Command Pause Parameter Parameter Pause Command Parameter Pause Parameter Figure 13 4 lines SPI Data Transfer Pause D IC oe TYEE 00000000 COMMAND PARAMETER COMMAND PARAMETER 190191 Driver TxData Mode Read Mode Throughout SDA line is possible to read some registers value ID Numbers Status byte temperature SDA output Driver is in High impedance in steady state and during data write Figure 14 4 lines SPI 8Bit Read Cycle DIC SCL SDA Input SDA Output 4 Ics DATA lt Read Command Next Command 1 1 1 1 1 1 1
7. DH TEH eomz 21H 22H 0 25 27H eomas coves 28H 29H 2CH COM48 COMIS 32H 33H 35H 36H COM54 COM10 39H 1 1 1 3CH 3EH 3FH COMI 308 41H ra 55 alumn address 515 5 5 5 5 5 wma Je le fe Direction SEG 4 90 191 2 9 9 Output 51518515 515 S S S 5 S Reverse e Direction JG G G G amp 6 a 95 94 93 92 91 ao 89 6 4 30 62 5 2007 5 Display Data DDRAM Figure 25 49 line Mode COM Output Normal Reverse direction direction Normal direction direction COMA7 2 COMZS 5 COAT Cows COMO COSS comio comae comz comis co
8. 19 4 2 2 Driver TxData Mode Read Mode 21 D XXE vernm 21 431 Communication Protocol 23 4 3 2 Starting the Communication 23 4 3 8 MCU TxData Mode Write Mode 24 434 Driver TxData Mode Read Mode 25 4 4 Reading 26 4 4 1 Ildentification byte 26 Display Data DDRAM 27 5 1 DDRAM Page column address circuit 27 5 2007 4 5 2 Line address 28 5 3 Partal DISPIAY ce 32 5 3 1 33 Line Partial Display Mode 33 5 3 2 25 Line Partial Display Mode 35 5 3 3 17 Line Partial Display Mode 36 5 3 4 9 Line Partial Display 37 5 4 Command Parameters Default Configuration 38 Instruction Setups 39 6 1 Initialization Power Sequence 39 6 2 Display Data Writing Sequence 39 6 3
9. 0 0 1 1 1 1 1 1 1 7 Display start line assress con be used in partial dispaly mode to relocate the partial display window on the screen Display start line Partial Display area with must be smaller or equal to the number of line selected 87 Segment driver direction select This command can reverse the correspondence between the DDRAM column address and the segment driver output Table 25 Segment driver direction select D C D7 D6 D5 D4 D3 D2 D1 DO HEX Setting 0 1 0 1 0 0 0 0 0 AO Normal 0 1 Al Reverse 8 8 driver direction select This command can reverse the correspondence between the DDRAM line address and the common driver output Table 26 Common driver direction select D C D7 D6 D5 D4 D3 D2 D1 DO Setting 0 1 1 0 0 0 7 7 Normal 1 id 2 Reverse Disabled bit y 45 62 8 Commands 5 2007 8 0 Display data write This command writes 8 bit data to the specified DDRAM address Since the column address is automatically incremented by 1 after each write the MCU can continuously write multiple word data Table 27 Display data write D C D7 D6 D5 4 D3 D2 D1 00 1 Write Data 8 10 Data reading from driver Driver TxData mode These commands set SDAOUT to Driver TxData mode and enable to read the identification byte Table 28 ID Byte D C D7 D6 D5 D4 D3 D2 D1 DO HEX Setting 0 1 1 0 1 1 0 1 1 DB Reads ID byte 0 0 0 IDB IDA 0 0
10. 0 0 9 0 Mico Vico R R R R 7 0 0 0 0 Vico 6R 5R 4R 2 2 Fo 9 0 5 0 0 3 Vico R R 1 1 1 1 Fo 9 0 9 0 4 R R R R gt Vss Vss Vss Vss BR 100 BR 101 BR 110 Vico 9 R R 4 7 0 T Mo R R R 3 75 Vico St 2R 18 2 6 0 0 9 0 FT R R all 1 1 6 9 0 5 9 0 FT R R R gt Vss Vss Vss 4 51 62 8 Commands STE2007 8 18 Temperature Compensation Its is possible to select different VLCD temperature compensation Coefficients Table 43 VLCD Temperature Compensation D C D7 D6 D5 D4 D3 D2 D1 Function 0 0 0 1 1 1 0 0 0 38 Command Identifier Thermal 0 Compensation Data Field TC Temperature Compensation Formula VLCD T 1 T C TC TC Temperature Compensation Coefficients T C Temperature VLCD TA LCD Voltage at T4 Temperature Room Temperature Table44 TC TC2 TC1 TCO TC Value 0 0 0 0 PPM 0 0 1 300 PPM 0 1 0 600 PPM 0 1 1 900 PPM 1 0 0 1070 PPM 1 0 1 1200 PPM 1 1 0 1500 PPM 1 1 1 1800 PPM 8 19 Char
11. _ ics gt Ous tcs POus 4 B i tpwhoFF1 20 ms tpwrorr2 gt 20ms gt Ure RES gt 4 trs max 5 5 gt le INTERNAL Ww WLL L RESET Reset State Trs max 5hs gt E Reset State 4 40 62 STE2007 7 Power ON Power OFF timing Sequence Table 18 Instruction Set Code Command Function D C D7 D6 D5 DA D3 D2 D1 DO 0 AE LCD display Displ N OFF 1 1 1 1 1 isplay 0 3 1 AF 0 OFF 1 ON Display normal 0 1 0 1 014 1 0 display reverse 1 A7 10 normal 1 reverse i i 0 A4 1 displa Display all points 0 1 0 1 01011 0 Isp 1 A5 0 normal display 1 all points ON Page address set 0 1 0 1 1 address Sets the DDRAM page address Col dd t 0 1 address upper 3 bit address Sets the DDRAM column address Column address set lower 4 bit address 0 UE ts the DDRAM display start li Display start line 0 0 1 address Sets the display start line address set address Sets the correspondence between Segment driver 0 1 0 4 9191406 0 AO DDRAM column address and 1 A1 SEG driver output 0 Normal 1 reverse Sets the correspondence between Common driver 0 1 1010 the DDRAM line address and the direction select 1 COM dr
12. 10 53 11 52 12 COM13 IL 2 0 COM51 COM50 olololelelelelelolelelelelelo E E E E el 5 al lt lt lt 5 COM51 COM49 COMIS COMAS COMi7 comis 46 COM19 COM20 COM21 22 COM22 40 COMAL COM25 8 Conse 37 26 COM38 COM27 6 COM27 7 5 1 COM28 COM36 M31 9 20H 9 COM32 COM32 21H COM33 lt 22H lt 23H gt 24H gt COM36 coves 25H 7 27 26H a ER 28H 29H COM41 E 2BH 2 T COM44 2 2DH om HE 5 30H 31H 49 328 33H 34H
13. comaa 30H cavaa 21H 22H cues 6 241 caua 25H comas coma 26H cuz 27H 28H 29H 2 comal 2BH comaa cau eer 20H eomas 2EH 30H 32H 33H 34H 35H 36H Yi 38H 39H 3DH 5715 15 5 5 5 9 90 91 gz 9 5 5 G Display start line does access 65th 66th 67th 68th line Display start line does not access 65th 66th 67th 68th line ICONMODE Output lormal Reverse rection direction 29 62 5 Display Data RAM DDRAM STE2007 Figure 24 65 line Mode ICONMODE 1 Page address Output pa b2 01 een D COMO T Cows COMO COMET 02H 55 03H 04H OSH DPA 06H 078 T comse OAH OBH OCH m OFH comas 10H 13 14H 17H Ecos
14. STE2007DIEQ 57 5 2007 96 x 68 Single Chip LCD Controller Driver Features 68 x 96 bits Display Data RAM 33 49 65 and 68 Lines Mode Row by Row Scrolling Interfaces 3 lines Serial Interface read and write read and write 4 Line Serial read and write Partial Display Mode 33 25 17 9 Lines Mode Fully Integrated Oscillator requires no external components CMOS Compatible Inputs Programmable ID Number Programmable Bias Ratio Programmable Columns Organization Fully Integrated Configurable LCD bias voltage generator with Selectable multiplication factor 3x 4X and 5X Effective sensing for High Precision Output Eightselectable temperature compensation coefficients m Designed for chip on glass COG applications November 2005 Low Power Consumption suitable for battery operated systems m interfaces Supply Voltage range from 1 6 to 3 6V m High Voltage Generator Supply Voltage range from 2 4 to 3 6V m Display Supply Voltage range from 3 to 13 2V Tamp 25 C Description The STE2007 is a low power LCD driver capable to drive 96 columns and up to 68 lines designed for monochrome displays The STE2007 includes fully integrated bias voltage generator up to 5x multiplication factor and internal oscillator thus reducing to minimum the number of external components required and the current consumption The STE2007 features the three
15. address set D C D7 D6 D5 D4 D3 D2 D1 DO HEX Setting 0 1 0 1 1 0 0 0 0 0 0 0 0 1 1 0 0 0 1 0 2 2 0 0 1 0 0 0 8 8 5 Column address set This command specifies the column address of the DDRAM The column address is split into two sections the upper 3 bits and lower 4 bits when it is set Each time the DDRAM is accessed the column address automatically increments by 1 imaging it possible for the MCU to continuously access to the display data After the last column address 5FH column address returns to OOH Table 23 Column address set D C D7 D6 D5 D4 D3 D2 D1 DO Setting 0 0 0 0 1 li A6 A5 A4 Upper bit address 0 A3 A2 A1 0 Lower bit address Disabled bit D C 6 5 4 2 1 0 Column address 0 0 0 0 0 0 0 0 00H 0 0 0 0 0 0 0 1 01H 0 0 0 0 0 0 1 0 02H 0 1 0 1 1 1 1 0 5EH 0 1 0 1 1 1 1 1 5FH 44 62 57 5 2007 8 Commands 8 6 Display start line address set This command is used to specify the display start line address of the DDRAM If the display start line address is changed dynamically using this command then screen scrolling page swapping can be performed Table 24 Display start line address set D C D7 D6 D5 D4 D3 D2 D1 DO HEX Setting 0 0 1 0 0 0 0 0 0 40 0 0 1 0 0 0 0 0 1 41 0 0 1 0 0 0 0 1 0 42 2 0 0 1 1 1 1 1 1 0
16. 32 62 Figure 26 33 line Mode ICONMODE 1 Normal 29 26 OMS COM23 21 COMM 17 COMIS COMIG COMIS COMIS 17 COM14 COMIB COMIS COM20 COMIS 12 11 21 22 10 COM23 COM24 COM25 26 comes COMS COME 5 ololelololelolelelelololo elelelelelelelelelelelsle E ES S RSS 99 RS RSS Ken elelelelel EE EEE SSES SEES 29 COMO oa fa od ie OFH 10H 42H 13H 15H 16H 17H 18H 19H 1BH alumn address SEG Output STSTSTSTSTS TS 515 75 5 5 5 5 Normal J J Direction G G a a 6 a G 0 4 5 191 192 9410 575 5 5 5 5 5 5 5 5 5 5 15 5 Reverse JE Direction G a 95 93 22 91 90 59 6
17. When a sequence is terminated another sequence of any type can follow or 2 STOP condition can be sent to close the communication In a single or multiple data bytes sequence every data byte received is stored in the DDRAM at the location specified by the current values of data pointers Data pointers are automatically updated after each single data byte written 4 5 2007 4 INTERFACE 4 3 4 Driver TxData Mode Read Mode If the R W bit is set to logic 1 the chip will output data immediately after the slave address If the D C bit during the last write access is set to a logic 0 the byte read is the status byte Figure 17 Communication Protocol WRITE MODE STE2007 ACK COMMUNICATION 12 START o 4 4 1 A START COND R W SLAVE ADDRESS Co D C STE2007 ACK STE2007 ACK i SINGLE COMMAND 9 o 9 0 ofA COMMAND Byte SEQUENCE Control Byte Command Byte Co D C STE2007 ACK STE2007 ACK STE2007 ACK MULTIPLE COMMAND 9 9 9 0 0 ofa COMMAND Byte JA COMMAND Byte JA SEQUENCE Control Byte First Command Byte Last Command Byte Co D C STE2007 ACK STE2007 ACK SINGLE DATA 1100000 DATA Byte A SEQUENCE Control Byte Data Byte Co D C STE2007 ACK STE2007 ACK STE2007 ACK MULTIPLE DATA SEQUENCE UW Control Byte First Data Byte Last Data Byte COMMUNICATION 12C STOP STOP COND READ MODE STE2007 ACK MASTER ACK Y Y STATUS BYTE READ ST
18. 4 5 2007 3 Display Driver Electrical Characteristics 3 2 DC Characteristics Table 8 DC characteristics Symbol Parameter Test Condition Min Typ Max Unit Power Supply Voltage Operating Voltage 2 4 3 6 V Power Supply Voltage Logic I O supply Voltage 1 6 3 6 Booster Output 13 5 V Booster Sense Input 13 5 V Vicp 10V VDD 2 6V Tamb LCD Supply Voltage Accuracy 25 display Load 2 2 2 ower Saver 3 ji Interfaces quiescent Logic Supply Current Power Saver Mode OFF 6 20 A Interfaces quiescent Write Mode 120 250 Vicp 10V Booster 5X Analog Supply onda 90 180 pA Vop Vbpce Analog Supply Current Refresh Rate 75Hz no display load Tamp 25 C Logic Inputs Logic High level input voltage uos Vppi V Vit Logic Low level input voltage Vss ee Logic High level input current 1 Logic Low level input current 1 Logic Outputs _ 0 8 Logic High level output voltage lour 500uA VDDI 1 6V Vppi V VoL Logic Low level output voltage 500 VDDI 1 6V Vss 0 2Vpg Note 1 Tamp 40 to 85 C unless otherwise specified 4 11 62 3 Display Driver Electrical Characteristics STE2007 3 3 AC Charact
19. 514 35 C67 77 967 5 514 35 C95 105 2227 5 514 35 C68 78 1012 5 514 35 R1 106 2272 5 514 35 69 79 1057 5 514 35 R3 107 2317 5 514 35 80 1102 5 514 35 R5 108 2362 5 514 35 71 81 1147 5 514 35 R7 109 2407 5 514 35 72 82 1192 5 514 35 R9 110 2452 4 514 35 C73 83 1237 5 514 35 R11 111 2497 5 514 35 C74 84 1282 5 514 35 R13 112 2542 5 514 35 ky 57 62 9 Mechanical Drawing STE2007 Table 55 Pad Coordinates continued Table 55 Pad Coordinates continued NAME PAD PAD X um R15 113 2587 5 514 35 TEST4 141 2304 0 517 5 R17 114 2632 5 514 35 VSS AUX 142 1944 0 517 5 R19 115 2831 85 450 0 VSS AUX 143 1872 0 517 5 R21 116 2831 85 405 0 VSS AUX 144 1800 0 517 5 R23 117 2831 85 360 0 VSS AUX 145 1728 0 517 5 R25 118 2831 85 315 0 5 146 1584 0 517 5 R27 119 2831 85 270 0 N CS 147 1512 0 517 5 R29 120 2831 85 225 0 T2 148 1368 0 517 5 R31 121 2831 85 180 0 T1 149 1296 0 517 5 R33 122 2831 85 135 0 TO 150 1224 0 517 5 R35 123 2831 85 90 0 VSS 151 1152 0 517 5 R37 124 2831 85 45 0 VSS 152 1080 0 517 5 R39 125 2831 85 0 0 VSS 153 1008 0 517 5 R41 126 2831 85 45 0 VSS LCD 154 936 0 517 5 R43 127 2831 85 90 0 VSS LCD 155 864 0 517 5 R45 128 2831 85 135 0 VSS LCD 156 792 0 517 5 R47 129 2831 85 18
20. Drivers Analog Ground VSS_CP Power Booster Ground VDDI Power Digital Power VDD Power Analog Supply VDD_CP Power Booster Power Supply VSSAUX Power Auxiliar Vss Output Table 4 High Voltage Pins PIN Signal Type Description Note Vico eus SENSE 2 Booster Sense Input 4 7 62 2 Driver Pin Description STE2007 Table 4 High Voltage Pins continued PIN Signal Type Description Note CUP poe COMS ee LCD Row Driver Output mst Be LCD Column Driver Output esi millet Pe 2 3 Configuration Pins Table 5 Configuration Pin Description PIN Signal Type Config Description Note VSS VSSAUX Internal Oscillator Stopped OSCIN Internal Oscillator Active SEL1 SELO Interface VSS VSSAUX VSS NSSAUX SELO SEL1 VSS VSSAUX VDD1 SPI 4 Lines 8 bit VDD1 VSS VSSAUX Serial 3 Lines 9 bit VDD1 VDD1 Not Used VSS VSSAUX 0 IDA IDA 1 VSS VSSAUX IDB 0 IDB IDB 1 2 4 Test Pins Table 6 Test Pin Description PIN Signal Type Description Note Must Be connected to VSS T2 Test Input Enable Test Mode in Normal Working Mode Must Be connected to VSS T1 Test Input Enable Test Mode in Normal Working Mode Must Be connected to VSS l Test Input in Normal Wo
21. 0 0 Pad Default 8 11 Power Control Set This command sets the power supply function ON OFF Table 29 Power Control Set D C 07 D6 D5 D4 D3 D2 D1 DO HEX Setting 0 0 0 1 0 1 0 0 0 28 0 0 0 1 29 0 0 1 0 2 Booster OFF 0 0 1 1 2B Voltage Regulator OFF 0 1 0 0 2 Voltage Follower OFF 0 1 0 1 2D 0 1 1 0 2E Booster ON 0 1 1 1 2F Voltage regulator ON Voltage follower ON 4 46 62 STE2007 8 Commands 8 12 VLCD set The LCD Voltage VLCD at reference temperature 25 C be set using the Voltage Range VOR Electronic Volume EV and VOP registers content according to the following formula VLCD VOP 7 0 EV 4 0 16 32 VOR 2 0 VLCDyjin with the following values Symbol Value Unit Note B 0 04 V Single Voltage Step VLCDyiN 3 V TA 25 Room Temperature For information VLCD thermal compensation see PAR 8 18 Figure 35 Vout A 13 20V EV 3 0 M VOP 7 0 B V OR SV pe FERRER SERRE FERRER HHH Figure 36 VOR 2 0 EV 4 0 1 p IE DAC Compensation Step 40mV Range 3V 13 20V 8 12 1 VOR Voltage Range Set This command sets a value of the Voltage Range Table 30 VOR Volt
22. 0 517 5 R40 208 2831 85 45 0 VDD 181 1296 0 517 5 R38 209 2831 85 0 0 VDD 182 1368 0 517 5 R36 210 2831 85 45 0 VDD 183 1440 0 517 5 R34 211 2831 85 90 0 VDD 184 1512 0 517 5 R32 212 2831 85 135 0 VDD 185 1584 0 517 5 R30 213 2831 85 180 0 VDD_CP 186 1656 0 517 5 R28 214 2831 85 225 0 VDD_CP 187 1728 0 517 5 R26 215 2831 85 270 0 VLCD_SNS 188 1872 0 517 5 R24 216 2831 85 315 0 VLCD 189 1944 0 517 5 R22 217 2831 85 360 0 VLCD 190 2016 0 517 5 R20 218 2831 85 405 0 VLCD 191 2088 0 517 5 R18 219 2831 85 450 0 VLCD 192 2160 0 517 5 TEST4 193 2304 0 517 5 5 5 194 2376 0 517 5 R66 195 2497 5 514 35 R64 196 2542 5 514 35 ky 59 62 9 STE2007 Figure 38 Alignment marks dimensions Table 56 Alignment marks coordinates MARKS X Y Mark1 2834 55 517 05 Mark2 2834 55 517 05 2834 55 517 05 2834 55 517 05 5 2205 0 517 05 60 62 35 4 5 2007 10 Revision history 10 4 Revision history Date 9 Nov 2005 Revision 1 Initial release Changes 61 62 STE2007 Information furnished is believed to be accurate and reliable However STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its u
23. 62 MCU TxData Mode Write Mode If the R W bit is set to logic 0 the STE2007 is set to be a receiver and the master can send commands or data After the communication has started and slaves have acknowledged the master sends a control byte defined as follows and waits for its acknowledgement CONTROL BYTE Co DG 0 Co bit is the control byte MSB and defines if after this control byte will follow a single byte sequence Co 1 or a multiple bytes sequence Co 0 The D C bit defines whether the following byte if Co 1 or the following stream of bytes if Co 0 are command D C 0 or DDRAM data D C 1 Depending on state of flags Co and D C four writing sequences are possible SINGLE COMMAND BYTE SEQUENCE Co 1 D C 0 a single byte interpreted as a command will follow the control byte SINGLE DATA BYTE SEQUENCE Co 1 D C 1 a single byte interpreted as a data to be written in DDRAM will follow the control byte MULTIPLE COMMAND BYTES SEQUENCE Co 0 D C 0 a stream of bytes will follow the control byte with each single byte interpreted as a command MULTIPLE DATA BYTES SEQUENCE Co 0 D C 1 a stream of bytes will follow the control byte with each byte interpreted as a data byte to be written in DDRAM Every single byte of a sequence must be acknowledged by all addressed units A multiple data sequence is terminated only by sending a STOP condition on the bus
24. Figure 15 transfer and START STOP conditions definition DATA LINE STABLE DATA VALID START CHANGE OF STOP CONDITION DATA ALLOWED DOOIN TAS CONDITION Figure 16 Acknowledgment on the I C bus CLOCK PULSE FOR START ACKNOWLEDGEMENT SCLK FROM MASTER 1 2 8 9 DATA OUTPUT i DATA OUTPUT BY RECEIVER DOOIN1152 Communication Protocol The STE2007 is slave The access to the device is bi directional since data write and status read are allowed Four are the device addresses available for the device All have in common the first 5 bits 01111 The two least significant bit of the slave address are set by connecting the SAO and SA1 inputs to a logic 0 or to a logic 1 Starting the Communication To start the communication between the bus master and the slave LCD driver the master must initiate a START condition Following this the master sends an 8 bit byte on the SDA bus line Most significant bit first This consists of the 7 bit Device Address Code and the 1 bit Read Write Designator R W The R W bit has to be set to logic 1 to logic 0 according to the type of communication read or write All slaves with the corresponding address acknowledge in parallel all the others will ignore the 2 transfer STE2007 SLAVE ADDRESS ADDRESS BYTE 01111 READ or WRITE DESIGNATOR 23 62 4 5 2007 4 3 3 24
25. Pump Multiplication 52 8 20 Refresh 53 B 21 leon Mod 2255 RR DUE 53 8 22 5 5 8 29 Number of Lines 54 Chip Mechanical Drawing 55 61 STE2007 1 Introduction 1 Introduction In this document is specified LCD driver for Black amp White full graphic displays with a resolution of 96x68 96x65 96x49 and 96x33 ColumnsXRows Abbreviations LCD Liquid Crystal Display COG On Glass technology MCU Micro Controller Unit DDRAM Display Data Random Access Memory MSB Most Significant Bit LSB Least Significant Bit T B D To Be Defined Table 1 General Driver Parameters Driver assembly technology Chip On Glass COG Memory Size Columns x Rows 96x68 DDRAM capacity 6528 bits Mux 1 68 1 65 1 49 1 33 Frame frequency Hz 65 70 75 80 4 5 62 1 Introduction STE2007 Figure 1 Chip Mechanical Drawing 454m STE2007 BUMP SIDE 0 0 72hm
26. in DDRAM is displayed as ON dot on display Figure 20 DDRAM vs display on LCD COMO 1 2 COM3 COM4 DDRAM Display on LCD Each pixel can be selected when page address and column address are specified The MCU issues Page address set command to change the page and access to another page In DDRAM page address 8 03 02 01 00 1 0 0 0 only display data 00 01 02 amp D3 are valid The DDRAM column address is specified by Column address set command The specified column address is automatically incremented by 1 when a Display data write command is entered After the last column address 5Fh column address returns to 00h and page address incremented by 1 After the very last address column 5Fh page 8h both column address and page address return to column address 00h page address Oh Figure 21 Column address in normal mode Data LSBit EN Data for page address to 07H 94 95 i MSBit 2H 192 193 194 __ 286 287 288 1382 383 Page address 384 385 78 479 5H 480 482 57 575 6H 576 578 __ 670 671 7H 672 673 674 ___ 766 767 768 __ 862 863 1 00H 01H 02H Column address Data for page address 8H 27 62 5 Display Data DDRAM STE2007 5 2 28 62 Figure 22 Column address in revers
27. short circuited in normal working conditions Figure 8 AC timing characteristics _ Timing _ Timing a SCLK X N i 4 Y MCU TxData Command 1 1 MCU Data direction I Rx l Tx X 7 X Driver TxData X Staus N 2 X gt gt Sat T1 T2 e SCLK zu 190 d wuna X y 1 1 Driver TxData X Driver SDA direction in Timing ICS Timing B T3 T4 SCLK JT Fi UN 2 3 MCU TxData x X Driver SDA direction out in T5 5 le 1 2SCLK 1 2 SCLK 4 18 62 STE2007 4 INTERFACE 4 2 4 2 1 4 Figure 9 Timing chart for start and stop of data reading from driver Self Test command writing Reading of status D C writing SCLK 14 124 84 lof Laf 24 7 24147124 I High Z SET Ci X Driver Dati en ICS L z MCU TxData begins Driver TxData begins MCU TxData begins 4 Line SPI STE2007 4 lines serial interface is a bidirectional link between the display driver and the host processor It consists of four lines SDA Serial Data SCL Serial Clock CS Peripheral enable Active Low Enables and Disables the serial interface Mode selection D C The serial interface is active only if the CS line is low If CS i
28. the communication is interrupted and the interface is forced in reset state When CS line becomes low again to start a new communication session STE2007 is ready to receive the same byte interrupted re transmitted or a new command identifier 57 STE2007 4 INTERFACE Figure 6 3 lines SPI Data Transfer break condition 1 COMMAND PARAMETER COMMAND PARAMETER 1 0204 4 1 1 2 Data Command Transfer pause It is possible while transferring Frame Memory Data Commands or Command Parameters to insert a pause in the data transmission CS Line HIGH after 8 Bits Received When CS is forced high after a whole byte received the received byte is processed Then STE2007 is forced in a wait state ready to restart processing incoming data from the point where the communication has been paused new command identifier is transferred after a pause condition the previous communication session is definitively closed Four are the possible conditions Command Pause Command Command Pause Parameter Parameter Pause Command Parameter Pause Parameter Figure 7 3 lines SPI Data Transfer Pause COMMAND PARAMETER COMMAND PARAMETER 180203 4 1 2 Driver TxData Mode Read Mode The Driver TxData mode is a method to check the electrical interconnection between LCD driver and baseband to identify
29. timing Sequence In Figure 33 is the timing diagram for power on power down sequences Figure 33 Timing for phone s power on sequence when VDD VDDCP Up before VDDI VDDI VDD gt Ous gt 0us Inputs High z 4 1 Outputs ans 42222222222222222 2 O 2 tcs gt Ous tcs POus 14 lt N 5 522 f tpwRoFF1 20 ms tpwRoFF2 20ms tp2 Ous A IRES eo ee 4 irs 5 trs max Sys INTERNAL Reset State Trs max 5 5 gt E Reset State XCS SDAIN XRES can become High simultaneously with tcs gt 0 tpi gt 0 tp2 gt 0 trs max 5000ns Internal Reset Time see AC Characteristics Paragraph tPwRorr1 0ms must be considered when driver is in Power Saver or Booster OFF status tPwRorre 20ms must be considered when driver is in Normal Working Condition VDDI VDD and VDD CP can come up go down in any sequence VDDI can be Up with VDD VDDCP down and viceversa If only one supply rail is up the driver is forced in reset state If VDD is high after VDDI all timing referred to VDDI must be referred to VDD Fig 24 Figure 34 Timing for phone s power on sequence when VDDI Up before VDD lt 0 lt 0 VDD gt 0us gt Ous SDAIN p imz
30. 0 COMO LJ Display start line does not access 65th 66th 67th 68th line Normal E Direction Reverse TE TEITE EIE Direction 6 6 33 62 5 Display Data DDRAM STE2007 Figure 29 Example Partial Display 33 lines amp MUX68 ICONMODE 0 Page address Normal Reverse direction direction COM2 COMS COM64 COM63 COM62 COM61 COMO COM59 58 COM57 COM56 COM55 COM54 5 COM52 Normal Reverse rection direction COMI COM6 OMS 10 IL 2 0 12 COM13 COM14 15 16 COM17 18 19 20 21 COM22 23 OMA COM25 COM26 COM41 COM27 COM COM28 COM COM29 COM COM30 COM37 COM31 OM COM33 COM34 5 6 ele 5 5 COM34 COM33 COM32 COM31 COM30 COM29 28 27 COM26 COM25 COM38 COM41 COM44 5 23 22 21 COM20 9 18 elelelelelal lol Ol EE
31. 0 0 VSS CP 157 720 0 517 5 R49 130 2831 85 225 0 VSS CP 158 648 0 517 5 R51 131 2831 85 270 0 VSS CP 159 576 0 517 5 R53 132 2831 85 315 0 DC 160 432 0 517 5 R55 133 2831 85 360 0 SDAOUT 161 360 0 517 5 R57 134 2831 85 405 0 SDIN 162 288 0 517 5 R59 135 2831 85 450 0 SDOUT 163 216 0 517 5 R61 136 2632 5 514 35 SCLK 164 144 0 517 5 R63 137 2587 5 514 35 VREF BUFF 165 72 0 517 5 R65 138 2542 0 514 35 VSS AUX 166 72 0 517 5 R67 139 2497 5 514 35 SEL1 167 144 0 517 5 TEST3 140 2376 0 517 5 SELO 168 216 0 517 5 58 62 5 2007 9 Chip Mechanical Drawing Table 55 Pad Coordinates continued Table 55 Pad Coordinates continued NAME PAD PAD X um SA1 169 288 0 517 5 R62 197 2587 5 514 35 SAO 170 360 0 517 5 R60 198 2632 5 514 35 IDB 171 432 0 517 5 R58 199 2831 85 450 0 IDA 172 504 0 517 5 R56 200 2831 85 405 0 OSC_IN 173 576 0 517 5 R54 201 2831 85 360 0 VDDI 174 720 0 517 5 R52 202 2831 85 315 0 175 792 0 517 5 50 203 2831 85 270 0 176 864 0 517 5 R48 204 2831 85 225 0 177 936 0 517 5 46 205 2831 85 180 0 178 1008 0 517 5 44 206 2831 85 135 0 179 1080 0 517 5 842 207 2831 85 90 0 180 1224
32. 337 5 514 35 15 25 1552 5 514 35 C43 53 292 5 514 35 16 26 1507 5 514 35 44 54 247 5 514 35 17 27 1462 5 514 35 45 55 202 5 514 35 C18 28 1417 5 514 35 C46 56 157 5 514 35 56 62 ky 5 2007 9 Chip Mechanical Drawing Table 55 Pad Coordinates continued Table 55 Pad Coordinates continued NAME PAD PAD X um 47 57 112 5 514 35 C75 85 1327 5 514 35 C48 58 112 5 514 35 C76 86 1372 5 514 35 49 59 157 5 514 35 77 87 1417 5 514 35 50 60 202 5 514 35 C78 88 1462 5 514 35 C51 61 247 5 514 35 79 89 1507 5 514 35 52 62 292 5 514 35 C80 90 1552 5 514 35 C53 63 337 5 514 35 C81 91 1597 5 514 35 C54 64 382 5 514 35 C82 92 1642 5 514 35 55 65 427 5 514 35 C83 93 1687 5 514 35 C56 66 472 5 514 35 C84 94 1732 5 514 35 57 67 517 5 514 35 85 95 1777 5 514 35 58 68 562 5 514 35 86 96 1822 5 514 35 59 69 607 5 514 35 87 97 1867 5 514 35 60 70 652 5 514 35 88 98 1912 5 514 35 C61 71 697 5 514 35 C89 99 1957 5 514 35 62 72 742 5 514 35 90 100 2002 5 514 35 C63 73 787 5 514 35 C91 101 2047 5 514 35 C64 74 832 5 514 35 C92 102 2092 5 514 35 C65 75 877 5 514 35 C93 103 2137 5 514 35 C66 76 922 5 514 35 C94 104 2182 5
33. 35H 36H COMS4 37H Ccomss 38H e 58 5 3BH 59 5 3CH COM2 cowe2 COMI 6 COMO 3 COMI 41H 42H 5 15 15 5 5 Normal Direction a SEG gl 92 5 5 5 5 5 Reverse Direction 6 a a lt 4 0 35 62 5 Display Data RAM DDRAM STE2007 5 3 3 17 Line Partial Display Mode Partial Display Area is composed of 17 Lines Memory vs Row Drivers Mapping is defined according to the following parameters Multiplexing Value 1 2 0 Figure 31 Partial Display 17 Lines ICONMODE 1 ICONMODE 0 Output Normal Reverse direction direction COMO COMES COMET 59 COM7 COMS6 01H IL 2 0 IL 2 0 elelelelelelele tza fea 0 55 COMTO COMSS 5 16 20 1 53 Column address O2 OSH OSH LSPA SCHISDALSERISE A SEG O
34. 4 0 comes COMES Display start line does not access 65th 66th 67th 68th line Start COM Output ormal Reverse rection direction COMO COMED COMO coMs 27 Coma 20271 COM9 OMS 25 COME COMS COM3 olelelelolalolelelelelelolol celelelelelelelelelelelelele Est Ea ca Ea E Ed Eat nsa Ea 955885 Ic ce eo fo en co olelelelelelolelelelelelelol fe e e Ea E E E Ed Ea SEIS olelolelolo SEE EE Partial Display STE2007 feature four configuration for Partial Display function Partial display Area location on the screen is defined by Image Location Parameter 33 Line Partial Display 25 Line Partial display 16 Line Partial Display 9 Line Partial Display Image Location Partial display area gt Multiplexing rate 5 2007 5 Display Data DDRAM Figure 27 Display Image Location Partial display area width lt Multiplexing rate Image Location Partial display area width gt Multiplexing rate When Partial Display Mode is enabled the user has to Update the Operative Voltage Bias Ratio and Charge Pump Setting to match the new working conditions 5 31 33 Line Partial Display Mode
35. ART 2 START R W SLAVE ADDRESS LROO08d 4 25 62 4 INTERFACE STE2007 4 4 4 4 1 26 62 Reading Mode STE2007 features a reading Command to transmitt data from the LCD driver to Host Processor After the reading command STE2007 transfers 8 bits to the Host controller Identification Byte Command Code Identification byte Identification byte is an 8 Bit code that identify the module revision Number Table 15 ID byte format Bitnr D7 MSB D6 D5 D4 D3 D2 D1 DO LSB 0 0 IDB PAD IDA PAD 0 0 0 0 Figure 18 STE2007 Power IC Command decoder MCU TxData p D gt lt Driver TxData Auto return 8 bit register Voltage booster CD Powe Li r Supply circuit BaseBand side Driver side Figure 19 Identification Information Send rading command DBh Read status ID data Send reset command Command E2H 4 5 2007 5 Display Data DDRAM 5 5 1 4 Display Data DDRAM DDRAM and Page column address circuit The DDRAM stores pixel data for LCD It is 68 8 page by 8 bits 4 by 96 column addressable array D7 to DO display data from MCU corresponds to the LCD common direction 0 bit in DDRAM is a OFF dot on display and 1 bit
36. E ofo Ol E i 48 12 Partial Display Area 33 54 13 55 12 Partial Display Area 32 1 COM58 COMS COM65 _ 228 COM66 COMS COMS Display start line does not access 65th 66th 67th 68th line Normal EIETEIE TE E TETE Direction G G SEG 0 i G 90 91 92 9 9 Output 5 5 5 5 5 5 5 5 5 5 5 5 5 5 Reverse JEIJE IE E E Direction G G G 95 94 93 92 91 90 89 4 0 34 62 5 2007 5 Display Data DDRAM 5 3 2 25 Line Partial Display Mode Partial Display Area is composed of 25 Lines Memory vs Row Drivers Mapping is defined according to the following parameters Multiplexing Value IL 2 0 Figure 30 Example Partial Display 25 lines amp MUX65 ICONMODE 1 ICONMODE 0 COM Output COM Output Normal Reverse direction direction Norr mal Reverse direction direction 5 COMO COM63 CONT COM62 COM2 COM61 COM60 4 59 5 58 COME 57 8 56 55 9 54
37. Item Symbol Condition Rating Units Min Max Data hold time T1 Note 1 100 125 ns Access time T2 10 100 ns Output disable time T3 25 100 5 Data setup time T4 100 ns 5 pulse width high T5 250 5 Note 1 Data Hold Time 1 depends SCLK high time and Max Data Hold time It is Always 3 8ns before SCLK pulse falling edge 2 The input signal rise and fall times must be within 10ns 3 Every timing is specified on the basis of 30 6 and 70 of VDDI 4 Tamp 40 to 85 C unless otherwise specified Table 13 Timings based 1 MHz SCLK Speed Item Symbol Condition Rating Units Min Max Data hold time T1 100 125 ns Access time T2 10 450 5 Output disable time 25 450 ns Data setup time 100 ns 1CS pulse width high T5 250 ns Note 1 The signal rise and fall times must be within 10ns 2 Every timing is specified on the basis of 30 and 70 of VDDI 40 to 85 C unless otherwise specified 4 13 62 3 Display Driver Electrical Characteristics STE2007 Figure 3 Driver TxData Mode AC timing characteristics Timing A_ Timing B ae p X Posez 7 ar TS MCU TxData MCU Data direction x imi I NI 5 57 Timing UN 7 SCLK X J Driver SDA direction in ICS Timing B
38. Partial Display Area is composed of 33 Lines Memory vs Row Drivers Mapping is defined according to the following parameters Multiplexing Value ICONMODE 1 ICONMODE 0 COM Output Tine COM Output Normal Reverse Address Normal Reverse Mem Gram 8 02H cows 6 59 cows 06H Cow7 COMS 07H IL 2 0 COM55 08H cows COMS4 09H OAH COMS OBH COM12 5 MIA MAS COMIS 15 cona oH TH Lt 19H cow27 TBH ACH sun 3FH 2255 coma T 20H com 23H T 5 ES o 27H lt lt 29H gt gt 20H CE 2 a ei 30 32H 33H E E En 36H 37H a COMS0 5
39. Power d DD 39 Power ON Power OFF timing Sequence 40 ee 43 8 1 Display ON OFF 43 8 2 Display normal reverse 43 8 3 Display all points ON OFF 43 8 4 Pagesagdress Sel 25555552 ER SEE 44 85 Column address Set 44 8 6 Display start line address set 45 8 7 Segment driver direction 45 8 8 Common driver direction select 45 8 9 Display Ola WING dee Sega exe ee soe 46 8 10 Data reading from driver Driver 46 8 11 Power Control Set a xa TE eam 46 8 12 VLCD AKER EA Ed RR aes 47 8 12 1 Voltage Range Set 47 8 12 2 VOP vv ge xe Es Pokaan RU Palacio 48 8 12 3 Electronic volume 49 8 13 Power saver mode 49 nc MM PR ET 50 815 NOP MP Tnm 50 8 16 1 50 3 62 STE2007 10 4 62 OAL Blas Ra 51 8 18 Temperature Compensation 52 8 19 Charge
40. T3 T4 Il SCLK MCU TxData f foe Driver TxData xX Driver SDA direction out in T5 ICS 1 2SCLK 1 25 3 4 2 Reset Timing Table 14 Reset Timing Description Signal Symbol Min Max Unit Reset time 5 trs 2500 Reset low pulse width for valid reset IRES trw 2500 ns Reset rejection for noise spike IRES trj 1000 Note 1 The input signal rise and fall times must be within 10ns 2 Every timing is specified on the basis of 3096 and 70 of VDDI 3 40 to 85 C unless otherwise specified 4 14 62 5 2007 3 Display Driver Electrical Characteristics Figure 4 Internal circuit status IRES Ni P 4 15 62 4 INTERFACE STE2007 4 4 1 Figure 5 INTERFACE 3 lines 9 bit Serial Interface STE2007 3 lines 9 bits serial interface is a bidirectional link between the display driver and the host processor It consists of three lines J SDAIN SDAOUT Serial Data Serial Clock ICS Peripheral enable Active Low Enables and Disables the serial interface The serial interface is active only if the CS line is low If CS is low after the positive edge of IRES the serial interface is ready to receive data after the internal reset time Serial data must be input to SDA in the sequence 07 to DO STE2007 read data on SCLK rising e
41. age Range D C D7 D6 D5 D4 D3 D2 D1 DO Setting 0 0 0 1 0 0 VOR Voltage Range Command Identifier Data Field 47 62 8 Commands STE2007 Table 31 VOR VOR D C 07 06 05 D4 03 02 D1 DO HEX Value 32 VOR 0 0 0 1 0 0 0 0 0 20 0 3 00 0 0 0 1 21 1 4 28 V 0 0 1 0 22 2 5 56 V 0 0 1 1 23 3 6 84 V 0 1 0 0 24 4 8 12 V Default 0 1 0 1 25 5 9 40 V 0 1 1 0 26 6 10 68 V 0 1 1 1 27 7 11 96 V 8 12 2 VOP Set Contrast Setting Adjustment Table 32 Set D C D7 D6 D5 D4 D3 D2 D1 DO HEX Function 0 1 1 1 0 0 0 0 1 E1 Command Identifier 0 6 5 Data Field Table 33 VOP VOP7 VOP6 VOP5 2 VOPO HEX VOP Adjustment 0 0 0 0 0 0 0 0 00 0 Step Default 0 0 0 0 0 0 0 1 01 1 Step 0 0 0 0 0 0 1 0 02 2 Step 0 1 1 1 1 1 1 1 7F 127 Step 1 0 0 0 0 0 0 0 80 0 Step 1 0 0 0 0 0 0 1 81 1 Step 1 1 1 1 1 1 0 1 FD 125 Step 1 1 1 1 1 1 1 0 FE 126 Step 1 1 1 1 1 1 1 1 FF 127 Step 48 62 4 5 2007 8 Commands 8 12 3 Electronic volume This command sets a
42. cy 0 Bias ratio 0 0 0 1 1 0 Bias Ratio Sets the VLCD 1 1 N line Inversion 0 FA N Line Inversion Number of Lines 0 1 1 0 1 0 Mux Rate 0 1 1 1 0 0 SET Initial Row on Display Image Location IL 2 0 Icon Mode olo 1 1 1 STM TEST Reserved for STM STM Test 0 STM TEST 0 1 ewe STM Test STM TEST MODE3 p Lael mua HAB Peserved STM Test Mode STM TEST 4 oe od ag Mode STM TEST 5 o 1 Reserved fors TM STM Test Mode STM TEST MODE6 0 a Se Reserved for STM STM Test Mode STM TEST MODE7 o o E pose prac Mode STM TEST MODE8 1 1 1 1 1 1 0 1 FD Disabled bits 42 62 4 STE2007 8 Commands 8 Commands 8 1 Display ON OFF This command turns the display ON and OFF Table 19 Display ON OFF D C D7 D6 D5 D4 D3 D2 D1 DO HEX Setting 0 1 0 1 0 1 1 1 0 AE Display OFF 0 1 AF Display ON When the Display OFF command is executed in the Display all points ON mode Power saver mode is entered See the section on the Power saver for details 8 2 Display normal reverse This command can reverse the l
43. ddress Ohex Ohex Ohex Display Start line Ohex Ohex Ohex Segment drivers Direction Normal Normal Normal Common Drivers Direction Normal Normal Normal VOR Voltage Range 4hex 4hex 4hex Electronic Volume 90hex 90hex 90 Power Control Register Booster OFF Booster OFF Booster OFF ID byte Ohex Ohex Ohex IDA IDB Pads Charge Pump 5x 5x 5x Bias Ratio 1 10 1 10 1 10 VLCD Temeprature Comp Oppm Oppm Oppm N Line Inversion Frame Inv Frame Inv Frame Inv Multiplexing Rate 1 68 1 68 1 68 Refresh Rate 80Hz 80Hz 80Hz Image Location Ohex Ohex Ohex Icon Mode Disabled Disabled Disabled 5 2007 6 Instruction Setups 6 Instruction Setups 6 1 Initialization Power ON Sequence Power ON Reset status 0 Range H Electronic volume H Power saver OFF Display all points OFF A4H Power control set 2FH 6 2 Display Data Writing Sequence Page address set B H Column address set Upper 3 bit address 1 H Column address set Lower 4 bit address 0 H Display AFH This command is need ed only at 1st time after initialization 6 3 Power OFF Optional Status IRES Pin Low Level min 20ms VDD GND Power OFF VDDI GND Power OFF Power Saver Status or Booster OFF Status IRES Pinz Low Level min 4 39 62 7 Power ON Power OFF timing Sequence STE2007 7 Power ON Power OFF
44. dge The first bit of serial data D IC is data command flag When 1 D7 to DO bits are display RAM data or Command Parameters When 0 D7 to DO bits identify a command MCU TxData Mode Write Mode STE2007 is always a slave device on the communication bus and receive the communication clock on the SCLK pin from the master Information are exchanged word wide Every word is composed by 9 bit The first bit is named D C and indicates whether the following byte is a command D C 0 or a Display Data Byte D IC 1 During data transfer the data line is sampled by the receiver unit on the SCLK rising edge The data command received is transferred to DDRAM or Executed on the first falling edge after the latching rising edge or on the CS rising edge If CS stays low after the last bit of command data byte the serial interface expects the D C bit of the next data byte on the next SCLK positive edge A reset pulse on RES pin interrupts any transmission 5 SDA DeX DX DX DIX DOXDICX D7X DEX D4 81 of af ha haf haf 2 28 laf 5 let lz 4 1 1 1 Data Command Transfer break 16 62 If the Host processor generates an break condition CS Line HIGH before having received Bit DO while transferring a Data byte to the Frame Memory or a Command identifier or a command parameter the not complete received byte is discarded
45. ed mode Data for page address to 07H Data DO LSBit D2 D3 D4 95 94 __________ 2 1 0 05 19190 5 98 97 96 tH 06 287 286 ____________ ___ 194 193 192 2 gt 57 3831382 __ 230 289 288 3H mE 479 478 385 384 address 575 574 482 481 480 5 671 670 ________ 578 577 576 6H 77146 674 673 672 7H 18631862 1177017691768 8 02H 01H Column address B Do Data for page address 8H Data can be written to the DDRAM at the same time as data is being displayed without causing the LCD to flicker Segment driver direction command can be used to reverse the relationship between the DDRAM column address and segment output This function is achieved writing data into in reverse order from Right to left Table 16 Column address direction coun 01H 02H 5DH 5EH 5FH 5DH address Normal SEGO SEG1 sEG2 SEG93 52694 SEG95 Direction Reverse SEG95 SEG94 SEG93 SEG2 SEG1 SEGO Direction Line address circuit The line address circuit specifies the line address relating to the COM output when the contents of the DDRAM are displayed The display start line that is normally the top line of the display can be speci
46. eristics Table 9 Operation Internal Oscillator Symbol Parameter Test Condition Min Typ Max Unit VDDI 1 6 VDD 2 9V Frame Frequency Default Rafresh Rate 75Hz 68 75 82 Hz Tamb 20 C to 70 C 3 4 MCU Tx Data Mode Table 10 AC Characteristics for Serial interface Description Signal Symbol Notes Min Typ Max Unit 1255 60 5 Chip Select ICS tcsh 100 ns tchw 50 ns t Dat tup ti 1 Input Serial Data Interface SDAIN sds ad ail tsdh Data hold time 100 125 ns tac Access Time 0 100 ns Output Serial Data interf SDAOUT i tog Output Disable 25 100 ns Time tscyc Serial clock cycle 250 ns Serial clock H Serial clock input SCLK pulse width 100 tslw Serial clock L 100 pulse width Note 1 The input signal rise and fall times must be within 10ns 2 Every timing is specified on the basis of 30 and 70 of VDDI Tamb 40 to 85 C unless otherwise specified Figure 2 MCU TxData timing ICS SCLK 4 12 62 5 2007 3 Display Driver Electrical Characteristics Table 11 Input Signals Change Time Signal Symbol Parameter Minimum Typical Maximum Unit Notes Nominal Inputs tr tf 10 ns to 30 amp 70 levels 3 41 Driver TxData Mode Table 12 Timings based on 4 MHz SCLK Speed
47. fied by Display start line address set command STE2007 features Four different Multiplexing Mode to fine tune the duty ratio on the display size 68 Lines Display 65Lines Display 49 Lines Display 33 Lines Display 4 5 2007 5 Display Data DDRAM Figure 23 68 line Mode address 5 5 Normal Direction SEG 4 6 5 G Output 51515 5 5 5 5 5 S 5 5 5 Reverse Direction 4 93 22 191 50 59 6 4 ICONMODE 1 m Normal Reverse Address direction direction OM66 00H eom 04H OSH 06H couss 081 09H OAH OBH COM12 OCH coms cousa eoma 2 cows 0FH Cow 15 causa cauaa 21 15H 11 25 1 1 H TDH comas TEH
48. ge Pump Multiplication Factor It is possible to select different Charge Pump Multiplication Factors Table 45 Charge Pump Setting D C D7 D6 D5 D4 D3 D2 D1 DO HEX Function 0 0 0 1 1 1 1 0 1 3D Command Identifier 0 Data Field 4 52 62 STE2007 8 Commands Table 46 Charge Pump Multiplication Factor CP1 CPO Function 0 0 5x 0 1 4x 1 0 3x 1 1 Not Used 8 20 Refresh Rate It is possible to select different Refresh Rate Table 47 Refresh Rate D C D7 D6 D5 04 03 02 D1 DO HEX Function 0 1 1 1 0 1 1 1 1 EF Command Identifier 0 i RR1 RRO Data Field Table 48 Refresh Rate RR1 RRO Function 0 0 80 Hz 0 1 75 Hz 1 0 70 Hz 1 1 65 hz 8 21 Icon Mode Icon Mode 0 Icon Mode Disabled 1 Icon Mode Enabled Table 49 Icon Mode D C D7 D6 D5 D4 D3 D2 D1 DO Function 0 1 1 1 1 1 0 ICON Command Identifier 8 22 N Line Inversion N line Inversion Function Table 50 N Line Inversion D C D7 D6 D5 D4 D3 D2 D1 DO HEX Function 0 1 0 1 0 1 1 0 1 AD Command Identifier F1 4 NL2 NL1 NLO Data Field 0 53 62 8 Commands 5 2007
49. it and unlit without overwriting the contents of the DDRAM Table 20 Display normal reverse D C D7 D6 D5 D4 D3 D2 D1 DO HEX Setting 0 1 0 1 0 0 1 1 0 Normal DDRAM Data ON voltage 0 1 A7 Reverse DDRAM Data L ZLCD ON voltage 8 3 Display all points ON OFF This command makes it possible to force all display points ON regardless of the content of the DDRAM Even when this is done the DDRAM contents are maintained This command takes priority over the Display normal reverse command Table 21 Display all points ON OFF D C D7 D6 D5 4 03 02 D1 DO HEX Setting 0 1 0 1 0 0 1 0 0 4 Normal Display Mode 0 1 A5 Display All Points ON When the Display all points ON command is executed when in the Display OFF mode Power saver mode is entered See the section on the Power Saver for details 4 43 62 8 Commands 5 2007 8 4 address set This command specifies the page address of the DDRAM Specifying the page address and column address enables to access a desired bit of the DDRAM After the last column address 5FH page address is incremented by 1 After the very last address column 5FH page 8H page address return to OH Table 22
50. iver must signal an end of data to the slave transmitter by not generating an acknowledge on the last byte that has been clocked out of the Slave In this case the transmitter must leave the data line High to enable the master to generate the STOP condition Connecting SDA IN and SDA OUT together the SDA line become the standard data line Having the acknowledge output SDAOUT separated from the serial data line is advantageous in Chip On Glass COG applications In COG applications where the track resistance from the SDAOUT pad to the system SDA line can be significant a potential divider is generated by the bus pull up resistor and the Indium Tin Oxide ITO track resistance It is possible that during the acknowledge cycle the STE2007 will not be able to create a valid logic O level By splitting the SDA input from the output the device could be used in a mode that ignores the acknowledge bit In COG applications where the acknowledge cycle is required it is necessary to minimize the track resistance from the SDACK pad to the system SDA line to guarantee a valid LOW level To be compliant with the 2 Hs mode specification the STE2007 is able to detect the special sequence 500001 After this sequence no acknowledge pulse is generated Since no internal modification are applied to work in Hs mode the device is able to work in Hs mode without detecting the master code 57 STE2007 4 INTERFACE 4 3 1 4 3 2 4
51. iver output 0 normal 1 reverse Display data write 1 Write data Writes to the DDRAM If Test Identificati Sell TesuidenileaHon e Da ae aha OB Byte data reading Operatin chi Power control set 0 0 0 1 0 1 Sets ue ae chip power supply mode circuit operating mode VO Range 0 010 1 0 0 VO Range Sets the electronic volume value Electronic volume 0 1 0 O Electronic volume value Sets the electronic volume value Compound command of Display OFF Display all points ON Reset 0 1 1 1 1 0 E2 Internal reset 0 1 1 1 1 1 0 1 1 1 0 0 Sets the VLCD 0 VOP 7 0 0 0 0 1 1 1 0 0138 SET VLCD Slope in temperature Termal Compensation Thermal Comp ky 41 62 7 Power ON Power OFF timing Sequence STE2007 Table 18 Instruction Set continued Code Command Function D C D7 D6 05 D4 D3 D2 D1 DO Hex Charge ets the arge rump Factor 0 Pump 1 EF the Display Refresh Refresh Rate Refersh Frequen
52. mand is issued the driver is initialized This command doesn t change DDRAM content Table 36 Reset D C D7 D6 D5 D4 D3 D2 D1 DO HEX Function 0 1 1 1 0 0 0 1 0 E2 Command Identifier 8 15 NOP Non operation command Table 37 D C D7 D6 D5 D4 D3 D2 D1 DO HEX Function 0 1 1 1 0 0 0 1 1 E3 Command Identifier 8 16 Image Location Image Location Command Table 38 Image Location D C D7 D6 D5 D4 D3 D2 D1 DO HEX Function 0 1 0 1 0 1 1 0 0 AC Command Identifier 0 E IL2 IL1 ILO Data Field Table 39 Image Location IL2 IL1 ILO Function 0 0 0 0 Lines 0 0 1 8 Lines 0 1 0 16 Lines 0 1 1 24 Lines 1 0 0 32 Lines 1 0 1 48 Lines 1 1 0 56 Lines 1 1 1 64 Lines 50 62 4 STE2007 8 Commands 8 17 Bias Ratio It is possible to select different Bias Ratio Table 40 Bias Ratio D C D7 D6 D5 D4 D3 D2 D1 DO Function 0 0 0 1 1 0 BR2 BR1 BRO Command Identifier Data Field Table 41 BIAS Ratio BR2 BR1 BRO Function 0 0 0 Bias Ratio 21 10 81 Lines 0 0 1 Bias Ratio 1 9 65 Lines 0 1 0 Bias Ratio 21 8 49 Lines 0 1 1 Bias Ratio 1 7 33 Lines 1 0 0 Bias Ratio 21 6 25 Lines 1 0 1 Bias Ratio 1 5 17 Lines 1 1 0 Bias Ratio 1 4 9 Lines 1 1 1 Not Used Table 42 Bias levels Generator BR 000 BR 001 BR 010 BR 011 Vico Vico 9 9 R R R R 8
53. nes the STOP condition Data Valid The state of the data line represents valid data when after a start condition the data line is stable for the duration of the High period of the clock signal The data on the line may be changed during the Low period of the clock signal There is one clock pulse per bit of data Each data transfer starts with a start condition and terminated with a stop condition The number of data bytes transferred between the start and the stop conditions is not limited The information is transmitted byte wide and each receiver acknowledges with the ninth bit By definition a device that gives out a message is called transmitter the receiving device that gets the signals is called receiver The device that controls the message is called master The devices that are controlled by the master are called slaves Acknowledge Each byte of eight bits is followed by one acknowledge bit This acknowledge bit is a low level put on the bus by the receiver whereas the master generates an extra acknowledge related clock pulse A slave receiver which is addressed must generate an acknowledge after the reception of each byte Also a master receiver must generate an acknowledge after the reception of each byte that has been clocked out of the slave transmitter The device that acknowledges has to pull down the SDA IN line during the acknowledge clock pulse Of course setup and hold time must be taken into account A master rece
54. rding to the following parameters Multiplexing Value IL 2 0 Figure 32 Partial Display 9 Lines 5 5 5 5 5 5 5 5 5 5 5 5 5 5 Reverse E Direction G 95 94 93 92 91 90 89 4 0 Partial Display Area 8 1 ICONMODE 1 COM Output COM Output Normal Reverse Normal Reverse rection direction direction direction COMO COM64 63 COM2 cov62 COMS COM5S m Ens IL 2 0 cows 55 2 COM8 COMES COM9 COM9 55 COM10 5 COM53 gt 52 comis 51 comso 15 18 19 COM20 21 23 25 COM26 COM27 comis 19 20 21 COM22 coves 2 25 26 27 COM28 COM29 O29 gt GOMAT COMO 47 COMTE COMIS coms conse comes COM comes Image Location 1L 2 0 display Area Width 11hex lt Multiplexing Rate 40hex 5 5 5 5 5 TS 5 5 5 5 5 TS Noma
55. rking Mode Must Be OPEN in Normal T3 Test Output Working Mode 8 62 57 5 2007 2 Driver Pin Description 4 6 Test Pin Description continued PIN Signal Type Description Note Test Output T5 Output We he oe Test Output NOH 2 Analog Test Output Must be left floating 9 62 3 Display Driver Electrical Characteristics STE2007 3 3 1 Note 10 62 Display Driver Electrical Characteristics Absolute maximum ratings Table 7 Absolute maximum ratings Symbol Parameter Value Unit Supply Voltage Range 0 510 5 Supply Voltage Range 0 510 5 LCD Supply Voltage Range 0 5 to 14 0 155 50 to 50 mA Vi Digital Inputs Voltage 0 5 to 0 5 V lin DC Input Current 10to 10 mA lout DC Output Current 1010 10 Total Power Dissipation T 85 C 300 mW Po Power Dissipation per Output 30 mW Tj Operating Junction Temperature 40 to 85 Storage Temperature 65 to 150 SO ESD Maximum Withstanding Voltage Range Allother Test Condition CDF AEC Q100 002 Human Body Model pins pin Acceptance Criteria Normal Performance 2000 combination ESD tests have been performed with VSS VSS_LCD and VSS_CP shorted together
56. s low after the positive edge of IRES the serial interface is ready to receive data after the internal reset time MCU TxData Mode Write Mode STE2007 is always a slave device on the communication bus and receive the communication clock on the SCL pin from the master Information are exchanged byte wide During data transfer the data line is sampled by the receiver unit on the SCL rising edge line status set whether the byte is a command D C 0 or a data D IC 1 D IC line is read on the eighth SCL clock pulse during every byte transfer If CS stays low after the last bit of command data byte the serial interface expects the MSB of the next data byte on the next SCL positive edge If ICS line is forced high in the middle of a data transfer not complete Data bytes and Commands bytes are discarded A reset pulse on RES pin interrupts any transmission 19 62 4 STE2007 Figure 10 4 lines SPI Commands Transfe
57. se No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics Specifications mentioned in this publication are subject to change without notice This publication supersedes and replaces all information previously supplied STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics The ST logo is a registered trademark of STMicroelectronics All other names are the property of their respective owners 2005 STMicroelectronics All rights reserved STMicroelectronics group of companies Australia Belgium Brazil Canada China Czech Republic Finland France Germany Hong Kong India Israel Italy Japan Malaysia Malta Morocco Singapore Spain Sweden Switzerland United Kingdom United States of America www st com 57 62 62
58. standard serial interfaces 3 and 4 lines serial 5 Ordering Number Bumped Dice on Waffle Pack STE2007DIE2 Rev 1 1 62 www st com 5 2007 2 62 Contents Introduction 5 Driver Pin Description 7 2 1 CPU E RR ap BoE eR RERO ERR 7 2 2 Power Supply Pins 7 2 3 Configuration PINS ACER 8 2 4 Test PIAS ba KOC Ewe de deca ee eae dos 8 Display Driver Electrical Characteristics 10 3 1 Absolute maximum ratings 10 3 2 DC Characteristics GE E ARA ROO REESE 11 S Characteristics 42 08 eX Dre ERR IQ nad 12 3 4 MCU Tx Data Mode xw ac REP OE EGRE AREA ES eee 12 341 Driver TxData Mode 13 3 4 2 Reset Timing 14 INTERFACE 16 4 1 3 lines 9 bit Serial Interface 16 411 MCU TxData Mode Write Mode 16 4 1 2 Driver TxData Mode Read Mode 17 S2 De RR ER ERR ROC OR 19 4 2 4 MCU TxData Mode Write Mode
59. the driver and for VDD Intercfonnection electrical self testing 4 17 62 4 INTERFACE STE2007 Self Testing of the electrical contacts is based on the monitoring of VLCD The improper electrical contact on VDD can be noted from a too low level of VLCD The serial interface Driver TxData mode is controlled by three input signals The serial data output SDAOUT Driver TxData and serial clock input SCLK are enabled when CS is low after having received one Reading Command To access Driver TxData mode a Reading command must be sent to STE2007 driver The first bit D C is low to indicates next 8 bits are for command The data is read to the driver on the rising edge of SCLK see section MCU TxData mode After last command bit bit 0 is read SDAOUT becomes active Low impedance and MCU is able to read data from driver SDAOUT is forced in high impedence when CS line is forced high or after the eight SCLK rising edges from the last SCLK rising edge of teh reading command transfer Figure 8 After sending out all 8 bits the driver release automatically the bus and go back to the MCU TxData mode MCU Txdata line changes from high z to active low or high in the falling edge of 8th SCLK pulse CS must be set high and low again before D C writing can continue If is forced high during the Driver TxDAta mode the Driver Tx data session is aborted and SDAOUT is forced in high impedance Mode SDAOUT and SDAIN line can be
60. tween Bumps 17um 4 55 62 9 Chip Mechanical Drawing STE2007 Table 55 Pad Coordinates Table 55 Pad Coordinates continued NAME PAD X um R16 1 2632 5 514 35 C19 29 1372 5 514 35 R14 2 2587 5 514 35 C20 30 1327 5 514 35 R12 3 2542 5 514 35 C21 31 1282 5 514 35 R10 4 2497 5 514 35 C22 32 1237 5 514 35 R8 5 2452 5 514 35 C23 33 1192 5 514 35 R6 6 2407 5 514 35 C24 34 1147 5 514 35 R4 7 2362 5 514 35 C25 35 1102 5 514 35 R2 8 2317 5 514 35 C26 36 1057 5 514 35 RO 9 2272 5 514 35 C27 37 1012 5 514 35 10 2227 5 514 35 28 38 967 5 514 35 C1 11 2182 5 514 35 29 39 922 5 514 35 2 12 2137 5 514 35 C30 40 877 5 514 35 C3 13 2092 5 514 35 C31 41 832 5 514 35 C4 14 2047 5 514 35 C32 42 787 5 514 35 C5 15 2002 5 514 35 C33 43 742 5 514 35 C6 16 1957 5 514 35 C34 44 697 5 514 35 C7 17 1912 5 514 35 C35 45 652 5 514 35 C8 18 1867 5 514 35 C36 46 607 5 514 35 C9 19 1822 5 514 35 C37 47 562 5 514 35 C10 20 1777 5 514 35 C38 48 517 5 514 35 C11 21 1732 5 514 35 C39 49 472 5 514 35 C12 22 1687 5 514 35 C40 50 427 5 514 35 C13 23 1642 5 514 35 C41 51 382 5 514 35 C14 24 1597 5 514 35 C42 52
61. utput Reverse JE 2 Direction 95 54 93 52 51 50 59 6 4 0 Display start line does not access 65th 66th 67th 68th line Image Location 1L 2 0 Partial display Area Width 11hex lt Multiplexing Rate 40hex 5 5 5 5 5 5 5 5 5 5 5 5 5 E Direction G 4 6 oo 91 92 93 94 9 gt COMs2 ot COMS7 CONST c 7 cT Ta Comes OL COMIS 7 COMIS comaa COMIS 51 COM12 52 COMIT comsa COMS comsa COMTO Fco OM56 COM56 57 COME CoMo Cose COMS comes comer comes comes 2 comes COMI COMO 36 62 5 2007 5 Display Data DDRAM 5 3 4 9 Line Partial Display Mode Partial Display Area is composed of 9 Lines Memory vs Row Drivers Mapping is defined acco
62. value of electronic volume EV for the VLCD voltage regulator to adjust the contrast of LCD panel display End User Table 34 Electronic volume D C D7 D6 D5 D4 D3 D2 D1 DO Setting 0 1 0 0 Electronic Volume Value Command Identifier Data Field Table 35 EV D C D7 D6 D5 D4 D3 D2 D1 DO Hex EV Value VLCD voltage 0 1 0 0 0 0 0 0 0 80 0 Step low 0 0 0 0 0 1 81 1 Step 0 0 0 0 1 0 82 2 Step 0 1 0 0 0 0 90 16 Step Default 0 1 1 1 1 0 9E 30 Step 0 1 1 1 1 1 OF 31 Step high 813 Power saver mode 4 If the display all points ON command is executed when the display is display OFF mode power saver mode is entered This mode stops every operation of the LCD display system Figure 37 Power saver mode Power saver Display OFF amp Display all points ON Powersaver OFF Display all points OFF Power saver mode canceled The internal states in power saver mode are as follows The oscillation circuit is stopped The LCD power supply circuit is stopped The LCD driver circuit is stopped and segment common driver outputs to the Vss level 49 62 8 Commands 5 2007 display data and operation mode before execution of the Power saver held and the MCU can access to the DDRAM and internal registers 8 14 Reset When this com
63. ws Cows coman comio 2 2 COM27 COM27 25 OSH 09H OBH OCH 0DH 10H COM32 15 1 COM33 COMS4 SS SS DS DS S ES DR S S DS S DS IS a ES s Sasamo E br es pa pra en Ed eg Cbd s as COMAS 32H 33H address Normal Direction G 6 6 6 G 6 G SEG 0 4 6 54 192 Output 5 5 5 5 5 5 5 5 5 5 5 Reverse JE E Direction 95 193 92 191 90 6 4 0 ky 31 62 5 Display Data DDRAM STE2007 5 3
Download Pdf Manuals
Related Search