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ST LNBH25L LNB supply control IC with step-up I C interface handbook

1. GND BYP VCC AM10460v1 Doc ID 022634 Rev 2 LNBH25L Application information 2 2 1 2 2 Application information This IC has a built in DC DC step up converter that from a single source 8 V to 16 V generates the voltages Vyp that let the integrated LDO post regulator generating the 13 V 18 V LNB output voltages plus the 22 kHz DiSEqC tone to work with a minimum dissipated power of 0 5 W typ 500 mA load the LDO drop voltage is internally kept at Vup Vout 1 V typ The IC is also provided with an undervoltage lockout circuit that disables the whole circuit when the supplied Vcc drops below a fixed threshold 4 7 V typically The step up converter soft start function reduces the inrush current during startup The SS time is internally fixed at 4ms typ to switch from 0 to 13 V and 6 ms typ to switch from 0 to 18 V DiSEqC data encoding DSQIN pin The internal 22 kHz tone generator is factory trimmed in accordance to DiSEqC standards and can be activated in 3 different ways 1 by an external 22 kHz source DiSEqC data connected to the DSQIN logic pin TTL compatible In this case the 12C tone control bits must be set EXTM TEN 1 2 by an external DiSEqC data envelope source connected to the DSQIN logic pin In this case the I2C tone control bits must be set EXTM 0 and TEN 1 3 through the TEN ISC bit if a 22 kHz presence is requested in continuous mode
2. A N VSEL4 VSEL3 VSEL2 AM10463v1 ACK Acknowledge S Start P Stop R W 1 0 Read Write bit X 0 1 set the values to select the CHIP ADDRESS see Table 15 for pin selection and to select the REGISTER ADDRESS see Table 6 to Table 11 a The writing procedure can start from any register address by simply setting the X values in the register address byte after the chip address It can be also stopped from the master by sending a stop condition after any acknowledge bit ky Doc ID 022634 Rev 2 15 28 ISC interface protocol LNBH25L 7 2 Read mode transmission In read mode the bytes sequence must be as follows e astart condition S a chip address byte with the LSB bit R W 0 the register address byte of the internal first register to be accessed a stop condition P a new master transmission with the chip address byte and the LSB bit R W 1 after the acknowledge the LNBH25L starts to send the addressed register content As long as the master keeps the acknowledge LOW the LNBH25L transmits the next address register byte content e the transmission is terminated when the master sets the acknowledge HIGH with a following stop bit Figure 11 Example of reading procedure starting with first status address 0X0 REGISTER ADDRESS X CHIP ADDRESS CHIP ADDRESS STATUS 2 Add 0x1 STATUS 1 Add 0x0 U DATA 4
3. GI LNBH25L LNB supply and control IC with step up and ISC interface Features Complete interface between LNB and PC bus m Built in DC DC converter for single 12 V supply operation and high efficiency typ 93 0 5 A m Selectable output current limit by external resistor m Compliant with main satellite receiver output voltage specifications m Accurate built in 22 kHz tone generator suits widely accepted standards m 22 kHz tone waveform integrity guaranteed also at no load condition m Low drop post regulator and high efficiency step up PWM with integrated power N MOS allowing low power losses m Overload and overtemperature internal protection with PC diagnostic bits m LNB short circuit dynamic protection m 4kV ESD tolerant on output power pins Applications m STB satellite receivers m TV satellite receivers m PC card satellite receivers Description Intended for analog and digital satellite receivers Sat TV and Sat PC cards the LNBH25L is a monolithic voltage regulator and interface IC assembled in QFN24 4x4 specifically designed to provide the 13 18 V power supply and the 22 kHz tone signalling to Table 1 Device summary QFN24 4 x 4 mm the LNB down converter in the antenna dish or to the multi switch box In this application field it offers a complete solution with extremely low component count and low power dissipation together with a simple design and 2C standard interfa
4. Add 0x5 DATA 1 Add 0x2 DATA 2 Add 0x3 MSB LSB M s lt s ti uli s s s S S E SI s s s s s N gt ACK Acknowledge S Start P Stop R W 1 0 Read Write bit X 0 1 set the values to select the CHIP ADDRESS see Table 15 for pin selection and to select the REGISTER ADDRESS see Table 6to Table 11 N A N N NIA VSEL4 AM10464v1 b The reading procedure can start from any register address Status 1 2 or Data1 4 by simply setting the X values in the register address byte after the first chip address in the above figure It can be also stopped from the master by sending a stop condition after any acknowledge bit 16 28 Doc ID 022634 Rev 2 ky LNBH25L I2C interface protocol 7 3 Data registers The data 1 4 registers can be addressed both in write and read mode In read mode they return the last writing byte status received in the previous write transmission The following tables provide the register address values of data 1 4 and a function description of each bit Table 6 Data 1 read write register Register address 0X2 BIT Name Value Description ise VSEL1 0 1 Bit 1 VSEL2 0 1 Output voltage selection bits Refer to Table 13 Bit 2 VSEL3 0 1 Bit 3 VSEL4 0 1 Bit 4 N A 0 Reserved Keep to 0 Bit 5 N A 0 Reserved Keep to 0 Bit 6 N A 0 Reserved Keep to 0 kez N A 0 Reserved Keep t
5. In this case the DSQIN TTL pin must be pulled HIGH and EXTM bit set to 0 Data encoding by external 22 kHz tone TTL signal In order to improve design flexibility an external tone signal can be input to the DSQIN pin by setting the EXTM bit to 1 The DSQIN is a logic input pin which activates the 22 kHz tone to the Voyz pin by using the LNBH25L integrated tone generator The output tone waveforms are internally controlled by the LNBH25L tone generator in terms of rise fall time and tone amplitude while the external 22 kHz signal on the DSQIN pin is used to define the frequency and the duty cycle of the output tone A TTL compatible 22 kHz signal is required for the proper control of the DSQIN pin function Before sending the TTL signal on the DSQIN pin the EXTM and TEN bits must be previously set to 1 As soon as the DSQIN internal circuit detects the 22 kHz TTL external signal code the LNBH25L activates the 22 kHz tone on the Vour output with about 1 us delay from TTL signal activation and it stops with about 60 us delay after the 22 kHz TTL signal on DSQIN has expired refer to Figure 2 Figure 2 Tone enable and disable timing using external waveform at E ul t sous Tone Output AM10426v1 Doc ID 022634 Rev 2 5 28 Application information LNBH25L 2 3 2 4 2 5 6 28 Data encoding by external DiSEqC envelope control through the DSQIN pin If an external DiSEqC envelope source is availa
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7. condition s sina sda ves de ae dee A OE es eda es 12 6 3 Byte format sc giiend Canes See R R RRR hes eee keene RO R 12 6 4 Acknowledge c0eies Ae nase ee eis Ee ROE te je spe a ve Sees 12 6 5 Transmission without acknowledge 12 7 PC interface protocol 0666 ceiver estes tee sasa ka en eeee ee es 14 7 1 Write mode transmission 22205 s42ceders oeaveevees seus deenee ex 14 7 2 Read mode transmission 22 602 je su des pod tija ee pole koda a s 15 7 3 Data registers izra obre ole roke ag deke el ae sika ase 16 2 28 Doc ID 022634 Rev 2 ky LNBH25L Contents 7 4 laws registers a ae ona bine poder sees esi ee Siege Ad ae z 18 8 Electrical characteristics 20 9 Package mechanical data 23 10 Revision history sss s s s x de vek Cie k KN ka di 27 ky Doc ID 022634 Rev 2 3 28 Block diagram LNBH25L 1 4 28 Block diagram Figure 1 Block diagram ADDR SCL SDA IR H 1 Lx gt m 12C Digital core z DSQIN 5 T i z o j z A E DAC Drop control Tone ctrl Pro PGND Diagnostics Protections la VUP ISEL Current Limit y selection E Linear Regulator 3 LI VOUT Voltage reference
8. 0 0 0 1 1 13 188 13 667 14 145 0 1 0 0 13 51 14 000 14 490 1 0 0 0 17 515 18 150 18 785 1 0 0 1 17 836 18 483 19 130 1 0 1 0 18 158 18 817 19 475 1 0 1 1 18 48 19 150 19 820 SI Doc ID 022634 Rev 2 21 28 Electrical characteristics LNBH25L T from 0 to 85 C V 12 V Table 14 PC electrical characteristics Symbol Parameter Test conditions Min Typ Max Unit Vy Low level input voltage SDA SCL 0 8 V Via High level input voltage SDA SCL 2 V lin Input current SDA SCL Viw 0 4 to 4 5 V 10 10 UA Var Low level output voltage 1 SDA open drain lol 6 mA 0 6 V Fmax Maximum clock frequency SCL 400 kHz 1 Guaranteed by design T from 0 to 85 C V 12 V Table 15 Address pin characteristics Symbol Parameter Test condition Min Typ Max Unit V 0001000 R W address pin R W bit determines the transmission 0 08 V ADDR 1 voltage range mode read R W 1 write R W 0 i V 0001001 R W address pin R W bit determines the transmission 2 5 V ADDR 2 voltage range mode read R W 1 write R W 0 22 28 Doc ID 022634 Rev 2 ky LNBH25L Package mechanical data 9 Package mechanical data In order to meet environmental requirements ST offers these devices in different grades of ECOPACK packages depending on their level of environmental compliance ECOPACK specifications gra
9. 022634 Rev 2 11 28 Typical application circuits LNBH25L 5 12 28 Typical application circuits Figure 6 DiSEqC 1 x application circuit D2 D1 LNBH25L DiSEqC 22KHz TIL or DiSEqC Envelope TTL I AM10462v1 Table 5 Typical application circuit bill of material Component Notes R1 RSEL SMD resistor Refer to Table 12 and ISEL pin description in Table 2 C1 C2 gt 25 V electrolytic capacitor 100 F is suitable C3 From 470 nF to 2 2 uF ceramic capacitor Higher values allow lower DC DC noise C5 From 100 nF to 220 nF ceramic capacitor Higher values allow lower DC DC noise C4 C7 220 nF ceramic capacitors D1 STPS130A or similar schottky diode BAT54 BAT43 1N5818 or any low power schottky diode with Ir AV gt 0 2 A D3 Vero gt 25 V Vp lt 0 5 V To be placed as close as possible to Voyr pin D2 1N4001 07 S1A S1M or any similar general purpose rectifier L1 10 HH inductor with lsat gt Ipeak Where Ipeak is the boost converter peak current s Doc ID 022634 Rev 2 LNBH25L I2C bus interface 6 6 1 6 2 6 3 6 4 6 5 I2C bus interface Data transmission from the main microprocessor to the LNBH25L and vice versa takes place through the 2 wire ISC bus interface consisting of the 2 line SDA and SCL pull up resistors to positive supply voltage must be externally connected Data validity As shown in Figure 7 th
10. 13 for exact programmable values Register writing is accessible via the I2C bus Doc ID 022634 Rev 2 ki LNBH25L Application information 2 6 2 7 2 8 2 9 Diagnostic and protection functions The LNBH25L has 3 diagnostic internal functions provided via the I2C bus by reading 3 bits on the STATUS1 register in read mode All the diagnostic bits are in normal operation that is no failure detected set to LOW Two diagnostic bits are dedicated to the overtemperature and overload protection status OTF and OLF One bit is dedicated to the input voltage power not good function PNG Once the OLF or OTF or PNG bit has been activated set to 1 it is latched to 1 until the relevant cause is removed and a new register reading operation is done Surge protection and TVS diodes The LNBH25L device is directly connected to the antenna cable in a set top box Atmospheric phenomenon can cause high voltage discharges on the antenna cable causing damage to the attached devices Surge pulses occur due to direct or indirect lightning strikes to an external outdoor circuit This leads to currents or electromagnetic fields causing high voltage or current transients Transient voltage suppressor TVS devices are usually used as shown in the following schematic to protect the STB output circuits where the LNBH25L and other devices are electrically connected to the antenna cable Figure 4 Surge protection circuit to
11. 16 BYP Bypass capacitor S this pin to external current or voltage sources may cause permanent damage to the device 17 Voc Supply input 8 to 16 V IC DC DC power supply 20 Vout LNB output port Output of the integrated very low drop linear regulator See Table 13 for voltage selection and description Input of the linear post regulator The voltage on this pin is 21 Vup Step up voltage monitored by the internal step up controller to keep a minimum dropout across the linear pass transistor SI Doc ID 022634 Rev 2 9 28 Pin configuration LNBH25L Table 2 Pin description continued Pin n Symbol Name Pin function It can be used as DiSEqC envelope input or external 22 kHz TTL DSQIN for input depending on the EXTM ISC bit setting as follows DiSEqC envelope EXTM 0 TEN 1 it accepts the DiSEqC envelope code from the input main microcontroller The LNBH25L uses this code to modulate the 22 DSQIN or internally generated 22 kHz carrier External 22 kHz EXTM TEN 1 it accepts external 22 kHz logic signals which TTL input activate the 22 kHz tone output refer to Section 2 3 Pull up high if the tone output is activated only by the TEN I C bit To be connected with power grounds and to the ground layer Epad Epad Exposed pad through vias to desise the Ki i f 1 5 10 11 N C Not internally Not internally connected pins These pins can be connected to GND 12 13 14 24 O connected to improve thermal per
12. Doc ID 022634 Rev 2 LNBH25L Revision history 10 Revision history Table 17 Document revision history Date Revision Changes 09 Jan 2012 1 lnitial release 15 Feb 2012 2 Modified D1 and D3 Table 5 on page 12 Doc ID 022634 Rev 2 27 28 LNBH25L Please Read Carefully Information in this document is provided solely in connection with ST products STMicroelectronics NV and its subsidiaries ST reserve the right to make changes corrections modifications or improvements to this document and the products and services described herein at any time without notice All ST products are sold pursuant to ST s terms and conditions of sale Purchasers are solely responsible for the choice selection and use of the ST products and services described herein and ST assumes no liability whatsoever relating to the choice selection or use of the ST products and services described herein No license express or implied by estoppel or otherwise to any intellectual property rights is granted under this document If any part of this document refers to any third party products or services it shall not be deemed a license grant by ST for the use of such third party products or services or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoever of such third party products or services or any intellectual property contained therein UNLESS OTHERWISE
13. LNB IF connector LNBTVSxx LNBH25L For this purpose we recommend the use of LNBTVSxx surge protection diodes specifically designed by ST The selection of the LNBTVS diode should be made based on the maximum peak power dissipation that the diode is capable of supporting see the LNBTVS datasheet for further details Power on SC interface reset and undervoltage lockout The ISC interface built into the LNBH25L is automatically reset at power on As long as the Voc stays below the undervoltage lockout UVLO threshold 4 7 V typ the interface does not respond to any ISC command and all data register bits are initialized to zeroes therefore keeping the power blocks disabled Once the Vcc rises above 4 8 V typ the IC interface becomes operative and the data registers can be configured by the main microprocessor PNG input voltage minimum detection When input voltage Vec pin is lower than LPD low power diagnostic minimum thresholds the PNG ISC bit is set to 1 and the FLT pin is set low Refer to Table 12 for threshold details Doc ID 022634 Rev 2 7 28 Application information LNBH25L 2 10 2 11 8 28 OLF overcurrent and short circuit protection and diagnostic In order to reduce the total power dissipation during an overload or a short circuit condition the device is provided with a dynamic short circuit protection It is possible to set the short circuit current protection either s
14. ble it is possible to use the internal 22 kHz generator activated during the tone transmission by connecting the DiSEqC envelope source to the DSQIN pin In this case the I2C tone control bits must be set EXTM 0 and TEN 1 In this way the internal 22 kHz signal is superimposed to the vour DC voltage to generate the LNB output 22 kHz tone During the period in which the DSQIN is kept HIGH the internal control circuit activates the 22 kHz tone output The 22 kHz tone on the Voyrt pin is activated with about 6 us delay from the DSQIN TTL signal rising edge and it stops with a delay time in the range from 15 us to 60 us after the 22 kHz TTL signal on DSQIN has expired refer to Figure 3 Figure 3 Tone enable and disable timing using envelope signal DSQIN 5 60 US US Output current limit selection The linear regulator current limit threshold can be set by an external resistor connected to the ISEL pin The resistor value defines the output current limit by the equation Equation 1 o 13915 Imax typ ASELTTIT where RSEL is the resistor connected between ISEL and GND expressed in kQ and Imax typ is the typical current limit threshold expressed in mA Imax can be set up to 750 mA Output voltage selection The linear regulator output voltage level can be easily programmed in order to accomplish application specific requirements using 4 bits of an internal DATA1 register see Section 7 3 and Table
15. cing Order code LNBH25LPOR Package QFN24 4 x 4 Packaging Tape and reel February 2012 Doc ID 022634 Rev 2 1 28 www st com Contents LNBH25L Contents 1 Block diagram ee ee a lahk ee 3 2 Application information 4 2 1 DiSEqC data encoding DSQIN pin 4 2 2 Data encoding by external 22 kHz tone TTL signal 4 2 3 Data encoding by external DISEqC envelope control through tne DSGIN pin i004 sedncases cehadasdecahouscd need 5 2 4 Output current limit selection een seeded ert meas odenes 5 2 5 Output voltage selection cscude sm eipa E sd olja kesa seated bele ka 5 2 6 Diagnostic and protection functions 5 2 7 Surge protection and TVS diodes 6 2 8 Power on I C interface reset and undervoltage lockout 6 2 9 PNG input voltage minimum detection 6 2 10 OLF overcurrent and short circuit protection and diagnostic 7 2 11 OTF thermal protection and diagnostic 7 3 Pin configuration ss x a wn a mm Gace ei ne a RL ia 8 4 Maximum raliNGS ses x x x x x cee wenden aie eee eee 10 5 Typical application circuits 11 6 PO bus interface te mem i i oa te pn rn UE la ho 12 6 1 Data validity 6 O Speen tb RR NE TOM 12 6 2 Start and stop
16. de definitions and product status are available at www st com ECOPACK is an ST trademark Table 16 GFN24L 4 x 4 mm mechanical data mm Dim Min Typ Max A 0 80 0 90 1 00 A1 0 00 0 02 0 05 0 18 0 25 0 30 D 3 90 4 00 4 10 D2 2 55 2 70 2 80 E 3 90 4 00 4 10 E2 2 55 2 70 2 80 e 0 45 0 50 0 55 L 0 25 0 35 0 45 Doc ID 022634 Rev 2 23 28 Package mechanical data LNBH25L 24 28 Figure 12 QFN24L 4 x 4 mm package dimensions D lu TOP VIEW i annnnol SIDE VIEW e ve x m l l 1 PIN 1 ID BOTTOM VIEW 7596209_D Doc ID 022634 Rev 2 ky LNBH25L Package mechanical data Tape amp reel QFNxx DFNxx 4x4 mechanical data mm inch Dim Min Typ Max Min Typ Max A 330 12 992 C 12 8 13 2 0 504 0 519 D 20 2 0 795 N 99 101 3 898 3 976 T 14 4 0 567 Ao 4 35 0 171 Bo 4 35 fF 0 171 Ko 1 1 0 043 Po 4 0 157 P 8 0 315 V N C 1 1 A G A T Po Bo IE P 6 o d J Ko _ AO si aP Note Drawing not in scale G Doc ID 022634 Rev 2 25 28 Package mechanical data LNBH25L Figure 13 QFN24L 4 x 4 footprint recommended data mm 26 28
17. e data on the SDA line must be stable during the high semi period of the clock The HIGH and LOW state of the data line can only change when the clock signal on the SCL line is LOW Start and stop condition As shown in Figure 8 a start condition is a HIGH to LOW transition of the SDA line while SCL is HIGH The stop condition is a LOW to HIGH transition of the SDA line while SCL is HIGH A STOP condition must be sent before each START condition Byte format Every byte transferred to the SDA line must contain 8 bits Each byte must be followed by an acknowledge bit The MSB is transferred first Acknowledge The master microprocessor puts a resistive HIGH level on the SDA line during the acknowledge clock pulse see Figure 9 The peripheral LNBH25L that acknowledges must pull down LOW the SDA line during the acknowledge clock pulse so that the SDA line is stable LOW during this clock pulse The peripheral which has been addressed must generate an acknowledge after the reception of each byte otherwise the SDA line remains at the HIGH level during the ninth clock pulse time In this case the master transmitter can generate the STOP information in order to abort the transfer The LNBH25L does not generate an acknowledge if the Vcc supply is below the undervoltage lockout threshold 4 7 V typ Transmission without acknowledge To avoid detection of the LNBH25L acknowledges the microprocessor can use a simpler transmission it simp
18. fficiency loyT lt 500mA 93 Few SAJ switching 440 kHz ue Undervoltage lockout UVLO threshold rising 4 8 V thresholds UVLO threshold falling 4 7 Vip Low power diagnostic LPD Vip threshold rising 7 2 V thresholds Vp threshold falling 6 7 20 28 Doc ID 022634 Rev 2 ky LNBH25L Electrical characteristics Table 12 Electrical characteristics continued Symbol Parameter Test conditions Min Typ Max Unit Vi DSQIN pin logic low 0 8 V Vin DSQIN pin logic high 2 V liu DSQIN pin input current Vjas5 V 15 HA loBK Output backward current All VSELx 0 Vogx 30 V 3 6 mA IsiNK Output low side sink current Vout forced at Vout nomt0 1 V 70 mA ISINK_TIME ow side sink current timeout Vout forced at Voyt nemt0 1 V 10 ms OUT Vout forced at V 0 1 V IREv Max reverse current OUT torced al VOUT nom 2 mA after Isink Time our IS elapsed TsHon Thermal shutdown threshold 150 C ATauny Thermal shutdown hysteresis 15 C 1 In applications where Vce Voyr gt 1 3 V the increased power dissipation inside the integrated LDO must be taken into account in the application thermal management design 2 Guaranteed by design Table 13 Output voltage selection table Data1 register write mode VSEL4 VSEL3 VSEL2 VSEL1 Our m Your Function 0 0 0 0 0 000 Vout disabled LNBH25L set in standby 0 0 0 1 12 545 13 000 13 455 0 0 1 0 12 867 13 333 13 80
19. formances 10 28 s Doc ID 022634 Rev 2 LNBH25L Maximum ratings 4 Maximum ratings Table 3 Absolute maximum ratings Symbol Parameter Value Unit Vec DC power supply input voltage pins 0 3 to 20 V Vup DC input voltage 0 3 to 40 V lout Output current Internally limited mA Vout DC output pin voltage 0 3 to 40 V V Logic input pins voltage SDA SCL DSGIN ADDR pins 0 3 to 7 V LX LX input voltage 0 3 to 30 V Veyp Internal reference pin voltage 0 3 to 4 6 V ISEL Current selection pin voltage 0 3 to 3 5 V TsTG Storage temperature range 50 to 150 C Ty Operating junction temperature range 25 to 125 C ESD rating with human body model HBM all pins unless power output 2 kV ESD pins ESD rating with human body model HBM for power output pins 4 Table 4 Thermal data Symbol Parameter Value Unit Rthsc Thermal resistance junction case 2 C W Rua Thermal resistance junction ambient with device soldered on 2s2p 4 40 C W layer PCB provided with thermal vias below exposed pad Note Absolute maximum ratings are those values beyond which damage to the device may occur SI These are stress ratings only and functional operation of the device at these conditions is not implied Exposure to absolute maximum rated conditions for extended periods may affect device reliability All voltage values are with respect to the network ground terminal Doc ID
20. lectronics All rights reserved STMicroelectronics group of companies Australia Belgium Brazil Canada China Czech Republic Finland France Germany Hong Kong India Israel Italy Japan Malaysia Malta Morocco Philippines Singapore Spain Sweden Switzerland United Kingdom United States of America www st com 28 28 Doc ID 022634 Rev 2 ky
21. less otherwise stated Typical values are referred to Ty 25 C Voyt Vout pin voltage See software description section for ISC access to the system register Section 6 and Section 7 Table 12 Electrical characteristics Symbol Parameter Test conditions Min Typ Max Unit ViN Supply voltage 1 8 12 16 V lout lt 0 mA 6 mA ik Supply current 22 kHz tone enabled TEN 1 10 DSQIN High loyr 0 mA VSEL1 VSEL2 VSEL3 VSEL4 0 1 Vout Output voltage total accuracy Valid at any Voyr selected level 3 5 43 5 Vout Line regulation Vin 8 to 16 V 40 mV Vout Load regulation lout from 50 to 500 mA 75 100 Ivax Output current limiting RSEL 16 2 kQ 500 750 thresholds RSEL 22 kQ 350 550 Isc Output short circuit current RSEL 16 2 kQ 350 mA SS Soft start time Vout from 0 to 13 V 4 ms SS Soft start time Vout from 0 to 18 V 6 ms T13 18 Soft transition rise time Vout from 13V to 18 V 1 5 ms T18 13 Soft transition fall time Vout from 18V to 13 V 1 5 ms Torr a protoctian PCL 0 output shorted 900 ms Ton oe overload protection PCL 0 output shorted Topr 10 DSQIN High EXTM 0 TEN 1 Arone _ Tone amplitude lout from 0 to 500 mA 0 55 0 675 0 8 Vpp Caus from 0 to 750 nF Frone _ Tone frequency 20 22 24 kHz Drone Tone duty cycle DSQIN High EXTM 0 TEN 1 43 50 57 th ty Tone rise or fall time 5 8 15 us Eff pcoc DC DC converter e
22. lowing tables Table 10 STATUS 1 Read register Register address 0X0 BIT Name Value Description l 1 Vout Pin overload protection has been triggered our gt Imax Refer to Table 8 for J OLF the overload operation settings PCL bit LSB 0 No overload protection has been triggered to the Vour pin lout lt Imax Bit 1 N A Reserved Bit 2 N A Reserved Bit 3 N A Reserved Bit 4 N A Reserved Bit 5 N A Reserved 1 Junction overtemperature is detected Tj gt 150 C See also the THERM bit setting in Table 9 Bit 6 OTF 0 Junction overtemperature not detected Tj lt 135 C Ty is below thermal protection threshold Bit 7 gue 1 Input voltage Vcc pin lower than LPD minimum thresholds Refer to Table 12 MSB 0 Input voltage Vec pin higher than LPD thresholds Refer to Table 12 N A Reserved bit All bits reset to O at power on Table 11 STATUS 2 Read register Register address 0X1 BIT Name Value Description Bit 0 LSB N A Reserved Bit 1 N A Reserved Bit 2 N A Reserved Bit 3 N A Reserved Bit 4 N A Reserved Bit 5 N A Reserved Bit 6 N A Reserved Bit 7 N A Reserved MSB N A Reserved bit All bits reset to O at power on ky Doc ID 022634 Rev 2 19 28 Electrical characteristics LNBH25L 8 Electrical characteristics Refer to Section 5 Tj from 0 to 85 C all data 1 4 register bits set to 0 unless VSEL1 1 RSEL 16 2 kO DSQIN LOW Vinx 12 V lour 50 mA un
23. ly waits one clock cycle without checking the slave acknowledging and sends the new data This approach is of course less protected from misworking and decreases the noise immunity Doc ID 022634 Rev 2 13 28 PC bus interface LNBH25L Figure 7 Data validity on the I C bus SCL SDA DATA LINE STABLE DATA CHANGE DATA VALID ALLOWED CS11340 Figure 8 Timing diagram of PC bus SCL SDA START s C511440 Figure 9 Acknowledge on the PC bus SCL 1 7 9 SDA MSB E ACKNOWLEDGMENT START FROM SLAVE CS11450 14 28 Doc ID 022634 Rev 2 Q LNBH25L I2C interface protocol 7 ISC interface protocol 7 1 Write mode transmission The LNBH25L interface protocol is made up of a start condition S a chip address byte with the LSB bit R W 0 a register address internal address of the first register to be accessed a sequence of data byte to write in the addressed internal register acknowledge the following bytes if any to be written in successive internal registers a stop condition P The transfer lasts until a stop bit is encountered the LNBH25L as slave acknowledges every byte transfer Figure 10 Example of writing procedure starting with first data address 0x2 a REGISTER ADDRESS CHIP ADDRESS DATA 2 Add 0x3 DATA 3 DATA 4 Add 0x5 DATA 1 Add 0x2 lala ziziz
24. n the overload condition is cleared and a register reading is done After the overload condition is removed normal operation can be resumed in two ways according to the OLR IC bit on the DATA4 register If OLR 1 all VSEL 1 4 bits are reset to O and LNB output Voyz pin is disabled To re enable the output stage the VSEL bits must be set again by the microprocessor and the OLF bit is reset to 0 after a register reading operation If OLR 0 output is automatically re enabled as soon as the overload condition is removed and the OLF bit is reset to 0 after a register reading operation OTF thermal protection and diagnostic The LNBH25L is also protected against overheating when the junction temperature exceeds 150 C typ the step up converter and the linear regulator are shut off the diagnostic OTF bit in the STATUS1 register is set to 1 After the overtemperature condition is removed normal operation can be resumed in two ways according to the THERM C bit on the DATA4 register If THERM 1 all VSEL 1 4 bits are reset to O and LNB output Voyr pin is disabled To re enable the output stage the VSEL bits must be set again by the microprocessor while the OTF bit is reset to O after a register reading operation If THERM 0 output is automatically re enabled as soon as the overtemperature condition is removed while the OTF bit is reset to O after a register reading operation Doc ID 022634 Re
25. o 0 N A Reserved bit All bits reset to O at power on Table 7 Data 2 read write register Register address 0X3 BIT Name Value Description Bit 0 1 22 kHz tone enabled Tone output controlled by the DSQIN pin LSB bay 0 22 kHz tone output disabled Bit 1 N A 0 Reserved Keep to 0 1 DSOIN input pin is set to receive external 22 kHz TTL signal source Bit 2 EXTM 0 DSOIN input pin is set to receive external DiSEqC envelope TTL signal Bit 3 N A 0 Reserved Keep to 0 Bit 4 N A 0 Reserved Keep to 0 Bit 5 N A 0 Reserved Keep to 0 Bit 6 N A 0 Reserved Keep to 0 ee N A 0 Reserved Keep to 0 N A Reserved bit All bits reset to O at power on Doc ID 022634 Rev 2 17 28 ISC interface protocol LNBH25L Table 8 Data 3 read write register Register address 0X4 BIT Name Value Description Bit 0 Rag LSB N A 0 Reserved Keep to O Bit 1 N A 0 Reserved Keep to 0 1 Pulsed Dynamic LNB output current limiting is deactivated Bit 2 PCL 0 Pulsed Dynamic LNB output current limiting is activated Bit 3 N A 0 Reserved Keep to 0 Bit 4 N A 0 Reserved Keep to 0 Bit 5 N A 0 Reserved Keep to 0 Bit 6 N A 0 Reserved Keep to 0 Bit 7 N A 0 Reserved Keep to 0 MSB p N A Reserved bit All bits reset to 0 at power on Table 9 Data 4 read write register Register address 0X5 BIT Name Value Description Bi
26. t 0 ipa LSB N A 0 Reserved Keep to O Bit 1 N A 0 Reserved Keep to 0 Bit 2 N A 0 Reserved Keep to 0 In case of overload protection activation OLF 1 all VSEL 1 4 bits are reset to 1 0 and LNB output Voyr pin is disabled The VSEL bits must be set again by the master after the overcurrent condition is removed OLF 0 Bit 3 OLR at In case of overload protection activation OLF 1 the LNB output Voyr pin is 0 automatically enabled as soon as the overload condition is removed OLF 0 with the previous VSEL bits setting Bit 4 N A 0 Reserved Keep to 0 Bit 5 N A 0 Reserved Keep to 0 If thermal protection is activated OTF 1 all VSEL 1 4 bits are reset to O and 1 LNB output Vout pin is disabled The VSEL bits must be set again by the master after the overtemperature condition is removed OTF 0 Bit 6 THERM In case of thermal protection activation OTF 1 the LNB output Vout pin is 0 automatically enabled as soon as the overtemperature condition is removed OTF 0 with the previous VSEL bits setting Bit 7 ina MSB N A 0 Reserved Keep to O 18 28 N A Reserved bit All bits reset to O at power on SI Doc ID 022634 Rev 2 LNBH25L I2C interface protocol 7 4 Status registers The STATUS 1 2 registers can be addressed only in read mode and provide the diagnostic functions described in the fol
27. tatically simple current clamp or dynamically by the PCL bit of the I2C DATA3 register When the PCL pulsed current limiting bit is set to LOW the overcurrent protection circuit works dynamically as soon as an overload is detected the output current is provided for a Toy time of 90 ms after which the output is set in shutdown for a Torr time of typically 900 ms Simultaneously the diagnostic OLF IC bit of the system register is set to 1 After this time has elapsed the output is resumed for a time Toy At the end of Ton if the overload is still detected the protection circuit cycles again through Torr and Toy At the end of a full Toy in which no overload is detected normal operation is resumed and the OLF diagnostic bit is reset to LOW after a register reading is done Typical Ton Torr time is 990 ms and an internal timer determines it This dynamic operation can greatly reduce the power dissipation in a short circuit condition still ensuring excellent power on startup in most conditions However there may be some cases in which a highly capacitive load on the output can cause a difficult startup when the dynamic protection is chosen This can be solved by initiating any power startup in static mode PCL 1 and then switching to the dynamic mode PCL 0 after a chosen amount of time depending on the output capacitance Also in static mode the diagnostic OLF bit goes to 1 when the current clamp limit is reached and returns LOW whe
28. v 2 ki LNBH25L Pin configuration 3 Pin configuration Figure 5 Pin connections top view 24 23 22 21 20 19 NC GND DSQIN VUP VOUT GND 1 NC GND 18 2 GND VCC 17 3 LX VBYP 16 LNBH25L 4 PGND GND 1115 5 NC NC 14 6 ADDR NC 13 SCL SDA ISEL NC NC NC 7 8 9 10 11 12 autodata Table 2 Pin description Pin n Symbol Name Pin function 3 LX N MOS drain Integrated N channel Power MOSFET drain 4 P GND Power ground Ed converter power ground To be connected directly to the s S F 6 ADDR Address setting Two I C bus addresses available by setting the address pin level voltage See Table 15 7 SCL Serial clock Clock from I2C bus 8 SDA Serial data Bi directional data from to the 1 C bus 9 ISEL C rr nt selection The resistor RSEL connected between ISEL and GND defines the linear regulator current limit threshold Refer to Section 2 4 2 15 18 19 ee 23 GND Analog ground Analog circuits ground To be connected directly to the Epad Needed for internal pre regulator filtering The BYP pin is intended only to connect an external ceramic capacitor Any connection of

ST LNBH25L LNB supply control IC with step-up I C interface handbook

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