ST STM6513 handbook
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1. CH VREF i Three state selector Oscillator AM00374V2 K 10 29 Doc ID 16490 Rev 2 STM6513 Block diagram a STM6513 hookup with RST1 and RST2 bridging the PS hold reset pulse during the microprocessor reset initiated by the STM6513 Smart Reset device Figure4 Typical application diagram Voc PU resistor RST_n RST POWER PS hold PS_hold GPIO1 GPIOn FS Forces PS hold RST2 OD high during reset period AM00375a Figure 5 Timing waveforms POR initiated Smart Reset initiated SRC SRO SR1 i t 210 ms t 210 RST2 OD REC2 210 ms REC 210 ms Factory j programmed RST1 PP by C nEC i REC1 1 S REC1 1 AM00376V2 Doc ID 16490 Rev 2 11 29 Typical operating characteristics STM6513 5 12 29 Typical operating characteristics Figure 6 Smart Reset delay tsnc vs temperature and supply voltage Vcc TSR Vss tenc S 0 20 40 60 Temperature C 5 5V 3 3V 80 100 120 140 AM00632 Doc ID 16490 Rev 2 STM6513 Typical operating characteristics a Figure 7 Output reset timeout period tRec2 vs temperature and supply voltage Vcc trec option E tREC2 ms2. 4 ei tpe rude d 13 Supply current lcc vs temperature and supply voltage Voc 13 Reset voltage Vest falling vs temperature threshold option S 2 925 Vtyp a a sk a sla ka kak anka eee al a kk 14 Input leakage current TSR pin logic low vs temperature and supply voltage Vcc 14 Input leakage current TSR pin logic high vs temperature and supply voltage Voc 15 AC testing input output waveforms KK en 17 TDFN 8 lead 2 x 2x 0 75 mm 0 5 mm pitch 20000 RR RR RR RR KK KK 20 Landing pattern TDFN 8 lead 2 x 2 mm without thermal pad 22 Carrer tape iex ei ik ERE Rl eG DR r a mnn 23 Reeldimensions 0 24 Tapetraile leader hh 25 Pin 1 orlentation west ek ia w 2 h xal Sar dd dr dia W k meleri did peed 25 Package marking area top view i kk kk kk kk kk KK kK KK KK KK KI KK KK kK KK kk kk 27 Doc ID 16490 Rev 2 ky STM6513 Description 1 Description The STM6513 has two separate delayed Smart Reset inputs SRO SR1 which when taken low simultaneously provide three user selectable delayed Smart Reset setup time tsnc options of 2 s 6 s and 10 s These are selected through a three state TSR input pin when connected to ground tsnc 2 s when left open tsnc 6 s when connected to Vcc tenc 10 s all the times are minimum There are
3. 60 40 20 0 20 40 60 80 100 120 140 Temperature C 5 5 V 3 3 V AM00633 Figure 8 Supply current Icc vs temperature and supply voltage Vcc Icc pA 60 40 20 0 20 40 60 80 100 120 140 Temperature C mm 5 5 V 3 3 V AM00634 Doc ID 16490 Rev 2 13 29 Typical operating characteristics STM6513 Figure 9 Reset voltage Vgsrz falling vs temperature threshold option S 2 925 V typ Vast falling V 60 40 20 0 20 40 60 80 100 120 140 Temperature C AM00635 Figure 10 Input leakage current TSR pin logic low vs temperature and supply voltage Vcc ILI TSR LO HAI 0 60 j 2 2 4 140 Temperature C 5 5V 3 3 V 2V AM00636 14 29 Doc ID 16490 Rev 2 ky STM6513 Typical operating characteristics Figure 11 Input leakage current TSR pin logic high vs temperature and supply voltage Vcc IL TSR Hi HA 60 2 4 20 40 60 80 100 120 140 Temperature C mm 5 5 V 3 3 V w 2 V AM00637 Doc ID 16490 Rev 2 15 29 Maximum rating STM6513 6 16 29 Maximum rating Stressing the device above the rating listed in the Table 3 Absolute maximum ratings may cause permanent damage to the d
4. Ay STM6513 Dual push button Smart Reset with dual reset outputs and user selectable setup delay Features Dual Smart Reset push button inputs with user selectable extended reset setup delay by three state input logic tsnc 2 6 10 s min Capacitor adjustable reset pulse duration tRec1 Power on reset m Dual reset output RST1 is active high push pull type RST2 is active low open drain Factory programmable thresholds to monitor Vcc in the range of 1 575 to 4 625 V typ Operating voltage 1 0 V active low output valid to 5 5 V Low supply current 3 pA m Operating temperature industrial grade 40 C to 85 C TDFN8 package 2 mm x 2 mm x 0 75 mm m RoHS compliant June 2010 ew TDFN8 DG 2 mm x 2 mm Applications Doc ID 16490 Rev 2 Mobile phones smartphones e books MP3 players Games Portable navigation devices Any application that requires delayed reset push button s response for improved system stability 1 29 www st com Contents STM6513 Contents 1 Description EEE A E ERE 5 2 Device overview a si kk kk kk b kk ii RR kk kk a kk kk lk k8 7 3 Pin descriptions resi kk kK KK KIR KK kK kK kK kk kk kk kk REG kk lk kk 8 3 1 Power supply Meg kk kk kk kk kk kk eR Rx ed KK KK KK seeds 8 3 2 Ground Vos sussesurt A b0 4404020 EORR ayyuka 8 3 3 Smart Reset inputs SRO SR1 8 3 4 User programmable
5. 9 2009 etc D assembly work week WW 01 to 52 20 WW20 etc E marking area topmark AM00479 ky Doc ID 16490 Rev 2 27 29 Revision history STM6513 13 28 29 Revision history Table 13 Document revision history Date Revision Changes 22 Oct 2009 1 Initial release Updated title Features Applications replaced smart reset by 21 Jun 2010 2 Smart Reset and Smart Reset updated Section 1 Table 1 Section 3 Table 2 Figure 3 Figure 5 Figure 6 Table 3 Table 5to Table 8 Table 11 and Table 12 lt Doc ID 16490 Rev 2 STM6513 Please Read Carefully Information in this document is provided solely in connection with ST products STMicroelectronics NV and its subsidiaries ST reserve the right to make changes corrections modifications or improvements to this document and the products and services described herein at any time without notice All ST products are sold pursuant to ST s terms and conditions of sale Purchasers are solely responsible for the choice selection and use of the ST products and services described herein and ST assumes no liability whatsoever relating to the choice selection or use of the ST products and services described herein No license express or implied by estoppel or otherwise to any intellectual property rights is granted under this document If any part of this document refers to any third party product
6. Vas Supply Ground Doc ID 16490 Rev 2 7 29 Pin descriptions STM6513 3 3 1 3 2 3 3 3 4 3 5 3 6 8 29 Pin descriptions Power supply Vcc This pin is used to provide the power to the Smart Reset device and to monitor the power supply A 0 1 uF decoupling ceramic capacitor is recommended to be connected between Voc and Vgs pins Ground Vss This is the ground for the device and all supplies Smart Reset inputs SRO SR1 Push button Smart Reset inputs Both inputs need to be held active at the same time for at least tspc to activate the reset outputs When only one Smart Reset input is used connect the unused one permanently to Vas User programmable Smart Reset delay TSR pin Used to allow the user to program the setup time before the push buttons action is validated by reset output Controlled by different voltage levels on the TSR pin when connected to ground tsnc 2 s when left open tsnc 6 s when connected to Vec tsnc 10 s all times are minimum TSR is a DC type input intended to be either permanently grounded permanently connected to Vcc or permanently left open If left open for improved system glitch immunity it is strongly recommended to connect a 0 1 uF decoupling ceramic capacitor between the TSR and Vss pins Reset outputs RST1 RST2 Reset outputs RST1 active high push pull type RST2 active low open drain Adjustable output reset timeout period inp
7. 05 40 05 40 05 0 05 30 10 0 05 3000 0 10 0 00 ky Doc ID 16490 Rev 2 23 29 Tape and reel information STM6513 24 29 Figure 16 Reel dimensions 40 mm min acces hole at slot location Full radius Tape slot in core for tape start 25 mm min width G measured at hub AM00443 Table 10 Reel dimensions Tape sizes A max B min C D min N min G T max 8mm 180 7 inches 1 50 13 0 0 20 20 20 60 8 4 2 0 14 40 Doc ID 16490 Rev 2 ky STM6513 Tape and reel information Note Figure 17 Tape trailer leader End Top No components Components 100 mm min No components cover tape TRAILER LEADER gt lt gt lt 160 mm min 400 mm min e Sealed with cover tape gt User direction of feed AM00444 Figure 18 Pin 1 orientation o O O O O 0 0 User direction of feed AM00442 1 Drawings are not to scale 2 Alldimensions are in mm unless otherwise noted Doc ID 16490 Rev 2 25 29 Part numbering STM6513 11 Part numbering Table 11 Ordering information scheme Example STM6513 V E E DG 6 F Device type STM6513 Reset Vcc monitoring threshold voltage Vast L 4 625 V typ falling M 4 375 V T 3 075 V S 2 925 V R 2 625 V Z 2 313 V Y 2 188 V W 1 665 V V 1 575 V Smart Reset setup delay tsnc presence of internal input pull up
8. 3 152 3 014 3 137 V S falling 2 925 2 852 2 998 2 867 2 984 V R falling 2 625 2 559 2 691 2 573 2 678 V Z falling 2 318 2 255 2 371 2 267 2 359 V Y falling 2 188 2 133 2 248 2 144 2 232 V W falling 1 665 1 623 1 707 1 632 1 698 V V falling 1 575 1 536 1 614 1 544 1 607 V 7974 Doc ID 16490 Rev 2 19 29 Package mechanical data STM6513 8 20 29 Package mechanical data In order to meet environmental requirements ST offers these devices in different grades of ECOPACK packages depending on their level of environmental compliance ECOPACK specifications grade definitions and product status are available at www st com ECOPACK is an ST trademark Figure 13 TDFN 8 lead 2 x 2 x 0 75 mm 0 5 mm pitch 5 lt gt gt A B PIN 1 INDEX AREA Le A 030 C 2x ZZ Z 9 10 G 2x TOP VIEW o 10 C A A1 C both V SEATING PLANE SIDE VIEW o o8 c PERDAN e PIN 1 INDEX AREA lt gt b 1 Ja 0 100 C A B K up Pint ID Z2 S i rd T A i 8 5 BOTTOM VIEW TDFN 8L Doc ID 16490 Rev 2 ky STM6513 Package mechanical data 3 Table 7 TDFN 8 lead 2 x 2 x 0 75 mm 0 5 mm package mechanical data Dimension mm Dimension inches Symbol Min Nom Max
9. Min Nom Max A 0 70 0 75 0 80 0 028 0 030 0 031 A1 0 00 0 02 0 05 0 000 0 001 0 002 b 0 15 0 20 0 25 0 006 0 008 0 010 D 1 9 2 00 2 1 0 075 0 079 0 083 BSC E 1 9 2 00 2 1 0 075 0 079 0 083 BSC 2 j i e 0 50 0 020 L 0 45 0 55 0 65 0 018 0 022 0 026 Doc ID 16490 Rev 2 21 29 Package footprint STM6513 9 22 29 Package footprint Figure 14 Landing pattern TDFN 8 lead 2 x 2 mm without thermal pad Ji Ti I AM00441 Table 8 Parameter for landing pattern TDFN 8 lead 2 x 2mm package Dimension mm Parameter Description Min Nom Max L Contact length 1 05 1 15 b Contact width 0 25 0 30 E Max land pattern Y direction 2 85 E1 Contact gap spacing 0 65 D Max land pattern X direction 1 75 Contact pitch 0 5 Doc ID 16490 Rev 2 STM6513 Tape and reel information 10 Tape and reel information Figure 15 Carrier tape Po T yf Tap cover tape W lt Ko Center lines of cavity Py US e Sa pn ag ge oe un ts ee Sa ge a dese feed a a EL ea gt User direction of feed AM03073v2 Table 9 Carrier tape dimensions Bulk Package W D E Po P2 F Ao Bo Ko P4 T Unit qty 8 00 1 50 1 75 4 00 2 00 3 50 2 30 2 30 1 00 4 00 0 250 TDFN8 0 30 0 10 o 0 10 0 10 0
10. two reset outputs both going active simultaneously after both the Smart Reset inputs were held active for the selected tsnc delay time The first reset output RST1 is active high push pull the second reset output RST2 is active low open drain requiring an external pull up resistor The duration of the output reset pulses is independently programmable tagc is user programmable by external capacitor Cingc treco is factory programmed to 210 ms typ with the option of 360 ms typ Additionally the Vcc is monitored and if it drops below the selected Vast threshold both the reset outputs go active and remain so while Vcc is below the Vast threshold plus the defined duration of the reset pulse taec on each output Smart Reset devices The Smart Reset device family STM65xx provides a useful feature that ensures inadvertent short reset push button closures do not cause system resets This is done by implementing extended Smart Reset input delay tsnc Once the valid Smart Reset input levels and setup delay are met the device generates an output reset pulse with user programmable timeout period trec The Smart Reset inputs can be also connected to the applications interrupt to allow the control of both the interrupt pin and the hard reset functions If the push buttons are closed for a short time the processor is only interrupted If the system still does not respond properly holding the push buttons for the extended setup time tgac
11. 8 Possible Voc voltagethresholds 19 TDFN 8 lead 2 x 2 x 0 75 mm 0 5 mm package mechanical data 21 Parameter for landing pattern TDFN 8 lead 2 x 2 mm package 22 Carriertapedimensions teeta 23 Reeldimensions iin 24 Orderinginformationscheme KI KIK keen KOK kK KOK KK kk 8 26 Package Marking xx es a ya ORE Be Kak ik a elin Res lk a 27 Document revision history ee kal 28 Doc ID 16490 Rev 2 3 29 List of figures STM6513 List of figures Figure 1 Figure 2 Figure 3 Figure 4 Figure 5 Figure 6 Figure 7 Figure 8 Figure 9 Figure 10 Figure 11 Figure 12 Figure 13 Figure 14 Figure 15 Figure 16 Figure 17 Figure 18 Figure 19 4 29 LOGIC diagram uud de so W0 sk d Reb degere wan d4 d k b Pe Wr d dob eoe Poco e d en ee 6 P M connections de sr bark mc kx p eee edad owed ka n AD KKD Fre EKAS NUR 6 Block diagram 20 eds a eek ee ed UE ea ee Pa ee ebd a be E E d 10 Typical application diagram s xil ka ak retiree Ak e lA ki III 11 Timingwaveforms mh 11 Smart Reset delay tsnc vs temperature and supply voltage Vcc ICQ 12 Output reset timeout period taecs vs temperature and supply voltage Voc REC option E esee irre xb e hb Rene Rem xu d r r
12. Parameter Value Unit Voc supply voltage 1 0 to 5 5 V Ambient operating temperature TA 40 to 85 C Input rise and fall times lt 5 ns Input pulse voltages 0 2 to 0 8 Vcc V Input and output timing ref voltages 0 3 to 0 7 Vec Figure 12 AC testing input output waveforms 0 8 Voc XX 0 7 Voc 0 2 Voc A 0 3Vcc Doc ID 16490 Rev 2 17 29 DC and AC parameters STM6513 Table 5 DC and AC characteristics Symbol Parameter Test conditions Min Typ Max Units Reset output valid active low 1 0 5 5 V Vcc Supply voltage range Reset output valid active high 1 2 5 5 V M T Voc 3 0 V TSR left open 3 5 UA I upply current uu CC Voc 5 0 V TSR left open 4 6 UA Voc gt 4 5 V sinking 3 2 mA 0 3 V VoL n output voltage y gt 3 3 V sinking 2 5 mA 0 3 V Vcc 2 1 0 V sinking 0 1 mA 0 3 V Voc gt 4 5 V IsoURCE 0 8 mA 0 8 Voc V Reset output voltage Vou high RST1 Voc gt 2 7 V ISOURCE 0 5 mA 0 8 Voc V Voc gt 1 2 V ISOURCE 0 05 mA 0 8 Voc V Fixed voltage trip 40 to 85 C VRST 2 596 VRST VRST 2 5 V point for Voc VRST monitoring refer to o o 9 25 C VRST 2 096 VnsT Vast 2 0 V Table 6 L M 0 5 V Hysteresis of V men RST s R Z Y W V 1 4 Vcc falling from Vast 100 mV Voc to reset delay o or 100 mV at 10 mV ys Sp HS Output reset timeout Option E 140 210 280 ms RECe period on RST2 i fa
13. Smart Reset delay TSR pin 8 3 5 Reset outputs RST1 RST2 kk kk kk kk kK kK KK KK KK KIR KIR KK KIR KK KK k 8 3 6 Adjustable output reset timeout period input pin TRECApJ 8 4 Block diagram 5 iaa adum ew e ei ba ele kk kk kk dea ka 10 5 Typical operating characteristics 12 6 Maximum rating e dC RR TR kk kk kk kk kk kK E RC NR CR RR kk ka 16 7 DCandACparameters aaa 17 8 Packagemechanicaldata ii 20 9 Package footprint sche tess cac kk kK KK KK KK kk kk kk kk kk kk RR ni 22 10 Tapeandreelinformation aaa 23 11 Par ti D R e ni n kk kk kk kK a km me k8 26 12 Package marking information 27 13 Revision history s men kk kk kk kk kk kk kk kk kk kk kk QR RR e a ic 28 2 29 Doc ID 16490 Rev 2 rezi STM6513 List of tables List of tables Table 1 Table 2 Table 3 Table 4 Table 5 Table 6 Table 7 Table 8 Table 9 Table 10 Table 11 Table 12 Table 13 Signal names bime oe Xewa n k k h n d k aland bbe pews eee n W d mec esee d er 4 7 tREc1 programmed byanidealexternalcapacitor 9 Absolute maximum ratings u kk kk kk kk kk KK KK KK KI KK KIRI KK KIR KI KIR KK KK KK KK kk e 16 Operating and measurementconditions 17 DC and AC characteristics 0 00 1
14. causes hard reset of the processor through the reset outputs The Smart Reset feature helps significantly increase system stability The STM65xx family of Smart Reset devices consists of low current microprocessor reset circuits targeted at applications such as MP3 players navigation smartphones or mobile phones generally any application that requires delayed reset push button s response for improved system stability The STM65xx devices feature single or dual Smart Reset inputs SR The delayed Smart Reset setup time tsr options of 2 s 6 s and 10 s all min are adjustable by an external capacitor on the SRC pin or selectable by three state logic The delayed setup period ignores switch closures shorter than tsgc thus preventing unwanted resets The STM65xx devices have active low optionally active high open drain reset RST output s with or without internal pull up resistor or push pull as output options with factory programmed or capacitor adjustable or push buttons defined output reset pulse duration with or without power on reset function Some devices also have an undervoltage monitoring feature the reset output is also asserted when the monitored supply voltage Vcc drops below the specified threshold The reset output remains asserted for the reset timeout period tagc after the monitored supply voltage goes above the specified threshold Doc ID 16490 Rev 2 5 29 Description STM6513 6 29 Figure 1 Log
15. ctory programmed Option F 240 360 480 ms User adjustable t output reset timeout 10 000 x 15 000 x 20 000 x in RE i C1 period on RST1 Ctrec HF Cirec HF Cirec HF Refer to Table 2 18 29 Doc ID 16490 Rev 2 ky STM6513 DC and AC parameters Table 5 DC and AC characteristics continued Symbol Parameter Test conditions Min Typ Max Units Smart Reset inputs SRx TSR Vss 2 2 5 3 S tsnc Smart Reset delay TSR floating 6 7 5 9 S TSR Vcc 10 12 5 15 S SRO SR1 input z VIL voltage low Vss 0 3 0 3 Voc V SRO SR1 input Vil voltage high 0 7 Vcc s v Input glitch C ds to th tual t t immunity orresponas to the actual tsnc SRC S Input leakage ILSR current SRO SR1 1 1 HA pins Input leakage _ ILICTSR current TSR pin 5 HA Valid for ambient operating temperature Ta 40 to 85 C Vec 1 0 V to 5 5 V except where noted Typical value is at 25 C and Vgc 3 3 V unless otherwise noted For devices with Vnsr lt 3 0 V Guaranteed by design Qu de oou a Input glitch immunity is equal to tsgc when both SR inputs are low otherwise infinite Table 6 Possible Vcc voltage thresholds mn i j 2 5 40 C to 85 C 2 0 25 C i threshold Vrsr m Min Max Min Max idi L falling 4 625 4 509 4 741 4 533 4 718 V M falling 4 375 4 266 4 484 4 288 4 463 V T falling 3 075 2 998
16. evice These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not implied Exposure to absolute maximum rating conditions for extended periods may affect device reliability Refer also to the STMicroelectronics SURE Program and other relevant quality documents Table 3 Absolute maximum ratings Symbol Parameter Value Unit TsrG Storage temperature Vcc off 55 to 150 C Tai p Lead solder temperature for 10 seconds 260 C Oya Thermal resistance junction to ambient TDFN8 149 0 C W Vio Input or output voltage 0 3 to 5 5 V Vec Supply voltage 0 3 to 7 V 1 Reflow at peak temperature of 260 C The time above 255 C must not exceed 30 s 2 For RST1 0 3 to Voc 0 3 V only Doc ID 16490 Rev 2 lt STM6513 DC and AC parameters 7 DC and AC parameters This section summarizes the operating measurement conditions and the DC and AC characteristics of the device The parameters in the Table 5 DC and AC characteristics that follow are derived from tests performed under the Measurement Conditions summarized in Table 4 Operating and measurement conditions Designers should check that the operating conditions in their circuit match the operating conditions when relying on the quoted parameters Table 4 Operating and measurement conditions
17. ic diagram Voc Vss AM00372 Figure 2 Pin connections RST1 O Vss l 2 SR1 l 3 RST2 4 8 Vcc 7 SRO 6 TRECap 5 TSR AMO00373 Doc ID 16490 Rev 2 K STM6513 Device overview 2 3 Device overview Table 1 Signal names Symbol Input output Description RST1 Output First reset output active high push pull RST2 Output Second reset output active low open drain SRO Input Primary push button Smart Reset input Active low SR1 Input Secondary push button Smart Reset input Active low A Three state Smart Reset input delay setup control When connected to ground tsnc 2 s when left open tenc 6 s when connected to Voc tsnc 10 s all times are minimum TSR is a DC type input TSR Input intended to be either permanently grounded permanently connected to Vcc or permanently left open If left open for improved system glitch immunity it is strongly recommended to connect a 0 1 uF decoupling ceramic capacitor between the TSR and Vgg pins Input pin for taec reset pulse duration adjustment Connect an TRECapy Input external capacitor Cingc to this pin to determine tpgc tagco is factory programmed Positive supply voltage input Power supply for the device and an input V Suppl for the monitored supply voltage A 0 1 uF decoupling ceramic es PPly capacitor is recommended to be connected between Vcc and Vss pins
18. on all Smart Reset inputs SRO SR1 E 2 or 6 or 10 s min user programmed three state no input pull up Outputs type RST1 active high push pull RST2 active low open drain no pull up Reset timeout period trec E treci user programmable external capacitor tRec2 factory programmed 210 ms typ F treci user programmable external capacitor taece factory programmed 360 ms typ Package DG TDFN8 2 x 2 x 0 75 mm 0 5 mm pitch Temperature range 6 40 C to 85 C Shipping method F ECOPACK package tape and reel For other options voltage threshold values etc or for more information on any aspect of this device please contact the ST sales office nearest you 26 29 Doc ID 16490 Rev 2 K STM6513 Package marking information 12 Package marking information Table 12 Package marking Full part number Pus Bessi VRST Nei tRECI RST2 output re Topmark control inputs type type programming type Option STM6513SEIEDG6F TSR AL NPU S AH PP CinEc AL OD NPU E 9SH STM6513REIEDG6F TSR AL NPU R AH PP Cirec AL OD NPU E 9RH Note AL active low AH active high PP push pull OD open drain PU internal pull up resistor NPU no internal pull up resistor Figure 19 Package marking area top view Topmark A dot pin 1 reference B assembly plant P C assembly year Y 0 9
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20. ty of ST ST and the ST logo are trademarks or registered trademarks of ST in various countries Information in this document supersedes and replaces all information previously supplied The ST logo is a registered trademark of STMicroelectronics All other names are the property of their respective owners 2010 STMicroelectronics All rights reserved STMicroelectronics group of companies Australia Belgium Brazil Canada China Czech Republic Finland France Germany Hong Kong India Israel Italy Japan Malaysia Malta Morocco Philippines Singapore Spain Sweden Switzerland United Kingdom United States of America www st com ky Doc ID 16490 Rev 2 29 29
21. ut pin TRECApJ The output reset timeout period taec on RST1 is adjustable by connecting an external capacitor Cingc to the TRECap pin Calculated taec and Ciggc examples are given in Table 2 Refer also to Table 5 Doc ID 16490 Rev 2 ky STM6513 Pin descriptions K Table 2 tngc1 programmed by an ideal external capacitor Cirec value pF trec1 ms D Closest common Min Typ Max Cirec value HF 0 001 10 15 20 0 001 0 002 20 30 40 0 0022 0 01 100 150 200 0 01 0 014 140 210 280 0 015 0 028 280 420 560 0 027 0 056 560 840 1120 0 056 0 112 1120 1680 2240 0 12 1 At25 C Example calculations based on an ideal capacitor During application design and component selection it should be considered that the current flowing into the external taec programming capacitor Cingc is on the order of 100 nA therefore a low leakage capacitor ceramic or film capacitor should be used and placed as close as possible to the TRECAp pin Also an adequate low leakage PCB environment should be ensured to prevent tpec accuracy from being affected A recommended minimum value of Cire is 0 001 UF intervals to fully discharge Cingc so that the next taec is as specified Doc ID 16490 Rev 2 In case of repeated activations of the internal tagc timer an interval of 10 ms min is needed between trec 9 29 Block diagram STM6513 4 Block diagram Figure 3 Block diagram
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ST STM6513 handbook