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ST PM6670S handbook

1. Table 18 Suitable dual MOSFETs Manufacturer Type Rpson m Gate charge nC Rated reverse voltage V ST STS8DNH3LL 25 10 30 IR IRF7313 46 33 30 8 1 5 Diode selection A rectifier across the synchronous switch is recommended The rectifier works as a voltage clamp across the synchronous rectifier and reduces the negative inductor swing during the dead time between turning the high side MOSFET off and the synchronous rectifier on Moreover it increases the efficiency of the system Choose a schottky diode as long as its forward voltage drop is very little 0 3 V The reverse voltage should be greater than the maximum input voltage Vijnmax and a minimum recovery reverse charge is preferable Table 19 shows some evaluated diodes Table 19 Evaluated recirculation rectifiers Forward Rated reverse Manufacturer Type voltage V voltage V Reverse current uA ST STPS1L30M 0 34 30 0 00039 ST STPS1L30A 0 34 30 0 00039 46 54 Doc ID 14432 Rev 4 ky PM6670S Application information 8 1 6 VDDG current limit setting The valley current limit is set by Rcsns and must be chosen to support the maximum load current The valley of the inductor current l yajey IS Eguation 45 Al Lvalley lLoap max The output current limit depends on the current ripple as shown in Figure 41 Figure 41 Valley current limit waveforms Inductor current Current Inductor current
2. 23 7 1 2 Output ripple compensation and loop stability 24 7 1 3 Pulse skip and no audible pulse skip modes 28 714 Mode of operation selection 30 7 1 5 Current sensing and current limit 31 7 1 6 POR UVLO and soft start 32 7 1 7 Power Good signal 0 AC CSCS KENE eee eee 33 7 1 8 VDDQ output discharge 34 7 1 9 Gate drivers so scce PE je ka p tee 35 7 1 10 Reference voltage and bandgap 35 7 1 11 Over voltage and under voltage protections 36 7 1 12 Device thermal protection 36 7 2 VTTREF buffered reference and VTT LDO section 37 7 2 1 VTT and VTTREF Soft Start 37 7 2 2 VTTREF and VTT outputs discharge 37 2 54 Doc ID 14432 Rev 4 ky PM6670S Contents 7 3 S8and S5 power management pins 38 8 Application information 39 8 1 External components selection 39 8 1 1 Inductor selection 41 8 1 2 Input capacitor selection 42 8 1 3 Output capacitor selection 43 8 1 4 MOSFETs s
3. PM6670S Block diagram 6 Block diagram Figure 27 Functional and block diagram VREF VTTSNS LDOIN VTTGND 1 236V Bandgap VTTREF Level a TI CO PHASE Anti Cross Mesi _ vcc O BOOT Q Es LGATE PGND Zero Crossing amp Current Limit CSNS COMP UVP OVP SGND QO AVCCO SWEN TD NTD BEN HIZ DDRSELO Thermal Shutdown DSCG CONTROL LOGIC L Q VSNS O O O S3 S5 MODE Table 7 Legend SWEN Switching controller enable TD Tracking discharge enable NTD Non tracking discharge enable BEN VTTREF buffer enable HIZ LDO high impedance mode enable ky Doc ID 14432 Rev 4 19 54 Device description PM6670S 7 20 54 Device description The PM6670SS is designed to satisty DDR2 3 power supply requirements combining a synchronous buck controller a 15 mA buffered reference and a high current low drop out LDO linear regulator capable of sourcing and sinking up to 2 Apk The switching controller section is a high performance pseudo fiked freguency constant on time COT based regulator specifically designed for handling fast load transient over a wide range of input voltages The DDR2 3 supply voltage VDDO can be easily set to 1 8 V DDR2 or 1 5 V DDR3 without additional c
4. Figure 17 1 8 A to 1 8 A VTT load transient 0 9 V Figure 18 0 mA to 9 mA VTTREF load transient 0 9 V Tek Stopped Single Seq 1 Acqs 26 May 06 15 34 52 a YIT 0 9 Pem AE 1 L HH i E NTT L 184 i Li ku i cl iaa Peria f Chi 500m Bw M 400ps 125MS s 80 0nsibt Ch4 20A A Ch4 200mA 1 Acas 29 May 06 13 51 31 Tek Stopped Single Seq isms dum VTTREF 0 9 M 200ys 25 0MS s 40 0ns4pt Ch4 10 0m4 Q Bw A Chi 887mY 16 54 Doc ID 14432 Rev 4 4 PM6670S Typical operating characteristics Figure 19 Non tracking soft discharge Figure 20 Tracking fast discharge LDOIN VDDQ 22 Jun 06 10 48 26 TTTTTUITT i T T pe WA Aa bcd ect i KAA AE ea a Chi 500mY Bw Ch2 500mY Bw M 2 0ms 12 5MS s 80 0nsipt Ch3 500mY Bw Ch4 soy Bw A Ch4 x 25V Tek Run Hi Res 21 Acgs 22 Jun 06 10 48 36 i t H in ih yoo T T VITREF VIT t I VDDQ 400mv f a gt T i 5355 I 1 F 1 E 1 ye s L 7 ji L Lax RARA PAPA KALANIWA SAPA EE E AAA AL Lac abc o Chi 500mY Bw Ch2 500mY Bw M 400ys 62 5MS s 16 0nsipt Ch3 500my Bw Chg 50V Bw A Ch4 25V Figure 21 0 A to 10 A VDDQ load transient PWM Figure 22 10 A to 0 A VDDQ load transient PWM Tek Stopped Single Seq 1 Aegs RIR T 22 Jun 06 10 22 48 YDDQ 1 8V IWDDO LI caasa Lac fi M 20 0ps 25 0MS s
5. The PM6670S uses a pseudo fixed frequency constant on time COT controller as the core of the switching section It is well known that the COT controller uses a relatively simple algorithm and uses the ripple voltage derived across the output capacitor s ESR to trigger the on time one shot generator In this way the output capacitors ESR acts as a current sense resistor providing the appropriate ramp signal to the PWM comparator Nearly constant switching frequency is achieved by the system s loop in steady state operating conditions by varying the on time duration avoiding thus the need for a clock generator The on time one shot duration is directly proportional to the output voltage sensed at VSNS pin and inversely proportional to the input voltage sensed at the VOSC pin as follows Equation 1 V Ton 7 Kosc V where Kosc is a constant value 130 ns typ and is the internal propagation delay 40ns typ The one shot generator directly drives the high side MOSFET at the beginning of each switching cycle allowing the inductor current to increase after the on time has expired an Off Time phase in which the low side MOSFET is turned on follows The off time duration is solely determined by the output voltage when lower than the set value i e the voltage at VSNS pin is lower than the internal reference Vg 0 9 V the synchronous rectifier is turned off and a new cycle begins Figure 26 Figure 28 Inductor current and ou
6. i7 PM6670S Complete DDR2 3 memory power supply controller Features m Switching section VDDQ 4 5 V to 28 V input voltage range 0 9 V 1 Yo voltage reference 1 8 V DDR2 or 1 5 V DDR3 fixed output voltages 0 9 V to 2 6 V adjustable output voltage 1 237 V 1 reference voltage available Very fast load transient response using constant on time control loop No Rgense Current sensing using low side MOSFET s Rps oN Negative current limit Latched OVP and UVP Soft start internally fixed at 3 ms Selectable pulse skipping at light load Selectable no audible 33 kHz pulse skip mode Ceramic output capacitors supported Output voltage ripple compensation m VTTLDO and VTTREF 2 Apk LDO with foldback for VTT Remote VTT sensing High Z VTT output in S3 Ceramic output capacitors supported 15 mA low noise buffered reference VFQFPN 24 4x4 Description The device PM6670S is a complete DDR2 3 power supply regulator designed to meet JEDEC specifications It integrates a constant on time COT buck controller a 2 Apk sink source low drop out regulator and a 15 mA low noise buffered reference The COT architecture assures fast transient response supporting both electrolytic and ceramic output capacitors An embedded integrator control loop compensates the DC voltage error due to the output ripple The 2
7. 40 Onsipt Ch4 5 04 Q Bw A Ch4 22A Tek Stopped Single Seq 1 Acgs 22 Jun 06 10 23 21 rrr rer AA rT3 TTC T ELIO i i t t 7 T E YDDQ 1 8V hE ill i AMI WO Tar T 1 i HAH HHH j iia E F F Wong E atiriitiiiil L 1 i iia Tank race aca Chi 200mV Bw M 20 0ps 25 0MSis 40 0ns pt Ch4 504 Q Bw A Ch4 224 Doc ID 14432 Rev 4 17 54 Typical operating characteristics PM6670S Figure 23 0 A to 10 A VDDQ Figure 24 10 A to 0 A VDDQ load transient pulse skip load transient pulse skip Tek Slopped Single seq Those r 22 Jun 06 10 24 38 Tek Preview Single Seq 0 Acgs 22 Jun 06 10 26 04 E x E YODO 1 84 i i vVDD0 1 8y opa i i asl m 1 p aa kaa Heud Ilis pa sac Enn m bail La AAA l Tr uix Dis id Li Chi 200m Bw M20 0us25 0MS s 40 0nsipt Ch 200my Bw M 100ps 5 0MSis 200nsiot Ch4 5 04 Q Bw A Ch4 22A Ch4 50A Q Bw A Ch4 X 2 2A Figure 25 Over voltage protection Figure 26 Under voltage protection VDDQ 1 8 V VDDQ 1 8 V Tek X Stopped Single Seq Y 1 Acgs 22 Jun 06 10 54 21 Tek Preview Hi Res 0 Acgs 22 Jun 06 11 02 27 I T T T I b RED T E F E t 3 YTT YTTREF T YTTREF i YODO 400mY Lig 4 Chi S00m Bw Ch2 S00my Bw M40 0ps 625MS s 1 6ns pt Chi 500mY Bw cha 500mVv Bw M 4 Oms 125MS 80 Det Ch3 S00 Bw A Chi x 15v Ch3 500mY Bw A Chl x 14V 18 54 Doc ID 14432 Rev 4 ky
8. 8 m 0 c t F 0 0 001 0 01 0 1 1 10 0 001 0 01 0 1 4 40 Output current A Output current A Figure 5 Switching frequency vs Figure 6 Switching frequency vs input voltage 1 8 V input voltage 1 5 V 500 500 450 450 s 400 400 H 360 3 350 H pop 300 3 250 25 200 200 150 i 150 0 0 5 0 10 0 15 0 20 0 25 0 30 0 0 0 5 0 40 0 45 0 20 0 25 0 30 0 Input voltage V Input voltage V Figure 7 VDDQ line regulation 1 8 V 7 A Figure 8 VDDQ line regulation 1 5 V 7 A 1 8009 1 4980 dan 1 4975 Forced PWM 1 4970 Forced PWM 1 7980 No Audible P S 2 No Audible P S Pulse Skip g 1 4965 Pulse Skip 4 7970 9 44960 E deed 14955 1 4950 1 7950 1 4945 1790 1 4940 i 0 0 5 0 10 0 15 0 20 0 25 0 30 0 0 0 5 0 40 0 45 0 20 0 25 0 30 0 Input voltage V Input voltage V 14 54 Doc ID 14432 Rev 4 ky PM6670S Typical operating characteristics Figure 9 VDDQ load regulation 1 8 V Figure 10 VDDG load regulation 1 5 V 1 860 T 1 530 S 1 850 Forcea pwm 1 520 ni Forced PWM d No Audible P S a No Audible P S 2 1 840 PSP Skip 1 510 Pulse Skip 9 1 830 1 500 1 4804 1 810 BH Ep 1 800 1 470 0 001 0 01 0 1 1 10 aid 0 01 D 1 10 Output current A Output current A Figu
9. 4TPE150MI 220 4V 18 4TPC220M 220 4V 40 HITACHI TNCB OE227MTRYF 220 2 5V 25 MOSFETSs selection In a notebook application power management efficiency is a high level reguirement Power dissipation on the power switches becomes an important factor in the selection of switches Losses of high side and low side MOSFETs depend on their working condition Considering the high side MOSFET the power dissipation is calculated as Eguation 39 Pohighside Feonduction P switching Maximum conduction losses are approximately given by Equation 40 Vout 2 Peonduction Rpson lLOAD MAX IN min Doc ID 14432 Rev 4 ky PM6670S Application information where Rpson is the drain source on resistance of the control MOSFET Switching losses are approximately given by Eguation 41 Al Al Vin Loan max oe ton few Min Loan max EE tor fsw Pswitching E 2 F 2 where toy and torr are the turn on and turn off times of the MOSFET and depend on the gate driver current capability and the gate charge Qgate A greater efficiency is achieved with low Rpgon Unfortunately low Rpson MOSFETs have a great gate charge As general rule the Rpson X Qgate product should be minimized to find out the suitable MOSFET Logic level MOSFETs are recommended as long as low side and high side gate drivers are powered by Vycc 5 V The breakdown voltage of the MOSFETs Verpss must be greater than the maximum in
10. 6 Q typ in order to prevent undesired ignition of the low side MOSFET due to the Miller effect Reference voltage and bandgap The 1 237 V internal bandgap reference has a granted accuracy of 1 over the 0 C to 85 C temperature range The VREF pin is a buffered replica of the bandgap voltage It can supply up to 100 uA and is suitable to set the intermediate level of MODE DDRSEL and DSCG multifunction pins A 100 nF min bypass capacitor toward SGND is required to enhance noise rejection If VREF falls below 0 8 V typ the system detects a fault condition and all the circuitry is turned OFF An internal divider derives a 0 9 V 1 voltage Vr from the bandgap This voltage is used as a reference by the switching regulator output The over voltage protection the under voltage protection and the power good signal are also referred to Vr Doc ID 14432 Rev 4 35 54 Device description PM6670S 71 11 71 12 36 54 Over voltage and under voltage protections When the switching output voltage is about 115 of its nominal value a latched over voltage protection OVP occurs In this case the synchronous rectifier immediately turns on while the high side MOSFET turns OFF The output capacitor is rapidly discharged and the load is preserved from being damaged The OVP is also active during the soft start Once an OVP has occurred a toggle on S5 pin or a power on reset is necessary to exit from the latched state Whe
11. assure system stability and jitter free operations see output capacitor selection paragraph The product of the output capacitor s ESR multiplied by the inductor ripple current must be taken into consideration A good trade off between the transient response time the efficiency the cost and the size is choosing the inductance value in order to maintain the inductor ripple current between 20 and 50 usually 40 of the maximum output current The maximum inductor ripple current Al max Occurs at the maximum input voltage Given these considerations the inductance value can be calculated with the following expression Equation 29 L Vin Vout Vout fsw All Vw where fsw is the switching frequency Vin is the input voltage Vour is the output voltage and Al is the inductor ripple current Once the inductor value is determined the inductor ripple current is then recalculated Equation 30 VNMAX Vout Vout fsw L Viu MAX Al Max The next step is the calculation of the maximum r m s inductor current Equation 31 Al max y I I 24 L RMS li LOAD MAX 12 The inductor must have an r m s current greater than I Rms in order to assure thermal stability Then the calculation of the maximum inductor peak current follows Equation 32 Ali max 2 lL Peak Loapmax lL peak Is important in inductor selection in term of its saturation current Doc ID 14432 Rev 4 41 54 Applica
12. greater frequencies mean smaller inductances In notebook applications real estate solutions i e low profile power inductors are mandatory also with high saturation and r m s currents e Efficiency switching losses are proportional to the frequency Generally higher frequencies imply lower efficiency Even if the switching frequency is theoretically independent from battery and output voltages parasitic parameters involved in power path like MOSFETs on resistance and inductor DCR introduce voltage drops responsible for a slight dependence on load current In addition the internal delay is due to a light dependence on input voltage Table 12 Typical values for switching frequency selection R1 ko R2 ko Approx switching frequency kHz 330 11 250 330 13 300 330 15 350 330 18 400 330 20 450 330 22 500 40 54 Doc ID 14432 Rev 4 ki PM6670S Application information 8 1 1 Inductor selection Once the switching freguency has been defined the inductance value depends on the desired inductor ripple current Low inductance value means great ripple current that brings poor efficiency and great output noise On the other hand a great current ripple is desirable for fast transient response when a load step is applied High inductance brings higher efficiency but the transient response is critical especially if Vinmin gt Vout is small Moreover a minimum output ripple voltage is necessary to
13. mode selection Refer to Section 7 1 8 VDDQ output discharge on page 34 for tracking non tracking discharge or no discharge options Switching controller enable Connect to S5 system status signal to meet SO 13 S5 S5 power management states compliance See Section 7 3 S3 and S5 power management pins on page 38 S5 pin can t be left floating Linear regulator enable Connect to S3 system status signal to meet S0 S5 14 S3 power management states compliance See Section 7 3 S8 and S5 power management pins on page 38 S3 pin can t be left floating Power Good signal open drain output High when VDDQ output voltage is 13 his within 10 of nominal value 16 PGND Power ground for the switching section 17 LGATE Low side gate driver output 6 54 Doc ID 14432 Rev 4 ky PM6670S Pin settings Table 2 Pin functions continued N Pin Function 18 VCC 5 V low side gate driver supply Bypass with a 100 nF capacitor to PGND Current sense input for the switching section This pin must be connected 19 CSNS through a resistor to the drain of the synchronous rectifier Rpson sensing to set the current limit threshold 20 PHASE Switch node connection and return path for the high side gate driver 21 HGATE High side gate driver output 22 BOOT Bootstrap capacitor connection Positive supply input of the high side gate driver Linear regulator input Connect to VDDQ in normal configu
14. to avoid or smooth output voltage overshoot during a load transient When the pulse skip mode is entered the clamping range is automatically reduced to 60 mV in order to enhance the recovering capability In the ripple amplitude is larger than 150 mV an additional capacitor CFILT can be connected between the COMP pin and ground to reduce ripple amplitude otherwise the integrator will operate out of its linearity range This capacitor is unnecessary for most of applications and can be omitted Doc ID 14432 Rev 4 ky PM6670S Device description The design of the external feedback network depends on the output voltage ripple If the ripple is higher than approximately 20 mV the correct CINT capacitor is usually enough to keep the loop stable The stability of the system depends firstly on the output capacitor zero frequency The following condition must be satisfied Equation 6 k few gt K fout D C ESR Vout where k is a fixed design parameter k gt 3 It determines the minimum integrator capacitor value Equation 7 9m Vr f Vout 27 E kau where gm 50 us is the integrator trans conductance Cnr gt In order to ensure stability it must be also verified that Equation 8 Om Vr Cint gt i 2T four Vout If the ripple on the COMP pin is greater than the integrator 150 mV the auxiliary capacitor CriLr can be added If q is the desired attenuation factor of the output ripple Cr is g
15. 10 4 Updated Table 2 on page 6 Table 6 on page 10 Section 7 1 on page 21 Figure 30 on page 23 and Section 7 1 5 on page 31 Doc ID 14432 Rev 4 53 54 PM6670S Please Read Carefully Information in this document is provided solely in connection with ST products S TMicroelectronics NV and its subsidiaries ST reserve the right to make changes corrections modifications or improvements to this document and the products and services described herein at any time without notice All ST products are sold pursuant to ST s terms and conditions of sale Purchasers are solely responsible for the choice selection and use of the ST products and services described herein and ST assumes no liability whatsoever relating to the choice selection or use of the ST products and services described herein No license express or implied by estoppel or otherwise to any intellectual property rights is granted under this document If any part of this document refers to any third party products or services it shall not be deemed a license grant by ST for the use of such third party products or services or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoever of such third party products or services or any intellectual property contained therein UNLESS OTHERWISE SET FORTH IN ST S TERMS AND CONDITIONS OF SALE ST DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY WITH RESPECT TO THE USE AN
16. 300 mV 650 750 850 DDRSEL ton On time duration high ns gh VOSC 500 mV 390 450 510 Vvsns 7 2 V OFF time SMPS lOFFMIN Minimum Off time 300 350 ns Voltage reference Voltage accuracy 4 5 V Viu 25 V 1 224 1 237 1 249 V Load regulation 50 A lt lypggr lt 50 pA 4 4 mV Undervoltage lockout fault 800 threshold a Tas TJ All parameters at operating temperature extremes are guaranteed by design and statistical analysis not production tested 10 54 Doc ID 14432 Rev 4 ki PM6670S Electrical characteristics Table 6 Electrical characteristics continued Values Symbol Parameter Test condition Unit Min Typ Max VDDG output MODE connected to AVCC VDDQ output voltage DDR3 ODRSEL tied to SGND No load 1s 7 V VDDO VDDQ output voltage DDR2 MODE and DDRSEL connected to 1 8 Feedback accuracy AVCC no load 1 5 1 5 96 Current limit and zero crossing comparator lesus CSNS input bias current 110 120 130 HA Comparator offset 6 6 mV R 1kQ Positive current limit threshold iini 120 mV Vpanp Vcsns Fi i TUE ixed negative current limit 110 mV threshold Zero crossing comparator VZC OFFS offset 11 5 1 mV High and low side gate drivers HGATE high state pull up 2 0 3 HGATE driver on resistance HGATE low state pull down 1 8 2 7 Q L
17. Apk sink source linear regulator provides the memory termination voltage with fast load transient response The device is fully compliant with system sleep states S3 and S4 S5 providing LDO output high Applications impedance in suspend to RAM and tracking m DDR2 3 memory supply discharge of all outputs in suspend to disk Table 1 Device summary m Notebook computers m Handheld and PDAs Order code Package Packaging m CPU and chipset I O supplies PM6670S VFQFPN 24 4x4 Tube m SSTL18 SSTL15 and HSTL bus termination PM6670STR Exposed pad Tape and reel February 2010 Doc ID 14432 Rev 4 1 54 www st com Contents PM6670S Contents 1 Typical application circuit 4 2 PIN settings AI aa 5 2 1 Connections siis ieee een Siew RE EO WA eRe des 5 2 2 Pin description 6 3 Electrical data EWW 8 3 1 Maximum RAVING IIIA AA a EE AA 8 3 2 iFfhermal data EE a i ni a A tana eee 2 8 3 3 Recommended operating conditions 9 4 Electrical characteristics 10 5 Typical operating characteristics 14 6 Block diagram 19 7 Device description eeeeeeeeeeeeeeeeeeeeeeeeeeeeeeee ee 20 7 1 VDDO section constant on time PWM controller 21 7 1 1 Constant on time architecture
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19. DE pin high level Vavcc 7 threshold 0 7 MODE MODE pin low level Vavcc threshold 1 3 DDRSEL pin high level VAVCC threshold 0 8 V DDRSEL pin middle level 10 Vwcc y DDRSEL window 1 5 DDRSEL pin low level 0 5 threshold l DSCG pin high level Vavcc threshold 0 8 DSCG pin middle level VDSCG window 1 0 2 0 DSCG pin low level 05 threshold IiN LEAK Logic inputs leakage current S3 S5 5 V 10 I Multilevel inputs leakage MODE DDRSEL and 10 IN3 LEAK current DSCG 5V uA losc vosc input leakage current VOSC 500 mV 1 LEAK Thermal shutdown Tsupw Shutdown temperature 1 150 C 1 Guaranteed by design Not production tested ky Doc ID 14432 Rev 4 13 54 Typical operating characteristics PM6670S 5 Typical operating characteristics Figure 3 Efficiency vs Figure 4 Switching frequency vs load 1 5 V and 1 8 V Vy 12 V load 1 8 V Vu 12V 100 500 90 4 T 450 4 MEN 80 4 400 amp 704 z 350 5 50 250 Forced PWM 9 40 Forced PWM J No Audible P S 30 dau 2 Pulse Skip lt 20 4 SF orced RWM 9 100 o waers
20. DQ output voltage drops 10 below or rises 10 above the nominal regulated value The PG output can sink current up to 4 mA ki Doc ID 14432 Rev 4 33 54 Device description PM6670S 7 1 8 VDDG output discharge Active discharge of VDDQ output occurs when PM6670S enters the suspend to disk system state S3 and S5 tied to GND and DSCG pin has been properly set Figure 39 DSCG pin connection for discharge mode selection 5V PM6670S VREF F 4 DSCG The PM6670S allows the user to choose between fast discharge tracking discharge soft discharge non tracking discharge or no discharge modes Voltage on DSCG multilevel pin determines discharge mode as shown in Table 9 on page 34 Table 9 Discharge mode selection DSCG voltage Soft End type Description VDSCG gt 4 2 V No discharge All outputs left floating VDDQ and VTT actively discharged by LDO trough LDOIN and VTT pins VDSCG lt 0 5V Soft non tracking All outputs discharged by dedicated internal MOS 1 V lt VDSCG lt 8 5 V Fast tracking Tracking discharge allows the fastest discharge of all outputs but requires the LDOIN to be self supplied from VDDQ output voltage When an external supply rail is connected to LDOIN it must be taken into account to avoid damage to the device Discharge current 1 A flows through the LDOIN pin until the output has reached approximately 400 mV and then a soft discharge completes the pro
21. GATE high state pull up 1 4 2 1 LGATE driver on resistance LGATE low state pull down 0 6 0 9 UVP OVP protections and PGOOD SIGNAL SMPS only OVP Over voltage threshold 112 115 118 UVP Under voltage threshold 67 70 73 Power Good upper threshold 107 110 113 PGOOD Power Good lower threshold 86 90 93 lpGo LEAK PG leakage current PG forced to 5 V 1 uA Vpg Low PG low level voltage Ipg sink 4 mA 150 250 mV Soft start section SMPS Soft start ramp time 4 steps current limit fa ms Soft start current limit step 30 HA ky Doc ID 14432 Rev 4 11 54 Electrical characteristics PM6670S Table 6 Electrical characteristics continued Values Symbol Parameter Test condition Unit Min Typ Max Soft end section VDDO discharge resistance in non tracking discharge 15 25 35 mode Q VTT discharge resistance in 15 25 35 non tracking discharge mode VTTREF discharge resistance in non tracking 1 1 5 2 kQ discharge mode VDDO output threshold synchronous for final tracking 0 2 0 4 0 6 V to non tracking discharge transition Vrr LDO section LDO input bias current in NS ILDOIN ON full on state S3 S5 5 V No load on VTT 1 10 poin LDO input bias current in S3 0 V S5 5 V 10 STR suspend to RAM state No Load on VTT ILpoin LDO input bias current in S3 S5 0 V No Load on VTT 4 STD suspend to disk state A V V IVTTSNS V
22. It determines the minimum integrator capacitor value Cint Equation 49 48 54 Doc ID 14432 Rev 4 ki PM6670S Application information If the ripple on pin COMP is greater than the integrator output dynamic 150 mV an additional capacitor Cg could be added in order to reduce its amplitude If q is the desired attenuation factor of the output ripple select Equation 50 Cu 1 Cpe ZNT 1 9 a In order to reduce noise on pin COMP it s possible to introduce a resistor Rinr that together with Cinr and Cg becomes a low pass filter The cutoff frequency fcur must be much greater 10 or more times than the switching frequency of the section Eguation 51 4 Cint Crit Cint Crit Rint 27 four For most of applications both Rinr and Cy are unnecessary If the ripple is very small e g such as with ceramic capacitors an additional compensation network called Virtual ESR network is needed This additional part generates a triangular ripple that substitutes the ESR output voltage ripple The complete compensation scheme is represented in Figure 43 Figure 43 Virtual ESR network PWM Comparator Ton Generation Block VREF Integrator Doc ID 14432 Rev 4 49 54 Application information PM6670S 50 54 Select C as shown Eguation 52 Then calculate R in order to have enough ripple voltage on the integrator input Eguation 53 L R __ Rvesr C Where Ryg
23. M6670S has been designed to satisfy the widest range of applications involving DDR2 3 memories SSTL15 18 buses termination and I O supplies for CPU chipset The device is provided with multilevel pins which allow the user to choose the appropriate configuration The MODE pin is used to firstly decide between fixed preset or adjustable user defined output voltages When the MODE pin is connected to 5 V the PM6670S allows setting the VDDQ voltage to 1 8 V or 1 5 V just forcing the DDRSEL multilevel pin to 5 V or to ground respectively see Figure 35a In this condition the pulse skip feature is enabled This device configuration is suitable for standard DDR2 3 memory supply applications avoiding the need for an external high accuracy divider for output voltage setting Applications requiring different output voltages can be managed by PM6670S simply setting the adjustable mode If MODE pin voltage is higher than 4 V the fixed output mode is selected Connecting an external divider to the MODE pin Figure 35b it is used as negative input of the error amplifier and the output voltage is given by expression 21 Equation 21 R8 R9 VDDQapy 0 9 ADJ R8 30 54 Doc ID 14432 Rev 4 ki PM6670S Device description VDDO output voltage can be set in the range of 0 9 V to 2 6 V Adjustable mode automatically switthes DDRSEL pin to become the power saving algorithm selector if tied to 5 V the forced PWM fixed frequency cont
24. TTSNS bias current WA ee 1 BIAS Vvttsns Vvsns 2 S3 0 V S5 5 V IVTTSNS VTTSNS leakage current 1 LEAK VvrrsNs Vvsns 2 S3 0 V S5 5 V lvrtLeak VTT leakage current 10 10 Vvrr Vysng 2 LDO linear regulator output S3 S52 5 V lyrr 0A 0 9 voltage DDR2 MODE DDRSEL 5 V V LDO linear regulator output S32 S52 5 V lyrr 0 A iss voltage DDR3 MODE 5 V DDRSEL 0 V f S3 S5 MODE 5 V Wr 20 20 1 mA lt lyrT lt 1 mA LDO output accuracy respect S3 S5 MODE 5 V 2 2 V to VTTREF 1A clar 1A gt So m gt V S32 S5 MODE 5 V 45 35 2A lt lvrr lt 2A 12 54 Doc ID 14432 Rev 4 ky PM6670S Electrical characteristics Table 6 Electrical characteristics continued Values Symbol Parameter Test condition Unit Min Typ Max V 1 10 V 2 2 2 3 3 LDO source current limit An Vvsns Vvrr gt 1 10 VysNs 2 1 1 15 1 4 VrreL Vyrr gt 0 90 V 2 3 2 3 2 LDO sink current limit ui iesus ii Vvrr lt 0 90 Vysns 2 1 4 1 15 1 VTTREF section VTTREF output voltage lvTTREF 0 A Vvsns 1 8V 0 9 V VvTTREF VTTREF output voltage 15 mA lt lyrrger lt 15 mA D 5 of accuracy respect to VSNS 2 Vysng 1 8 V d lvttRer VTTREF current limit VTTREF 0 or VSNS 40 mA Power management section Turn OFF level 0 4 3 S5 Turn ON level 1 6 MO
25. Valley current limit As the valley threshold is fixed the greater the current ripple the greater the DC output current will be If an output current limit greater than l oAp max over all the input voltage range is required the minimum current ripple must be considered in the previous formula Then the resistor Rcsns is Equation 46 Hpson i lLvalley Rosns 190uA where Rpson is the drain source on resistance of the low side switch Consider the temperature effect and the worst case value in Rpsor calculation typically 40 4 C The accuracy of the valley current also depends on the offset of the internal comparator x6 mV The negative valley current limit if the device works in forced PWM mode is given by Equation 47 110mV INEG Rpson Doc ID 14432 Rev 4 47 54 Application information PM6670S 8 1 7 All ceramic capacitors application Design of external feedback network depends on the output voltage ripple across the output capacitors ESH lf the ripple is great enough at least 20 mV the compensation network simply consists of a CjyT capacitor Figure 42 Integrative compensation Ton One shot generator VDDO COMP Integrator CINT The stability of the system depends firstly on the output capacitor zero freguency It must be verified that Eguation 48 ma 27 RoutC out fgw gt K out where k is a free design parameter greater than unity k gt 3
26. cess by discharging the output with an internal 22 O switch Figure 40 Fast discharge and soft discharge options VDDQ Fast discharge VDDQ dd Soft discharge P 400mV gt gt 34 54 Doc ID 14432 Rev 4 ki PM6670S Device description 7 1 9 7 1 10 Gate drivers The integrated high current gate drivers allow using different power MOSFETs The high side driver uses a bootstrap circuit which is supplied by the 45 V rail The BOOT and PHASE pins work respectively as supply and return path for the high side driver while the low side driver is directly fed through VCC and PGND pins An important feature of the PM6670S gate drivers is the adaptive anti cross conduction circuitry which prevents high side and low side MOSFETs from being turned on at the same time When the high side MOSFET is turned off the voltage at the PHASE node begins to fall The low side MOSFET is turned on only when the voltage at the PHASE node reaches an internal threshold 2 5 V typ Similarly when the low side MOSFET is turned off the high side one remains off until the LGATE pin voltage is above 1V The power dissipation of the drivers is a function of the total gate charge of the external power MOSFETs and the switching frequency as shown in the following equation Equation 23 Pp driver Vonv i Qy fsw The low side driver has been designed to have a low resistance pull down transistor 0
27. ch Republic Finland France Germany Hong Kong India Israel Italy Japan Malaysia Malta Morocco Philippines Singapore Spain Sweden Switzerland United Kingdom United States of America www st com 54 54 Doc ID 14432 Rev 4 ky
28. ches off nominal value Exit by a power on reset or toggling S5 LGATE pin is forced high after the soft end then the device latches off Exit by a power on reset or toggling S5 LGATE pin is forced high after the soft end then the Tj 4150 C device latches off Exit by a power on reset or toggling S5 after 15 C temperature drop VDDQ over voltage VDDQ lt 70 of the VDDQ under voltage nominal value Junction over temperature Doc ID 14432 Rev 4 ky PM6670S Device description 7 2 7 2 1 7 2 2 VTTREF buffered reference and VTT LDO section The PM6670S provides the required DDR2 3 reference voltage on the VTTREF pin The internal buffer tracks half the voltage on the VSNS pin and has a sink and source capability up to 15 mA Higher currents rapidly deteriorate the output accuracy A 10 nF to 100 nF 33 nF typ bypass capacitor to SGND is reguired for stability The VTT low drop out linear regulator has been designed to sink and source up to 2 A peak current and 1 A continuously The VTT voltage tracks VTTREF within 35 mV A remote voltage sensing pin VTTSNS is provided to recovery voltage drops due to parasitic resistance In DDR2 3 applications the linear regulator input LDOIN is typically connected to VDDQ output connecting LDOIN pin to a lower voltage if available in the system reduces the power dissipation of the LDO A minimum output capacitance of 20 uF 2x10 uF MLCC capa
29. citors is enough to assure stability and fast load transient response VTT and VTTREF Soft Start Soft Start on VTT and VTTREF outputs is achieved by current clamping The LDO linear regulator is provided with a current foldback protection when the output voltage exits the internal 10 Yo VTT Good window the output current is clamped at 1 A Re entering VTT Good window releases the current limit clamping The foldback mechanism naturally implements a two steps soft start charging the output capacitors with a 1 A constant current Something similar occurs at VTTREF pin where the output capacitor is smoothly charged at a fixed 40 mA current limit VTTREF and VTT outputs discharge The tracking discharge mechanism involves the VTT linear regulator When the suspend to disk state is entered the switching regulator is turned OFF At the same time the LDO drains a 1 A constant current from LDOIN and keeps VTT in track with VTTREF that in turn is half the voltage at the VSNS pin When the VDDQ output reaches 400 mV the PM66708 switches on the internal discharge MOSFETs to complete the process see Section 7 1 8 VDDQ output discharge on page 34 In soft discharge i e non tracking discharge the PM6670S disables the internal regulators and suddenly turns on the discharge MOSFETs on each output Doc ID 14432 Rev 4 37 54 Device description PM6670S 7 3 38 54 S3 and S5 power management pins According to DDR2 3 memor
30. election 44 8 1 5 Diode selection is ca eg RR RCB IR WAKIKE KUIINUA 46 8 1 6 VDDQ current limit setting 47 8 1 7 All ceramic capacitors application 48 9 Package mechanicaldata 51 10 Revision history 53 LI Doc ID 14432 Rev 4 3 54 Typical application circuit PM6670S 1 Typical application circuit Figure 1 Application circuit 5V VIN VDDQ LDO input C IN4 VDDO VTTREF C ouT3 c our VTT C INT 4 54 Doc ID 14432 Rev 4 ky Pin settings PM6670S Pin settings Connections 2 1 Pin connection through top view Figure 2 SNSO ASWHd ALVSH LOOd NIOQ1 11A VTTGND VTTSNS L DISA diNO2 3dQON SNSA ISOA dIHA a DDRSEL L 5 54 Doc ID 14432 Rev 4 Pin settings PM6670S 2 2 Pin description Table 2 Pin functions N Pin Function 1 VTTGND LDO power ground Connect to negative terminal of VTT output capacitor LDO remote sensing Connect as close as possible to the load via a low visa noise PCB trace DDR voltage selector if MODE is tied to VCC or pulse skip no audible 3 DDRSEL pulse skip selector in adjustable mode MODE voltage lower than 3 V See Section 7 1 4 Mode of operation selection on page 30 Low noise buffered DDR refere
31. ent limit threshold during start up reducing the input output surge currents At the beginning of start up the PM6670S current limit is set to 25 of nominal value and the under voltage protection is disabled Then the current limit threshold is sequentially brought to 100 in four steps of approximately 750 us Figure 37 Figure 37 Soft start waveforms Switching output Current limit threshold 32 54 Doc ID 14432 Rev 4 ky PM6670S Device description After a fixed 3 ms total time the soft start finishes and UVP is released if the output voltage doesn t reach the under voltage threshold within soft start duration the UVP condition is detected and the device performs a soft end and latches off Depending on the load conditions the inductor current may or may not reach the nominal value of the current limit during the soft start Figure 38 shows two examples Figure 38 Soft start at heavy load a and short circuit b conditions pulse skip enabled T EI LaL Lu Liu Bw Ch2 5 0 By M 400ys 25 0MS s 40 Onsipt Ch 50V Bw Ch4 50A Q Bw ACh2 2 19 M 400ps 25 0NIS s 40 Ons pt i Chi 1 0V A Ch2 z 24V a b 7 1 7 Power Good signal The PG pin is an open drain output used to monitor output voltage through VSNS in fixed output voltage mode or MODE in adjustable output voltage mode pins and is enabled after the soft start timer has expired PG signal is held low if the VD
32. er The switching regulator of the PM6670S owns a one shot generator that ignites the high side MOSFET when the following conditions are simultaneously satisfied the PWM comparator is high i e output voltage is lower than Vr 0 9 V the synchronous rectifier current is below the current limit threshold and the minimum off time has expired A minimum off time constraint 300 ns typ is introduced to assure the boot capacitor charge and allow inductor valley current sensing on low side MOSFET A minimum on time is also introduced to assure the start up switching sequence Once the on time has timed out the high side switch is turned off while the synchronous rectifier is ignited according to the anti cross conduction management circuitry When the output voltage reaches the valley limit determined by internal reference Vr 0 9 V the low side MOSFET is turned off according to the anti cross conduction logic once again and a new cycle begins Figure 30 Switching section simplified block diagram Ly Doc ID 14432 Rev 4 23 54 Device description PM6670S 7 1 2 24 54 Output ripple compensation and loop stability The loop is closed connecting the center tap of the output divider internally when the fixed output voltage is chosen or externally using the MODE pin in the adjustable output voltage mode The feedback node is the negative input of the error comparator while the positive input is internall
33. es a pseudo fixed frequency constant on time COT controller as the core of the switching section The switching frequency can be set by connecting an external divider to the VOSC pin The voltage seen at this pin must be greater than 0 8 V and lower than 2 V in order to ensure system s linearity Nearly constant switching frequency is achieved by the system s loop in steady state operating conditions by varying the on time duration avoiding thus the need for a clock generator The On Time one shot duration is directly proportional to the output voltage sensed at VSNS pin and inversely proportional to the input voltage sensed at the VOSC pin as follows Equation 24 NS Ton Kosc V T Osc where Kogc is a constant value 130 ns typ and is the internal propagation delay 40 ns typ The duty cycle of the buck converter is under steady state conditions given by Equation 25 D Vour Vin The switching frequency is thus calculated as Equation 26 Vout D Vin _Gosc 1 fsw V Ton Kren SNS out Kosc osc y Osc Doc ID 14432 Rev 4 39 54 Application information PM6670S where Eguation 27a Vosc Cosc V IN Equation 27b SNS Cour V OUT Referring to the typical application schematic figure in cover page and Figure 29 the final expression is then Equation 28 cosc Ro 1 Kosc R4 R2 Kosc The switching frequency directly affects two parameters e Inductor size
34. fied that Equation 12 Vr Cint gt an 2n t Vout where Equation 13 4 t 21 Court Ror and Doc ID 14432 Rev 4 ky PM6670S Device description Eguation 14 Rrot ESR Rygsn Moreover the Cinr capacitor must meet the following condition Equation 15 k 21 Cour Rror where Ryor is the sum of the ESR of the output capacitor and the equivalent ESR given by the Virtual ESR Network Ryesr The k parameter must be greater than unity k gt 3 and determines the minimum integrator capacitor value Cin Equation 16 Om Vr CC SS SA Vout The capacitor of the virtual ESR Network C is chosen as follows Eguation 17 and R is calculated to provide the desired triangular ripple voltage Eguation 18 B L Rvesr C Finally the R1 resistor is calculated according to expression 19 Eguation 19 Doc ID 14432 Rev 4 27 54 Device description PM6670S 7 1 3 28 54 Pulse skip and no audible pulse skip modes High efficiency at light load conditions is achieved by PM6670S entering the pulse skip mode if enabled When one of the two fixed output voltages is set pulse skip power saving is a default feature At light load conditions the zero crossing comparator truncates the low side switch on time as soon as the inductor current becomes negative in this way the comparator determines the on time duration instead of the output ripple see Figure 33 Figure 33 Ind
35. ies supply requirements the PM6670S can manage all SO to S5 system states by connecting S3 S5 pins to their respective sleep mode signals in the notebook motherboard Keeping S3 and S5 high the SO Full On state is decoded and the outputs are alive In Sa state S5 1 S3 0 the PM6670S maintains VDDQ and VTTREF outputs active and VTT output in high impedance as needed In S4 S5 states S5 S3 0 all outputs are turned off and according to DSCG pin voltage the proper Soft End is performed Table 11 S3 and S5 sleep states decoding S3 S5 System state VDDQ VTTREF VTT 1 1 SO full On On On On 0 1 S3 suspend to RAM On On Off Hi Z 0 0 S4 S5 suspend to Disk Off discharge Off discharge Off discharge Doc ID 14432 Rev 4 PM6670S Application information 8 8 1 Application information The purpose of this chapter is to show the design procedure of the switching section The design starts from three main specifications e Theinput voltage range provided by the battery or the AC adapter The two extreme values Vinmax and Vinmin are important for the design e The maximum load current indicated by l_oap max e The maximum allowed output voltage ripple VniPPLE MAX It s also possible that specific designs should involve other specifications The following paragraphs will guide the user into a step by step design External components selection The PM6670S us
36. iven by Equation 9 Cnt 1 s e 9 In order to reduce the noise on the COMP pin it is possible to add a resistor Rinr that together with CINT and Cp 7 becomes a low pass filter The cutoff frequency fcur must be much greater 10 or more times than the switching frequency Equation 10 1 Cint Crit Cint Crit Rint 27 fout If the ripple is very small lower than approximately 20 mV a different compensation network called Virtual ESR network is needed This additional circuit generates a triangular ripple that is added to the output voltage ripple at the input of the integrator The complete control scheme is shown in Figure 32 Doc ID 14432 Rev 4 25 54 Device description PM6670S 26 54 Figure 32 Virtual ESR network TNODE COMP PIN VOLTAGE VOLTAGE VREF PWM Comparator Rint Cint pu OUTPUT VOLTAGE The ripple on the COMP pin is the sum of the output voltage ripple and the triangular ripple generated by the Virtual ESR network In fact the Virtual ESR Network behaves like a another equivalent series resistor Rvgsn A good trade off is to design the network in order to achieve an RVESR given by Equation 11 Vi Rvesr XP AE ESR L where Al is the inductor current ripple and Vpipp is the total ripple at the T node chosen greater than approximately 20 mV The new closed loop gain depends on Cinr In order to ensure stability it must be veri
37. m capacitors are good in terms of low ESR and small size but they occasionally can burn out if subjected to very high current during operation Multi layers ceramic capacitors MLCC have usually a higher RMS current rating with smaller size and they remain the best choice The drawback is their quite high cost Doc ID 14432 Rev 4 ky PM6670S Application information It must be taken into account that in some MLCC the capacitance decreases when the operating voltage is near the rated voltage In Table 14 some MLCC suitable for most of applications are listed Table 14 Evaluated MLCC for input filtering Manufacturer Series Capacitance F Rated voltage V esis TAIYO YUDEN UMK325BJ106KM T 10 50 2 TAIYO YUDEN GMK316F106ZL T 10 35 2 2 TAIYO YUDEN GMK325F106ZH T 10 35 2 2 TAIYO YUDEN GMK325BJ106KN 10 35 2 5 TDK C3225X5R1E106M 10 25 Output capacitor selection Using tantalum or electrolytic capacitors the selection is made referring to ESR and voltage rating rather than by a specific capacitance value The output capacitor has to satisfy the output voltage ripple requirements At a given switching frequency small inductor values are useful to reduce the size of the choke but increase the inductor current ripple Thus to reduce the output voltage ripple a low ESR capacitor is required To reduce jitter noise between different switching regulators in the system it is preferable to wo
38. n the switching output voltage is below 70 of its nominal value a latched under voltage protection occurs This event causes the switching section to be immediately disabled and both switches to be opened The controller enters in soft end mode and the output is eventually kept to ground turning the low side MOSFET on when the voltage is lower than 400 mV If S3 and S5 are forced low the low side MOSFET is released and only the 22 O switch is active The under voltage protection circuit is enabled only at the end of the soft start Once an UVP has occurred a toggle on S5 pin or a power on reset is necessary to clear the fault state and restart the device Device thermal protection The internal control circuitry of the PM6670S self monitors the junction temperature and turns all outputs off when the 150 C limit has been overrun This event causes the switching section to be immediately disabled and both switches to be opened The controller enters in Soft End Mode and the output is eventually kept to ground turning the low side MOSFET on when the voltage is lower than 400 mV If S3 and S5 are forced low the low side switch is released and only the 22 O discharge MOSFET is active The thermal fault is a latched protection and normal operating condition is restored by a Power on reset or toggling S5 Table 10 OV UV and OT faults management Fault Conditions Action VDDQ gt 115 of the LGATE pin is forced high and the device lat
39. n to ambient 42 C W Tsre Storage temperature range 90 to 150 C TA Operating ambient temperature range 40 to 85 C Ty Junction operating temperature range 40 to 125 C Doc ID 14432 Rev 4 SA PM6670S Electrical data 3 3 Recommended operating conditions Table 5 Recommended operating conditions Values Symbol Parameter Unit Min Typ Max VIN Input voltage range 4 5 28 Vavcc IC supply voltage 4 5 5 5 V Vvec IC supply voltage 4 5 5 5 Doc ID 14432 Rev 4 9 54 Electrical characteristics PM6670S 4 Electrical characteristics TA 0 C to 85 C VCC AVCC 5 V and LDOIN connected to VDDQ output if not otherwise specified 9 Table 6 Electrical characteristics Values Symbol Parameter Test condition Unit Min Typ Max Supply section Sa S5 MODE and DDRSEL I Operating current connected to AVCC no load on VTT 08 2 IN P 9 and VTTREF outputs i VCC connected to AVCC mA S5 MODE and DDRSEL connected to AVCC S3 tied to SGND no load Istr Operating current in STR on VTTREF 0 6 1 VCC connected to AVCC 6 j T S3 and S5 tied to SGND perating current in i ISH shutdown Discharge mode active 1 10 HA VCC connected to AVCC AVCC under voltage lockout 4 1 4 25 44 upper threshold UVLO AVCC under voltage lockout 3 85 40 4 1 lower threshold UVLO hysteresis 70 mv ON time SMPS MODE and VOSC
40. nce voltage A 22 nF minimum ceramic 4 TREE bypass capacitor is required in order to achieve stability Ground reference for analog circuitry control logic and VTTREF buffer 5 SGND Connect together with the thermal pad and VTTGND to a low impedance ground plane See the Application Note for details 5 V supply for internal logic Connect to 5 V rail through a simple RC AVCC filtering network High accuracy output voltage reference 1 237 V for multilevel pins setting 7 VREF It can deliver up to 50 uA Connect a 100 nF capacitor between VREF and SGND in order to enhance noise rejection Freguency selection Connect to the central tap of a resistor divider to set 8 VOSC the desired switching freguency The pin cannot be left floating See Section 7 Device description on page 20 VDDO output remote sensing Discharge path for VDDA in Non Tracking Discharge Input for internal resistor divider that provides VDDO 2 to 9 ve VTTREF and VTT Connect as close as possible to the load via a low noise PCB trace Mode of operation selector If MODE pin voltage is higher than 4 V the fixed 10 MODE output mode is selected If MODE pin voltage is lower than 4 V itis used as negative input of the error amplifier See Section 7 1 4 Mode of operation selection on page 30 11 COMP DC voltage error compensation Input for the switching section Refer Section 7 1 4 Mode of operation selection on page 30 12 DSCG Discharge
41. ns on page 36 Doc ID 14432 Rev 4 31 54 Device description PM6670S Referring to Figure 36 the Rpsxon sensing technigue allows high efficiency performance without the need for an external sensing resistor The on resistance of the MOSFET is affected by temperature drift and nominal value spread of the parameter itself this must be considered during the Rj w setting resistor design It must be taken into account that the current limit circuit actually regulates the inductor valley current This means that Rj jy must be calculated to set a limit threshold given by the maximum DC output current plus half of the inductor ripple current Equation 22 I 120A Bum DSon The PM6670S provides also a fixed negative current limit to prevent excessive reverse inductor current when the switching section sinks current from the load in forced PWM a d guadrant working conditions This negative current limit threshold is measured between PHASE and PGND pins comparing the drop magnitude on PHASE pin with an internal 110 mV fixed threshold 7 1 6 POR UVLO and soft start The PM6670S automatically performs an internal startup seguence during the rising phase of the analog supply of the device AVCC The switching controller remains in a stand by state until AVCC crosses the upper UVLO threshold 4 25 V typ keeping active the internal discharge MOSFETs only if AVCC gt 1 V The soft start allows a gradual increase of the internal curr
42. o audible pulse skip mode Some audio noise sensitive applications cannot accept the switching freguency to enter the audible range as is possible in pulse skip mode with very light loads For this reason the PM6670S implements an additional feature to maintain a minimum switching freguency of 33 kHz despite a slight efficiency loss At very light load conditions if any switching cycle has taken place within 30 us typ since the last one because the output voltage is still higher than the reference a no audible pulse skip cycle begins The low side MOSFET is turned on and the output is driven to fall until the reference has been crossed Then the high side switch is turned on for a Ton period and once it has expired the synchronous rectifier is enabled until the inductor current reaches the zero crossing threshold see Figure 34 Figure 34 Inductor current and output voltage at light load with non audible pulse skip Inductor current For frequencies higher than 33 kHz due to heavier loads the device works in the same way as in pulse skip mode It is important to notice that in both pulse skip and no audible pulse skip modes the switching frequency changes not only with the load but also with the input voltage Doc ID 14432 Rev 4 29 54 Device description PM6670S 7 1 4 Mode of operation selection Figure 35 MODE and DDRSEL multifunction pin configurations VDDQ VDDQ PM6670S MODE The P
43. omponents The output voltage can also be adjusted in the 0 9 V to 2 6V range using an external resistor divider The switching mode power supply SMPS can handle different modes of operation in order to minimize noise or power consumption depending on the application needs A lossless current sensing scheme based on the Low Side MOSFET s on resistance avoids the need for an external current sense resistor The output of the linear regulator VTT tracks the memory s reference voltage VTTREF within 30 mV over the full operating load conditions The input of the LDO can be either VDDQ or a lower voltage rail in order to reduce the total power dissipation Linear regulator stability is achieved by filtering its output with a ceramic capacitor 20 uF or greater The reference voltage VTTREF section provides a voltage equal to one half of VSNS with an accuracy of 1 96 This regulator can source and sink up to 15 mA A 10 nF to 100 nF bypass capacitor is required between VTTREF and SGND for stability According to DDR2 3 JEDEC specifications when the system enters the suspend to RAM state the LDO output is left in high impedance while VTTREF and VDDQ are still alive When the suspend to disk state S3 and S5 tied to ground is entered all outputs are actively discharged when either tracking or non tracking discharge is selected Doc ID 14432 Rev 4 ky PM6670S Device description 7 1 VDDQ section constant on time PWM controller
44. put voltage V iNmax Table 16 lists tested high side MOSFETs Table 16 Evaluated high side MOSFETs Rpson Gate charge Rated reverse Manufacturer Type mo nC voltage V ST STS12NH3LL 10 5 12 30 IR IRF7811 9 18 30 In buck converters the power dissipation of the synchronous MOSFET is mainly due to conduction losses Equation 42 Ppi owSide Peonduction Maximum conduction losses occur at the maximum input voltage Equation 43 P R 1 Vout 2 conduction DSon V LOAD MAX IN MAX The synchronous rectifier should have the lowest Rpson as possible When the high side MOSFET turns on high dy d of the phase node can bring up even the low side gate through its gate drain capacitance Crrs causing a cross conduction problem Once again the choice of the low side MOSFET is a trade off between on resistance and gate charge a good selection should minimize the ratio Cass Cas where Equation 44 Cas Ciss E Crss Doc ID 14432 Rev 4 45 54 Application information PM6670S Tested low side MOSFETSs are listed in Table 17 Table 17 Evaluated low side MOSFETs Manufacturer Type Rpson m Can Cos Rated reverse voltage V ST STS12NH3LL 13 5 0 069 30 ST STS25NH3LL 4 0 0 011 30 IR IRF7811 24 0 054 30 Dual N MOS can be used in applications with lower output current Table 18 shows some suitable dual MOSFETs for applications reguiring about 3 A
45. ration or to a lower supply to reduce the power dissipation A 10 uF bypass ceramic 23 LDOIN mE pages i capacitor is suggested for noise rejection enhancement See Section 7 Device description on page 20 24 VIT LDO linear regulator output Bypass with a 20 uF 2x10 uF MLCC filter capacitor Doc ID 14432 Rev 4 7 54 Electrical data PM6670S 3 3 1 3 2 8 54 Electrical data Maximum rating Table 3 Absolute maximum ratings 1 Symbol Parameter Value Unit Vavcc AVCC to SGND 0 3 to 6 Vvcc VCC to SGND 0 3 to 6 PGND VTTGND to SGND 0 3 to 0 3 HGATE and BOOT to PHASE 0 3 to 6 HGATE and BOOT to PGND 0 3 to 44 VPHASE PHASE to SGND 0 3 to 38 V LGATE to PGND 0 3 to Vcc 40 3 CSNS PG S3 S5 DSCG COMP VSNS 0 3 to Vavcc 0 3 VOSC VREF MODE DDRSEL to GND VTTREF VREF VTT VTTSNS to SGND 0 3 to Vaycc 0 3 LDOIN VTT VTTREF LDOIN to VTTGND 0 3 to Vaycc 0 3 Pror Power dissipation 9 T 25 C 2 3 W 1 Free air operating conditions unless otherwise specified Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device Exposure to absolute maximum rated conditions for extended periods may affect device reliability 2 PHASE to SGND up to 2 5 V for t lt 10 ns Thermal data Table 4 Thermal data Symbol Parameter Value Unit Riha Thermal resistance junctio
46. re 11 VTT load regulation 0 9 V Figure 12 VTT load regulation 0 75 V LDOIN 1 8 V LDOIN 1 5 V 0 940 0 790 0 930 0 780 s 0 920 id J 5 g 0770 g 0 910 S 0 760 a 5 0 900 0 750 o o 0 890 0 740 0 880 T T T 0 730 T 2 5 1 5 0 5 0 5 1 5 2 5 2 5 1 5 0 5 0 5 1 5 2 5 Output current A Output current A Figure 13 VTTREF load regulation 0 9 V VSNS 1 8 V Figure 14 No audible pulse skip waveforms 0 8990 0 8985 0 8980 0 8975 0 8970 0 8965 0 8960 0 8955 Output voltage 0 8950 15 10 5 0 5 10 15 20 Sourced current mA 25 Tek Stopped Single Seq 1 cas 16 May 06 09 55 29 WA err ET TE rn TI IET T 7I Tti TIT KA HGATE M 4 0us 62 5MS s 16 0nsibt A Ch3 7 0 Chi 10 0V Bw Ch2 10 0V Bw Ch3 10 04 Bw Ch4 204 Q Bw 4 Doc ID 14432 Rev 4 15 54 Typical operating characteristics PM6670S Figure 15 Power up seguence AVCC above UVLO Figure 16 VDDG soft start 1 8 V heavy load Tek Preview Hi Res 22 Jun 06 10 41 41 Chi Ch3 500mY 500mY AVOC 4 2V AYCC SY L l Liu 1 500my Bw Bw Ch4 10V Bw M 400ps 6 25MS s 160ns4t A Chi S00mv Tek Preview Hi Res 4 Acgs 26 May 06 11 03 32 Y Tt T T VDDO 1 5v 400ns pt M 1 0ms 2 5MS s A Ch4 s 18A Chi 10V Bw Ch2 50y Bw Ch3 50V Bw Ch4 5 04
47. rk with an output voltage ripple greater than 25 mV As far as it concerning the load transient requirements the equivalent series resistance ESR of the output capacitor must satisfy the following relationship Equation 36 Vi ESR lt RIPPLEMAX Al max where Vgipp p is the maximum tolerable ripple voltage In addition the ESR must be high enough high to meet stability requirements The output capacitor zero must be lower than the switching frequency Equation 37 1 buf SW ZO 2n ESR Ca Doc ID 14432 Rev 4 43 54 Application information PM6670S 44 54 If ceramic capacitors are used the output voltage ripple due to inductor current ripple is negligible Then the inductance could be smaller reducing the size of the choke In this case it is important that output capacitor can adsorb the inductor energy without generating an over voltage condition when the system changes from a full load to a no load condition The minimum output capacitance can be chosen by the following eguation Eguation 38 L Loap MAX 2 Vit Vi C our min m where Vf is the output capacitor voltage after the load transient while V is the output capacitor voltage before the load transient In Table 15 are listed some tested polymer capacitors are listed Table 15 Evaluated output capacitors Manufact r r S ries Capacitance Rated voltage ESR max 100 kHz HF V mo 4TPE220MF 220 4V 15 to 25 SANYO
48. rol is performed If grounded or connected to VREF pin 1 237 V reference voltage the pulse skip or non audible pulse skip modes are respectively selected Table 8 Mode of operation settings summary Mode DDRSEL VDDQ Operating mode VppnsEL gt 4 2 V 1 8V Vuope gt 4 3 V 1V lt Vppnsgi lt 3 5 V isy Pulse skip lt 0 5 V VppnsEL gt 4 2 V Forced PWM Vmode lt 3 7 V 1V lt VpprseL lt 3 5 V ADJ Non audible pulse skip VppRSEL lt 0 5 V Pulse skip Current sensing and current limit The PM6670S switching controller uses a valley current sensing algorithm to properly handle the current limit protection and the inductor current zero crossing information The current is sensed during the conduction time of the low side MOSFET The current sensing element is the on resistance of the low side switch The sensing scheme is visible in Figure 36 Figure 36 Current sensing scheme PM6670S OUT Q 100HA Rum 4 7 CSNS Q La An internal 120 uA current source is connected to Ceng pin that is also the non inverting input of the positive current limit comparator When the voltage drop developed across the sensing parameter equals the voltage drop across the programming resistor Ry jy the controller skips subsequent cycles until the overcurrent condition is detected or the output UV protection latches off the device see Section 7 1 11 Over voltage and under voltage protectio
49. sg is the new virtual output capacitor ESR A good trade off is to consider an equivalent ESR of 30 50 mQ even though the choice depends on inductor current ripple Then choose R1 as follows Equation 54 Doc ID 14432 Rev 4 ky PM6670S Package mechanical data 9 Package mechanical data In order to meet environmental reguirements ST offers these devices in different grades of ECOPACK packages depending on their level of environmental compliance ECOPACK specifications grade definitions and product status are available at www st com ECOPACK is an ST trademark Table 20 VFQFPN 24 4 mm x 4 mm mechanical data mm Dim Min Typ Max A 0 80 0 90 1 00 A1 0 0 0 05 A2 0 65 0 80 D 4 00 D1 3 75 E 4 00 E1 3 75 12 0 24 0 42 0 60 0 50 N 24 00 Nd 6 00 Ne 6 00 L 0 30 0 40 0 50 b 0 18 0 30 D2 2 40 2 70 E2 2 40 2 70 Doc ID 14432 Rev 4 51 54 Package mechanical data PM6670S 52 54 Figure 44 Package dimensions SEATING PLANE nee lt D PIN 1 ID e C 0 35 qa Au Lu Uo BOTTOM VIEW Doc ID 14432 Rev 4 4 PM6670S Revision history 10 Revision history Table 21 Document revision history Date Revision Changes 06 Feb 2008 1 Initial release 23 Feb 2009 2 Updated Table 3 on page 8 30 Oct 2009 3 Updated package drawing in cover page Table 20 on page 51 03 Feb 20
50. tion information PM6670S 8 1 2 42 54 The saturation current of the inductor should be greater than Il peak not only in case of hard saturation core inductors Using soft ferrite cores it is possible but not advisable to push the inductor working near its saturation current In Table 13 some inductors suitable for notebook applications are listed Table 13 Evaluated inductors fsw 400 kHz Manufacturer Series Inductance HH paper e COILCRAFT MLC1538 102 1 13 4 21 0 COILCRAFT MLC1240 901 0 9 12 4 24 5 COILCRAFT MVR1261C 112 1 1 20 20 WURTH 7443552100 1 16 20 COILTRONICS HC8 1R2 1 2 16 0 25 4 In pulse skip mode low inductance values produce a better efficiency versus load curve while higher values result in higher full load efficiency because of the smaller current ripple Input capacitor selection In a buck topology converter the current that flows through the input capacitor is pulsed and with zero average value The RMS input current can be calculated as follows Equation 33 1 lcingms fion D 1 D sa Al Neglecting the second term the eguation 10 is reduced to Eguation 34 Icinams Loan D 1 D The losses due to the input capacitor are thus maximized when the duty cycle is 0 5 Eguation 35 Poss ESRcin Icinams max ESRGin 0 5 l o4p max The input capacitor should be selected with a RMS rated current higher than lcinnMs max Tantalu
51. tput voltage in steady state conditions Inductor current Output voltage Vreg Ton Toff t Doc ID 14432 Rev 4 21 54 Device description PM6670S The duty cycle of the buck converter is in steady state conditions given by Eguation 2 D Vout Vin The switching frequency is thus calculated as Equation 3 Vout few D Vin _Gosc 1 Ton K Vsus Gout Kosc osc y Osc where Equation 4a Vosc osc Vin Equation 4b Vsus aouT Vout Referring to the typical application schematic figures on cover page and Figure 29 the final expression is then Equation 5 _Gosc Ra 1 Kosc R1tR2 Kosc Even if the switching freguency is theoretically independent from battery and output voltages parasitic parameters involved in power path like MOSFETs on resistance and inductor s DCR introduce voltage drops responsible for slight dependence on load current In addition the internal delay is due to a small dependence on input voltage The PM6670S switching freguency can be set by an external divider connected to the VOSC pin Figure 29 Switching freguency selection and VOSC pin PM6670S The suggested voltage range for VOSC pin is 0 3 V to 2 V for better switching frequency programmability 22 54 Doc ID 14432 Rev 4 ky PM6670S Device description 7 1 1 Constant on time architecture Figure 30 shows the simplified block diagram of the constant on time controll
52. uctor current and output voltage at light load with pulse skip Inductor current i VDDQ Output Vreg Ton Torr t TIDLE As a consequence the output capacitor is left floating and its discharge depends solely on the current drained from the load When the output ripple on the pin COMP falls under the reference a new shot is triggered and the next cycle begins The pulse skip mode is naturally obtained enabling the zero crossing comparator and automatically takes part in the COT algorithm when the inductor current is about half the ripple current amount i e migrating from continuous conduction mode C C M to discontinuous conduction mode D C M The output current threshold related to the transition between PWM mode and pulse skip mode can be approximately calculated as Equation 20 TR US loup PWM2Skip 8 UT Toy At higher loads the inductor current never crosses zero and the device works in pure PWM mode with a switching frequency around the nominal value A physiological consequence of pulse skip mode is a more noisy and asynchronous than normal conditions output mainly due to very low load If the pulse skip is not compatible with the application the PM6670S when set in adjustable mode of operation allows the user to choose between forced PWM and no audible pulse skip alternative modes see Chapter 7 1 4 on page 30 for details Doc ID 14432 Rev 4 ky PM6670S Device description N
53. y connected to the reference voltage Vr 0 9 V When the feedback voltage becomes lower than the reference voltage the PWM comparator goes to high and sets the control logic turning on the high side MOSFET After the on time calculated as previously described the system releases the high side MOSFET and turns on the synchronous rectifier The voltage drop along ground and supply PCB paths used to connect the output capacitor to the load is a source of DC error Furthermore the system regulates the output voltage valley not the average as shown in Figure 28 Thus the voltage ripple on the output capacitor is an additional source of DC error To compensate this error an integrative network is introduced in the control loop by connecting the output voltage to the COMP pin through a capacitor Cint as shown in Figure 31 Figure 31 Circuitry for output ripple compensation COMP PIN VOLTAGE OUTPUT VOLTAGE The additional capacitor is used to reduce the voltage on the COMP pin when higher than 300 mVpp and is unnecessary for most of applications The trans conductance amplifier gm generates a current proportional to the DC error used to charge the CINT capacitor The voltage across the CINT capacitor feeds the negative input of the PWM comparator forcing the loop to compensate the total static error An internal voltage clamp forces the COMP pin voltage range to 150 mV with respect to VREF This is useful

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ST PM6670S handbook

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