ST STWD100 handbook
Contents
1. STWD100 20 25 Figure 12 SC70 SOT323 5 5 lead small outline transistor package outline SIDE VIEW GAUGE PLANE ALOT Ie COPLANAR LEADS SEATING PLANE b Nx 5 LEADS TOP VIEW SC70 SOT323 5 Doc ID 14134 Rev 6 STWD100 Package mechanical data Table 6 SC70 SOT323 5 5 lead small outline transistor package mechanical data Dimensions Symbol mm inches Typ Min Max Typ Min Max A 0 80 1 10 0 031 0 043 Al 0 00 0 10 0 000 0 004 A2 0 90 0 80 1 00 0 035 0 031 0 039 b 0 15 0 30 0 006 0 012 0 10 0 22 0 004 0 009 D 2 00 1 80 2 20 0 079 0 071 0 087 2 10 1 80 2 40 0 083 0 071 0 094 E1 1 25 1 15 1 35 0 049 0 045 0 053 e 0 65 0 026 e1 1 30 0 051 L 0 36 0 26 0 46 0 014 0 010 0 018 lt 0 8 0 8 N 5 5 kr Doc ID 14134 Rev 6 21 25 Part numbering STWD100 7 Part numbering Table 7 Ordering information scheme Example STWD100 N P WY 3 F Device type STWD100 Output type N open drain active low P push pull active low Device version P twp 3 4 ms tpw twp 3 4 ms W twD 6 3 ms tpw 210ms x two 102 ms tpw 210ms Y twp 1 6 s tpw 210 ms Package WY SOT23 5 W8 SC70 5 SOT323 5 Temperature range 3 40 to 125 C Shipping method E ECOPACK package tubes F ECOPACK2. Doc ID 14134 Rev 6 STWD100 DC and AC parameters Table 4 DC and AC characteristics Symbol Description Test condition Min Typ Max Unit Vcc Operating voltage 2 7 5 5 5 V loc Vec supply current 13 26 HA Lo Open drain output leakage current From output to the GND or Vcc 1 1 pA Input leakage current WDI 1 1 uA Vin Input high voltage WDI EN 0 7 Voc V Vi Input low voltage WDI EN 0 3 Vcc V Voc 22 7 V SINK 1 2 mA 0 3 V VoL Output low voltage WDO Vac 34 5 V SINK 3 2 mA 0 4 V V Output high voltage WDO push pull Vcc 2 2 7 V source 500 HA 0 8 Voc V H 9 only Vec gt 4 5 V SOURCE 800 pA 0 8 Vec V Enable pin EN EN input pulse width 1 us EN glitch rejection 100 ns EN to WDO delay 200 ns EN pull down resistance 32 63 100 kQ Watchdog Timer Vstart Timer startup voltage 1 9 2 2 2 7 V STWD100xP 2 3 3 4 4 6 ms STWD100xW 4 3 6 3 8 6 ms twp Watchdog timeout period STWD100xX 71 102 142 ms STWD100xY 1 12 1 6 2 24 s tpw _ Watchdog active time 140 210 280 ms WDI to WDO delay 150 ns WDI pulse width 1 us WDI glitch rejection 100 ns 1 Valid for ambient operating temperature Th 40 to 125 C Vog 2 7 V to 5 5 V except where noted WDO will assert for minimum of 10 us even if EN transitions high DO will assert for minimum of 10 us regardless of transition o
3. hJ STWD100 Watchdog timer circuit Features Current consumption 13 pA typ m Available watchdog timeout periods are 3 4 ms 6 3 ms 102 ms and 1 6 s m Chip enable input m Open drain or push pull WDO output m Operating temperature range 40 to 125 C m Package SOT23 5 SC70 5 SOT323 5 Applications m Telecommunications m Alarm systems m Industrial equipment m Networking m Medical equipment m UPS uninterruptible power supply Datasheet production data SOT23 5 WY SC70 5 SOT323 5 W8 March 2012 Doc ID 14134 Rev 6 1 25 This is information on a product in full production www st com Contents STWD100 Contents 1 Description miesas aumai dere PP me ae wn ale ee 5 2 Operati rsss a a E Sheena E eme de we 7 2 1 Watchdog input WDI 0 0 ees 7 2 2 Watchdog output WDO 11 121sk ks kaka aaa aaa aka RE 7 2 3 Chip enable input ss rn 8 2 4 Applications information 2 2 s 2sssas asas 8 Interfacing to microprocessors with bidirectional reset pins 8 3 Watchdog timing rr ana 10 4 Maximum Fn a aan eee on sa Mann deed MAGKA 15 5 DC and AC parameters 2sssssnnnnnnnnnnnnnnnn r 16 6 Package mechanical data 0 00 eee aaa 18 7 PUND a naa 22 8 Package marking information 00000000 eee eee eee eee 23 9 Revision history 3030 a 24 2 25 Doc ID 14134 Rev 6 ky STWD100 List of tables List of tabl
4. package tape and reel Note Please check device version availability on www st com Please contact local ST sales office for new device version request 22 25 Doc ID 14134 Rev 6 STWD100 Package marking information 8 Package marking information Table 8 Device versions with marking descriptions Watchdog Part number timing period Output configuration Topside marking manna twd tpw STWD100NPxxxx 3 4 ms 3 4 ms open drain WNP PYWW STWD100NWxxxx 6 3ms 210 ms open drain WNW PYWW STWD100NXxxxx 102ms 210 ms open drain WNX PYWW STWD100NYxxxx 1 6 s 210 ms open drain WNY PYWW STWD100PWxxxx 6 3ms 210 ms push pull WPW PYWW STWD100PXxxxx 102ms 210 ms push pull WPX PYWW STWD100PYxxxx 1 6s 210 ms push pull WPY PYWW 1 Description P assembly plant code Y assembly year 0 to 9 WW assembly work week 01 to 52 ky Doc ID 14134 Rev 6 23 25 Revision history STWD100 9 Revision history Table 9 Document revision history Date Revision Changes 08 Nov 2007 1 Initial release 23 Jan 2008 2 PU page and Table 4 document status upgraded to full 28 Jan 2008 3 Updated cover page 17 Mar 2008 4 Updated cover page Figure 4 7 9 and Table 4 8 31 Jul 2008 5 Updated Features on cover page and Table 4 Added product maturity information and section Applications 05 Mar 2012 6 updated Section 1 Section 2 4 Section 4 Section 5 Section 7 and Section 8
5. ECOPACK text minor text corrections throughout document 24 25 Doc ID 14134 Rev 6 STWD100 Please Read Carefully Information in this document is provided solely in connection with ST products STMicroelectronics NV and its subsidiaries ST reserve the right to make changes corrections modifications or improvements to this document and the products and services described herein at any time without notice All ST products are sold pursuant to ST s terms and conditions of sale Purchasers are solely responsible for the choice selection and use of the ST products and services described herein and ST assumes no liability whatsoever relating to the choice selection or use of the ST products and services described herein No license express or implied by estoppel or otherwise to any intellectual property rights is granted under this document If any part of this document refers to any third party products or services it shall not be deemed a license grant by ST for the use of such third party products or services or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoever of such third party products or services or any intellectual property contained therein UNLESS OTHERWISE SET FORTH IN ST S TERMS AND CONDITIONS OF SALE ST DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY WITH RESPECT TO THE USE AND OR SALE OF ST PRODUCTS INCLUDING WITHOUT LIMITATI
6. Kong India Israel Italy Japan Malaysia Malta Morocco Philippines Singapore Spain Sweden Switzerland United Kingdom United States of America www st com ky Doc ID 14134 Rev 6 25 25
7. WDO is high WDO Al12664 12 25 Doc ID 14134 Rev 6 STWD100 Watchdog timing Figure 9 Trigger after timeout STWD100xP Voc If a WDI trigger occurs after the WDO output has asserted the output will de assert but Na WDI V r E with a pulse width of at least 10 us min twD WDO N X gt 10 us min STWD100xW STWD100xX STWD100xY CC Trigger ignored while P WDO is low If a WDI trigger occurs after the WDO output has asserted it is ignored and the output remains asserted for the specified time tpyy Da WDI X Al12665 9 Doc ID 14134 Rev 6 13 25 Watchdog timing STWD100 Figure 10 Enable pin EN triggering STWD100xx 2 2 V Whenever EN is high all timing is Voc reset and the part is disabled Timing commences from 0 when WDI EN goes low X ie 1 or O but not floating STWD100xx If EN goes high while WDO is asserted WDO will de assert but only after the nominal minimum Ns WDI X ie 1 or O but not floating pulse width of 10 us has elapsed twp WDO _ EN X DISABLED Al12666 14 25 Doc ID 14134 Rev 6 STWD100 Maximum ratings 4 Maximum ratings Stressing the device above the rating listed in Table 2 may cause permanent damage to the device These are stress ratings only and operation of the device at these or any other conditions above those indicated in Table 3 of this s
8. ON IMPLIED WARRANTIES OF MERCHANTABILITY FITNESS FOR A PARTICULAR PURPOSE AND THEIR EQUIVALENTS UNDER THE LAWS OF ANY JURISDICTION OR INFRINGEMENT OF ANY PATENT COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT UNLESS EXPRESSLY APPROVED IN WRITING BY TWO AUTHORIZED ST REPRESENTATIVES ST PRODUCTS ARE NOT RECOMMENDED AUTHORIZED OR WARRANTED FOR USE IN MILITARY AIR CRAFT SPACE LIFE SAVING OR LIFE SUSTAINING APPLICATIONS NOR IN PRODUCTS OR SYSTEMS WHERE FAILURE OR MALFUNCTION MAY RESULT IN PERSONAL INJURY DEATH OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE ST PRODUCTS WHICH ARE NOT SPECIFIED AS AUTOMOTIVE GRADE MAY ONLY BE USED IN AUTOMOTIVE APPLICATIONS AT USER S OWN RISK Resale of ST products with provisions different from the statements and or technical features set forth in this document shall immediately void any warranty granted by ST for the ST product or service described herein and shall not create or extend in any manner whatsoever any liability of ST ST and the ST logo are trademarks or registered trademarks of ST in various countries Information in this document supersedes and replaces all information previously supplied The ST logo is a registered trademark of STMicroelectronics All other names are the property of their respective owners 2012 STMicroelectronics All rights reserved STMicroelectronics group of companies Australia Belgium Brazil Canada China Czech Republic Finland France Germany Hong
9. WD100xX STWD100xY At power up WDI is a don t care It can be 1 or 0 Low to high or high to low transition on WDI will reset timer But no input transition is required to begin timing Na Na Power up watchdog timer starts running as soon as Vcc rises above 2 2 V 2 2V Vcc Wop X ie 1 or O but not floating twp WDO Power up watchdog timer starts running as soon as Vcc rises above 2 2 V 2 2V Voc WDI X ie 1 or O but not floating t WD WDO Al12662V1 10 25 Doc ID 14134 Rev 6 STWD100 Watchdog timing Figure 7 Normal triggering STWD100xP Vec Trigger only on rising edge Falling edge is ignored WDI STWD100xW STWD100xX STWD100xY Vcc Trigger on rising and falling edge of WDI Kag WDI Al12663 9 Doc ID 14134 Rev 6 11 25 Watchdog timing STWD100 Figure 8 Timeout without re trigger STWD100xP After a timeout and WDO is asserted it will stay low for twp time period then return high If no WDI trigger event occurs WDO will again assert low after typ time period This cycle repeats until a WDI trigger event occurs STWD100xW STWD100xX STWD100xY After a timeout and WDO is asserted it will stay low for Vec WDI Vcc tpw time period then Ng WD return high If no WDI trigger event occurs within twp time period WDO will again assert low This cycle repeats until a WDI trigger event occurs while
10. es Table 1 SOT23 5 and SC70 5 SOT323 5 pin description 0 00 5 Table 2 Absolute maximum ratings ete 15 Table 3 Operating and AC measurement conditions 0c eee eee 16 Table 4 DC and AC characteristics 2220 eee 17 Table 5 SOT23 5 5 lead small outline transistor package mechanical data 19 Table 6 SC70 SOT323 5 5 lead small outline transistor package mechanical data 21 Table 7 Ordering information scheme 0000 22 Table 8 Device versions with marking descriptions eee 23 Table 9 Document revision history 0 0 0 0 eae 24 ky Doc ID 14134 Rev 6 3 25 List of figures STWD100 List of figures Figure 1 Figure 2 Figure 3 Figure 4 Figure 5 Figure 6 Figure 7 Figure 8 Figure 9 Figure 10 Figure 11 Figure 12 4 25 SOT23 5 and SC70 5 SOT323 5 package connections 1 1 2 aa 5 Logic diagram masa haaa Ph AK ARKA deere Sn RR ates aaa eee ied 6 Block diagrams sess rag Eka ever ees whew se eee NA ed tae De eta Pee waged ee 6 Open drain WDO output connection n s sasaaa aaaea aeea 8 Interfacing to microprocessors with bidirectional reset O 9 POWEr UpP sta whee a R RRR NYA ceeded deta a R GVARAR RRR FR 10 NORMAN 22 2c kvik bs peeled l k s k R a ee de V 11 Timeout without re trigger isssusssnsanssannannnsnnnnnnnnnnnnnia 12 Trigger after time
11. every twp and tpw on STWD100xW STWD100xxX and STWD100xY see Figure 8 Watchdog output WDO When the Vcc exceeds the timer startup voltage Vaart after power up the internal watchdog timer starts counting If the timer is not cleared within the twp the WDO will go low see Figure 6 After exceeding the twp the WDO is asserted for tpw on STWD100xW STWD100xX and STWD100xY regardless of possible WDI transitions see Figure 9 On STWD100xP WDO is asserted for a minimum of 10 us and a maximum of twp after exceeding the twp period see Figure 8 and Figure 9 The STWD100 has an active low open drain or push pull output An external pull up resistor connected to any supply voltage up to 6 V is required in case of open drain WDO output see Figure 4 Select a resistor value large enough to register a logic low and small enough to register a logic high while supplying all input current and leakage paths connected to the reset output line A 10 kQ pull up resistor is sufficient in most applications Doc ID 14134 Rev 6 7 25 Operation STWD100 Figure 4 Open drain WDO output connection STWD100 5 V system Al12645V2 2 3 Chip enable input EN All states mentioned in Section 2 1 Watchdog input WDI and Section 2 2 Watchdog output WDO are valid under the condition that EN is in logical low state The behavior of EN is common to all versions i e STWD100xP STWD100xW STWD100xX and STWD100xY If the EN goes
12. high after power up in less than twp from the moment that Voc exceeds the timer startup voltage Vstart the WDO will stay high for the same time period as EN plus twp see Figure 10 If the EN goes high anytime during normal operation the WDO will go high as well but the minimum possible WDO pulse width is 10 us see Figure 10 The pulses on the EN pin with a duration of at least 1 us are detected and glitches shorter than 100 ns are ignored 2 4 Applications information Interfacing to microprocessors with bidirectional reset pins 8 25 Microprocessors with bidirectional reset pins can contend with the STWD100 watchdog output WDO For example if the WDO output is driven high and the micro wants to pull it low signal contention will result To prevent this from occurring connect a 4 7 kQ resistor between the WDO output and the microprocessors reset I O as in Figure 5 Doc ID 14134 Rev 6 ky STWD100 Operation Figure 5 Interfacing to microprocessors with bidirectional reset I O Buffered reset to other system components Vcc STWD100 Microprocessor WDO RST Al12643V2 ky Doc ID 14134 Rev 6 9 25 Watchdog timing STWD100 3 Figure 6 Watchdog timing Power up STWD100xP At power up WDI is a don t care It can be 1 or 0 Can also transition from high to low Low to high transition on WDI will reset timer But no input transition is required to begin timing STWD100xW ST
13. n WDI valid for STWD100xP only Doc ID 14134 Rev 6 17 25 Package mechanical data STWD100 6 18 25 Package mechanical data In order to meet environmental requirements ST offers these devices in different grades of ECOPACK packages depending on their level of environmental compliance ECOPACK specifications grade definitions and product status are available at www st com ECOPACK is an ST trademark The maximum ratings related to soldering conditions are also marked on the inner box label Figure 11 SOT23 5 5 lead small outline transistor package outline bat o A2 w Hii 1 Cf ae ol D p ft ll _ LY LI 1 N J Al n S SOT23 5 Doc ID 14134 Rev 6 ky STWD100 Package mechanical data Table 5 SOT23 5 5 lead small outline transistor package mechanical data Dimensions Symbol mm inches Typ Min Max Typ Min Max A 1 20 0 90 1 45 0 047 0 035 0 057 Al 0 15 0 006 A2 1 05 0 90 1 30 0 041 0 035 0 051 0 40 0 35 0 50 0 016 0 014 0 020 0 15 0 09 0 20 0 006 0 004 0 008 D 2 90 2 80 3 00 0 114 0 110 0 118 D1 1 90 0 075 E 2 80 2 60 3 00 0 110 0 102 0 118 e 0 95 0 037 F 1 60 1 50 1 75 0 063 0 059 0 069 K 0 10 0 10 L 0 35 0 10 0 60 0 014 0 004 0 024 Doc ID 14134 Rev 6 19 25 Package mechanical data
14. oc Supply voltage Doc ID 14134 Rev 6 5 25 Description STWD100 Note Note 6 25 Figure 2 Logic diagram Voc WDI STWD100 Na EN GND Al12640a WDO output is available in open drain or push pull configuration Figure 3 Block diagram WDI Output timing CLR WDO Al12641V2 Positive pulse on enable pin EN longer than 1 us resets the watchdog timer Doc ID 14134 Rev 6 STWD100 Operation 2 2 1 2 2 Operation The STWD100 device is used to detect an out of control MCU The user has to ensure watchdog reset within the watchdog timeout period otherwise the watchdog output is asserted and MCU is restarted The STWD100 can be also enabled or disabled by the chip enable pin Watchdog input WDI The WDI input has to be toggled within the watchdog timeout period typ otherwise the watchdog output WDO is asserted The internal watchdog timer which counts the twp period is cleared either 1 by a transition on watchdog output WDO see Figure 8 or 2 by apulse on enable pin EN see Figure 10 or 3 by toggling WDI input low to high on all versions and high to low on STWD100xW STWD100xX and STWD100xY only The pulses on WDI input with a duration of at least 1 us are detected and glitches shorter than 100 ns are ignored If WDI is permanently tied high or low and EN is tied low the WDO toggles every 3 4 ms twp on STWD100xP and
15. out 2 nn 13 Enable pin EN triggering dct ada mak Gaan DARA ka Pata meee KB 14 SOT23 5 5 lead small outline transistor package outline 18 SC70 SOT323 5 5 lead small outline transistor package outline 20 Doc ID 14134 Rev 6 ky STWD100 Description Description The STWD100 watchdog timer circuits are self contained devices which prevent system failures that are caused by certain types of hardware errors non responding peripherals bus contention etc or software errors bad code jump code stuck in loop etc The STWD100 watchdog timer has an input WDI and an output WDO The input is used to clear the internal watchdog timer periodically within the specified timeout period twa While the system is operating correctly it periodically toggles the watchdog input WDI If the system fails the watchdog timer is not reset a system alert is generated and the watchdog output WDO is asserted The STWD100 circuit also has an enable pin EN which can enable or disable the watchdog functionality The EN pin is connected to the internal pull down resistor The device is enabled if the EN pin is left floating Figure 1 SOT23 5 and SC70 5 SOT323 5 package connections Al12639b Table 1 SOT23 5 and SC70 5 SOT323 5 pin description Pin number Name Description 1 WDO Watchdog output 2 GND Ground 3 EN Enable pin 4 WDI Watchdog input 5 V
16. pecification is not implied Exposure to absolute maximum rating conditions for extended periods may affect device reliability Refer also to the STMicroelectronics SURE program and other relevant quality documents Table 2 Absolute maximum ratings Symbol Parameter Value Unit TsTG Storage temperature Vcc off 55 to 150 C Tso Lead solder temperature for 10 seconds 260 NG Vio Input or output voltage 0 3 to Vog 0 3 V Voc Supply voltage 0 3 to 7 0 V lo Output current 20 mA Pp Power dissipation 320 mW 1 Reflow at peak temperature of 260 C total thermal budget not to exceed 245 C for greater than 30 seconds Doc ID 14134 Rev 6 15 25 DC and AC parameters STWD100 5 16 25 DC and AC parameters This section summarizes the operating measurement conditions and the DC and AC characteristics of the device The parameters in Table 4 that follows are derived from tests performed under the measurement conditions summarized in Table 3 Designers should check that the operating conditions in their circuit match the operating conditions when relying on the quoted parameters Table 3 Operating and AC measurement conditions Parameter Value Unit Voc supply voltage 2 7 to 5 5 V Ambient operating temperature Ta 40 to 125 C Input rise and fall times lt 5 ns Input pulse voltages 0 2 to 0 8 Voc Input and output timing ref voltages 0 3 to 0 7 Voc V
Download Pdf Manuals
Related Search
ST STWD100 handbook