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FUJITSU SEMICONDUCTOR MB90520 Series handbook

1. ES Details of A part Ex 0 20 E 1 50 0 10 z Ex EG ma Mounting height ES INDEX 059 tes 20 C FD a MAI bb bbb b b ob bo obo ob id LEAD No 1 l i 0 16 0 03 0 14540 055 0 50 0 20 004 004 0 40 016 006 001 8 10 07 003 8 006 002 020 008 ee ot 0 45 0 75 0 25 010 018 030 L zd 1998 FUJITSU LIMITED F1200065 3C 4 Dimensions in mm inches 120 pin Plastic QFP FPT 120P M13 22 60 0 20 890 008 SQ 3 85 152 MAX Mounting height 0 05 002 MIN STAND OFF 20 00 0 10 787 004 SQ Details of A part f 14 50 21 60 0 15 006 571 850 REF NOM I l 0 15 006 I I I I INDEX 0 15 006 MAX 0 40 016 MAX Details of B part Q LEAD No CO t 3 I I ME 0 50 0197 L 0 20 0 10 r 0 125 0 05 I 1 008 004 L9 10 08 003 005 002 i 0 10 J HIO 7 1 I 40 50 0 20 020 008 I 7 0 10 004 Br A cuj ar car car c ar ar car car ar car car ar E car car ar ar cx ar ar car ar E E Ex Ex E E E E E Ex E E E E E E E E
2. Gate input 3 P lValidclock Wait signal 7 Prescaler decision circuit To UART lt To 8 10 bit A D converter gt Output control circuit Di Output signal Input ni generation control iP circuit circuit Di P71 TOO OUTS5 External OE TM P73 TO1 OUT7 clock P70 TIO OUT4 5 lt P72 TI1 OUT6 gt Operation Function select control circuit Jestfestefroogrooipoodoureourypetofvre uF enre me Timer control status register TMCSRO Clear lt TMCSR1 gt EPCS lt gt Interrupt request signal 38 1 2 1 The timer has ch 0 and ch 1 and figures bracketed by lt gt are for ch 1 lt 40 gt 2 Interrupt number Machine clock frequency 45 MB90520 Series 46 6 16 bit I O Timer The 16 bit I O timer module consists of two 16 bit free run timers two input capture circuits ICU and eight output comparators OCU This module allows two independent waveforms to be output on the basis of the 16 bit free run timer Input pulse width and external clock periods can therefore be measured Block diagram Internal data bus Input capture 0 1 y Dedicated 16 bit Dedicated Output compare 0 1 ICU bus free run timer 1 2 OCU MB90520 Series EE 1 16 bit Free run Timer 1 2 The 16 bit free run timer consists of a 16 bit up counter a control register and a communications prescaler
3. Pins dedicated to segment output C pin output Pin for capacitor connection N C pin for the MB90F523 Analog power input protector Standby control for input interruption Hysteresis input DAO CMOS hysteresis input output Pin for analog output CMOS output During analog output CMOS output is not produced Analog output has priority over CMOS output DAE 1 Provided with a standby control function for input interruption Continued 15 16 MB90520 Series Circuit Remarks Input pin for ref power for the A D converter Provided with power protection Hysteresis input Standby control for input interruption Analog input lo 4 mA Hysteresis input analog input CMOS output Provided with a standby control for input interruption Hysteresis input Standby control for input interruption lo 4 mA CMOS hysteresis input output Segment input Standby control to cut off the input is available in segment input operation Jo gt Hysteresis input L Standby control for input interruption Hysteresis input Nch open drain output High current for LCD drive Standby control to cut off the input is available in segment input operation lo 10 mA Reference power supply pin for the LCD controller MB90520 Series EE
4. 1 AVcc AVRH AVRL and DVcc shall never exceed Vcc AVRL shall never exceed AVRH 2 Vcc 2 AVcc 2 DVcc2 3 0V 8 Vi and Vo shall never exceed Vcc 0 3 V 4 The maximum output current is a peak value for a corresponding pin 5 Average output current is an average current value observed for a 100 ms period for a corresponding pin 6 Total average current is an average current value observed for a 100 ms period for all corresponding pins Note Average output current operating current x operating efficiency WARNING Semiconductor devices can be permanently damaged by application of stress voltage current temperature etc in excess of absolute maximum ratings Do not exceed these ratings 80 MB90520 Series EE 2 Recommended Operating Conditions AVss Vss 0 0 V Parameter Remarks Normal operation MB90522 MB90523 Normal operation MB90F523 Guaranteed frequency 10 MHz Power supply voltage j at 4 0 V to 4 5V Retains status at the time operation stops Smoothing capacitor Operating temperature Use a ceramic capacitor or a capacitor with equivalent frequency characteristics The smoothing capacitor to be connected to the Vcc pin must have a capacitance value higher than Cs WARNING The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device All of the device s electrical characteris
5. P43 SOTO Receive parity counter e DU P42 SINO Shift register for transmission U Start transmission I l b TP decision circuit complete To El OS reception error generation signal to CPU Internal data bus SCR register EE SMA ese register 55 FRE SSR gt register DE Interrupt number 60 10 DTP External Interrupt Circuit MB90520 Series The DTP Data Transfer Peripheral which is located between the peripheral circuit outside the device and the F MC 16LX CPU receives an interrupt request or DMA request generated by the external peripheral circuit for transmission to the FAMC 16LX CPU It is used to activate the intelligent I O service or interrupt processing As with request levels two types of H and L can be selected for the intelligent I O service Rising and falling edges as well as H and L can be selected for an external interrupt request The external peripheral circuit is connected outside the MB90520 series device 1 Register Configuration DTP interrupt factor register EIRR Address bit15 bit14 bit13 bit12 bit 11 RW RW RW RW RW DTP interrupt enable register ENIR Address bit 7 bit 6 bit 5 bit 4 bit 3 RW RW RW RW Request level setting e ELVR Address bit7 bit6 bit5 bit4 bit3 RW RW RW RW bit 15 bit14 bit13 bit12 bit
6. 62 MB90520 Series EE Wake up Interrupt Wake up interrupts transmit interrupt request L level generated by peripheral equipment located between external peripheral devices and the F MC 16LX CPU to the CPU and invoke interrupt processing The interrupt does not conform to the exterded intelligent I O service EIPOS 1 Register Configuration Wake up interrupt flag register EIFR Address bit 15 biti4 bit13 bit12 bitii bit10 bit9 bit8 Initial value R W Wake up interrupt enable register EICR Address bit 15 bit14 bit13 bit12 bit11 bit10 bit9 bits Initial value w w w w w w w w R W Readable and writable W Write only Undefined bits read value undefined 2 Block Diagram Internal data bus Wake up interrupt flag Wake up interrupt register EIFR enable register EICR P11 WIH 3 gt prenw Pn di Wake up interrupt request 16 P14 W14 Pin EN D P16 WI6 Do P17 WI7 c Interrupt number 63 64 MB90520 Series 12 Delayed Interrupt Generation Module The delayed interrupt generation module generates interrupts for switching tasks By using this module hardware interrupt requests to the CPU can be generated and cancelled using software This module does not conform to the extended intelligent I O service EI OS 1 Register Configurat
7. FUJITSU SEMICONDUCTOR 16 bit Proprietary Microcontroller CMOS F2MC 16LX MB90520 Series MB90522 523 F523 V520 m DESCRIPTION The MB90520 series is a general purpose 16 bit microcontroller developed and designed by Fujitsu for process control applications in consumer products that require high speed real time processing The instruction set of the FAMC 16LX CPU core inherits AT architecture of the family with additional instruction sets for high level languages extended addressing mode enhanced multiplication division instructions and enhanced bit manipulation instructions The microcontroller has a 32 bit accumulator for processing long word data The MB90520 series has peripheral resources of 8 10 bit A D converter 8 bit D A converter UART SCI extended I O serial interfaces 0 and 1 8 16 bit up down counter timers 0 and 1 8 16 bit PPG timers 0 and 1 I O timer 16 bit free run timers 1 and 2 input captures 0 and 1 ICU output compares 0 and 1 OCU and an LCD controller driver F MC stands for FUJITSU Flexible Microcontroller a registered trademark of FUJITSU LIMITED B FEATURES Clock Embedded PLL clock multiplication circuit Operating clock PLL clock can be selected from divided by 2 of oscillation or one to four times the oscillation at oscillation of 4 MHz 4 MHz to 16 MHz The system can be operated by a sub clock rated at 32 768 kHz Minimum instruction execut
8. 1995 FUJITSU LIMITED F12001382C3 Dimensions in mm inches 105 MB90520 Series EE FUJITSU LIMITED For further information please contact Japan FUJITSU LIMITED Corporate Global Business Support Division Electronic Devices Shinjuku Dai Ichi Seimei Bldg 7 1 Nishishinjuku 2 chome Shinjuku ku Tokyo 163 0721 Japan Tel 81 3 5322 3347 Fax 81 3 5322 3386 http edevice fujitsu com North and South America FUJITSU MICROELECTRONIGS ING 3545 North First Street San Jose CA 95134 1804 U S A Tel 1 408 922 9000 Fax 1 408 922 9179 Customer Response Center Mon Fri 7 am 5 pm PST Tel 1 800 866 8608 Fax 1 408 922 9179 http www fujitsumicro com Europe FUJITSU MICROELECTRONICS EUROPE GmbH Am Siebenstein 6 10 D 63303 Dreieich Buchschlag Germany Tel 49 6103 690 0 Fax 49 6103 690 122 http www fujitsu fme com Asia Pacific FUJITSU MICROELECTRONICS ASIA PTE LTD 05 08 151 Lorong Chuan New Tech Park Singapore 556741 Tel 65 281 0770 Fax 65 281 0220 http www fmap com sg Korea FUJITSU MICROELECTRONICS KOREA LTD 1702 KOSMO TOWER 1002 Daechi Dong Kangnam Gu Seoul 135 280 Korea Tel 82 2 3484 7100 Fax 82 2 3484 7111 F0012 FUJITSU LIMITED Printed in Japan All Rights Reserved The contents of this document are subject to change without notice Customers are advised to consult with FUJITSU sales representatives bef
9. P50 SIN2 AIN1 Control circuit P52 SCK2 ZIN1 P51 SOT2 BI Shift clock counter Internal clock Serial mode control status register SMCSH L Interrupt number Interrupt request gt 15 SMCSO0 17 SMCS1 57 MB90520 Series bsa 9 UART SCI UART SCI is a general purpose serial data communication interface for performing synchronous or asynchronous communication start stop synchronization system Data buffer Full duplex double buffer Transfer mode Clock synchronized with start and stop bit Clock asynchronized start stop synchronization system Baud rate Embedded dedicated baud rate generator External clock input possible Internal clock a clock supplied from 16 bit re load timer 0 can be used Asynchronization 9615 bps 31250 bps 4808 bps 2404 bps 1202 bps CLK synchronization 1 Mbps 500 kbps 250 kbps 125 kbps 62 5 kbps I 12 MHz and 16 MHz Data length 8 bit without a parity bit 7 bit with a parity bit Signal format NRZ Non Return to Zero system Reception error detection Framing error Overrun error Parity error multi processor mode is supported enabling setup of any baud rate by an external clock Interrupt request Receive interrupt reception complete receive error detection Transmit interrupt transmisson complete Transmit receive conforms to extended intelligent I O
10. Ta 25 C 6 0 9 9 9 0 4 9 4 0 9 9 0 Vcc 2 5 V 4 0 12 0 16 0 Fc MHz Icct uA 20 TA 25 C 18 16 M Fc 8 kHz 12 10 8 6 4 2 3 0 6 0 Voc V lccr UA 10 9 8 Vcc 6 0 V 7 Vcc 5 5 V 6 Vcc 5 0V Vcc 4 5 V 5 Vcc 4 0 V 4 Vcc 3 5 V Vcc 3 0 V 3 Vcc 2 5 V 2 1 20 100 Ta C lt lt lt lt lt lt lt Iccs Fe 6 0 8 4 5 7 35 6 3 0 5 Voc 2 5 4 3 2 1 6 0 8 0 12 0 16 0 Fc MHz Voc IccH UA 10 Ta 25 C 9 8 7 6 5 4 3 2 1 4 0 6 0 Voc V IccH Ta Ico UA 10 9 8 Vcc 6 0 V Vcc 5 5 V 7 Vcc 5 0 V 6 Vcc 4 5 V Vcc 2 4 0V 5 Vcc 3 5 V 4 Vcc 3 0 V Vcc 2 5 V 3 2 1 10 40 100 Ta C lt lt lt lt lt lt lt lt MB90520 Series UA UA 20 Vcc 6 0 V i 18 pr Vcc 5 5 V 12 Vcc 6 0 V 16 Vec 5 0 V Vcc 5 5 V Vcc 4 5 V Veo B0 V 14 Vcc 4 0 V 10 M dc Vcc 2 3 5 V OG i Vec 8 0 V 8 Voc 4 0 V c Voc 2 5 V Voc
11. gt 27 interrupt request OCU control status register ch 67 OCS67 TE bebe reborn ffx x E EE NN l Compare control circuit 7 OCP7 43 e OCU compare register ch 7 gt Output control circuit 7 Compare control circuit 6 OCP6 OCU compare register ch 6 Compare control circuit 5 OCP5 OCU compare register ch 5 Compare control circuit 4 P73 TO1 OUT7 P72 TM OUT6 Internal data bus P71 TO0 QUT5 Output control circuit 6 Output control circuit 5 Output control circuit 4 P70 TI0 OUT4 OCP4 dub OCU compare register ch 4 T L Pee en ene Fe T Foy OCU control status register ch 45 OCS45 ES Output compare D gt 25 interrupt request Interrupt number 52 8 16 bit Up Down Counter Timer 0 1 The 8 16 bit up down counter timer consists of six event input pins two 8 bit up down counters two 8 bit re load compare registers and their controllers 1 Register Configuration MB90520 Series Up down count register 0 UDCRO Address bit7 bit6 bit5 bit 4 bit 3 bit2 bill EP Read only Write only RW RW RW RW Readable and writable Undefined bits read value undefined R W R W bit 0 or oor ov om oo oe om om om R R R R R R R R Up down count register 1 UDCR1 Address bit15 bit14 bit
12. Pull up resistance 00 to 07 P10 to P17 P40 to P47 RST MDO MD1 Pull down resistance MD2 Continued MB90520 Series EE AVcc Voc 5 0 V 10 AVss Vss 0 0 V Ta 40 C to 85 C Parameter Symbol Pin name Condition Internal operation at 16 MHz Vcc at 5 0 V Normal operation Remarks MB90522 MB90523 MB90F523 Internal operation at 16 MHz Vcc at 5 0 V A D converter operation MB90522 MB90523 MB90F523 Internal operation at 16 MHz Vcc at 5 0 V D A converter operation MB90522 MB90523 MB90F523 When data is written or erased in flash mode MB90F523 Internal operation at 16 MHz Vcc at 5 0 V In sleep mode MB90522 MB90523 MB90F523 Internal operation at 8 kHz Vcc at 5 0 V Ta 25 C Subsystem operation MB90522 MB90523 MB90F523 Internal operation at 8 kHz Vcc at 5 0 V Ta 25 C In subsleep mode MB90522 MB90523 MB90F523 Internal operation at 8 kHz Vcc at 5 0 V Ta 25 C In clock mode MB90522 MB90523 MB90F523 Ta 25 C In stop mode MB90522 MB90523 MB90F523 Input capacitance Other than AVcc AVss C Vcc Vss Continued 84 MB90520 Series EEE Sen Continued Parameter Symbol Pin name VO to Vi V1 to V2 V2 to V3 AVcc
13. 1 9 Peripheral clock 4 0 1 9 Peripheral clock 2 Peripheral clock 1 0 1 9 Count clock selector 3 Select signal HCLK Oscillation clock frequency Fees oso romere power ren PPGO 1 Output control register PPGOEO 1 Interrupt number 0 Machine clock frequency 43 MB90520 Series EE 5 16 bit Re load Timer 0 1 With an Event Count Function The 16 bit re load timer has an internal clock mode for counting down in synchronization to three types of internal clocks and an event count mode for counting down by detecting a given edge of the pulse input to the external bus pin Either of the two functions can be selectively used For this timer an underflow is defined as the timing of transition from the counter value of 0000k to FFFFu According to this definition an underflow occurs after a counter value of re load register setting value 1 In operating the counter the re load mode for repeating counting operation after re loading a counter value after anunderflow orthe one shot mode for stopping the counting operation after an underflow can be selectively used Because the timer can generate an interrupt upon an underflow the timer conforms to the extended intelligent I O service EI OS The MB90520 series has 2 channels of 16 bit re load timers 1 Register Configuration Timer control status register upper digits ch 0 ch 1
14. clock Divided Divided Divided Divided by 2048 by 4 by 4 by 8 Sub clock Clock timer 78 21 Clock Monitor Function The clock monitor function outputs the frequency divided machine clock signal for monitoring purposes from the CKOT pin 1 Register configuration MB90520 Series EEE Sen Clock output enable register bit6 bit5 bit4 X bit3 R W R W Readable and writable Undefined bits read value undefined bit2 biti bitO Address Initial value RW RW RW 2 Block Diagram Internal data bus p Machine clock frequency Divider circuit P31 CKOT 79 MB90520 Series EE ELECTRICAL CHARACTERISTICS 1 Absolute Maximum Ratings AVss Vss 0 0 V Parameter Remarks Vss 6 0 Vss 6 0 Power supply voltage PES J Vss 6 0 Vss 6 0 Input voltage Vcc 6 0 Output voltage Vcc 6 0 L level maximum output current 15 L level average output current loLav L level total maximum output current L level total average output current H level maximum output current loH H level average output current loHav H level total maximum output current Xlou H level total average output current Xlouav Power consumption Pp Operating temperature TA Storage temperature
15. 3 5 V 6 Voc 3 0 V 8 Vcc 2 2 5 V 6 4 LE 4 2 2 440 70 100 20 470 100 TA C TA C 2 Power Supply Current MB90F523 lec mA lccs mA 140 40 Ta 25 C T Ta 25 C 120 35 Fc 16 MHz 30 109 Fc 16 MHz Fc 12 5 MHz 25 a Fc 12 5 MHz FREE 29 Fc 10 MHz eg Fc 5 MH ec 15 Fc 8 MHz Fc 4 MHz 40 Fc 5 MHz 2 MHZ 10 Fc 4 MHz 20 5 Fc 2 MHz 3 0 6 0 3 0 6 0 Voc V Vcc V P i lccs mA 120 p 5 0 V Vcc 5 0 V 100 35 a ee eee Fc 16 MHz 30 Fe 12 5 MHz 25 MTT Foe 10 MHz 20 Fc 16 MHz TITT Fc 8 MHz Fc 12 5 MHz 15 40 Fo 5 MHz Fc 10 MHz Fc 4 MHz 10 Fc 8 MHz 20 LT Fe 2 MHz Fc 5 MHz 5 Fc 4 MHz Fc 2 MHz 100 20 70 100 Ta C Ta C 101 102 MB90520 Series lccs Voc Iccts UA 200 T Ta 25 C 180 160 Fc 8 MHz 140 120 100 80 60 40 20 3 0 4 0 5 0 6 0 Voc V loc Fe Iccs Fe lec mA lccs mA 120 40 i T 2550 Ta 12550 ATIR Voc 6 0 V 35 100 Vcc 6 0 V Vcc 5 5 V 30 80 Vcc 5 0 V T Voc 5 5 V Vcc 4 5 V Vcc 5 0 V 60 Vcc 4 0 V 20 Voc 4 5 V 40 Vcc 3 5 V 15 Voc 4 0 V Vcc 3 5 V 5 Voc 3 0 V 19 Vcc 3 0 V Vcc 2 5 V 5 Veo 2
16. MB90520 Series lcc mA 35 15 10 UA 160 140 120 100 80 60 40 20 Ta 25 C Fc 16 MHz Fe 12 5 MHz pp Fc 10 MHz Z Fc 5 MHz TT ro Mz C tt Fo 2 MHz 6 0 Voc V Fe 16 MHz Fe 12 5 MHz Fc 10 MHz Fc 8 MHz Fc 5 MHz Fc 4 MHz Fc 2 MHz 100 Ta C Ta 25 Fc 8 kHz 6 0 Vcc V Iccs Vcc lccs mA 10 i 9 Ta 25 G 8 Fc 16 MHz 7 6 Fc 12 5 MHz 5 Fc 10 MHz 4 Fc 8 MHz 3 Fc 5 MHz 4 MHz 2 Fc 2 MHz 1 3 0 4 0 5 0 6 0 Vcc V locs Ta lccs mA 10 TL TL 9 Vcc 5 0 V 8 Fc 16 MHz 7 L eee RE 6 Fc 12 5 MHz 5 L L Fc 10 MHz 4 Fe 8 MHz 3 L M M Fe 5 MHz Fc 4 MHz 2 Fe 2 MHz 1 20 10 40 70 4100 Ta C lcc s mA lcc s Vcc 70 Ta 25 C 60 50 40 Fc 8 kHz 30 20 10 3 0 4 0 5 0 6 0 Voc V MB90520 Series loc mA 35
17. Voc 5 0 V 10 AVss Vss 0 0 V Ta 40 C to 85 C Condition Remarks COMO to COM3 impedance for SEG00 to SEG31 SEG00 to SEG31 Vito V32 5 0V LCDC leak current VO to V3 COM1 to COM3 to SEG31 The current value is preliminary and may be subject to change for enhanced characteristics without previous notice The power supply current is measured with an external clock MB90520 Series 4 AC Characteristics 1 Reset Hardware Standby Input Timing AVcc Voc 5 0 V 10 AVss Vss 0 0 V Ta 40 C to 85 C Reset input time RST Hardware standby input time tusr HST For tor internal operating clock cycle time refer to 3 Clock Timings RSTL tHSTL 0 2 Vcc 0 2 Vcc Measurement conditions for AC ratings Pin is a load capacitance connected to a pin under test C of 80 pF must be connected to address data bus AD15 to ADOO 85 MB90520 Series 2 Specification for Power on Reset Power supply rising time Power supply cut off time AVss 0 0 V Ta 40 C to 85 C Due to repeated Vcc must be kept lower than 0 2 V before power on Notes The above ratings are values for causing a power on reset operations There are internal registers which can be initialized only
18. 240 tce Sampling time Vcc 5 0 V 10 at machine clock of 16 MHz 64 tcr Analog port input current Analog input voltage Reference voltage Power supply current Supply current when CPU stopped and 8 10 bit A D converter not in operation Vcc AVcc AVRH 5 0 V Reference voltage supply current Supply current when CPU stopped and 8 10 bit A D converter not in operation Vcc AVcc AVRH 5 0 V Offset between channels For ter internal operating clock cycle time refer to 3 Clock Timings 95 MB90520 Series nuu 6 A D Converter Glossary Resolution Analog changes that are identifiable with the A D converter Linearity error The deviation of the straight line connecting the zero transition point 00 0000 0000 lt gt 00 0000 0001 with the full scale transition point 11 1111 1110 11 1111 1111 from actual conversion characteristics Differential linearity error The deviation of input voltage needed to change the output code by 1 LSB from the theoretical value Total error The total error is defined as a difference between the actual value and the theoretical value which includes zero transition error full scale transition error and linearity error Total error 3FF 3FE Actual conversion pas 0 5 LSB charac
19. P50 SIN2 AIN1 P51 SOT2 BIN1 P52 SCK2 ZIN1 P53 DA0 P54 DA1 DVcc DVss Notes Actually 16 bit free run timer 1 is supported although two free run timers are seemingly supported 1 The clock control circuit comprises a watchdog timer a timebase timer and a power consumption controller 5 Also used for LCD output With this port used as is Nch open drain output develops A register for setting a pull up resistor MEMORY MB90520 Series Single chip mode A mirroring function is supported Part number MB90522 Address 1 FE00004 0100004 Address 2 0040004 002000k Address 3 0001004 0000C0 0000004 Address 413 FF0000u Register Peripheral Address 2 004000k Address 3 0011004 MB90523 FE0000u 004000u 0011004 MB90F523 FE0000x PI Access prohibited Addresses 1 2 and 8 vary with product type 004000u Internal access memory 0011004 Note The ROM data of bank FF is reflected in the upper address of bank 00 realizing effective use of the C compiler small model The lower 16 bit of bank FF and the lower 16 bit of bank 00 are assigned to the same address enabling reference of the table on the ROM without stating far For example if an attempt has been made to access 00C000k the contents of the ROM at FFCO00k are actually accessed Since the ROM area of the FF bank exceeds 48k
20. RW RW RW RW RW RW Port 1 input pull up pe RDR1 Address bit 15 bit14 bit13 bit12 bitii bit10 bit9 bits e mor noe mre ors ront vor RW RW RW RW RW RW Port 4 input pull up resistor setup RDR4 Address bit7 bit6 bit5 bit4 bit3 bit2 biti bitO mes noe ne ane rou row woe o RW RW RW RW RW RW Analog input enable or ADER Address bit 15 bit14 bit13 bit12 bit11 bit10 bit9 bits me EE RW RW RW RW RW RW Port 7 COM pin selection LCDCMR Address bit 15 bit14 bit13 bit12 bit11 bit10 bit9 bits omme sone co eon pow R W Readable and writable X Indeterminate Undefined bits read value undefined R W R W R W R W Initial value 000000008 Initial value 000000008 Initial value 000000008 Initial value 000000008 Initial value 000000008 Initial value 111111118 Initial value XXXX00008 35 MB90520 Series EEE Sen 3 Block Diagram Input output port PDR port data register PDR read Internal data bus Direction latch DDR write DDR read Standby control Stop timebase timer mode and SPL 1 or hardware standby mode Standby control SPL 1 36 Input pull up resistor setup register RDR To resource input PDR port data register J T Pull up resistor T About 50 5 0 V Standby
21. TMCSRO TMCSR1 H Address bit15 bit14 bit13 bit12 bitii bit10 bit9 bits Initial value mes moe ostt osto wooe moor 190x000 RW RW RW Timer control status register lower digits ch 0 ch 1 TMCSRO TMCSR1 L Address bit7 bit6 bitS bit4 bit3 bit2 bitt bitO Initial value TUSSE vono ovre oum ne ore vr Lowe me 00000000 RW RW RW RW R W RW R W 16 bit timer register upper and lower digits ch 0 ch 1 TMRO TMR1 Address bit 15 bit 14 bit 13 bit 12 bit 11 bit10 bit9 bit8 bit7 bit6 bit5 bit4 bit3 bit2 bitt bitO Initial value TMRO 00004 XXXXXXXXB 00004Ax TMR1 00004 XXXXXXXX B 00004 R R R R R R R R R R R R R R R R KOO 16 bit re load register upper and lower digits ch 0 ch 1 TMRLR0 TMRLR1 Address bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit9 bit8 bit7 bit6 bit5 bit4 bit3 bit2 bit bit 0 Initial value TMRLRO 00004Bx XXXXXXXX B 00004 XXXXXXXX 5 TMRLR1 00004Ex XXXXXXXX 8 00004 W W W W W W W W W W W W W W W W XxxXXxXXXs p Readable and writable Read only W Write only X Indeterminate Undefined bits read value undefined 44 MB90520 Series 2 Block Diagram Internal data bus TMRLRO lt TMRLR1 gt 16 bit re load register Re load signal Re load control circuit TMRO lt TMR1 gt 16 bit timer register down counter UF Count clock generation circuit
22. m HANDLING DEVICES 1 Ensuring that the Voltage does not exceed the Maximum Rating to Avoid a Latch up In CMOS ICs a latch up phenomenon is caused when a voltage exceeding VCC or below VSS is applied to input or output pins or if a voltage exceeding the rating is applied across VCC and VSS When latch up is caused the power supply current may be dramatically increased resulting in thermal breakdown of devices To avoid the latch up make sure that the voltage does not exceed the maximum rating In turning on turning off the analog power supply make sure the analog power voltages AVCC AVRH DVCC and analog input voltages do not exceed the digital voltage Vcc And also make sure the voltages applied to the LCD power supply pins V3 to VO do not exceed the power supply voltage Vcc Handling Unused Pins Unused input pins left open may cause abnormal operation or latch up leading to permanent damage Unused input pins should be pulled up or pull down through at least 2 kQ resistance Unused input output pins may be left open in output state but if such pins are in input state they should be handled in the same way as input pins Notes on Using External Clock In using the external clock drive XO pin only and leave X1 pin unconnected Using external clock MB90520 series Unused Sub Clock Mode If sub clock modes are not used the oscillator should be connected to the XOA pin and X14 p
23. register The value output from the timer counter is used as basic time base timer for input capture ICU and output compare OCU A counter operation clock can be selected from four internal clocks 0 4 16 6 64 and 4 256 An interrupt can be generated by overflow of counter value or compare match with OCU compare register 0 and 4 Compare match requires mode settings The counter value can be initialized to 0000 by a reset software clear or compare match with OCU compare register 0 and 4 Register configuration Free run timer data register 1 2 TCDT1 TCDT2 Address bit 15bit 14bit 13bit 12bit 11bit 10 bit 9 bit 8 bit 7 bit6 bit5 bit4 bit3 bit2 bit bitO Initial value TCDT1 0000574 See eTremereTr Tres rer e T e T 9809990 TCDT2 0000674 000000008 000066u R W R W R W R W R W R W R W RW RW RW RW RW RW RW RW R W 00000000 amp 000000008 Free run timer control status register 1 2 TCCS1 TCCS2 Address bit7 bit6 bit5 bit4 bit3 bit2 biti bito Initial value reese o00088 fesened we wee stor vone our cu orro R d 000000008 TCCS2 000068 eserved IVF IVFE STOP CLR CLK1 CLKO 000000008 RW RW RW RW RW RW RW RW R W Readable and writable Block diagram Count value output Free run timer data register TCDT1 lt TCDT2 gt to ICO and OCU OF 16 bit counter CLK STOP CLR Communications prescaler re
24. 00000Au PDRA Port A data register Port A XXXXXXXXs 00000Bu LCDCMR Port 7 COM pin selection register Port 7 LCD controller driver XXXX00008 00000C 00000Du OCP4 OCU compare register ch 4 16 bit I O timer output compare 1 OCU section XXXXXXXXs XXXXXXXXs 00000E Disabled Wake up interrupt flag register Wake up interrupt XXX XXX XO 5 0000104 Port 0 direction register Port 0 000000008 00001 1 Port 1 direction register Port 1 000000008 00001 2 Port 2 direction register Port 2 000000008 0000134 Port 3 direction register Port 3 00000000s 00001 41 Port 4 direction register Port 4 000000008 000015 Port 5 direction register Port 5 XXX000008 000016 Port 6 direction register Port 6 000000008 00001 7u Port 7 direction register Port 7 000000008 0000184 Port 8 direction register Port 8 000000008 000019u Port 9 direction register Port 9 000000008 00001 Ak Port A direction register Port A 000000008 00001Bu Analog input enable register Port 6 A Dconverter 111111118 00001C 00001Du OCU compare register ch 5 16 bit I O timer output compare 1 OCU section XXXXXXXXs XXXXXXXXs 00001Eu Disabled 00001Fu Wake up interrupt enable register Wake up inter
25. 16 bit re load timer 0 FFFF64u UART SCI transmission complete FFFF60k 16 bit re load timer 1 FFFF5Cu Reserved FFFF58u FFFF78 0000BB FFFF74 7 0000BC FFFF6C 0000BDu 0000BEn Delayed interrupt generation module O Can be used X Can not be used Can be used with EI OS stop function FFFF544 31 MB90520 Series m vr rvs srcaarmmsna B PERIPHERALS 1 I O Port 1 Input Output Port Port 0 through A are general purpose ports having a combined function as a resource input The I O ports can be used as general purpose ports only in the single chip mode Operation as output port The pin is configured as an output port by setting the corresponding bit of the DDR register to 1 Writing data to PDR register when the port is configured as output the data is retained in the output latch in the PDR and directly output to the pin The value of the pin the same value retained in the output latch of PDR can be read out by reading the PDR register Note When a read modify write type instruction e g bit set instruction is performed to the port data register the destination bit of the operation is set to the specified value not affecting the bits configured by the DDR register for output However values of bits configured as inputs by the DDR register are changed because input values to the pins are written int
26. 2 5 V 4 0 8 0 12 0 16 0 4 0 8 0 12 0 16 0 Fc MHz Fc MHz lccr Vcc lccH Vcc lccr UA UA 50 10 r Ta 25 G Ta 25 G 9 40 8 Fc 8 kHz i ma 6 5 20 4 3 10 2 1 3 0 4 0 5 0 6 0 3 0 4 0 5 0 6 0 Voc V Voc V MB90520 Series locr TA CUR lccr UA UA 10 10 9 9 8 8 7 7 6 6 5 5 Vcc 6 0 V 4 Voc 5 5 V 59 5 Voc 5 0 V 3 Voc 5 0 V Vcc 4 5 V Vcc 4 5 V Voc 4 0 V 2 Vec 4 0 V Vcc 3 5 V Vec 3 5 V Voc 3 0 V 1 Voc 3 0 V Vcc 2 5 V Vcc 2 5 V 20 10 40 70 100 20 10 40 70 100 Ta C TAEC Iccts TA Iccts UA 20 18 16 Vcc 6 0 V 14 ff Vo 5 5 V 12 Veco 5 0 V 10 Vcc 4 5 V aec E Vec 40V 8 pp 11 Vo 8 5 V 6 m Vee 3 0 V _ Vc 2 2 5 V 4 2 20 10 40 70 100 Ta C 103 MB90520 Series EEE Sen E ORDERING INFORMATION Part number Package Remarks MB90523PFF MB90522PFF 120 pin Plastic LQFP MB90F523PFF FPT 120P M05 MB90523PFV MB90522PFV 120 pin Plastic QFP MB90F523PFV FPT 120P M13 104 MB90520 Series EEE Sen i PACKAGE DIMENSIONS 120 pin Plastic LQFP FPT 120P M05 16 00 0 20 630 008 SQ 14 00 0 10 551 004 SQ J 0 08 003
27. 211 x 212 x 213 of HOLK gt u To oscillation stabilization time selector of clock control block Power on reset Counter Interval CKSCR MCS 1 0 1 Set TBOF Clear TBOF Timebase timer control register Timebase timer interrupt signal 112 1 Switch machine clock from oscillation clock to PLL clock 2 Interrupt number OF Overflow HCLK Oscillation clock frequency MB90520 Series 3 Watchdog Timer The watchdog timer is a 2 bit counter operating with an output of the timebase timer and resets the CPU when the counter is not cleared for a preset period of time 1 Register Configuration Watchdog timer control register WDTC Address bit7 bit6 bitS bit4 bit3 bit2 biti bit 0 ds Initial value wore ponn erem wer emer wre wr wm R R R R R w w w R Read only W Write only X Indeterminate 2 Block Diagram Watchdog timer control register WDTC Pone rente rer wr Watchdog timer CLR and start I Overflow Start sleep mode gt I Watchdog timer Start hold status Dee 2 bit reset generation gt To tena Start stop mode Circuit generation circui Timebase timer counter HCLK Oscillation clock frequency Divided by 2 of HCLK Fa 39 MB90520 Series nuu 4 8 16 bit PPG Timer 0 1 The 8 16 bit PPG timer i
28. 5 kbps to 1 Mbps Clock asynchronized transmission 1202 bps to 9615 bps Transmission can be performed by bi directional serial transmission or by master slave connection 8 10 bit A D converter Conversion precision 8 10 bit can be selectively used Number of inputs 8 One shot conversion mode converts selected channel only once Scan conversion mode converts two or more successive channels and can program up to 8 channels Continuous conversion mode converts selected channel continuously Stop conversion mode converts selected channel and stop operation repeatedly 8 16 bit PPG timers 0 1 Number of channels 1 8 bit x 2 channels PPG operation of 8 bit or 16 bit Pulse wave of given intervals and given duty ratios can be output Pulse interval 62 5 ns to 1 us at machine clock frequency of 16 MHz 8 16 bit up down counter timers 0 1 Number of channels 1 8 bit x 2 channels Event input 6 channels 8 bit up down counter timer used 2 channels 8 bit re load compare function supported 1 channel 16 bit 16 bit free run I O timer timers 1 2 Number of channels 2 Overflow interrupts Continued Continued Part number Output compares 0 1 OCU MB90520 Series MB90523 MB90523 MB90F523 MB90V520 Number of channels 8 Pin input factor Match signal of compare register Inputcaptures 0 1 ICU Number of channels 2 Rewriting register value upon pin input rising fallin
29. Europe Management GmbH TEL 49 91 1 66870 Murata Electronics Singapore Pte TEL 65 758 4233 TDK Corporation TDK Corporation of America Chicago Regional Office TEL 1 708 803 6100 TDK Electronics Europe GmbH Components Division TEL 49 2102 9450 TDK Singapore PTE Ltd TEL 65 273 5022 TDK Hong Kong Co Ltd TEL 852 736 2238 Korea Branch TDK Corporation TEL 82 2 554 6636 Not required 91 92 MB90520 Series m s s Fs Y 5 UART SCI Timing Parameter Serial clock cycle time tscvc AVcc Vcc 5 0 V 10 AVss Vss 0 0 V Ta 40 C to 85 C Pin name SCKO to SCK2 SCK I gt SOT delay time SCKO to SCK2 SOTO to SOT2 Valid SIN gt SCK T tivsH SCKO to SCK2 SINO to SIN2 SCK T gt valid SIN hold time tsHix SCKO to SCK2 SINO to SIN2 Condition Internal shift clock mode 80 pF 1 TTL for an output pin Remarks Serial clock H pulse width tsHsL SCKO to SCK2 Serial clock L pulse width tsLsH SCKO to SCK2 SCK J SOT delay time SCK0 to SCK2 SOTO to SOT2 Valid SIN gt SCK T tivsH SCKO to SCK2 SINO to SIN2 SCK T gt valid SIN hold time For tcp internal operating clock cycle time refer to 3 Clock Timings tsuix SCKO to SCK2 SINO to SIN2 External shift clock mode 80 p
30. OCU The output compare OCU is two sets of compare units each consisting of an eight channel OCU compare register a comparator and a control register An interrupt request can be generated for each channel upon a match detection by performing time division comparison between the OCU compare data register setting value and the counter value of the 16 bit free run timer The OUT pin can be used as a waveform output pin for reversing output upon a match detection or a general purpose output port for directly outputting the setting value of the CMOD bit Register Configuration ch 01 ch 45 ch 01 ch 23 ch 45 ch 67 ch 23 ys OCS45 lower ch 67 OCP1 OCPO lower OCP1 lower OCP2 lower OCP3 lower OCPA lower OCP5 lower OCP6 er Address 0000063x 00000651 000002Du 000002F Address OCS01 lower OCS23 lower OCS67 lower 0000624 0000644 00002C 00002 Address 00005Bk 00005D 00005F 000061 00000D 00001Du 000035 00006D Address OCP7 lower 00005A 00005C 00005 000060 00000C 00001C 0000344 00006C bit 15 bit 14 bit13 bit12 bit11 bit7 bit6 bit5 em em Terr Te T errem R W R W bit 4 R W e OCU control status register ch 0 to ch 7 OCSO to OCS7 R W bit 3 bit15 bit14 bit13 bit12 bit11 RW RW RW bit7 bit6 bi
31. Program address detection register 3 to 5 PADR1 bit23 bit22 bit 21 R W R W R W R W bit 4 R W R W bit 3 R W R W bit 10 R W bit 2 R W R W bit 9 R W bit 1 R W R W bit 8 R W bit 0 R W bit20 bit 19 bit18 bit17 bit 16 R W bit 15 bit14 bit13 bit12 11 R W bit 7 R W bit 7 R W R W R W R W Undefined bits read value undefined R W bit 6 R W bit 6 R W bit 5 R W bit 5 R W bit 4 R W Program address detection control status register PACSR bit 4 RW RW RW RW bit 10 bit9 bits RW RW RW RW bit3 bit2 biti bit 0 RW RW RW RW bit3 bit2 biti bit 0 R W R W R W R W Initial value XXXXXXXX 8 Initial value XXXXXXXX 5 Initial value XXXXXXXX 8 Initial value XXXXXXXX 5 Initial value XXXXXXXX 8 Initial value XXXXXXXX 5 Initial value 000000008 2 Block Diagram MB90520 Series Internal data bus Address latch Address detection register Enable bit INT9 instruction F2MC 16LX CPU core 75 MB90520 Series m s rvaa 19 ROM Mirroring Function Selection Module The ROM mirror function select module enables the ROM data from the FF bank to be read also from the 00 bank 1 Register Configuration ROM mirroring function selection register ROMM Address bit15 bit14 bit13 bit12 bit1t bit10 bit9 bit8 Initial value
32. by a power on reset Apply power according to this rating to ensure initialization of the registers Vcc smoothly to suppress fluctuations as shown below second however the PLL clock may be used Vcc 02V 0 AE ae mama nas Vss Sudden changes in the power supply voltage may cause a power on reset To change the power supply voltage while the device is in operation it is recommended to raise the voltage In this case change the supply voltage when the PLL clock is not in use If the voltage drops 1 V or less per It is recommended to keep the rising speed of the supply voltage at 50 mV ms or slower 86 3 Clock Timings Parameter Clock frequency MB90520 Series EE AVcc Voc 5 0 V 10 AVss Vss 0 0 V Ta 40 C to 85 C Pin name XO X1 Condition Remarks XO X1 MB90F523 X0A X1A Clock cycle time XO XO X1 MB90F523 X0A X1A Input clock pulse width Recommended duty ratio of 30 to 70 Input clock rising falling time External clock operation Internal operating clock frequency When the main clock is used When the main clock is used When the subclock is used Internal operating clock cycle time When the main clock is used When the main clock is used When the subclock is used Frequency fluctuation rate locked The fr
33. control SPL 1 Internal data bus RDR input pull up resistor setup register Standby control Stop timebase timer mode and SPL 1 MB90520 Series nuu Analog input enable register ADER ADER analog input enable register ADER read To analog input RMW Internal data bus Standby control DDR read U SPL 1 Standby control Stop timebase timer mode and SPL 1 read modify write type instruction 37 38 MB90520 Series Timebase Timer The timebase timer is a 18 bit free run counter timebase counter for counting up in synchronization to the internal count clock divided by 2 of oscillation with an interval timer function for selecting an interval time from four types 21 HCLK 2 4 HCLK 216 HCLK and 2 9 HCLK The timebase timer also has a function for supplying operating clocks for the timer output for the oscillation stabilization time or the watchdog timer etc 1 Register Configuration Timebase timer control register TBTC Address bit 15 bit 14 bit 13 bit 12 bitii bit 10 bit9 bit8 Initial value RW RW RW RW RW RW R W Readable and writable Undefined bits read value undefined 2 Block Diagram To 8 16 bit PPG timer To watchdog tim r Timebase timer counter Divided by 2 gt x 21 x 22 x 29 x 28 x 29 x 214 x
34. facility and equipment such as redundancy fire protection and prevention of over current levels and other abnormal operating conditions If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Control Law of Japan the prior authorization by Japanese government should be required for export of those products from Japan
35. ir Re load compare register 0 Re load control circuit UDCRO CARRY Up down count register 0 BORROW to channel 1 Counter control register 0 CCRLO P26 ZINO INT7 Counter clear Edge level circuit Pin detection circuit Internal data bus Compare control circuit Overflow Underflow Counter status register 0 CSRO 9 Prescaler EN P24 AINO UP down count cite UDIE CMPF OVFF UDFF upF1 UDFO clock selector P25 BINO F gt Interrupt request 21 mE Interrupt request E gt 420 Count trol register 0 CCRHO ounter control reg Suis gt to channel 1 Interrupt number Q Machine clock frequency 54 MB90520 Series Block diagram of 8 16 bit up down counter timer 1 RCR1 qa Re load compare register 1 UDCR1 Up down count register 1 Counter control register 1 1 Counter clear circuit Count clock Counter status registert CSR1 9 Prescaler EN P50 SIN2 AIN1 UP down count csTR CITE UDIE CMPF OVFF UDFF UDF1 UDFO clock selector ipii iji 3 request 29 from channel 1 ECL e lnterrupt request 30 F F E P FeF Fe Counter control register 1 CCRH1 Internal data bus Re load control circuit
36. service EI OS MB90520 Series m rr Hsar w 1 Register Configuration Serial control register SCR bit 15 bit14 bit13 bit12 bitii bit10 bit9 bits Address 000021 000001008 R W RW R W RW RW RW RW w Serial mode register SMR bit7 bit6 bit5 bit4 bit3 bit2 bitt bitO Address 000020u 000000008 R W RW RW RW RW RW RW R W Serial status register SSR PR bit 15 bit14 bit13 bit12 bit11 bit10 bit9 bits Initial value R R R R R RW R W Serial input data register SIDR Address bit7 bit6 bit5 bit4 bit3 bit2 biti _ bit 0 Initial value 4 D D2 R R R R R R R R Serial output data register SODR Address bit7 bit6 bit5 bit4 bit2 bitt bito Initial value w w w w w w w w Communications prescaler control register CDCR bit 15 bit14 bit13 bit12 bit11 bit10 bit9 bits Address 000027 OXXX11118 R W RW RW RW RW R W Readable and writable R Read only W Write only X Indeterminate Undefined bits read value undefined 59 MB90520 Series 2 Block Diagram Control bus Receive interrupt signal Dedicated baud Transmit es rate generator clock re Transmit interrupt signal Clock 39 16 bit re load timer 0 selector Receive External clock clock Receive Transmit control circuit control circuit Transmit start circuit Transmit bit counter l Transmit parity counter I P42 SCK0
37. 1 bit10 bit9 bits Initial value 000045 PEN1 EN PE10 1 PUF1 MD1 MDO Reserved 0X0000018 RW RW RW RW RW RW PPGO output control ms Address bit7 bit6 bit5 bit4 bit3 bit2 bitt bitO Initial value 000046 PCS2 PCS1 Peso PCM2 PCM PCMO PE11 PEO1 000000005 Rw RW RW RW RW RW RW PPG1 output control Ne I PPGOE1 Address bit7 bit6 bits bit4 bits bit2 biti bit 0 Initial value 000046u PCS2 PCS1 PCSO PCM2 PCM1 PCMO PE11 000000008 RW RW RW RW RW RW RW RW PPGO re load register H PRLHO Address bit15 bit14 bit13 bit12 bit11 bit10 bit9 bits Initial value RW RW RW RW RW RW RW RW e PPG1 re load register H PRLH1 Address bit15 bit14 bit13 bit12 bit11 bit10 bit9 bits Initial value RW RW RW RW RW RW RW RW PPGO re load register L PRLLO Address bit7 bit6 bits bit4 bit3 bit2 bitt BbitO Initial value RW RW RW RW RW HW RW RW PPG1 re load register L PRLL1 Address bit6 bit5 bit4 bit3 bit2 biti bitO Initial value RW RW RW RW RW RW RW RW R W Readable and writable X Indeterminate Undefined bits read value undefined 41 MB90520 Series 2 Block Diagram Block diagram of 8 16 bit PPG timer 0 PPGO re load register Temporary buffer PRLBHO SZ Re load selector L H selector Count value Down counter Underflow Select signal Data bus for H digits Data bus for L digits PPGO operatin
38. 11 RW RW RW RW R W Readable and writable X Indeterminate bit 10 R W bit 2 R W bit 2 R W bit 10 R W bit 9 R W bit 1 R W bit 1 R W bit 9 R W bit 8 mes ewe em em ero ene em em R W bit 0 mmo E7 oo ee am R W bit 0 amter ao te ue ue r ta tn oe R W R W bit 8 Address De iso T eT iss e eu ELVR upper 0000334 Initial value XXXXXXXX 8 Initial value 000000008 Initial value 000000008 Initial value 000000008 61 Jequunu 1dnueju una 21860 eu idnuetuyaro ona ina awa ena pna ena swa 2na a E OLNI 00d uld LLNI LOd une I 0 ELNI EOd veto ud jeuBis 1senbau 1dn ueju o 2 V LNI FOd rs EIE m SIN SOd no uonoejep 1ndui S jdnuejul 2U181X9 d LA uld l EN 01010965 Z 1910865 t 1o o9 s 9 1ol9 s mj oDpo Lr oDpo oDpo jane oDpo RT 91NI 90d F lua ped I 10199 95 1 0 95 S J0129Jos J0199Jos FILI z epe FEM z eDpo epe jane LINIONIZ 9Zd Fa EG ud z z 4 4 z 4m3 49181601 Bunes 15enbeu 2 Block Diagram MB90520 Series
39. 13 biti2 bitii bit10 bit9 bit8 0000814 D17 D16 Di4 D13 D12 D11 R R R R R R R R Re load compare register 0 RCRO Address bit7 bit6 bit5 bit4 bit3 bit2 biti bitO 000082 D07 D06 D04 D03 Do2 Do1 D00 W W W W W W W W Re load compare register 1 I I f f Address bit15 bit14 bit13 bit12 bitii bit10 bit9 bit8 000083 D17 D16 Di4 D13 D12 Dt1 W W W W W W W W Counter status register 0 1 CSRO CSR1 Address bit7 bit6 bit5 bit4 bit3 bit2 biti bitO RO 4 CSTR CITE UDIE CMPF OVFF UDFF UDF1 UDFO RW RW RW RW RW RW R R Counter control register 0 1 CCRLO CCRL1 Address bit7 bit6 bit5 bit4 bit3 bit2 biti bitO CCRLO 000086u CCRL1 00008A GTUT UCRE RLDE UDCC CGSC CGE1 CGEO RW RW RW RW RW RW RW Counter control register 0 CCRHO Address bit15 bit14 bit13 biti2 bitii bit10 bit9 bits 0000874 M16E CDCF CFIE CLKS CMS1 CMSO CES1 CESO RW RW RW RW RW RW RW RW Counter control register 1 CCRH1 Address bit15 bit14 bit13 biti2 bitii bit10 bit9 bit8 00008B cocr CFIE CLKS CMS1 CMSO CES1 CESO R W Initial value 000000008 Initial value 000000008 Initial value 000000008 Initial value 000000008 Initial value 000000008 Initial value X00000008 Initial value 000000008 Initial value X00000008 53 MB90520 Series 2 Block Diagram Block diagram of 8 16 bit up down counter timer 0 RCRO
40. 3 bit2 bitt bitO 0000364 E ANS2 ANS1 ANSO ANE2 ANE1 ANEO RW RW RW RW RW RW RW A D data register upper digits ADCR2 Address bit 15 bit14 bit13 bit12 bitidi bit10 bit9 bits w w w w w R R A D data register lower digits ADCR1 Address bit7 bit6 bit5 bit4 bit3 bit2 bitt bitO oem or os os pa pe pr po R R R R R R R R R W Readable and writable Read only Write only Indeterminate Undefined bits read value undefined x Initial value 000000008 Initial value 000000008 Initial value 00001XXXs Initial value XXXXXXXX 8 2 Block Diagram MB90520 Series A D control status register ADCS P27 ADTG P73 TO1 OUT7 Clock selector P67 AN7 66 6 P65 AN5 FRE nalog P64 AN4 channel P63 AN3 selector P62 AN2 P61 AN1 P60 AN0 Decoder AVRH AVRL AVcc AVss 8 bit D A converter Internal data bus Control circuit A D data register ADCR SS oe Ed ETE TO 16 bit re load timer channel 1 output Interrupt number Machine clock frequency 67 68 MB90520 Series m rsa Dww c 14 8 bit D A Converter The 8 bit D A converter which is based on the R 2R system supports 8 bit resolution mode It contains two channels each of which can be controlled in t
41. 4 D23 D22 D21 D2 000012 227 026 pes 024 pes pez 021 020 00000008 RW RW RW RW RW RW RW RW Port 3 direction register DDR3 Address bit 15 bit14 bit13 bit12 bit11 bit10 bit9 bits Initial value 000013 00000000 RW RW RW RW RW Port 4 direction register DDR4 wedges bit7 bite bit5 bit4 bit3 bit2 bitt bitO Initial value RW RW RW RW RW RW RW RW Port 5 direction register DDR5 bit15 bit14 bit13 bit12 bit11 bit10 bit9 8 iti Address Initial value mme l1 I lI 10000000 RW RW RW RW RW RW RW RW Port 6 direction register DDR6 Address bit7 bit6 bit5 bit4 bit3 bit2 bitt bit 0 Initial value RW RW RW RW RW RW RW RW Port 7 direction register DDR7 Address bit15 bit14 bit13 bit12 bit11 bit10 bit9 bits Initial value 0000171 07 00000000 RW RW RW RW RW RW RW RW e Port 8 direction register DDR8 Address bit7 bit6 bit5 bit4 bit3 bit2 bitt bitO Initial value 000018 00000000 RW RW RW RW RW RW RW RW Continued Continued MB90520 Series EE Port 9 direction register DDR9 Address bit 15 bit14 bit13 bit12 bit11 bit10 bit9 bits swore vor oo n T moa mo wo oor om RW RW RW RW RW RW Port A direction register Da Address bit6 bit5 bit4 bit3 bit2 bitt bito wes Ds ore pss ore T pas T oae om ovo RW RW RW RW RW RW HW RW Port 0 input pull up resistor setup register RDRO Address bit7 bite bit5 bit4 bit3 bit2 bitt bit0 ser noor roos ros or eoo now row ee
42. Compare control circuit P52 SCK2 ZIN1 ve Edge level Pin detection circuit CARRY BORRW from channel 0 Overflow Underflow Interrupt number Q Machine clock frequency 55 56 MB90520 Series 8 Extended I O Serial Interface 0 1 The extended I O serial interface transfers data using a clock synchronization system having an 8 bit x 1 channel configuration For data transfer you can select LSB first MSB first 1 Register Configuration Serial mode control upper status register 0 1 SMCSHO SMCSH1 Address bit 15 bit14 bit13 bit12 bit1t bit10 bit9 bit8 SMCSHO 000025 ee SNe S401 swoo Tresa RW RW RW RW R RW RW Serial mode control wi status register 0 1 SMCSL0 SMCSL1 Address bit6 bit5 bit 4 bit3 bit2 biti bit 0 1 vo os o soor RW RW RW Serial data 0 1 SDRO SDRI Address bit7 bit6 bit5 bit4 bits bit2 bitt bitO SDRO 0000264 SDR1 00002Ak D7 D5 D4 D3 D2 RW RW RW RW RW RW RW RW R W Readable and writable R Read only X Indeterminate Undefined bits read value undefined Initial value 000000108 Initial value XXXX00008 Initial value XXXXXXXX 8 2 Block Diagram MB90520 Series Internal data bus MSB first DO to D7 D7 to DO LSB first Serial data register SDR Transfer direction selection
43. D controller driver This function is valid with port output specified for the LCD controller driver control register 17 to 24 SEG00 to SEG07 These are pins dedicated to LCD segments 00 to 07 for the LCD controller driver 25 to 32 PAO to PA7 SEG08 to SEG15 1 FPT 120P M05 2 FPT 120P M13 This is a general purpose I O port This function is valid with port output specified for the LCD controller driver control register These are pins for LCD segments 08 to 15 for the LCD controller driver Units of four ports or segments can be selected by the internal register in the LCD controller Continued MB90520 Series Continued LGFP 120 QFP 120 Pin name Circuit type Function This is a capacitance pin for power supply stabilization Connect an external ceramic capacitor rated at about 0 1 uF This capacitor is not however required for the M90F523 flash product 82 to 85 VO to V3 N This is a pin for the reference power supply for the LCD controller driver 8 54 94 Voc Power supply This is a power supply 5 0 V input pin to the digital circuit 33 63 91 119 Power supply This provides the GND level 0 0 V input pin for the digital circuit 42 This is a power supply for the analog circuit Make sure to turn on turn off this power supply with a voltage exceeding AVcc applied to Vcc 43 This is a referenc
44. F 1 TTL for an output pin Notes These are AC ratings in the CLK synchronous mode Ciis the load capacitor value connected to pins while testing MB90520 Series EEE Sen Internal shift clock mode SCK SOT SIN External shift clock mode SCK SOT SIN 93 MB90520 Series 6 Timer Input Timing AVoc Vcc 5 0 V 10 AVss Vss 0 0 V Ta 40 C to 85 C Val Parameter Symbol EL Condition iie Unit IC00 1C01 IC10 For tcr internal operating clock cycle time refer to 3 Clock Timings 7 Timer Output Timing AVcc Voc 5 0 V 10 AVss Vss 0 0 V Ta 40 C to 85 C ve Parameter Symbol Condition Unit Remarks CLK Tour me to OUTS transition time PGO01 PG10 PG11 24V CLK tro Tour e 94 5 A D Converter Parameter Resolution AVoc Vcc 5 0 V 10 AVss Vss 0 0 V 3 0 V AVRH AVRL Ta 40 C to 85 C Pin name Total error Non linear error Differential linearity error Zero transition voltage Full scale transition voltage Condition MB90520 Series 5 0 2 5 1 9 AVss 3 5 LSB 0 5 LSB AVss 4 5 LSB AVRH 6 5LSB AVRH 1 5 LSB AVRH 1 5 LSB Conversion time Vcc 5 0 V 10 at machine clock of 16 MHz
45. Low power consumption mode control register 0000A1u Clock select register Low power consumption stand by mode 000110008 111111008 0000A2u to 0000A7 Disabled 0000A8u Watchdog timer control register RorW Watchdog timer XX XXX XX X 8 0000A9u Timebase timer control register R W Timebase timer 1XX000003 0000AAu Clock timer control register R W or R Clock timer 1X0010008 0000 to 0000ADu Disabled 0000AEu Flash control register R W Flash interface 1XX001008 0000AFu Disabled 0000B0u ICROO Interrupt control register 00 R W 000001118 0000B1u ICRO1 Interrupt control register 01 R W 00000111s 0000B2 ICR02 Interrupt control register 02 R W 00000111s 0000B3 ICR03 Interrupt control register 03 R W 00000111s 0000B4 ICR04 Interrupt control register 04 R W 00000111s 0000B5 ICR05 Interrupt control register 05 R W 00000111s 0000B6k ICRO6 Interrupt control register 06 R W Interrupt 000001118 0000B7 ICRO7 _ Interrupt control register 07 R W controller 000001118 0000B8 8 Interrupt control register 08 R W 00000111s 0000B9 ICR09 Interrupt control register 09 R W 00000111s 0000 ICR10 Interrupt control register 10 R W 00000111s 0000BBk ICR11 Interrupt control register 11 R W 0000011158 0000BC ICR12 Inte
46. O IPCP1 Address bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit8 Initial value ad 000081 cpi5 Cris cP12 CP11 CP10 CP09 CPO8 xXXXXXXXs R R R R R R R R Address bite bit 5 bit 4 bit 3 bit 2 bit 1 bitO Initial value IPCPO 000050 IPCP1 l ver 000052 CP07 CP06 CP05 CP04 CPOS CP02 cPoo XXXXXXXXe R R R R R R R R Note This register holds a 16 bit free run timer value when the valid edge of the corresponding external pin input waveform is detected This register can be word accessed but not programmed ICU control status register ICSO1 Address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 Initial value 0000544 ICP1 ICPO ICE1 ICEO EG11 EG10 EGO1 EGOO 00000000s R W R W R W R W R W R W R W R W R W Readable and writable R Read only X Indeterminate MB90520 Series Block diagram Internal data bus ZN Latch signal Output latch H Edge detection circuit ICU data register IPCP syn pone Pp a s gt Data latch signal 1e EN j T L t IPCPO upper IPCPO lower P22 IC10 2 T i gt IPCP1 H Pin mfl CP1 upper IPCP1 lower ee castes Soe I P23 C11 ia T Pe ICU control status register ICSO1 pros ee en een an E Interrupt request 4913 e lt Interrupt request 32 Interrupt number 49 50 MB90520 Series 3 Output Compare 0 1
47. O serial interface 0 Wake up interrupt 0000B2u Extended I O serial interface 1 FFFFB8 DTP2 DTP3 external interrupt 2 external interrupt 3 4 8 16 bit PPG timer 0 counter borrow DTP4 DTP5 external interrupt 4 external interrupt 5 0000B4H 8 16 bit up down counter timer 0 compare match FFFFAOu 8 16 bit up down counter timer 0 overflow up down inversion FFFFA4 8 16 bit PPG timer 1 counter borrow DTP6 DTP7 external interrupt 6 external interrupt 7 FFFF9CH 0000B6u Output compare 1 OCU ch 4 ch 5 match FFFF98x Clock prescaler FFFF94n Output compare 1 OCU ch 6 ch 7 match FFFF904 16 bit free run timer 2 overflow FFFF8C 8 16 bit up down counter timer 1 compare match FFFF884 8 16 bit up down counter timer 1 overflow up down inversion FFFF844 0000B9 Input capture 0 ICU include FFFF80 Input capture 1 ICU include FFFF7C 0000BA Continued MB90520 Series Continued Interrupt vector Interrupt control register Interrupt source Priority Number Address ICR Address Output compare 0 OCU ch 0 match Output compare 0 OCU ch 1 match Output compare 0 OCU ch 2 match Output compare 0 OCU ch 3 match UART SCI reception complete FFFF68u
48. O serial interface 1 This function becomes valid when serial data output from SOT2 is enabled This port can be used as count clock B input for 8 16 bit up down counter timer 1 P52 SCK2 ZIN1 This is a general purpose I O port This is a serial clock I O pin for extended I O serial interface 1 This function becomes valid when serial clock output from serial SCK2 is enabled This port can be used as control clock Z input for 8 16 bit up down counter timer 1 P53 P54 DAO DA1 This is 8 general purpose I O port These are analog signal output pins for 8 bit D A converter ch 0 and ch 1 46 to 53 P60 to P67 ANO to AN7 1 FPT 120P M05 2 FPT 120P M13 This is a general purpose I O port The input function become valid when the analog input enable register ADER is set to select a port These are analog input pins of the 8 10 bit A D converter This function is valid when the analog input enable register ADER is enabled Continued 11 MB90520 Series 12 LQFP 120 QFP 120 Pin name OUTA OUT6 Circuit type Function This is a general purpose I O port These are event input pins for 16 bit re load timers 0 and 1 Since this input is used as required for 16 bit re load timers 0 and 1 operation output by other functions must be suspended except for intentional operation These are event output pins for output com
49. Request level setting register DTP external interrupt circuit 00000000s XXXXXXXXs 000000008 000000008 000034u 000035u OCU compare register ch 6 16 bit I O timer output com pare 1 OCU section XXXXXXXXs XXXXXXXXs 000036u A D control status register lower digits 000037u A D control status register upper digits 000038u A D data register lower digits 000039u A D data register upper digits 8 10 bit A D converter 000000008 000000008 XXXXXXXXs 00001XXXs 00003Ak D A converter data register ch 0 00003Bu D A converter data register ch 1 00003C D A control register 0 00003Dx 00003Ex CLKR D A control register 1 Clock output enable register 8 bit D A converter Clock monitor function XXXXXXXXs XXXXXXXXs XXXXXXX0B XXXXXXX0B XXXX00008 Continued 25 26 MB90520 Series Address 00003FH Abbreviated register name Register name Disabled Resource name Initial value 000040u PRLLO PPGO re load register L 0000414 PRLHO PPGO re load register H 000042u PRLL1 PPG1 re load register L 000043u PRLH1 PPG1 re load register H 000044 PPGCO PPGO operating mode control register 000045u PPGC1 PPG1 operating mode control register 000046u PPGOEO PPGOE1 PPGO and 1 output control reg
50. U compare register ch 0 00005C 00005Dk 00005E 00005F OCU compare register ch 1 OCU compare register ch 2 000060u 0000614 OCU compare register ch 3 16 bit I O timer output compare 0 OCU section XXXXXXXXs XXXXXXXXs XXXXXXXXs XXXXXXXXs XXXXXXXXs XXXXXXXXs XXXXXXXXs XXXXXXXXs Continued Address 000063u Abbreviated register name Register name OCU control status register ch 01 000064 000065 OCU control status register ch 23 MB90520 Series Resource name 16 bit I O timer output compare 0 OCU section Initial value 0000XX00B XXX000008 0000XX00B XXX000008 000066 000067 Free run timer data register 2 000068u Free run timer control status register 2 16 bit I O timer 16 bit free run timer 2 section 000000008 000000008 000000008 000069u Disabled 00006Ak 00006Bk LCDC control registers 0 and 1 R W R W LCD controller driver 00010000s 00000000s 00006C 00006Du OCU compare register ch 7 R W 16 bit I O timer output compare 1 OCU section XXXXXXX X 8 XX XX XXX X 8 00006E Disabled 00006Fu ROM mirroring function selection register W ROM mirroring function selection module XXXXXXX 1B 000070u to 00007Fu RAM for LCD indication LCD controller driver XXXXXXXX
51. al Characteristics Assurance for the MB90V520 is given only for operation with a tool at a power voltage of 3 0 V to 5 5 V an operating temperature of 0 to 55 degrees centigrade and an operating frequency of 1 MHz to 16 MHz MB90520 Series E PACKAGE AND CORRESPONDING PRODUCTS FPT 120P M05 O O O FPT 120P M13 O O O O Available x Not available Note For more information about each package see section BI Package Dimensions DIFFERENCES AMONG PRODUCTS Memory Size In evaluation with an evaluation chip note the difference between the evaluation chip and the chip actually used The following items must be taken into consideration The MB90V520 does not have an internal ROM However operations equivalent to those performed by a chip with an internal ROM can be evaluated by using a dedicated development tool enabling selection of ROM size by setting the development tool In the MB90V520 images from FF4000 to FFFFFF are mapped to bank 00 and FE0000r to FF3FFFu are mapped to bank FE and FF only This setting can be changed by configuring the development tool In the MB90522 images from FF4000 to FFFFFFa are mapped to bank 00 and FF00004 to FF3FFF to bank FF only In the MB90523 F523 images from FF4000u to FFFFFF are mapped to bank 00 and FE0000 to FF3FFFu to bank FE and bank FF E PIN ASSIGNMENT MB90520 Series P30 Vss Top view N z OS5oo e CO LO st CO QN O H222rr58rens
52. al interrupt 1 Register Configuration Clock timer control register WTC Address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 Initial value 0000AAk WDCS WTIE WTOF WTC2 WTC1 WTCO 1X0010008 R R W RW RW RW RW R W Readable and writable R Read only X Indeterminate 2 Block Diagram gt To watchdog timer Timer counter ie i ad ra dra i LCLK Power on reset i Counter Shift to a hardware stand by clear circuit To sub clock stabilization time controller ER timer ER Clock timer control register WTC Shift to stop mode Clock timer interrupt request 22 Interrupt number OF Overflow LCLK Sub clock frequency 70 MB90520 Series asar Sn 16 LCD Controller Driver The LCD liquid crystal display controller driver which contains a 16 byte display data memory controls LCD indication using four common output pins and 32 segment output pins It can select three types of duty output and directly drive the LCD panel 1 Register Configuration LCDC control register 0 LCRO Address bit7 bit5 bit4 bit3 bit2 bitt bitO Initial value RW RW RW RW RW RW RW RW LCDC control register 1 LCR1 Address bit 15 bit14 bit13 bit12 bitid bit10 bit9 bits Initial value 000068 ml SEG4 d SEG3 SEG2 SEG1 SEGO de RW RW RW RW RW RW Port 7 COM pin selection register LCDCMR Address bit 15 bit14 bit13 bit12
53. alue undefined bit15 bit14 bit13 bit12 bitii bit10 bit9 bit8 Address Initial value RW RW RW 73 74 MB90520 Series EE 18 Address Match Detection Function When the address is equal to a value set in the address detection register the instruction code loaded into the CPU is replaced forcibly with the INT9 instruction code 01H As a result when the CPU executes a set instruction the INT9 instruction is executed Processing by the INT 9 interrupt routine allows the program patching function to be implemented Two address detection registers are supported An interrupt enable bit is prepared for each register If the value set in the address detection register matches an address and if the interrupt enable bit is set at 1 the instruction code loaded into the CPU is replaced forcibly with the INT9 instruction code 1 Register Configuration Address PADRO High order address 001FF2u Address PADRO Middle order address 001FF1h Address PADRO Low order address 001FFOk Address PADR1 High order address 001FF5u Address PADR1 Middle order address 001FF4 Address Address 00009 R W Readable and writable X Indeterminate Program address detection register 0 to 2 PADRO bit23 bit22 bit21 R W R W R W bit20 bit 19 bit18 bit17 bit16 R W R W bit15 bit14 bit13 bit12 bit11 R W bit 7 R W R W bit 6 R W R W bit 5 R W
54. bitii bit10 bit9 bit8 Initial value 000008 Tz Tee eve eon ow XXXX0000s RW RW RW RW RAM for LCD indication VRAM Address bit7 bit6 bit5 bit4 bit3 bit2 bitt bitO Initial value om frfufufufuf fufu 00007Fu RW RW RW RW RW R W Readable and writable X Indeterminate Undefined bits read value undefined 71 72 MB90520 Series 2 Block Diagram LCDC control register 0 i LCRO Split resistor Prescaler Timing controller Common driver generator Internal data bus Indication RAM 16 bytes Segment driver Controller section HCLK Oscillation frequency LCLK Sub clock frequency VO V1 V2 V3 P74 COMO P75 COM1 P76 COM2 P77 COM3 SEG00 SEGO1 SEG02 P95 SEG29 P96 SEG30 P97 SEG31 17 Communications Prescaler Register This register controls machine clock division MB90520 Series EEE Sen Output from the communications prescaler register is used for UART SCI and extended I O serial interface The communications prescaler register is so designed that a constant baud rate may be acquired for various machine clocks 1 Register Configuration Communications prescaler control register CDCR R W R W R W Readable and writable Undefined bits read v
55. bytes the whole area cannot be reflected in the image for the 00 bank The ROM data at FF4000 to FFFFFFu looks therefore as if it were the image for 004004 to OOFFFFu Thus it is recommended that the ROM data table be stored in the area of FFA000u to FFFFFFu 21 MB90520 Series m s s r E F2MC 16LX CPU PROGRAMMING MODEL Dedicated registers Accumlator A AH AL Dual 16 bit register used for storing results of calculation etc The two 16 bit registers can be combined to be used as a 32 bit register USP User stack pointer USP 16 bit pointer for containing a user stack address SSP System stack pointer SSP 16 bit pointer for displaying the status of the system stack address Processor status PS 16 bit register for displaying the system status Program counter PC 16 bit register for displaying the storing location of the current instruction code Direct page register DPR 8 bit register for specifying bit 8 through 15 of the operand address in the short direct addressing mode U U B Program bank register PCB 8 bit register for displaying the program space DTB Data bank register DTB 8 bit register for displaying the data space USB User stack bank register USB 8 bit register for displaying the user stack space SSB System stack bank register SSB 8 bit register for displaying the system stack space ADB Additional data ban
56. e voltage input to the analog circuit Make sure to turn on turn off this power supply with a voltage exceeding AVRH applied to AVcc This is a reference voltage input to the analog circuit This is a GND level of the analog circuit This is the Vref input pin for the D A converter The voltage to be applied must not exceed Vcc 1 FPT 120P M05 2 FPT 120P M13 This is the GND level pin for the D A converter The potential must be the same as Vss 13 14 MB90520 Series B CIRCUIT TYPE Circuit Nch 0 T ec1 Standby control signal Remarks High speed oscillation feedback resistor approx 1MQ gt AOYT Q Standby control signal Low speed oscillation feedback resistor approx 1MQ R mE gt Hysteresis input Hysteresis input Selecting signal with or without a input pull up resistor Hysteresis input lo 4 mA Standby control for input interruption Hysteresis input can be set with the input pull up resistor CMOS level output Pull up resistor approx 50 kQ Provided with a standby control function for input interruption Continued Circuit Hysteresis input MB90520 Series Remarks CMOS hysteresis input output CMOS level output Provided with a standby control function for input interruption
57. egister PDR5 Address bit15 bit14 bit13 bit12 bitll bit10 bit9 bits Initial value ww sa rae rst ee 000000 RW RW RW RW RW Port 6 data register PDR6 Address bite bits bit4 bit3 bitt bitO Initial value cons ee ee res Poe ver Poe ver poo r000000 RW RW RW RW RW RW RW RW Port 7 data register PDR7 Address bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 Initial value RW RW RW RW RW RW RW RW Port 8 data register PDR8 Address bit7 bite bit5 bit4 bit3 bit2 bitt bitO Initial value RW RW RW RW RW RW RW RW Port 9 data register PDR9 Address bit15 bit14 bit13 bit12 bitii bit10 bit9 bits Initial value RW RW RW HW HW HW HW RW Continued 33 MB90520 Series Port A data register PDRA f f I f I f I Address bit7 bit6 bitS bit4 bit3 bit2 bill bit 0 Initial value PA7 PA6 PA5 PA4 PA3 PA2 PA1 PAO oa S P Ras Ps PAE PAT T s00000600 RW HW HW HW HW HW HW HW Port 0 direction register DDRO n bit7 bit6 bit5 bit4 bits bit2 bitt bitO initial value D07 DO5 D04 D03 D02 DOi m 207 06 905 pos Do DU DO9 00000000 RW RW RW RW RW RW RW RW Port 1 direction register DDR1 Address bit 15 bit14 bit13 bit12 bit11 bit10 bit9 bits Initial value ao Ve 0009000 RW RW RW RW RW RW RW RW Port 2 direction register DDR2 bit7 bite bit5 bit4 bit3 bit2 bitt bitO Initial value D27 D26 D25 D2
58. equency fluctuation rate is the maximum deviation rate of the preset center frequency when the multiplied PLL signal is locked Af 161 x 100 Center frequency fo The PLL frequency deviation changes periodically from the preset frequency about CLK x 1CYC to 50 CYO thus minimizing the chance of worst values to be repeated errors are minimal and negligible for pulses with long intervals 87 88 MB90520 Series EEE Sn clock timing m tHCYL 0 8 Vcc 0 8 Vcc 0 8 Vcc X0 0 2 Vcc 0 2 Vcc Pwu Pw tor tcr XOA X1A clock timing lt tLeyL XOA PLL operation guarantee range Power supply voltage Vcc Internal clock fce V Relationship between internal operating clock frequency and power supply voltage MB90F523 operation guarantee range MB90522 MB90523 operation guarantee range NOR 3 8 10 12 16 Internal clock fce Relationship between oscillating frequency and internal operating clock frequency Multiplied Multiplied Multiplied by 4 by 3 by 2 by 1 Multiplied B90V520 operation guarantee range Not multiplied gt 12 Oscillation clock Fc MHz MB90520 Series The AC ratings are measured for the following measurement reference voltages Input signal waveform Output signal waveform Hystheresis input pin Hystheres
59. erms of output by the D A control register 1 Register Configuration D A converter data register ch 0 DADR0 Address bit7 bit6 bit5 bit4 bit3 00003A DA07 oe 5 DAO4 DA03 DA02 RW RW D A converter data register ch 1 DADR1 Address bit15 bit14 bit13 bit12 bit 11 00003Bk DA17 DA16 DA15 DA14 DA13 DA12 DA11 DA10 RW RW RW RW D A control register 0 DACRO Address bit7 bite bit5 bit4 bit3 wwo T J J p D A control register 1 DACR1 Address bit 15 bit14 bit13 bit12 bit 11 R W Readable and writable X Indeterminate Undefined bits read value undefined bit 2 R W bit 10 R W bit 2 bit 10 bit 1 R W bit 9 R W bit 1 bit 9 bit 0 R W bit 8 R W bit 0 R W bit 8 R W Initial value XXXXXXXX 5 Initial value XXXXXXXX 5 Initial value 8 Initial value 5 MB90520 Series Block Diagram Internal data bus D A converter data register ch 1 DADR1 D A converter data register ch 0 DADRO converter 1 DVRH DVRL DA17 DA07 gen eH ci P54 DA1 n P53 DA0 DA16 R DA06 R Internal data bus 69 MB90520 Series m Sen 15 Clock Timer The clock timer control register WTC controls operation of the clock timer and time for an interv
60. eure EEEEEEE lt m lt 9OSOzzzzzzz 2222222 see D O LO st CO N T TOKN O LO CO N O O iO SE MONTO o NI N N QI QN QN QV QN O O gt O O O O O O O AAAAAAAAAARNAANAAAAGAGAGAASXX gt 119 P31 CKOT P32 OUTO P33 OUT1 P34 OUT2 P35 OUT3 P36 PG00 P37 PG01 Vcc P40 PG10 P41 PG11 P42 SINO P43 SOTO P44 SCKO P45 SIN1 P46 SOT1 P47 SCK1 SEG00 SEG01 SEG02 SEG03 SEG04 SEG05 SEG06 SEG07 PA0 SEG08 PA1 SEG09 PA2 SEG10 PA3 SEG11 PA4 SEG12 PAS SEG13 120 118 P97 SEG31 P96 SEG30 P95 SEG29 P94 SEG28 P93 SEG27 P92 SEG26 P91 SEG25 X0A X1A P90 SEG24 P87 SEG23 P86 SEG22 P85 SEG21 P84 SEG20 P83 SEG19 P82 SEG18 P81 SEG17 P80 SEG16 Vss P77 COM3 P76 COM2 PA6 SEG14 PA7 SEG15 Bae P o SON EDN ED Ta 2302025 SEX or OrANMY HOR Yo r23 200 lt lt 22222222 ODD 9 OO I4 XX4444X4X o Ora amp Ls FolkMsoraQanfH KR yOra amp ndTn D tO tO gt gt 10 ub gt gt gt gt 0 co cO c co o dodo 0 8 gt gt o0aanrnnra axaaanaranaana gt nnnnnn FPT 120P M05 FPT 120P M13 MB90520 Series EE PIN DESCRIPTION LQFP 120 QFP 120 2 92 93 Pin name XO Circuit type Function This is a high speed crystal oscillator pin 74 73 XOA X1A This is a low speed crystal oscillator pin 89 to 87 MDO to MD2 This is an input pi
61. g or both edges DTP external interrupt circuit Number of inputs 8 Started by rising edge falling edge H level input or L level input External interrupt circuit or extended intelligent I O service EIPOS can be used Wake up intrrupt Number of inputs 8 Started by L level input Delayed interrupt generation module Interrupt generation module for switching tasks Used in real time operating systems Extended I O serial interfaces O 1 Clock synchronized transmission 3125 bps to 1 Mbps LSB first MSB first Timebase timer 18 bit counter Interrupt interval 1 024 ms 4 096 ms 16 384 ms 131 072 ms at oscillation of 4 MHz 8 bit D A converter 8 bit resolution Number of channels 2 channels Based on R 2R system LCD controller driver Number of common output pins 4 Number of segment output pins 32 Number of power supply pins for LCD drive 4 RAM for LCD indication 16 bytes Booster for LCD drive Internal Split resistor for LCD drive Internal Watchdog timer Reset generation interval 3 58 ms 14 33 ms 57 23 ms 458 75 ms at oscillation of 4 MHz minimum value Low power consumption stand by mode Sleep stop CPU intermittent operation clock timer hardware stand by Process CMOS Power supply voltage for operation 3 0 V to 5 5 V 4 0 V to 5 5 V 3 0 Vto 5 5 V Varies with conditions such as the operating frequency See section Bl Electric
62. g mode control register PPGCO zs Interrupt request 19 eal mode control signal PPG1 underflow Re load CER lt PPG0 underflow to PPG1 Y Clear Pulse selector PCNTO CLK PPGO output latch Reverse P36 PG00 PPG output control circuit 42 Timebase timer output 512 HCLK o Peripheral clock 16 6 4 o Peripheral clock 8 6 Peripheral clock 4 0 o Peripheral clock 2 0 o Peripheral clock 1 0 Count clock selector 3 P37 PG01 Select signal PPGO 1 output control register PPGOEO 1 Interrupt number HCLK Oscillation clock frequency Machine clock frequency Legen MB90520 Series Block diagram of 8 16 bit PPG timer 1 Data bus for H digits Data bus for L digits PPG1 operating mode PPG1 re load control register PPGC1 register Operating mode control signal Temporary buffer PRLBH1 n Interrupt Re load selector Select signal L H selector 3 Count value qi Re load Down counter Underflow 14 PPG1 IN PCNT1 Reverse output latch U P40 PG10 PPG1 underflow CLK PPG output control circuit to PPG0 MDO P41 PG11 PPGO underflow Timebase timer output 512 HCLK 1 Peripheral clock 16 0 1 9 Peripheral clock 8 0
63. gister OCU compare register 0 match signal Internal data bus Free run timer control status register TCCS1 lt TCCS2 gt a 16 bit free run timer interrupt request 1431 4285 1 The timer has ch 1 and ch 2 and figures bracketed by lt gt are for ch 2 2 Interrupt number Machine clock frequency OF Overflow 47 48 MB90520 Series EEE SSS 2 Input Capture 0 1 ICU The input capture ICU generates an interrupt request to the CPU while storing the current counter value of the 16 bit free run timer to the ICU data register IPCP upon input of a trigger edge from the external pin There are two sets two channels of input capture external pins and ICU data registers enabling measurements of a maximum of four events The input capture has two sets of external input pins INO IN1 and ICU registers IPCP enabling measurements of a maximum of four events Trigger edge direction can be selected from rising falling both edges The input capture can be set to generate an interrupt request at the storage timing of the counter value of the 16 bit free run timer to the ICU data register IPCP The input compare conforms to the extended intelligent I O service 2 8 The input capture ICU function is suited for measurements of intervals frequencies and pulse widths Register configuration CU data register ch 0 ch 1 IPCP
64. in Power Supply Pins In products with multiple Vec or Vss pins pins with the same potential are internally connected in the device to avoid abnormal operations including latch ups However the pins should be connected to external powers and ground lines to lower the electro magnetic emission level to prevent abnormal operation of strobe signals caused by the rise in the ground level and to conform to the total current rating Make sure to connect Vcc and Vss pins via lowest impedance to power lines It 15 recommended that a bypass capacitor of around 0 1 uF be placed between the Vcc and Vss pins near the device 17 18 MB90520 Series Using power supply pins Voc Vcc Vss Vcc MB90520 series Vcc Vss Vss Voc Crystal Oscillator Circuit Noise around the X0 and X1 pins may cause abnormal operation in this device In designing printed circuit boards the XO and X1 pins and crystal oscillator or ceramic oscillator as well as the bypass capacitor to the ground should be placed as close as possible and the related wiring should have as few crossings with other wiring as possible Circuit board artwork in which the area of the XO and X1 pins is surrounded by grounding is recommended for stabilizing the operation Turning on Sequence of Power Supply to A D Converter and Analog Inputs Make sure to turn on the A D converter power supply D A converter power supply AVcc AVRH AVRL DVcc DV
65. ion Delayed interrupt factor generation cancellation register DIRR Address bit15 bit14 bit13 bit12 bit11 bit10 Note Upon a reset an interrupt is cancelled R W Readable and writable Undefined bits read value undefined bit9 bit8 Initial value ww I l1 l1 I l1 lI lI xs m R W The DIRR is the register used to control delay interrupt request generation cancellation Programming this this register with 0 cancels a delay interrupt request Upon a reset an interrupt is canceled The undefined bit area can be programmed with either 0 or 1 For future extension however it is recommended that bit set and clear instructions be used to access this register with 1 generates a delay interrupt request Programming register 2 Block Diagram Internal data bus Delayed interrupt factor generation cancellation register DIRR Interrupt number Interrupt request signal lt gt 4 S factor R latch MB90520 Series EE 13 8 10 bit A D Converter The 8 10 bit A D converter converts analog voltage input to the analog input pins input voltage to digital values A D conversion and has the following features Minimum conversion time minimum 15 0 us at machine clock frequency of 16 MHz including sampling time Minimum sampling period 4 us 8 us at machine clock frequency of 16 MHz Compare time 99 176 machine cycles per channel 99 machine c
66. ion of digital output from 3FEC to 9 7 Notes for A D Conversion Analog inputs should have external circuit impedance of approximately 5 or less External capacitance if used should be several thousand times the level of the chip s internal capacitance in consideration of the effects of partial potential between the external and internal capacitance Ifthe impedance of the external circuit is too high the analog voltage sampling interval may be insufficient using a sampling interval of 4 00 us and a machine clock frequency of 16 MHz Block diagram of analog input circuit model Ron C Analog input LE AAN MB90522 MB90523 Ron Approx 1 5 kQ C Approx 30 pF MB90F523 Ron Approx 3 0 kQ C Approx 65 pF Note Listed values must be considered standards Error The smaller AVRH AVRIL is the greater the error is 97 98 MB90520 Series m aVa aF a 8 D A Converter Parameter Resolution AVcc Voc 5 0 V 10 AVss Vss DVss 0 0 V TA 40 C to 85 C Pin name Remarks Differential linearity error Absolute accuracy Linearity error Conversion time Load capacitance 20 pF Analog reference voltage Vss 3 0 Reference voltage supply current In sleep mode Analog output impedance E EXAMPLE CHARACTERISTICS 1 Power Supply Current MB90523
67. ion time 62 5 ns at oscillation of 4 MHz four times the oscillation clock operation at Vcc of 5 0 V Continued E PACKAGES 120 pin Plastic LQFP 120 pin Plastic QFP FPT 120P M05 MB90520 Series mm a rrC lt n Continued Maximum memory space 16 Mbytes Instruction set optimized for controller applications Rich data types bit byte word long word Rich addressing mode 23 types Enhanced signed multiplication division instruction and RETI instruction functions Enhanced precision calculation realized by 32 bit accumulator Instruction set designed for high level language C and multi task operations Adoption of system stack pointer Enhanced pointer indirect instructions Barrel shift instructions Program patch function for two address pointers Enhanced execution speed 4 byte instruction queue Enhanced interrupt function 8 levels 34 factors Automatic data transmission function independent of CPU operation Extended intelligent I O service function 2 5 Up to 16 channels Embedded ROM size and types Mask ROM 64 kbytes 128 kbytes Flash ROM 128 kbytes Embedded RAM size Mask ROM 4 kbytes Flash ROM 4 kbytes Evaluation product 6 kbytes Low power consumption stand by mode Sleep mode mode in which CPU operating clock is stopped Stop mode mode in which oscillation is stopped CPU intermittent operation mode Hardware stand by mode Clock mode mode in
68. is input pin 24Vc NVV Ny 8 Veo seo Noon ene JER Pins other than hystheresis input MD input 0 7 Vcc 89 MB90520 Series 4 Recommended Resonator Manufacturers Resonator manufacturer Murata Mfg Co Ltd Resonator CSA2 00MG040 Sample application of ceramic resonator Mask ROM product MB90522 MB90523 Frequency MHz Not required CSA4 00MG040 Not required CSA8 00MTZ Not required CSA16 00MXZ040 Not required CSA32 00MXZ040 Not required TDK Corporation CCR3 52MC3 to CCR6 96MC3 Built in Built in Not required CCR7 0MC5 to CCR12 0MC5 Built in Built in Not required CCR20 0MSC6 to CCR32 0MSC6 Not required 90 Continued MB90520 Series Continued Flash ROM product MB90F523 Resonator Frequency manufacturer Resonator Hz CSA2 00MG040 Not required CSA4 00MG040 Not required Murata Mfg Co Ltd 0 Not required CSA16 00MXZ040 Not required CSA32 00MXZ040 Not required CCR3 52MC3 to CCR6 96MC3 Built in Built in Not required CCR7 0MC5 to CCR12 0MC5 Built in Built in TDK Corporation Not required CCR20 0MSC6 to CCR32 0MSC6 Built in Built in Inquiry Murata Mfg Co Ltd Murata Electronics North America Inc TEL 1 404 436 1300 e Murata
69. isabled because it is used in the system 4 Area used by the system is the area set by the resistor for evaluating tool Notes For bits initialized by reset operations the initial value set by the reset operation is listed as an initial value Note that the values are different from reading results For LPMCR CKSCR WDTC there are cases in which initialization is performed or not performed depending on the types of the reset The value listed is the initial value in cases where initialization is per formed The addresses following OOOOFFu are reserved No external bus access signal is generated Boundary between the RAM area and the reserved area varies with the product models Channels 0 to 3 ofthe OCU compare register use 16 bit free run timer 2 while channels 4 to 7 of the OCU compare register use 16 bit free run timer 1 16 bit free run timer 1 is also used by input captures ICU 0 and 1 29 MB90520 Series 30 INTERRUPT FACTORS INTERRUPT VECTORS INTERRUPT CONTROL REGISTERS Interrupt source Reset Interrupt vector Interrupt control register Number Address FFFFDCk Priority Address INT9 instruction FFFFD8 Exception FFFFD4 8 10 bit A D converter Timebase timer 0000B0u DTPO DTP1 external interrupt 0 external interrupt 1 FFFFC8 16 bit free run timer 1 overflow FFFFC4 0000B1u Extended I
70. isters 8 16 bit PPG timer 0 1 XXX XXX XX 8 XXX XXX XX 8 XXX XXX XX 8 XXX XXX XX 8 OX000XX1 5 0X0000018 000000008 0000471 Disabled 000048u 000049u TMCSRO Timer control status register lower ch 0 Timer control status register upper ch 0 00004Au 00004Bu TMRO TMRLRO 16 bit timer register upper lower ch 0 16 bit re load register upper lower ch 0 16 bit re load timer 0 000000008 XXXX00008 XXXXXXXXs XXXXXXXXs 00004C 00004Du TMCSR1 Timer control status register lower ch 1 Timer control status register upper ch 1 00004Eu 00004F TMR1 TMRLR1 16 bit timer register upper lower ch 1 16 bit re load register upper lower ch 1 16 bit re load timer 1 000000008 XXXX00008 XXXXXXXXs XXXXXXXXs 000050u 0000514 IPCPO ICU data register ch 0 000052u 000053u IPCP1 ICU data register ch 1 000054u ICS01 ICU control status register 16 bit I O timer input compare 0 1 ICU section XXX XXX XX 8 XXX XXX XX 8 XXX XXX XX 8 XXX XXX XX 8 000000008 000055u Disabled 000056u 000057u Free run timer data register 1 R W 000058u Free run timer control status register 1 R W 16 bit I O timer 16 bit free run timer 1 section 000000008 000000008 000000008 000059u 00005Ak 00005Bu Disabled OC
71. k register ADB 8 bit register for displaying the additional data space p MB90520 Series EEE Sen General purpose registers Maximum of 32 banks RL3 RL2 RL1 RLO 000180k RP x 10 Processor status PS ILM RP CCR Z ooo UN bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit9 bit8 bit7 bit6 bit5 bit4 bit3 bit2 biti bito e peepee 2 ee T E eT Initial value 0 0 0 0 0 0 0 0 0 1 X X X X X Unused X Indeterminate 23 MB90520 Series EE 24 B MAP Address 0000004 Abbreviated register name PDRO Register name Port 0 data register Resource name Port 0 Initial value XXX XX XXX 8 0000014 PDR1 Port 1 data register Port 1 XXX XX XXX 8 0000024 PDR2 Port 2 data register Port 2 XXXXXXXXs 0000034 PDR3 Port 3 data register Port 3 XXX XX XXX 8 0000044 PDR4 Port 4 data register Port 4 XXX XX XXX 8 000005 PDR5 Port 5 data register Port 5 XXX XX XXX 8 0000064 PDR6 Port 6 data register Port 6 XXX XX XXX 8 000007 PDR7 Port 7 data register Port 7 XXX XX XXX 8 000008 PDR8 Port 8 data register Port 8 XXX XX XXX 8 0000094 PDR9 Port 9 data register Port 9 XXXXXXXXs
72. l is enabled This is a general purpose I O port This function becomes valid when waveform output from the OUT2 is disabled This is an event output pin for output compare 0 OCU ch 2 This function is valid when output for each channel is enabled This is a general purpose I O port This function becomes valid when waveform output from the OUTS is disabled This is an event output pin for output compare 0 OCU ch 3 This function is valid when output for each channel is enabled 1 FPT 120P M05 2 FPT 120P M13 This is a general purpose I O port This function becomes valid when waveform output from the PGOO is disabled This is an output pin of 8 16 bit PPG timer 0 This function becomes valid when waveform output from PGOO is enabled Continued MB90520 Series EE LQFP 120 QFP 120 Pin name Circuit type Function This is a general purpose I O port This function becomes valid when waveform output from the PGO1 is disabled This is an output pin of 8 16 bit PPG timer 0 This function becomes valid when waveform output from PG01 is enabled This is a general purpose I O port This function becomes valid when waveform output from the PG10 and PG11 are disabled This function can be set by the pull up resistor setup register RDR4 for input For output however this function is invalid This is an output pin of 8 16 bit PPG timer 1 This f
73. mer 0 P25 BINO 1 FPT 120P M05 2 FPT 120P M13 This is a general purpose I O port This port can be used as count clock B input for 8 16 bit up down counter timer 0 Continued MB90520 Series LQFP 120 QFP 120 Pin name Circuit type Function This is a general purpose I O port This port can be used as count clock Z input for 8 16 bit up down counter timer 0 This is a request input pin of the DTP external interrupt circuit ch 7 This is a general purpose I O port This is an external trigger input pin of the 8 10 bit A D converter Since this input is used as required for 8 10 bit A D converter input operation output by other functions must be suspended except for intentional operation This is a general purpose I O port This is a general purpose I O port This is a clock monitor function output pin This function is valid when clock monitor output is enabled This is a general purpose I O port This function becomes valid when waveform output from the OUTO is disabled This is an event output pin for output compare 0 OCU ch 0 This function is valid when output for each channel is enabled This is a general purpose I O port This function becomes valid when waveform output from the OUT1 is disabled This is an event output pin for output compare 0 OCU ch 1 This function is valid when output for each channe
74. n for selecting operation modes Connect directly to Vcc or Vss 90 RST This is an external reset request signal input pin 86 HST This is a hardware stand by input pin 95 to 101 00 to 06 INTO to INT6 This is a general purpose I O port This function can be set by the port 0 input pull up resistor setup register RDRO for input For output however this function is invalid This is a request input pin of the DTP external interrupt circuit ch 0 to ch 6 P07 This is a general purpose I O port This function can be set by the port 0 input pull up resistor setup register RDRO for input For output however this function is invalid 103 to 110 P10 to 17 WIO to WI7 This is a general purpose I O port This function can be set by the port 1 input pull up resistor setup register RDR1 for input For output however this function is invalid This is an I O pin for wake up interrupts P20 P21 P22 P23 IC00 IC01 IC10 IC11 This is a general purpose I O port This is a trigger input pin for input capture ICU 0 and 1 Since this input is used as required for input capture 0 and 1 ICU ch 0 ch 01 ch 10 and ch 11 input operation output by other functions must be suspended except for intentional operation P24 AINO This is a general purpose I O port This port can be used as count clock A input for 8 16 bit up down counter ti
75. nerates an interrupt request for switching tasks 8 10 bit A D converter 8 channels 8 10 bit resolution can be selectively used Starting by an external trigger input Conversion time minimum 15 0 us at machine clock frequency of 16 MHz including sampling time 8 bit D A converter based on the R 2R system 8 bit resolution 2 channels independent Setup time 12 5 us Clock timer 1 channel LCD controller driver A common driver and a segment driver that can directly drive the LCD liquid crystal display panel Clock output function Note Do not set external bus mode for the MB90520 series because it cannot be operated in this mode MB90520 Series PRODUCT LINEUP Part number Classification MB90522 MB90523 MB90F523 MB90V520 Mask ROM product Flash ROM product Evaluation product ROM size 64 kbytes 128 kbytes None RAM size 4 kbytes 6 kbytes Number of instructions 351 Instruction bit length 8 bits 16 bits Instruction length 1 byte to 7 bytes Data bit length 1 bit 8 bits 16 bits CPU functions Minimum execution time 62 5 ns at machine clock frequency of 16 MHz Interrupt processing time 1 5 us at machine clock frequency of 16 MHz minimum value General purpose I O ports CMOS output 53 General purpose I O ports via pull up resistor 24 General purpose I O ports N ch open drain output 8 Total 85 UART SCI Clock synchronized transmission 62
76. nterface 0 Since this input is used as required for serial data input operation output by other functions must be suspended except for intentional operation When using other output functions as well disable output during SIN operation Continued MB90520 Series LQFP 120 QFP 120 Pin name Circuit type Function This is a general purpose l O port This function can be set by the port 4 input pull up resistor setup register RDR4 for input For output however this function is invalid This is a data output pin for extended I O serial interface 0 This function becomes valid when serial data output from SOT1 is enabled This is a general purpose O port This function can be set by the port 4 input pull up resistor setup register RDR4 for input For output however this function is invalid This is a serial clock I O pin for extended I O serial interface 0 This function becomes valid when serial clock output from SCK1 is enabled AIN1 This is a general purpose l O port This is a data input pin for extended I O serial interface 1 Since this input is used as required for serial data input operation output by other functions must be suspended except for intentional operation This port can be used as count clock A input for 8 16 bit up down counter timer 1 P51 SOT2 BIN1 This is a general purpose O port This is a data output pin for extended I
77. o the output latch To avoid this situation configure the pins by the DDR register as output after writing output data to the PDR register when switching the bit used as input to output Operation as input port The pin is configured as input by setting the corresponding bit of the DDR register to 0 When the pin is configured as an input the output buffer is turned off and the pin is put into a high impedance status When data is written into the PDR register the data is retained in the output latch of the PDR but pin outputs are unaffected Reading the PDR register reads out the pin level 0 or 1 MB90520 Series 2 Register Configuration Port 0 data register PDRO Address bit6 bit5 bit4 bit3 bit2 bitt bitO Initial value oco P07 roe os pos Pao roe ror Poo 20000000 RW RW RW RW HW HW HW RW Port 1 data register PDR1 Address bit15 bit14 bit13 bit12 bit11 bit10 bit9 bits Initial value RW RW RW RW RW RW RW RW Port 2 data register PDR2 Address bit7 bit6 bits bit4 bit3 bit2 bitt bitO Initial value enne rer res res Poe rs me rer 000000 RW RW RW RW RW RW RW RW Port 3 data register PDR3 Address bit15 bit14 bit13 bit12 bit11 bit10 bit9 bits Initial value sonne rer pas Pos eoe res eee rev ra 20000000 RW RW RW RW RW RW RW RW Port 4 data register PDR4 Address bit6 bitS bit4 bit3 bit2 bitt bitO Initial value RW RW RW RW RW RW RW RW Port 5 data r
78. ore ordering The information and circuit diagrams in this document are presented as examples of semiconductor device applications and are not intended to be incorporated in devices for actual use Also FUJITSU is unable to assume responsibility for infringement of any patent rights or other rights of third parties arising from the use of this information or circuit diagrams The contents of this document may not be reproduced or copied without the permission of FUJITSU LIMITED FUJITSU semiconductor devices are intended for use in standard applications computers office automation and other office equipments industrial communications and measurement equipments personal or household devices etc CAUTION Customers considering the use of our products in special applications where failure or abnormal operation may directly affect human lives or cause physical injury or property damage or where extremely high levels of reliability are demanded such as aerospace systems atomic energy controls sea floor repeaters vehicle operating controls medical devices for life support etc are requested to consult with FUJITSU sales representatives before such use The company will not be responsible for damages arising from such use without prior approval Any semiconductor devices have inherently a certain rate of failure You must protect against injury damage or loss from such failures by incorporating safety design measures into your
79. p down circuit setting time Vcc power supply pin Va PONR power on reset signal _ A ij RST external asynchronous reset signal E RST internal reset signal A v l Oscillation clock signal and ULL UL LLL e KA internal operation clock A signal KB internal operation clock B signal ATNA PORT port output signal indereterminate period Dts 1 Step down circuit setting time 217 oscillation clock frequency oscillation clock frequency of 16 MHz 8 19 ms 2 Oscillation setting time 21 oscillation clock frequency oscillation cllock frequency of 16 MHz 16 38 ms 13 Initialization The device contains internal registers that can be initialized only by a power on reset To initialize the internal registers restart the power supply 14 Interrupt Recovery from Standby If an external interrupt is used for recovery from standby use an H level input request An L level request causes abnormal operation 15 Precautions for Use of DIV A Ri and DIVW A Ri Instructions The signed multiplication division instructions DIV A Ri and DIVW A RWi should be used when the corresponding bank registers DTB ADB USB SSB are set to value 00h If the corresponding bank registers DTB ADB USB SSB are set to a value other than 00h then the remainder obtained after the execution of the instruction will not be placed in the ins
80. pare 1 OCU ch 4 and ch 6 This function is valid when output for each channel is enabled 71 P73 TOO TO1 OUTS OUT7 This is a general purpose I O port This function is valid when TOO and TO1 output are disabled These are output pins for 16 bit re load timers 0 and 1 This function is valid when TOO and TO1 output are enabled These are event output pins for output compare 1 OCU ch 5 and ch 7 This function is valid when output for each channel is enabled 59 to 62 P74 to P77 COMO to COM3 This is a general purpose I O port This function is valid with port output specified for the LCD controller driver control register These are common pins for the LCD controller driver This function is valid with common output specified for the LCD controller driver control register 64 to 71 P80 to P87 SEG16 to SEG23 This is a general purpose I O port This function is valid with port output specified for the LCD controller driver control register These are segment outputs for the LCD controller driver This function is valid with segment output specified for the LCD controller driver control register 72 75 to 81 P90 P91 to P97 SEG24 SEG25 to SEG31 This is a general purpose I O port The maximum lo can be 10mA This function is valid with port output specified for the LCD controller driver control register These are segment outputs for the LC
81. rrupt control register 12 R W 000001118 0000BDk ICR13 Interrupt control register 13 R W 000001118 Continued MB90520 Series EE Continued Abbreviated Address register Register name Resource name Initial value name 0000BEk Interrupt control register 14 Interrupt 0000011128 Interrupt control register 15 controller 000001118 0000C0 to External area 0001004 to RAM area OOH HHHH OO HH to Reserved area 001FEFu 001FFOk Program address detection register 0 R W XXXXXXXXs Program address detection register 1 R W XXXXXXXXs Address match 001FF2k Program address detection register 2 R W detection XXXXXXXXs 001FF3u Program address detection register 3 R W function XXXXXXXXs Program address detection register 4 R W XXXXXXXXs 001FF5u Program address detection register 5 R W XXXXXXXXs 001FF6u Reserved area to 001FFFu Descriptions for read write R W Readable and writable R Read only W Write only Descriptions for initial value 0 The initial value is 0 1 The initial value is 1 X The initial value is indeterminate 1 This area is the only external access area having an address of OOOOFF or lower An access operation to this area is handled as that to external I O area 2 For details of the RAM area see the memory map 3 The reserved area is basically d
82. rupt 000000008 Continued Address 0000204 Abbreviated register name SMR Register name Serial mode register 0000214 SCR Serial control register 0000224 SIDR SODR Serial input data register serial output data register 000023u SSR Serial status register MB90520 Series Resource name Initial value 000000008 000001008 XXXXXXXXs 00001X00B 000024u SMCSLO Serial mode control lower status register 0 000025u SMCSHO Serial mode control upper status register 0 000026u SDRO Serial data register 0 Extended I O serial interface 0 XXXX00008 000000108 XXXXXXXXs 000027u CDCR Communications prescaler control register Communica tions prescaler control register OXXX 11115 000028u SMCSL1 Serial mode control lower status register 1 000029u SMCSH1 Serial mode control upper status register 1 00002Au SDR1 Serial data register 1 Extended I O serial interface 1 XXXX00008 000000108 XXXXXXXXs 00002Bu Disabled 00002C 00002Dx OCU control status register ch 45 00002E 00002F OCU control status register ch 67 16 bit I O timer output com pare 1 OCU section 0000XX005 XXX000008 0000XX00B XXX000008 000030u DTP interrupt enable register 0000314 DTP interrupt factor register 0000324 0000334
83. s 000080 Up down count register 0 000081 Up down count register 1 000082u Re load compare register 0 000083 Re load compare register 1 000084 Counter status register 0 8 16 bit up down counter timer 0 1 000000008 000000008 000000008 000000008 000000008 000085 Reserved area 3 000086 000087 Counter control register 0 R W 000088u Counter status register 1 R W 8 16 bit up down counter timer 0 1 X00000008 000000008 000000008 000089u Reserved area 00008A4 CCRL1 8 16 bit up down X0000000 amp Counter control register 1 R W counter timer 00008B CCRH1 0 1 X00000005 00008C RoRo PertO input pull up resistor setup R W Port 0 000000005 register 00008DH RDR1 Port 1 input pull up resistor setup R W Port 1 000000008 register 00008Ex RDR4 P9rt4 input pull up resistor setup R W Port 4 000000005 register Continued 27 28 MB90520 Series Address 00008FH to 00009Du Abbreviated register name WI UE Read write Resource name Area used by the system Initial value 00009Eu Program address detection control status register R W Address match detection function 000000008 00009Fu Delayed interrupt factor generation cancellation register Delayed inter rupt generation module XXXXXXX0B 0000A0u
84. s a 2 CH re load timer module for outputting pulse having given frequencies duty ratios The two modules perform the following operation by combining functions 8 bit PPG timer output 2 CH independent output mode This is a mode for operating independent 2 CH 8 bit PPG timers in which PGOO and PG10 pins correspond to outputs from PPGO and PPG1 respectively 16 bit PPG timer output operation mode In this mode PPGO and PPG1 are combined to be operated as a 1 CH 8 16 bit PPG timer 0 and 1 operating as a 16 bit timer Because outputs during 16 bit PPG timer output operation mode are reversed by an underflow from PPG1 the same output pulses are output from PG10 and PG11 pins 8 8 bit PPG timer output operation mode In this mode PPGO is operated as an 8 bit prescaler register in which an underflow output of PPGO is used as a clock source for PPG1 A prescaler output of PPGO is output from PG00 and PGO1 pins PPG output of PPG1 is output from PG10 and PG11 pins PPG output operation A pulse wave with any period duty ratio is output The module can also be used as a D A converter with an external add on circuit MB90520 Series EE 1 Register Configuration PPGO operating mode control register PPGCO Address bit7 bit6 bit5 bit4 bit3 bit2 bitt bitO Initial value sw Pene evo eu pere RW RW RW RW PPG1 operating mode control register PPGC1 Address bit 15 bit14 bit13 bit12 bit1
85. ss and analog inputs ANO to AN7 after turning on the digital power supply Vcc Turn off the digital power after turning off the A D converter supply and analog inputs In this case make sure that AVRH and DVcc do not exceed AVcc turning on off the analog and digital supplies simultaneously is acceptable Connection of Unused Pins of A D Converter Connect unused pins of A D converter and those of D A converter to AVcc DVcc Vcc AVss AVRH AVRL Vss N C Pin The N C internally connected pin must be opened for use 10 Notes on Energization To prevent the internal regulator circuit from malfunctioning set the voltage rise time during energization at 50 us or more 0 2 V to 2 7 V 11 Use of SEG COM Pins for the LCD Controller Driver as Ports In MB90520 series pins SEG08 to SEG31 and COMO to COM3 can also be used as general purpose ports The electrical standard is such that pins SEGO8 to SEG23 and COMO to COMG have the same ratings as the CMOS output port while pins SEG24 to SEG31 have the same ratings as the open drain type MB90520 Series 12 Indeterminate outputs from ports 0 and 1 The outputs from ports 0 and 1 become indeterminate during oscillation setting time of step down circuit during a power on reset after the power is turned on Pay attention to the port output timing shown as follow Timming chart of indeterminate outputs from ports o and 1 Oscillation setting time T Ste
86. supply to the CPU by the low power consumption control circuit sleep mode stopping clock supplies to the CPU and peripheral functions timebase timer mode and stopping oscillation clock stop mode hardware stand by mode Of these modes modes other than the PLL clock mode are low power consumption modes 1 Register Configuration Clock select register CKSCR Low power consumption EN control register LPMCR Address bit 15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 Boon 11111008 R RW RW RW RW RW RW Address bit7 bit6 bit5 X bit4 bit3 gt lbit 2 bit 1 bit 0 Initial value R W w w RW RW RW R W Readable and writable R Read only W Write only MB90520 Series 2 Block Diagram control circuit CPU clock control circuit CPU intermittent operation cycle selector Clock mode Sleep signal CPU operation clock Stop signal Hardware de Peripheral clock control circuit Peripheral function standby operation clock d s olr Hs o D p Panli 2o LS Machine clock Reset S Q S Q Interrupt D B xo Fr x Pn XOA Pin X1A Sub clock oscillator S Set R Reset Q Output lock Oscillation stabilization time selector Express us eos Clock select register CKSCR Divided E by 2 Main
87. t5 R W R W Readable and writable X Indeterminate Undefined bits read value undefined R W bit 4 R W R W bit 3 R W OCU control status register ch 01 ch 23 ch 45 ch 67 OCS01 OCS23 OCS45 OCS67 bit10 bit9 bit8 RW RW RW bit2 bill bit 0 bit 10 R W bit 2 R W bit 9 R W bit 1 R W bit 8 R W bit 0 R W Initial value XXX000008 Initial value 0000XX008 Initial value XXXXXXXX 8 Initial value XXXXXXXX 5 MB90520 Series Block diagram Output compare 0 OCU 36 Output compare interrupt request es ans OCU control status register ch 23 OCS23 C EE ele Compare control circuit 3 OCP3 4 4a OCU compare register ch 3 Compare control circuit 2 P35 OUT3 o 8 Sonrel Pin OCP2 circuit 3 s OCU compare register ch 2 3 K OV omaro registeren 2 c Output D control Pin t circuit 2 Compare control circuit 1 P33 OUT1 Output OCP1 T control Pin dup OCU compare register ch 1 circuit 1 P32 OUTO e fen x 7 contro Compare control circuit 0 circuit 0 OCPO i OCU compare register ch 0 2 9 een in OCU control status register ch 01 me lt gt 434 OCS01 Output compare 33 interrupt request Interrupt number 51 MB90520 Series Output compare 1 OCU Output compare
88. teristics 9 3FD passa T pet 1 LSB x N 1 0 5 LSB Q 5 E 004 i Var a l measured value 003 i Actual conversion characteristics 002 Theoretical characteristics 001 0 5 LSB AVRL Analog input AVRH 1 LSB Theoretical value VRH AVRL Iv Total error tor digital output N V 1 LSB x N 1 0 5 LSB 1 sg 1024 1 LSB Vor Theoretical value AVRL 0 5 LSB V Var Voltage at a transition of digital output from N 1 to N Vrsr Theoretical value AVRH 1 5 LSB V Continued 96 MB90520 Series Continued Linearity error Differential linearity error Theoretical 3FF characteristics Actual conversion 3FE z N 1 Actual conversion 1 LSB x N 1 characteristics 3FD Vor measured value N 5 59 S amp 3 Var 3 N 1 I 004 ii me measured value 3 Actual conversion Ve enr 2 9003 characteristics A wN 2pL i measured value 002 Var measured value Theoretical Actual conversion it characteristics 1 characteristics Vor mesured value AVRL Analog input AVRH AVRL Analog input AVRH Linearity error of Vxt 1 LSB x N 1 Vor LSB digital output N 1LSB Differential linearity error VN 07 Vt 1 LSB LSB of digital N 1 LSB 1LsB VNO iy 1022 Vor Voltage at transition of digital output from 000 to 001 Vest Voltage at transit
89. tics are warranted when the device is operated within these ranges Always use semiconductor devices within their recommended operating condition ranges Operation outside these ranges may adversely affect reliability and could result in device failure No warranty is made with respect to uses operating conditions or combinations not represented on the data sheet Users considering application outside the listed conditions are advised to contact their FUJITSU representatives beforehand C pin diagram 81 82 MB90520 Series nuu 3 DC Characteristics Parameter H level input voltage Symbol Pin name P20 to P27 P30 to P37 P53 P54 P70 to P77 P80 to P87 PAO to PA7 MDO to MD2 L level input voltage P20 to P27 P30 to P37 P53 P54 P70 to P77 P80 to P87 PAO to PA7 MDO to MD2 AVcc Vcc 5 0 V 10 AVss Vss 0 0 V Ta 40 C to 85 C Condition Vcc 3 0 V to 5 5 V MB90523 Vcc 4 0 V to 5 5 V MB90F523 Remarks Vec 0 3 Vss 0 3 H level output voltage Other than P90 to P97 Vcc 4 5 V lou 2 0 mA L level output voltage All output pins Vcc 4 5 V lo 2 0 mA Open drain output leakage current Output pin P90 to P97 Input leakage current Other than P90 to P97 Vcc 5 5 V Vss Vi Vcc
90. truction operand register 16 Precautions for Use of REALOS Extended intelligent I O service EI OS cannot be used when REALOS is used 20 MB90520 Series E BLOCK DIAGRAM LCD controller driver Output compare timer 2 Input 2 capture 1 lt ICU Intrnal data bus 8 10 bit A D converter 8 bit D A converter x 2 ch Oscillation clock X0 X1 Sub clock Clock control XOA X1A ig block RST gt including HST timebase timer P07 7 to PO6 INT6 DTP external interrupt circuit P24 AINO 8 16 bit P25 BINO P26 ZINO INT7 I O timer 1 P20 1C00 a E I P21 IC01 S ICU P32 OUTO gt P33 OUT1 compare 0 P34 OUT2 OCU P35 OUT3 en P31 CKOT P30 P36 PG00 PPG P40 PG10 i P41 PG11 tmar oi P42 SINO P43 SOTO P44 SCKO P45 SIN1 P46 SOT1 SIO ch 0 P47 SCK1 8 Wake up P10 WIO to P17 WI7 V Other pins MDO to MD2 C Vcc Vss 2 A register for setting a pull up resistor is supported 8 This is a high current port for an LCD drive 4 A register for setting a pull up resistor is supported Signals in the CMOS level are input and output is supported P80 SEG16 to P87 SEG23 P90 SEG24 to P97 SEG31 PAO SEG08 to PA7 SEG15 SEG00 to SEG07 VO to V3 P74 COMO to P77 COM3 P70 TI0 OUT4 P71 TOO OUT5 P72 TI1 OUT6 P73 TO1 OUT7 P22 IC10 P23 IC11 P60 ANO to P67 AN7 AVcc AVss AVRH AVRL P27 ADTG
91. unction becomes valid when waveform outputs from PG10 and PG11 are enabled This is a general purpose l O port This function can be set by the pull up resistor setup register RDR4 for input For output however this function is invalid This is a serial data input pin of UART SCI Because this input is used as required when UART SCI is performing input operations it is necessary to stop outputs by other functions unless such outputs are made intentionally When using other output functions as well disable output during SIN operation This is a general purpose l O port This function can be set by the pull up resistor setup register RDR4 for input For output however this function is invalid This is a serial data output pin of UART SCI This function becomes valid when serial data output from UART SCI is enabled This is a general purpose O port This function can be set by the pull up resistor setup register RDR4 for input For output however this function is invalid This is a serial clock I O pin of UART SCI This function becomes valid when serial clock output from UART SCI is enabled 1 FPT 120P M05 2 FPT 120P M13 10 This is a general purpose l O port This function can be set by the port 4 input pull up resistor setup register RDR4 for input For output however this function is invalid This is a data input pin for extended I O serial i
92. which other than sub clock and timebase timer are stopped Process CMOS technology I O port General purpose ports CMOS 53 ports General purpose l O ports via pull up resistors 24 ports General purpose ports open drain 8 ports Total 85 ports Timer Timebase timer watchdog timer 1 channel 8 16 bit PPG timers 0 1 8 bit x 2 channels or 16 bit x 1 channel 16 bit re load timers 0 1 2 channels Continued MB90520 Series EE Continued 16 bit I O timer 16 bit free run timers 1 2 2 channels Input captures 0 1 ICU Generates an interrupt request by latching a 16 bit free run timer counter value upon detection of an edge input to the pin Output compares 0 1 OCU Generates an interrupt request and reverses the output level upon detection of a match between the 16 bit free run timer counter value and the compare setting value 8 16 bit up down counter timers 0 1 1 channel 8 bit x 2 channels Extended I O serial interfaces 0 1 1 channel UART SCI With full duplex double buffer Clock asynchronized or clock synchronized transmission can be selectively used DTP external interrupt circuit 8 channels A module for starting extended intelligent I O service 8 and generating an external interrupt triggered by an external input Wake up interrupt Receives external interrupt requests and generates an interrupt request upon an L level input Delayed interrupt generation module Ge
93. ww I I I L I Ll L w W Write only Undefined bits read value undefined Note Do not access this register during operation at addresses 004000 to 2 Block Diagram ROM mirroring function selection register ROMM Address area Address FF bank 00 bank Internal data bus 76 MB90520 Series 20 Low power Consumption Stand by Mode The F MC 16LX has the following CPU operating modes configured by selection of an operating clock and clock operation control Clock mode PLL clock mode A mode in which the CPU and peripheral equipment are driven by PLL multiplied oscillation clock Main clock mode A mode in which the CPU and peripheral equipment are driven by drivided by 2 of the oscillation clock The PLL multiplication circuits stops in the main clock mode Sub clock mode The sub clock mode causes the CPU to operate only with the sub clock This mode uses the sub clock frequency divided by four as the operating clock frequency while stopping the main clock and PLL clock CPU intermittent operation mode The CPU intermittent operation mode is a mode for reducing power consumption by operating the CPU intermittently while external bus and peripheral functions are operated at a high speed Hardware stand by mode The hardware standby mode is a mode for reducing power consumption by stopping clock
94. ycles are used for a machine clock frequency below 10 MHz Conversion method RC successive approximation method with a sample and hold circuit 8 10 bit resolution Analog input pins Selectable from eight channels by software Single conversion mode Selects and converts one channel Scan conversion mode Converts two or more successive channels Up to eight channels can be programmed Continuous conversion mode Repeatedly converts specified channels Stop conversion mode Stops conversion after completing a conversion for one channel and wait for the next activation conversion can be started synchronously Interrupt requests can be generated and the extended intelligent I O service EOS can be started after the end of A D conversion Furthermore A D conversion result data can be transferred to the memory enabling efficient continuous processing When interrupts are enabled there is no loss of data even in continuous operations because the conversion data protection function is in effect Starting factors for conversion Selectable from software activation external trigger falling edge and timer rising edge 66 MB90520 Series EEE Sen 1 Register Configuration A D control status register upper digits ADCS2 Address bit 15 bit14 bit13 bit12 bit11 bit10 bit9 bits 000037 BUSY INT INTE PAUS STS1 STS0 STRT RW RW RW RW RW RW w A D control status register lower digits ADCS1 Address bit7 bit6 bit5 bit4 bit

FUJITSU SEMICONDUCTOR MB90520 Series handbook

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