Home

FUJITSU SEMICONDUCTOR MB90520A/520B Series handbook

image

Contents

1. 16 00 0 20 630 008 SQ D 14 00 0 10 551 004 SQ 7 ex 59 EE E3 10 08 003 Details of A part E 15022 E 059725 Mounting height e OFo DEEP DEP ED 3 T f LEAD No 1 j E 0 10 0 10 0 16 0 03 0 145 0 055 0 50 0 20 004 004 0 40 016 006 001 2 10 07 003 006 002 020 008 Stand on 0 45 0 75 0 25 010 018 030 L 1998 FUJITSU LIMITED F120006S 3C 4 Dimensions in mm inches Continued 98 Continued 120 pin Plastic QFP FPT 120P M13 MB90520A 520B Series Pins width and pins thickness include plating thickness 22 60 0 20 890 008 SQ 20 00 0 10 787 004 SQ og O e li 0 50 020 II 009 002 2000 FUJITSU LIMITED F1200138 c 3 5 5 0 08 003 0 145 0 055 006 002 0 08 003 r Details of A part 3 53 05 4013 139 tos Mouting height um 0 20 0 15 8 008 7006 I Y Stand off 0 50 0 20 10 25 010 020 008 0 60 0 15 024 006 Dimensions in mm
2. Continued Address 000060 000062 000063u Abbreviated Register Name MB90520A 520B Series Register Name OCU compare register ch 3 OCU control status register 0 ch 1 000064u 000065u OCU control status register ch 2 ch 3 Peripheral Name 16 bit timer Initial Value 0000 00 00000 0000 00 00000 000066 000067 000068 Freerun timer data register 1 Freerun timer control status register 1 16 bit timer 0000000 0s 0000000 0s 00000000 000069 Access prohibited 00006 control register 0 00006 control register 1 LCD controller driver 00010000s 0000000 0s 00006 00006 00006 compare register ch 7 16 bit timer Access prohibited 00006 ROM mirror function selection register ROM mirror function selection module XXXXXXX1B 000070u to 00007Fu Data memory for LCD display LCD controller driver 000080u Up down count register 0 0000814 Up down count register 1 000082u 000083u Reload compare register 0 Reload compare register 1 000084
3. DTP external interrupt enable register ENIR 58 MB90520A 520B Series 11 Wakeup Interrupts The wakeup interrupt function detects wakeup interrupt requests from external devices by detecting L levels input to the wakeup interrupt input pins WIO to WI7 and passes these to the CPU for interrupt processing Wakeup interrupts can used to wakeup the microcontroller from standby mode However wakeup interrupts cannot be used to recover from hardware standby mode Not supported by the extended intelligent service EIPOS Wakeup interrupt functions Function and Control Input pins 8 channels 8 pins WIO to WI7 Interrupt trigger e L level inputs One interrupt flag is shared by all eight channels Interrupt control Interrupt flag e Interrupt requests can be enabled or disabled in the wakeup interrupt control register EICR Interrupt requests are stored in the wakeup interrupt flag register EIFR 5 support Block diagram e Not supported by the extended intelligent I O service EIOS Undefined Internal data bus Wakeup interrupt Wakeup interrupt control register EICR flag register EIFR Interrupt request detection circuit vo s es D Wakeup interrupt request we gt gt
4. Power supply voltage Smoothing capacitor Operating temperature Note Use a ceramic capacitor or other capacitor with equivalent frequency characteristics The capacitance of the smoothing capacitor connected to the Vcc pin must be greater than Cs WARNING The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device All of the device s electrical characteristics are warranted when the device is operated within these ranges Always use semiconductor devices within their recommended operating condition ranges Operation outside these ranges may adversely affect reliability and could result in device failure No warranty is made with respect to uses operating conditions or combinations not represented on the data sheet Users considering application outside the listed conditions are advised to contact their FUJITSU representatives beforehand C pin diagram Cs 77 78 90520 520 Series 3 DC Characteristics AVcc Voc 5 0 V 10 AVss Vss DVss 0 0 V Ta 40 C to 85 C Parameter Pin Name P20 to P27 P30 to P37 P53 P54 H level input P70 to P77 voltage P80 to P87 PAO to PA7 to MD2 P20 to P27 P30 to P37 P53 P54 L level input P70 to P77 voltage P80 to P87 PAO to PA7 to MD2 Condition Vcc 3 0 V to 5 5 V level outpu
5. pes Function selection Timer control status register TMCSR Interrupt lt gt request output 45 90520 520 Series 6 16 bit I O Timers The 16 bit I O timers consist of a two channel 16 bit freerun timer two channel input capture and eight channel output compare The output compare channels can be used to generate eight independent waveform outputs based on the 16 bit freerun timer The input capture channels can be used to measure input pulse widths and external clock periods Structure of I O timers in the MB90520A 520B series 16 bit Freerun Timer Output Compare Input Capture 16 bit timer m Output compare 0 to 3 Input capture 0 and 1 unit 0 16 bit freerun timer 0 unit 0 unit 0 16 bit VO timer 16 bit freerun timer 1 Output compare 4 to 8 __ 1 1 16 bit freerun timer functions The count value for the 16 bit freerun timer sets the base time for the input capture and output compare functions An interrupt can be generated when the 16 bit freerun timer overflows Extended intelligent I O service EIOS be generated 16 bit freerun timers 0 and 1 can be cleared to 0000 when an external reset is input on setting the timer clear bit TCCS CLR 1 and when a compare match occurs on output compare 0 to 4 The count clock frequency can be selected from the following four clocks 4
6. 00 0000 00018 and the full scale transi tion point 11 1111 11108 gt 11 1111 11118 The variation from the ideal input voltage required to change the output code by 1 LSB The total error is the difference between the actual value and the theoretical value This includes the zero transition error full scale transition error and linearity error 1 LSB Theoretical value Total error for digital output N Total Error 3FFH 3FEH Actual conversion characteristic 3FDH a I 1 LSB x 1 0 5 LSB 2 24 J zu BU digs o 004H a Measured value 0034 T Actual conversion characteristic 002H dua Theoretical characteristic 001H helt 0 5 LSB AVRL AVRH Analog Input AVRH AVRL V 1024 Vnr 1 LSB x 1 40 5 LSB TLSB LSB Vor Theoretical value AVRL 0 5 LSB V Vest Theoretical value 1 5 LSB V Voltage at which digital output changes from 1 to N For 10 bit resolution this value is 1024 210 For 8 bit resolution this value is 256 28 Continued MB90520A 520B Series Continued Linearity Error Differential Linearity Error 3FFH Theoretical characteristic Actual conversion characteristic T LSBx N 1 N 1 ctual conversion 3FDH VFST 5 Measured 2 value 2 E au 1
7. 2 HCLK to 2 5 HCLK 2 HCLK to 226 8 8 bit PPG output operation mode 9 1 62 5 ns 1 0 to 29 0 1 0 to 29 0 1 0 to 219 1 0 to 27 0 9 2 125 ns 2 to 29 9 to 20 0 22 0 to 21 23 0 to 211 2 0 to 217 0 22 to 21 2216 to 21 23 to 21 9 4 250 ns 23 to 211 0 24010 212 0 23 6 to 21 24 to 220 0 9 8 500 ns 9 16 1000 ns 24 9 to 212 25 0 to 23 0 24 to 220 25 0 to 22 512 128 us 29 HCLK to 2 HCLK 2 HCLK to 2 8 HCLK 29 HCLK to 225 HCLK 2 HCLK to 226 1 8 8 output operation mode consists of using the lower 8 bits as prescaler for the PPG timer 2 The values enclosed in indicate the times for a machine clock frequency of 16 MHz MB90520A 520B Series PPG timer channels and PPG pins The figure below shows the relationship between the 8 16 bit PPG channels and PPG pins on the MB90520A 520B series PPGO PPGOO output pin 01 output pin PPG1 PPG10 output pin PPG11 output pin 42 90520 520 Series Block diagram 8 16 bit PPG timer 0 H level data bus L level data bus PPGO reload register PPGO operation mode control register TG SE PPGCO PRLHO PRLLO level register L level register PPGO tempor
8. FUJITSU SEMICONDUCTOR 16 bit Proprietary Microcontroller CMOS 161 MB90520A 520B Series MB90522A 523A 522B 523B F523B V520A DESCRIPTION The 90520 520 series is a general purpose 16 bit microcontroller designed for process control applications in consumer products that require high speed real time processing The microcontroller instruction set is based on the AT architecture of the F2MC family with additional instructions for high level languages extended addressing modes enhanced multiplication and division instructions and a complete range of bit manipulation instructions The microcontroller has a 32 bit accumulator for processing long word 32 bit data The MB90520A 520B series peripheral resources include an 8 10 bit A D converter 8 bit D A converter UART SCI extended serial interfaces 0 and 1 8 16 bit up down counter timers 0 and 1 8 16 bit PPG timers 0 and 1 a range of I O timers 16 bit free run timers 1 and 2 input capture ICU 0 and 1 and output compare OCU 0 and 1 an LCD controller driver 8 external interrupt inputs and 8 wakeup interrupts F2MC stands for FUJITSU Flexible MicroController a registered trademark of FUJITSU LIMITED FEATURES Clock Internal PLL clock multiplication circuit Selectable machine clock PLL clock Base oscillation divided by two or multiplied by one to four For a 4 MHz base oscillation the machi
9. ws WI6 gt wir Pn H gt 59 90520 520 Series sr rw 12 Delayed Interrupt Generation Module The delayed interrupt generation module is used to generate the task switching interrupt Generation of this hardware interrupt can be specified by software Delayed interrupt generation module functions Function and Control Writing 1 to bit RO of the delayed interrupt request generation clear register nterrupt tant DIRR 1 generates an interrupt request pt trigg e Writing 0 to bit RO of the delayed interrupt request generation clear register DIRR RO 0 clears the interrupt request Interrupt control No enable disable register is provided for this interrupt Interrupt flag Set in bit RO of the delayed interrupt request generation clear register DIRR 5 support e Not supported by the extended intelligent I O service EOS Block diagram Internal data bus Pd Interrupt request signal S Interrupt R request latch Delayed interrupt request generation clear register DIRR Undefined 60 MB90520A 520B Series 13 8 10 bit A D Converter The 8 10 bit A D converter uses RC successive approximation to convert analog input voltages to an 8 bit or 10 bit digital value The input signals can be selected from the eight analog input pin channels Either a software trigg
10. 0000 8 0000 9 Watchdog timer control register Watchdog timer Timebase timer control register Timebase timer 1 00000 0000 Clock timer Clock timer control register 1 001000 0000 to 0000ADu Access prohibited 0000 Flash memory control status register 1 Mbit flash memory 000X0000s 0000 Access prohibited 0000 0 0000 1 Interrupt control register 00 Interrupt control register 01 0000 2 Interrupt control register 02 0000B3u Interrupt control register 03 0000B4 Interrupt control register 04 0000B5u Interrupt control register 05 0000 6 Interrupt control register 06 0000 7 Interrupt controller Interrupt control register 07 0000B8 Interrupt control register 08 0000B9 Interrupt control register 09 0000 Interrupt control register 10 0000 Interrupt control register 11 0000 Interrupt control register 12 0000BDu Interrupt control register 13 0000011 1s 0000011 1s 000001 1 1s 000001 1 1 000001 1 1 000001 1 1 000001 1 1 000001 1 1 000001 1 1 000001 1 1 0000011 1 000001 1 1 000001 1 1 000001 1 1 Continued MB90520A 520B Series Continued Abbrevi
11. Circuit y control circuit SCK Start bit Transmission detection circuit start circuit Transmit bit counter Transmit parity counter Receive parity counter Receive bit i counter Transmission shift register Receive shift register Receive complete Transmission start Serial input Serial output data register data register Receive status evaluation circuit Receive error gt detection signal for 5 Internal data bus PE RE Communi ial EE cation Serial Serial Seria RDRF mode control status prescaler ist radleter TDRE register register register egis RIE TIE 56 MB90520A 520B Series 10 DTP Data Transfer Peripheral External Interrupt Circuit The DTP external interrupt function detects interrupt requests and data transfer requests input from external devices and passes these to the CPU as external interrupt requests This block can also activate the extended intelligent I O service EI OS DTP external interrupt functions External Interrupt DTP Function Input pins e 8 channels INTO to INT7 Interrupt conditions Interrupt control Can be set independently for each channel each pin in the detection level setup register ELVR e H level L level rising edge or falling edge input Interrupts can be enabled or d
12. Counter status register 0 8 16 bit up down counter timer 0 1 0000000 0s 0000000 0s 0000000 0s 0000000 0s 0000000 0s 0000854 Reserved 0000861 0000874 Counter control register 0 0000884 Counter status register 1 8 16 bit up down counter timer 0 1 0000000 0000000 0s 0000000 0s 0000894 Reserved 00008A 00008 Counter control register 1 8 16 bit up down counter timer O 1 0000000 0000000 00008 Port 0 input pull up resistor setup register Port 0 0000000 0s 00008 1 input pull up resistor setup register Port 1 0000000 0s Continued 25 26 90520 520 Series Address 00008 Abbreviated Register Name Register Name Peripheral Name Port 4 input pull up resistor setup register Initial Value 000000008 00008 to 00009Dk 00009 Ek Access prohibited Area reserved for system use 4 Address match detection Address detection control register function 000000008 00009 Delayed interrupt request output clear register Delayed interrupt generation module XXXXXXX 0000 0 Low power consumption mode control register Low power consumption 0000 1 standby mode Clock selection register 00011000s 11111100 0000A2u to 0000 7 Access prohibited
13. The os cillation clock stops The peripheral functions only operate using the sub clock SCLK The oscillation clock stops Clock The clock timer only operates using the sub clock SCLK The oscillation clock stops Stop The oscillation clock and sub clock are stopped and the CPU and peripherals halt operation CPU intermittent operation Normal run The oscillation clock HCLK divided by 2 operates intermittently for fixed time in tervals Hardware standby 72 Stop The oscillation clock and sub clock are stopped and the CPU and peripherals halt operation MB90520A 520B Series 21 Clock Monitor Function The clock monitor function outputs the machine clock divided by a specified amount to the clock monitor pin CKOT Clock monitor functions Output frequency e Machine clock divided by 2 to 32 8 settings available Interrupts e None EI OS support e Not supported by the extended intelligent I O service EIOS Output frequency of the clock monitor function When 8 MHz When 4 MHz Machine Clock Divide Ratio When 16 MHz Period Frequency Period Frequency 4 MHz Period Frequency 2MHz 2MHz 1 MHz 1 MHz 500 kHz 500 kHz 500 kHz 250 kHz 250 kHz 125 kHz 250 kHz 125 kHz 62 5 kHz 125 kHz 62 5 kHz 31 25 kHz 62 5 kHz Block diagram 31
14. 6 0 Input voltage Vss 6 0 Output voltage Vss 6 0 L level maximum output current 15 L level average output current L level total maximum output current L level total average output current H level maximum output current level average output current level total maximum output current level total average output current 6 Power consumption Pd MB90522A 523A F523B MB90522B 523B Operating temperature Storage temperature 1 2 3 4 bs 6 AVRL and DVcc shall never exceed Vcc AVRH AVRL shall never exceed AVcc Also AVRL shall never exceed AVRH Vcc 2 AVcc 2 DVcc 2 3 0 V Vi and Vo shall never exceed Vcc 0 3 V The maximum output current is the peak value for a single pin The average output current is the average current value for a single pin during a 100 ms period The total average current is the average current for all pins during a 100 ms period Note Average output current operating current x operating ratio WARNING Semiconductor devices can be permanently damaged by application of stress voltage current 76 temperature etc in excess of absolute maximum ratings Do not exceed these ratings MB90520A 520B Series 2 Recommended Operating Conditions Vss AVss 0 0
15. i VNT Measured value i m M m 1 i Measured value 003H pes 1 SJ pe ERA 1 4 Actual conversion 002 ET characteristic Measured Theoretical characteristic Actual conversion 001H eo ies characteristic AVRL AVRH AVRL AVRH Analog Input Analog Input Vat 1 LSB N 1 Linearity error for digital output N TLSB ou LSB Differential linearity error for digital output N twee 1 LSB LSB Vest 1 LSB 1022 Vor Voltage at which digital output changes from 000 to 0014 Vest Voltage at which digital output changes from to For 10 bit resolution this value is 1022 219 2 For 8 bit resolution this value is 254 28 2 91 90520 520 Series 7T Notes for A D Conversion The recommended external circuit impedance of analog inputs for MB90V520 is approximately 5 or less that for MB90F523B is approximately 15 5 or less and that for MB90522A 523A 522B 523B is approximately 10 or less If using an external capacitor the capacitance should be several thousand times the level of the chip s internal capacitor to allow for the partial potential between the external and internal capacitance If the impedance of the external circuit is too high the analog voltage sampling interval may be too short for sampling time 4 us machine clock frequency 16 MHz Bloc
16. 004000H 002000H Address 3 Registers 000100H 50608 Fagene Part No Address 1 Address 2 MB90522A B 0000 004000 001100 MB90523A B 0000 004000 001100 90 523 0000 004000 001100 90 520 001900u Internal memory access gt Access prohibited The values of addresses 1 2 and 3 vary by product Note The upper part of 00 bank contains a mirror of the ROM data in FF bank This is called the mirror ROM function and enables use of the C compiler s small memory model As the lower 16 bits of the FF bank and 00 bank addresses are the same tables located in ROM can be referenced without needing to declare far pointers For example accessing 00 000 actually accesses the contents of ROM at 000 Note that as the FF bank ROM area exceeds 48 KBytes the entire ROM image cannot be mirrored in 00 bank Accordingly as ROM data from FF40004 to FFFFFFa is mirrored in 0040004 to OOFFFFu always locate ROM data tables in the range FF4000u to FFFFFFu 21 22 90520 520 Series MAP Address 000000 Abbreviated Register Name Register Name Port 0 data register Peripheral Name Initial Value 0000014 Port 1 data register 000002u Port 2 data register 000003 Port 3 data register
17. clock mode pseudo clock mode stop mode hardware standby mode and CPU intermittent operation mode General purpose I O ports CMOS outputs 53 General purpose ports inputs with pull up resistors General purpose ports Nch open drain outputs 8 Total 85 24 Timebase timer 18 bit counter Interrupt interval 1 024 ms 4 096 ms 16 384 ms 131 072 ms for a 4 MHz base oscillation Watchdog timer Reset trigger period e For a 4 MHz base oscillation 3 58 14 33 57 23 458 75 ms For 32 768 sub clock operation 0 438 3 500 7 000 14 000 s 16 bit freerun timer Number of channels 2 Generates an interrupt on overflow 16 bit output compare Number of channels 8 Pin change timing Free run timer register value equals output compare register value 16 bit input capture Number of channels 2 Saves the value of the freerun timer register when a pin input occurs rising edge falling edge either edge 16 bit reload timer Number of channels 2 Count clock frequency 0 125 0 5 or 2 0 us for a 16 MHz machine clock Can be used to count an external event clock Continued Continued Parameter Clock timer MB90520A 520B Series MB90522A MB90523A MB90522B MB90523B MB90F523B MB90V520A 15 bit timer Interrupt interval 0 438 0 5 or 2 0 us for sub clock frequency 32 768 kHz 8 16 bit PPG timer 8 16 bit up down counter
18. inches 90520 520 Series FUJITSU LIMITED Rights Reserved The contents of this document are subject to change without notice Customers are advised to consult with FUJITSU sales representatives before ordering The information and circuit diagrams in this document are presented as examples of semiconductor device applications and are not intended to be incorporated in devices for actual use Also FUJITSU is unable to assume responsibility for infringement of any patent rights or other rights of third parties arising from the use of this information or circuit diagrams The products described in this document are designed developed and manufactured as contemplated for general use including without limitation ordinary industrial use general office use personal use and household use but are not designed developed and manufactured as contemplated 1 for use accompanying fatal risks or dangers that unless extremely high safety is secured could have a serious effect to the public and could lead directly to death personal injury severe physical damage or other loss 1 nuclear reaction control in nuclear facility aircraft flight control air traffic control mass transport control medical life support system missile launch control in weapon system 2 for use requiring extremely high reliability i e submersible repeater and artificial satellite Please note that Fujitsu will not
19. 5 Output control circuit 1 5 Output control Pin Compare control circuit O 4 circuit 0 4 AP Output compare register 0 4 Output compare control 2 status registers 05 01 OSC45 Name for output compare unit 1 Z moden ren L Output compare gt interrupt request MB90520A 520B Series 7 8 16 bit Up Down Counter Timers 0 1 The 8 16 bit up down counter timers can operate in timer mode up down count mode and phase difference count mode The unit can be used as either a 2 channel x 8 bit or 1 channel x 16 bit up down counter timer 8 16 bit up down counter timer functions Operation Mode 8 bit x 2 channel mode Count Mode Timer mode Count Clock Count Edge 2 0 4 6 Machine clock frequency Function of ZIN Pin Up down count mode Counts up on detecting speci fied edge on the AIN pin Counts down on detecting spec ified edge on the BIN pin Counter clear function Gate function Phase difference count mode multiply by 2 Reads the AIN pin input level on detecting a rising or falling edge on the BIN pin and counts up or counts down Counter clear function Gate function Phase difference count mode multiply by 4 Reads the AIN pin input level on detecting a risi
20. MHz Relationship between oscillation frequency and internal operating clock frequency E Divided by 2 1 3 4 6 8 12 16 Source Oscillation Clock fcP MHz The AC ratings are measured at the following reference voltages Input signal waveform Hysteresis input pin Output signal waveform Output pin sis input or MD input pins MB90520A 520B Series 4 Clock Output Timings AVcc 5 0 V 10 AVss Vss DVss 0 0 V 40 to 85 Value Parameter Symbol Condition Min Typ Cycle time tcvc 62 5 CLK Vce 5 0 V 10 CLK T gt CLK I 20 85 86 90520 520 Series 5 UART SCI Timings Parameter Serial clock cycle time 5 0 V 1096 AVss Vss DVss 0 0 V Ta 40 to 85 Pin Name SCK0 to SCK2 SCK SOT delay time SCKO to SCK2 SOTO to SOT2 Valid SIN 3 SCK T SCKO to SCK2 SINO to SIN2 SCK T gt valid SIN hold time SCKO to SCK2 SINO to SIN2 Condition Internal shift clock mode output pin load is C 80 pF 1 TTL Serial clock H pulse width SCKO to SCK2 Serial clock L pulse width SCK SOT delay time SCKO to SCK2 SCK0 to SCK2 SOTO to SOT2 Valid SIN gt SCK T SCKO to SCK2 SINO to SIN2 SCK f 5 valid SIN hold time See 3 Clock Timings
21. O O O O O gt a B a n n n n n n n o n n n n n n o n n n n gt gt P31 CKOT RST P32 OUTO MDO P33 OUT1 MD1 P34 OUT2 MD2 P35 OUT3 HST P36 PG00 P37 PG01 V2 Vcc V1 P40 PG10 VO P41 PG11 P97 SEG31 P42 SINO P96 SEG30 P43 SOTO P95 SEG29 P44 SCKO P94 SEG28 P45 SIN1 P93 SEG27 P46 SOT1 P92 SEG26 P47 SCK1 P91 SEG25 SEGO SEG1 X1A SEG2 P90 SEG24 SEG3 P87 SEG23 SEG4 P86 SEG22 SEG5 P85 SEG21 SEG6 P84 SEG20 SEG7 P83 SEG19 PAO SEG8 P82 SEG18 PA1 SEG9 P81 SEG17 PA2 SEG10 P80 SEG16 PA3 SEG11 Vss PA4 SEG12 P77 COM3 PAS SEG13 P76 COM2 wot 2209044 0pr r22222220 EtDL2 20800006 OO aad NU SRL 0000000 S 2506 ao oo 200 SENETA em ud Sp 4332 120 05 120 13 90520 520 Series DESCRIPTIONS 120 QFP 1207 92 93 74 73 89 to 87 90 86 95 to 101 103 to 110 Pin Name XO X1 X1A MDO to MD2 RST HST POO to P06 INTO to 6 20 21 22 23 00 ICO1 IC10 IC11 1 FPT 120P M05 2 FPT 120P M13 Circuit Type Function Oscillator pin Sub oscillator pin Input pins for setting the operation mode Connect directly to Vcc or Vs
22. handler program The address match detection function provides a simple method of correcting programming errors patching using RAM or similar Address match detection functions No of address settings Two channels two addresses can be set e An interrupt is generated when the program address matches the detection Interrupts address setting register support e Not supported by the extended intelligent I O service EOS Block diagram PADRO 24 bit Detection address setting register pec 24 bit Detection address setting register Address latch 9 instruction generates 9 interrupt Internal data bus PACSR Address detection control register PACSR Reserved Always set to 0 70 MB90520A 520B Series 19 ROM Mirror Function Selection Module The ROM mirror function selection module enables ROM data in FF bank to be read by accessing 00 bank ROM mirror function selection module functions Mirror setting address e Data FFFFFFu to 4000 in FF bank can be read from OOFFFFu to 004000u in 00 bank Interrupts e None support e Not supported by the extended intelligent I O service EOS Relationship between addresses in the ROM mirror function 004000H 00 bank mirror area OOF
23. is enabled when the analog input enable register ADER is set P70 P72 TIO TI1 OUTA OUT6 1 120 05 2 FPT 120P M13 General purpose ports Event input pins for 16 bit reload timers 0 and 1 Input operates continuously when 16 bit reload timers 0 and 1 input an external clock Accordingly output to these pins from other functions that share the pins must be suspended unless performed intentionally Event output pins for ch 4 and ch 6 of output compare unit 1 OCU Only available when event output from output compare 1 is enabled Continued 11 90520 520 Series LQFP 120 QFP 1207 Pin Name P71 P73 TOO TO1 OUTS OUT7 Circuit Type Function General purpose I O ports Only available when event outputs from 16 bit reload timers 0 and 1 are disabled Output pins for 16 bit reload timers 0 1 Only available when output is enabled for 16 bit reload timers 0 and 1 Event output pins for ch 5 and ch 7 of output compare unit 1 OCU Only available when event output from output compare 1 is enabled 59 to 62 P74 to P77 COMO to COM3 General purpose I O ports Only available when the LCD controller driver control register is set to the ports Common pins for the LCD controller driver Only available when the LCD controller driver control register is set to the common outputs 64 to 71 72 75 to 81 P80
24. outputs and the electrical ratings for SEG24 to SEG31 are the same as for N ch open drain ports 90520 520 Series Conditions when output from ports 0 1 is undefined After turning on the power supply the outputs from ports 0 and 1 are undefined during the oscillation stabili zation delay time controlled by the regulator circuit during the power on reset The figure below shows the timing Note that this undefined output period does not occur on products without an internal regulator circuit as these products do not have an oscillation stabilization delay time Timing chart for undefined output from ports 0 and 1 Oscillation stabilization delay time 2 Regulator circuit stabilization delay time gt 7D n x F L Vcc Power supply pin PONR Power on reset signal RST External asynchronous reset signal RST Internal reset signal 424211 Oscillation clock signal LU LELELTETLTLTLTUT UT E KA Internal operating clock A signal Internal operating clock B signal PORT port output signal 6 Undefined output ime 1 Regulator circuit oscillation stabilization delay time 217 Oscillation clock frequency approx 8 19 ms for a 16 MHz oscillation clock frequency 2 Oscillation stabilization delay time 218 Oscillation clock frequency approx 16 38 ms for a 16 M
25. 0 Can be written and erased by the program Interrupts Write and erase completion interrupts EI OS support e Not supported by the extended intelligent I O service EIOS Embedded Algorithm is a trademark of Advanced Micro Devices Sector configuration of flash memory Flash memory CPU address Writer address 1 FEO000H 1 60000 64 Kbyte FEFFFH ______ FF0000 70000 SA1 32 Kbyte FF7FFFH 77FFFH ___ FF8000H 78000H SA2 8 Kbyte FFOFFFH 79FFFH gt FFAO00H 7A000H 8 Kbyte FFBFFFH 78 nu 7CO000H 16 TERRA ____ The writer address is the address to use instead of the CPU address when writing data from a parallel flash memory writer Use the writer address when programming or erasing using a general purpose parallel writer 74 MB90520A 520B Series Pins used for Fujitsu standard serial on board programming MD2 MD1 MDO Mode pins Setting MD2 MD1 1 MDO 0 selects flash memory serial program ming mode XO X1 Oscillation input pin Flash memory serial programming mode uses the PLL clock with the multiplier set to 1 as the machine clock Set the oscillation frequency used for serial programming to between 3 MHz and 16 MHz P01 Write program activation pins Input POO 0 L level and P01 1 H
26. 0 0 V 3 0 V lt AVRH AVRL 40 C to 85 C Parameter Resolution Total error Pin Name 25 0 Remarks Linearity error 22 5 Differential linearity error t1 9 Zero transition voltage ANO to AN7 AVss 3 5 LSB AVss 0 5 LSB AVss 4 5 LSB Full scale transition voltage ANO to AN7 AVRH 6 5 LSB AVRH 1 5 LSB AVRH 1 5 LSB A D conversion time Compare time 163 tcp 99 tcp At machine clock 16 MHz At machine clock 16 MHz Analog port input current ANO to AN7 10 Analog input voltage ANO to AN7 AVRL AVRH Reference voltage AVRH AVRL 3 0 AVRL 3 0 Power supply current AVcc AVcc Reference voltage supply current AVRH AVRH Variation between channels Current when 8 10 bit A D converter not used and CPU in stop mode Vcc ANO to AN7 AVRH 5 0 V Note See 3 Clock Timings in 4 AC Ratings for more information about tcr internal operating clock cycle time 89 90 90520 520 Series 6 A D Converter Glossary The change in analog voltage that can be recognized by the A D converter The deviation between the actual conversion characteristics and the line linking the Resolution Linearity error Differential linearity error Total error zero transition point 00 0000 0000
27. 000004 000005 Port 4 data register Port 5 data register 000006u Port 6 data register 000007 Port 7 data register 000008 Port 8 data register 000009u Port 9 data register 00000 00000 LCDCMR Port A data register Port 7 COM pin selection register Port 7 LCD controller driver XXXX 000 0s 00000 000000 4 OCU compare register ch 4 16 bit timer 00000 Access prohibited 00000 Wakeup interrupt flag register Wakeup interrupts 000010u 000011 Port 0 direction register Port 1 direction register Port 0 0000000 0s 00000000 000012 Port 2 direction register 0000000 0s 0000134 Port 3 direction register 0000000 0s 0000144 Port 4 direction register 00000000 000015 Port 5 direction register XXX 000005 000016u 000017u Port 6 direction register Port 7 direction register Port 7 00000000 00000000 000018 Port 8 direction register Port 8 00000000 000019 Port 9 direction register Port 9 0000000 0s 00001A Port A direction register Port A 0000000 0s 00001Bu Analog input enable regis
28. 25 kHz 15 625 kHz Internal data bus Undefined Machine clock frequency Count clock selector Output enable Clock output enable register CLKR Se CKEN FRQ2 FRQ1 FRQO 73 90520 520 Series 22 1 Mbit Flash Memory This section describes the flash memory on the MB90F523B and does not apply to evaluation products and MASK ROM versions The flash memory is located in banks FE to FF in the CPU memory map Flash memory functions Memory size 1 Mbit 128 KBytes Memory configuration 128 KWords x 8 bits or 64 KWords x 16 bits Sector configuration 16 KBytes 8 KBytes 8 KBytes 32 KBytes 64 KBytes Sector protect function Selectable for each sector e Automatic programming algorithm Embedded Algorithm Equivalent to 29 400 Compatible with JEDEC standard commands Includes an erase pause and restart function Data polling and toggle bit write erase completion Erasing by sector available sectors can be combined in any combination Programming algorithm Operation commands No of write erase cycles e Min 10 000 guaranteed Can be written and erased using a parallel writer Minato Electronics model 1890A Ando Denki AF9704 AF9705 AF9706 Memory write erase AF9708 and AF9709 method Can be written and erased using a dedicated serial writer YDC AF200 AF210 AF120 and AF11
29. 250 ns 16 9 1 0 us 64 0 4 0 us 256 16 0 us Note the machine clock frequency The values in are for 16 MHz machine clock Input capture functions The input capture saves the value of the 16 bit freerun timer and generates an interrupt request when the specified edge is detected on the trigger input from the external trigger input pin ICOO or ICO1 IC10 or IC11 Input capture channels 0 and 1 can perform input capture and generate interrupt request independently Extended intelligent I O service EIOS can be generated Detection of rising edges falling edges or either edge can be selected as the trigger edge When using input capture 0 either the 00 or 01 pin can be used Note however that masking one pin only is not possible When using input capture 1 either the IC10 or IC11 pin can be used Note however that masking one pin only is not possible Output compare functions The output compare channels compare the values set in output compare registers 0 to 7 with the 16 bit freerun timers 0 and 1 count values and invert the level of the corresponding output compare pin and clear the 16 bit freerun timer to 0000 when a match is detected Extended intelligent I O service El20S can be generated The initial output levels at the output compare pins can be set after the microcontroller boots The output levels from the eight output compare channels are controlled independently Simi
30. 48 ms for the main clock 2 5 HCLK approx 8 192 ms 2 HCLK approx 32 768 ms 2 HCLK approx 1 024 ms 2 4 HCLK approx 4 096 ms 216 approx 16 384 ms 2 9 HCLK approx 131 072 ms PPG timer 29 HCLK approx 0 128 ms HCLK Oscillation clock frequency The values enclosed in indicate the times for a clock frequency of 4 MHz Watchdog timer 36 MB90520A 520B Series Block diagram To PPG timer Timebase timer counter HCLK divided by2 Reset Clear stop mode 2 Counter clear Interval timer 7 H Switch clock 3 gt selector TBOF clear TBOF set TBR 1 TBCO Timebase timer control register TBTC Timebase timer interrupt signal lt gt OF Overflow HCLK Oscillation clock frequency 1 Power on reset release of hardware standby mode watchdog reset 2 Olear stop mode main clock mode PLL clock mode and pseudo clock mode 3 Main PLL clock Sub main clock Sub PLL clock To watchdog timer stabilization delay time selector To oscillation in clock controller The actual interrupt request number for the timebase timer is Interrupt request number 12 37 38 90520 520 Series 3 Watchdog Timer The watchdog timer is a timer counter used to detect faults such as progra
31. 5 External clock input 94 20 15 lt 10 9 5 0 2 3 4 5 6 Vcc V Vcc V Ice Ta 2 425 C External clock input 25 External clock input 70 20 60 15 50 f 8 kHz lt 40 8 kHz 3 30 5 20 10 0 2 3 4 5 6 0 Vcc V 2 3 4 5 6 Vcc V Continued Continued MB90520A 520B Series 10 uA 1000 900 Voc 25 External clock input 8 kHz 3 4 5 6 Voc V Example MB90523A Vou Characteristics 25 Vcc 4 5 V Vcc Vor mV Example MB90523A Vo lo Characteristics 25 Vcc 4 5 V 1000 900 lot mA 90520 520 Series ORDERING INFORMATION Part No Package Remarks MB90522APFF MB90523APFF 120 pin Plastic LQFP MB90522BPFF 120 5 MB90F523BPFF MB90522APFV MB90523APFV 120 pin Plastic QFP MB90522BPFV FPT 120P M13 MB90F523BPFV 96 90520 520 Series TETTE PACKAGE DIMENSIONS 120 pin Plastic LQFP 120 05 Pins width and pins thickness include plating thickness
32. F54 0000BFu 29 90520 520 Series PERIPHERAL RESOURCES 1 Ports The I O ports can be used as general purpose ports parallel I O ports The MB90520A and 5208 series have 11 ports 85 pins The ports share pins with the inputs and outputs of the peripheral functions The port data registers PDR used to output data to the I O pins and capture the input signals from the ports Similarly the port direction registers DDR set the direction input or output for each individual port bit The following tables list the ports and peripheral functions with which they share pins Pin Name Port P00 P06 Pin Name Peripheral INTO INT6 Peripheral Function that Shares Pin External interrupts P07 Not shared P10 P17 WIO WI7 Wakeup interrupts P20 P23 P24 P25 INOO IN11 AINO BINO Input capture unit 0 8 16 bit up down counter timer 0 P26 ZINO INT7 8 16 bit up down counter timer 0 external interrupt P30 Not shared P31 CKOT Clock monitor function P32 P35 OUTO OUT3 Output compare unit 0 P36 P37 P40 P41 00 PPGO1 PPG10 PPG11 8 16 bit timer 0 8 16 bit PPG timer 1 P42 P44 SINO SOTO SCKO UART SCI P45 P47 SIN1 SOT1 SCK1 Extended serial interface 0 SIN2 AIN1 SOT1 BIN1 SCK1 ZIN1 50 P52 8 16 bit up down c
33. FFFH 0000 ROM area in MB90523A 523B and F523B FEFFFFH 0000 FF4000H ROM area in MB90522A and 522B Mirrored ROM data area in FF bank FFFFFFH Block diagram ROM mirror function selection register ROMM Address o 3 FF bank 71 90520 520 Series 20 Low Power Consumption Standby Modes The power consumption of FAMC 16LX devices can be reduced by various settings relating to the operating clock selection Functions of each CPU operation mode CPU Operation Clock PLL clock Operation Mode Normal run Explanation The CPU and peripheral functions operate using the oscillation clock HCLK mul tiplied by the PLL circuit Sleep Pseudo clock The peripheral functions only operate using the oscillation clock HCLK multiplied by the PLL circuit The timebase timer only operates using the oscillation clock HCLK multiplied by the PLL circuit Stop The oscillation clock is stopped and the CPU and peripherals halt operation Main clock Normal run The CPU and peripheral functions operate using the oscillation clock HCLK di vided by 2 Sleep The peripheral functions only operate using the oscillation clock HCLK divided by 2 Stop The oscillation clock is stopped and the CPU and peripherals halt operation Sub clock Normal run Sleep The CPU and peripheral functions operate using the sub clock SCLK
34. Hz oscillation clock frequency Note See the M PRODUCT LINEUP section for details of which MB90520A 520B series products have an internal regulator circuit Initialization The device contains internal registers that are only initialized by a power on reset To initialize these registers restart the power supply Notes on using the DIV A Ri and DIVW A RWi instructions Set the corresponding bank registers USB SSB to when using the signed division instruc tions DIV A Ri and DIVW A RWi If the corresponding bank registers ADB USB SSB are set to other than 00 the remainder value produced by the instruction is not stored in the instruction operand register Notes on using REALOS The extended intelligent I O service EIOS cannot be used when using REALOS Caution on Operations during PLL Clock Mode If the PLL clock mode is selected the microcontroller attempt to be working with the self oscillating circuit even when there is no external oscillator or external clock input is stopped Performance of this operation however cannot be guaranteed 20 90520 520 Series BLOCK DIAGRAM F2MC 16LX CPU Clock controller Main clock clock XOA X1A pubic Includes RST timebase timer ST 7 POO INTO to PO6 INT6 E DTP external interrupt circuit P24 AINO 8 16 bit
35. P25 BINO updown counter P26 ZINO INT7 oe timer 1 20 00 21 1 01 capture 22 10 ICU P23 IC11 16 bit freerun timer 0 P32 OUTO P33 OUT1 4 P34 OUT2 P35 0UT3 i P31 CKOT P30 P36 PG00 P37 PG01 8 16 bit P40 PG10 d P41 PG11 0 P42 SINO P43 SOTO prid P44 SCKO SCI P45 SIN1 P46 SOT1 SIO ch 1 PA7 SCK1 P410 WIO to Other pins MDO to MD2 C Vcc Vss Wakeup interrupts circuits Internal data bus P80 SEG16 to P87 SEG23 P90 SEG24 to P97 SEG31 0 5 08 to PA7 SEG15 to SEGO7 to V3 P74 COMO to 77 controller driver P70 TIO OUTA4 P71 TOO OUT5 P72 TM OUT6 P73 TO1 OUT7 timer 2 Output compare 1 OCU 16 bit freerun timer 1 P60 ANO to P67 AN7 AVcc 8 10 bit AVas ven rter AVAR AVRL P27 ADTG P50 SIN2 AIN1 P51 SOT2 BIN1 P52 SCK2 ZIN1 8 bit P53 DA0 D A P54 DA1 converter x2ch DVcc DVss 1 The clock control circuit includes the watchdog timer and timebase timer low power consumption control 2 Incorporates a pull up register setting register CMOS level input and output 3 As this port shares pins with the LCD output the port uses N ch open drain circuits MB90520A 520B Series MEMORY Single chip mode with mirror function FFFFFFH Address 1 FE0000H 010000H Address 2
36. PPGO and PPG1 that can generate pulse outputs with the periods specified in the table below and with duty ratios between 0 and 10095 Note that the pulse periods are different depending on the operation mode Operation Mode 8 bit PPG output Independent 2ch operation mode Count Clock 9 1 62 5 ns 00 01 PPG10 PPG11 ch1 Interval Time to 28 9 Output Pulse Width 1 0 to 29 0 Interval Time to 25 9 Output Pulse Width to 29 0 9 2 125 ns to 29 0 22 to 21 9 22 9 to 210 0 23 0 to 211 0 to 29 9 22 to 2190 to 210 to 211 0 9 4 250 ns 23 0 to 211 0 24 9 to 212 23 0 to 211 0 to 22 0 9 8 500 ns 9 16 1000 ns 24 9 to 212 25 0 to 213 24 9 to 212 to 23 0 HCLK 512 128 us 2 HCLK to 2 HCLK 2 HCLK to 2 8 HCLK 2 HCLK to 2 HCLK 210 HCLK to 2 8 HCLK 16 bit PPG output operation mode 9 1 62 5 ns 1 0 to 21 1 0 to 2779 1 0 to 219 1 0 to 27 0 9 2 125 ns 2 to 27 0 22 0 to 218 0 22 0 to 21 23 0 to 21 2 0 to 217 0 22 0 to 218 0 22 0 to 218 0 23 0 to 21 9 8 500 ns 23 0 to 29 0 24 9 to 220 23 to 29 0 240 to 220 9 4 250 ns 9 16 1000 ns 24010 220 0 25 to 22 24010 22 25 0 to 22 HCLK 512 128 us 2 HCLK to 2 5 HCLK 2 HCLK to 226
37. Vcc 5 0 V 10 AVss Vss DVss 0 0 V 40 C to 85 Reset input time Hardware standby input time See 3 Clock Timings for more information about internal operating clock cycle time tRSTL tHSTL HST 0 2 Vcc 0 2 Vcc Measurement conditions for AC ratings Pin C is the load capacitance for the pin during testing CL 81 90520 520 Series 2 Power On Reset Parameter Power supply rise time ms Vcc 5 0 V 1096 AVss Vss DVss 0 0 V Ta 40 to 85 Power supply cutoff time torr ms For repeated operation Vcc must be less than 0 2 V before power on Notes e The above rating values are for generating a power on reset When HST 1 always apply the power supply in accordance with the above ratings regardless of whether a power on reset is required e Some internal registers are only initialized by a power on reset Always apply the power supply in cordance with the above ratings if you wish to initialize these registers Voc Sudden changes in the power supply voltage may cause a power on reset The recommended practice if you wish to change the power supply voltage while the device is operating is to raise the voltage smoothly as shown below Also changes to the supply voltage should be performed when the PLL clo
38. ary 2 18 buffer PRLBHO Reload register level H level 5 Select signal selector PPG1 underflow Count start value PPG0 underflow Reload y to PPG1 Pulse selector Underflow PPGO down counter PCNTO CLK PPGO output latch LE 00 Timebase timer output PPG output control circuit HCLK 512 Peripheral clock 6 1 Peripheral clock 0 2 1 o Peripheral clock 0 4 Count gt LE Peripheral clock 6 8 9 clock PPGO1 Peripheral clock 0 16 1 9 selector t Z Select signal reserenzram raven rn PPG01 output control register PPGOE Undefined Reserved Reserved bit HCLK Oscillation clock frequency Machine clock frequency request output lt gt Operation mode control signal MB90520A 520B Series 8 16 bit PPG timer 1 H level data bus E L level data bus PPG1 operation mode control register PPGC1 Su Ee Pe Tm 2 7 H level register register L level register Operation lt mode control signal Interrupt PPG1 temporar 2 18 buffer PRLBHT Y request output 5 Reload selector L level H level selector Select signal 4 PPG1 Invert output latch Count start value PPG1 down counte
39. aster slave communications Extended I O serial interface Number of channels 2 Clock synchronous transfer 31 25 Kbps to 1 Mbps Using internal shift clock Transmission format Selectable LSB first or MSB first LCD controller driver Number of common outputs 4 Number of segment outputs 32 Number of power supply pins for LCD drive 4 LCD display memory 16 bytes Divider resistor for LCD drive Internal 1 As for the necessity of switch setting 52 when using the emulation pod MB2145 507 Refer to the hardware manual for the emulation pod MB2145 507 fomr details 2 Take note of the maximum operating frequency and A D converter precision restrictions when operating at 3 0 V to 3 6 V See the Electrical Characteristics section for details 90520 520 Series PACKAGES AND CORRESPONDING PRODUCTS Package MB90522A MB90523A MB90522B MB90523B MB90F523B MB90V520A 120 05 LQFP FPT 120P M13 QFP PGA 256C A01 PGA Available X Not available Note See the PACKAGE DIMENSIONS section for more details 90520 520 Series PIN ASSIGNMENT TOP VIEW N ok 2222222 XO LO sh CO c L0 CO N QU IO SECO QN OO PANN QN N N N N N O O O
40. ated Address Register Register Name Peripheral Name Initial Value Name 0000 Interrupt control register 14 0000011 1 Interrupt controller 0000BFu Interrupt control register 15 0000011 1 0000 0 to Access prohibited 0000 000100 to RAM area 00 to Reserved area 001 001FFOu Detection address setting register 0 XXXXXXXXe low byte 001FF1 Detection address setting register 0 XXXXXXXXs middle byte 001FF2x Detection address setting register 0 XXXXXXXXs high byte Address match i i i detection function 001FF3x Detection address setting register 1 XXXXXXXXs low byte 001 4 Detection address setting register 1 XXXXXXXXs middle byte 001 Detection address setting register 1 XXXXXXXXs high byte 001 to Reserved area 001 Initial value notation Initial value of bit is 0 1 Initial value of bit is 1 X lnitial value of bit is undefined 1 Access is prohibited to the address range 0000 0 to 0000 See the MEMORY MAP section 2 See the MEMORY section for details of the RAM area 3 Reserved areas are addresses used internally by the system and may not be used 4 The Area reserved for system use contains setting registers used by the evaluation tools Notes e LPMCR CKSCR and WDTC are initialized by some types of reset and not by others The initial values listed are for th
41. be liable against you and or any third party for any claims or damages arising in connection with above mentioned uses of the products Any semiconductor devices have an inherent chance of failure You must protect against injury damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy fire protection and prevention of over current levels and other abnormal operating conditions If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Law of Japan the prior authorization by Japanese government will be required for export of those products from Japan F0203 FUJITSU LIMITED Printed in Japan
42. cillator to and X1A even if not using sub clock mode Treatment of unused pins Leaving unused input pins unconnected can cause misoperation or permanent damage to the device due to latchup Always pull up or pull down unused pins using a 2 or larger resistor If some pins are unused either set as outputs and leave open circuit or set as inputs and treat in the same way as input pins Treatment of N C pins Always leave N C non connect pins open circuit Treatment of pins when A D converter not used When not using the A D converter and D A converter always connect AVcc DVcc AVRH Vcc and AVss AVRL Vss Sequence for connecting and disconnecting the A D converter power supply and analog input pins Do not apply voltage to the A D and D A converter power supply AVcc AVRH AVRL DVss or analog inputs ANO to AN7 until the digital power supply Vcc is turned on When turning the device off turn off the digital power supply after disconnecting the A D converter power supply and analog inputs When turning the power on or off ensure that AVRH and DVcc do not exceed AVcc turning the analog and digital power supplies on and off simultaneously is OK Shared use of general purpose I O ports and LCD controller driver SEG COM pins The SEGO08 to SEG31 and COMO to COMS pins are shared with general purpose ports The electrical ratings for 8 to SEG23 and COMO to COMG are the same as for CMOS
43. ck is not in use The PLL clock may be used however if the rate of voltage change is 1 V s or less Vcc Recommended rate of voltage rise is 50 mV ms or less SOM s Maintain RAM data Vss 82 MB90520A 520B Series 3 Clock Timings AVcc Vcc 5 0 V 1096 AVss Vss DVss 0 0 V Ta 40 C to 85 Parameter 20 X1 X0A X1A 20 X1 X0A X1A Clock frequency Clock cycle time X0 Recommended duty Input clock pulse width ratio 30 to 70 Input clock rise fall When using an time external clock Internal operating When using main clock clock frequency When using sub clock Internal operating When using main clock clock cycle time When using sub clock X0 and X1 clock timing and X1A clock timing 83 84 90520 520 Series Fwwa Supply Voltage Vcc V 3 0 2 7 PLL guaranteed operation range Relationship between internal operating clock frequency and power supply voltage Guaranteed operation range for MB90V520A 1 PLL guaranteed operation range 7 r A D D A guaranteed 1 voltage range 1 1 1 1 V Guaranteed operation range for MB90522A 523A MB90522B 523B F523B 16 12 Internal Clock fcP MHz co 1 5 3 8 10 16 Internal Clock fcP
44. d When using internal shift clock Up to 1 MHz operation can be achieved for a 16 MHz machine clock with the divisor setting for the communication prescaler set to 8 Speeds faster than 1 MHz are not possible When using an external shift clock As a minimum of 5 machine cycles are required when the machine clock is 16 MHz the maximum input frequency for the external shift clock is 16 MHz 5 3 2 MHz Data transmission format LSB first or MSB first selectable e Data transfer only Number of data bits 8 fixed Interrupt request generation Interrupt generated when transfer completes support 52 Supports use of the extended intelligent service MB90520A 520B Series Block diagram Internal data bus D7 to DO MSB first B4 D7 to DO LSB first Transmission direction selection Pin Serial data register SDR SIN Read I Write l H Pin A Control circuit Shift clock counter SCK Machine clock Communications prescaler Serial mode control status register SMCS epe on E T Fede Interrupt request mo pro Communications prescaler register CDCR 53 90520 520 Series 9 UART SCI Serial Communication Interface The UART SCI is a general purpose serial communications interface for pe
45. e case when the registers are initialized The boundary address between the RAM area and Reserved area differs depending on the product See the B MEMORY section for details e OCU compare registers 0 to ch 3 use 16 bit freerun timer 0 and OCU compare registers ch 4 to ch 7 use 16 bit freerun timer 1 Note that 16 bit freerun timer 0 is also used by input capture 0 and 1 ICU 27 90520 520 Series INTERRUPTS INTERRUPT VECTORS AND INTERRUPT CONTROL REGISTERS Interrupt Reset EPOS Support Interrupt Vector No Address FFFFDCu Interrupt Control Register Address INT 9 instruction FFFFD8 Exception 4 8 10 bit A D converter FFFFDOH Timebase timer DTPO DTP1 external interrupt 0 external interrupt 1 16 bit freerun timer 0 overflow 4 0000 0 Extended serial interface 1 Wakeup interrupt 0000 2 Extended serial interface 2 8 DTP2 DTP3 external interrupt 2 external interrupt 3 8 16 bit PPG timer 0 counter borrow 4 5 external interrupt 4 external interrupt 5 0000B3k 0000 4 8 16 bit up down counter timer 0 compare match 8 8 16 bit up down counter timer 0 overflow up down direc
46. e error detected Transmit interrupt Transmission complete e Both transmit and receive support the extended intelligent service EIPOS Master slave communication function multi processor mode Used for 1 master to n slave communications Can only be used as master EI OS support 54 e Supports the extended intelligent I O service EIPOS MB90520A 520B Series UART SCI operation modes No of Data Bits Parity Bit No of Stop Bits Operation Mode 7 bits 8 bits None Use 1 bit 2 bits Normal mode 1 to 1 Multi processor mode 1 to n Clock synchronous mode Asynchronous Asynchronous Clock synchronous O Available X Not available 1 Address data bit used for communication control Notes The number of data bits must be set to eight for multi processor and clock synchronous modes A parity bit cannot be used in multi processor and clock synchronous modes Only data can be transferred in clock synchronous mode Start and stop bits cannot be added to the trans mission data 55 90520 520 Series Block diagram Control bus Receive interrupt Dedicated baud rate request output Transmit clock Transmit interrupt 16 bit Clock request output reload timer 0 selector Receive clock Receive control Transmission Pin
47. e used simultaneously Interrupts e None D A conversion trigger Set the digital value in the D A data register DADR then enable D A output in the D A control register DACR to start analog output from the D A output pin EI OS support e Not supported by the extended intelligent service EI OS D A converter theoretical output voltage D A Data Setting Theoretical Output Voltage Value 0 256 x DVcc voltage 0 1 256 x DVcc voltage 254 256 x DVcc voltage 255 256 x DVcc voltage Note DVcc voltage D A converter reference voltage This must not exceed Vcc Also always ensure that DVss is equipotential to Vss 63 90520 520 Series TETTE Block diagram Internal data bus D A data register DADR os ow o D A conversion circuit 2RZ DVss Standby control SPL 1 Internal data bus Standby control Controls stop mode SPL 1 pseudo clock mode SPL 1 clock mode SPL 1 and hardware standby mode 64 90520 520 Series 15 The clock timer is a 15 bit freerun timer that counts up synchronized with the sub clock Seven different interval time settings are available This timer provides the clock for the sub clock s oscillation stabilization delay timer and the watchdog timer This timer a
48. er RDR4 are enabled when ports are set as inputs The RDR4 settings are ignored when ports are set as outputs UART SCI serial data output pin Only available when serial data output is enabled for the UART SCI General purpose I O port The settings in the pull up resistor setup register RDR4 are enabled when ports are set as inputs The RDR4 settings are ignored when ports are set as outputs UART SCI serial clock input output pin Only available when serial clock output is enabled for the UART SCI General purpose I O port The settings in the pull up resistor setup register RDR4 are enabled when ports set as inputs The RDR4 settings are ignored when ports set are as outputs Data input pin for extended I O serial interface 1 Input operates continuously when the performing serial input Accordingly output to the pin from other functions that share this pin must be suspended unless performed intentionally 1 FPT 120P M05 2 FPT 120P M13 10 General purpose I O port The settings in the pull up resistor setup register RDR4 are enabled when ports set as inputs The RDR4 settings are ignored when ports are set as outputs Data output pin for extended serial interface 1 Only available when serial data output is enabled for SOT1 Continued MB90520A 520B Series LQFP 120 QFP 1207 Pin Name Circuit Type Function General purpose I O port The sett
49. er internal timer output or external pin trigger can be selected to trigger the start of A D conversion 8 10 bit A D converter functions A D conversion time Sampling time Can be selected from 64 128 or 4096 machine cycles The minimum is 4 us e Compare time Can be selected from 44 99 or 176 machine cycles The minimum is 4 4 us A D conversion time sampling time conversion time The minimum A D conversion time is 10 2 us Conversion method RC successive approximation with sample amp hold circuit Resolution Analog input pins e 8 bit or 10 bit selectable Up to eight channels can be used However two or more channels cannot be used simultaneously Interrupts An interrupt request can be generated when A D conversion completes A D conversion start trigger e Selectable software internal timer output or falling edge on input from external pin EI OS support e Supported by the extended intelligent I O service EIOS 8 10 bit A D converter conversion modes Single shot conversion mode Continuous conversion mode Performs A D conversion sequentially from the start channel to the end channel A D con version halts after conversion completes for the end channel Performs A D conversion sequentially from the start channel to the end channel A D con version starts again from the start channel after conversion completes for the end channel Inc
50. for more information about internal operating clock cycle time SCKO to SCK2 SINO to SIN2 External shift clock mode output pin load is C 80 pF 1 TTL Notes These are the AC ratings for CLK synchronous mode CL is the load capacitor connected to the pin for testing MB90520A 520B Series Internal shift clock mode SCKO to SCK2 SOTO to SOT2 SINO to SIN2 External shift clock mode SCKO to SCK2 SOTO to SOT2 SINO to SIN2 0 8 Vcc 0 2 Vcc 0 8 Vcc 0 2 Vcc 87 90520 520 Series 6 Timer Input Timings AVcc Vcc 5 0 V 1096 AVss Vss DVss 0 0 V Ta 40 to 85 Parameter Pin Name Condition 00 01 Input pulse width 10 11 TIO See 3 Clock Timings for more information about internal operating clock cycle time 00 01 10 11 TIO TH 7 Timer Output Timings AVcc Vcc 5 0 V 1096 AVss Vss DVss 0 0 V Ta 40 to 85 C Parameter Pin Name Condition OUTO to OUT7 00 01 PG10 11 TOO TO1 T Tour change time CLK 24V TOUT 08 V Tour OUTO to OUT7 PG00 01 PG10 11 TOO TO1 88 MB90520A 520B Series 5 Electrical Characteristics for the A D Converter AVcc 5 0 V 10 AVss Vss DVss
51. gister 0000314 DTP interrupt request register 000032u 000033u 000034 000035 Request level setting register OCU compare register ch 6 DTP external interrupt circuit 16 bit timer 0000000 0s 000000008 000000008 000036u 000037u A D control status register 000038 000039 A D data register 8 10 bit A D converter 0000000 0s 0000000 0s 00001 00003A D A converter data register ch 0 00003 D A converter data register ch 1 00003 D A control register 0 00003 D A control register 1 8 bit D A converter 00003E Clock output enable register Clock monitor function XXXX 000 0s Continued 23 24 90520 520 Series Address 00003 Abbreviated Register Name Register Name Peripheral Name Access prohibited Initial Value 000040u 000041 PPGO reload register L PPGO reload register H 000042u PPG1 reload register L 000043u PPG1 reload register 000044 PPGO operation mode control register 000045u PPG1 operation mode control register 000046u 000047u PPGO 1 output control register 8 16 bit PPG timer O 1 Access proh
52. gram 8 16 bit up down counter timer 0 Internal data bus RCRO Reload compare register 0 Reload control circuit UDCRO Carry Borrow Up down count register 0 to channel Counter control 1 register 0 CCRO L pops Counter clear circuit Compare control circuit Edge level detection circuit Overflow Underflow Count clock Counter status register 0 CSRO PE Up down count selector es Interrupt request Interrupt lt gt request Counter control register 0 CCRO M16E gt to channel 1 50 MB90520A 520B Series 8 16 bit up down counter timer 1 Internal data bus RCR1 Reload compare register 1 Reload control circuit Counter control register 1 CCR1 L Compare Edge level control circuit Frenchie fx bor detection Counter 1 clear circuit circuit Carry Borrow from channel 0 Overflow Underflow Count clock Counter status Machine clock Pre register 1 CSR1 AIN1 scaler Up down count clock CSTR CITE UDIE CMPFIOVFF UDFF UDF1 UDFO Edge selector detection circuit BINI A Fr Interrupt M16E reque
53. han Vcc or less than Vss is applied to an input or output pin other than high or medium withstand voltage pin or if the voltage applied between and Vss exceeds the rating If latch up occurs the power supply current increases rapidly resulting in thermal damage to circuit elements Therefore ensure that maximum ratings are not exceeded in circuit operation Similarly when turning the analog power supply on or off ensure the analog power supply voltages DVcc and analog input voltages do not exceed the digital voltage Vcc Also ensure that the voltages applied to the LCD power supply pins V3 to VO do not exceed the power supply voltage Voc Supply voltage stability Rapid changes in supply voltage may cause the device to misoperate even if the voltage remains within the allowed operating range Accordingly ensure that the Vcc supply is stable The standard for power supply voltage stability is a peak to peak Vcc ripple voltage at the mains supply frequency 50 to 60 Hz of 1095 or less of Vcc and a transient voltage change rate of 0 1 V ms or less when turning the power supply on or off Power on precautions To prevent misoperation of the internal regulator circuit at power on ensure that the power supply rising time 0 2 V to 2 7 V is at least 50 us Power supply pins When multiple Vcc and Vss pins are provided connect all Vcc and Vss pins to power supply or ground externally Although pins at the sa
54. he timebase timer output Events that stop the watchdog timer 1 Stop due to a power on reset 2 Reset due to recovery from hardware standby mode 3 Watchdog reset Events that clear the watchdog timer 1 External reset input from the RST pin O Writing 0 to the software reset bit Writing 0 to the watchdog control bit second and subsequent times Changing to sleep mode clears the watchdog timer and temporarily halts the count Changing to pseudo clock mode clears the watchdog timer and temporarily halts the count Changing to clock mode clears the watchdog timer and temporarily halts the count Changing to stop mode clears the watchdog timer and temporarily halts the count MB90520A 520B Series Block diagram Watchdog timer control register WDTC timer Reset Change to sleep mode gt Counter Counter Watchdog timer Change to pseudo clock mode clock counter reset reset generation circuit circuit Change to clock mode control circuit selector Change to stop mode gt Timebase timer counter Main clock HCLK divided by 2 Clock counter 508 5244 HCLK Oscillation clock frequency 39 40 90520 520 Series 4 8 16 bit PPG Programmable Pulse Generator Timers 0 and 1 The 8 16 bit PPG timer is a two channel reload timer module
55. hing Analog digital conversion 8 10 bit A D converter 8 channels Can be initiated by an external trigger Minimum conversion time 10 2 us for a 16 MHz machine clock 8 bit D A converter 2 channels R 2R type Settling time 12 5 us for a 16 MHz machine clock Display function LCD controller driver 32 x segment drivers 4 x common drivers Other Supports serial writing to flash memory Only on versions with on board flash memory Note The MB90520A 520B series cannot be used in external bus mode Always set these devices to single chip mode 90520 520 Series PRODUCT LINEUP Parameter Classification MB90522A MB90523A MB90522B MB90523B MB90F523B MB90V520A Evaluation Mask ROM product Flash ROM ROM size 64 Kbytes 128 Kbytes 128 Kbytes 128 Kbytes 64 Kbytes RAM size 4 Kbytes 6 Kbytes Separate emulator power supply No Process Operating power supply voltage 3 0 V to 5 5 V 27 5 5 3 0 V to 5 5 V Internal regulator circuit not mounted mounted CPU functions Number of instructions 340 Instruction sizes 8 bit 16 bit Instruction length 1 byte to 7 bytes Data sizes 1 bit 8 bit 16 bit Minimum instruction execution time 62 5 ns for a 16 MHz machine clock Interrupt processing time 1 5 us min for a 16 MHz machine clock Low power operation standby modes ports Sleep mode
56. ibited 0X000XX 18 0X00000 1s 0000000 0s 0000481 0000494 TMCSRO Timer control status register 0 00004 00004 TMRO TMRLRO 16 bit timer register ch 0 16 bit reload register 0 16 bit reload timer 0 0000000 0s XXXX 000 0s 00004 000040 TMCSR1 Timer control status register ch 1 00004 00004 TMR1 TMRLR1 16 bit timer register ch 1 16 bit reload register ch 1 16 bit reload timer 1 0000000 0s 0000 000050u 0000514 IPCPO ICU data register 0 000052u 000053u IPCP1 ICU data register ch 1 000054u ICS01 ICU control status register 16 bit timer 00000000 000055 Access prohibited 000056u 000057u Freerun timer data register O 000058u Freerun timer control status register 0 16 bit timer 0000000 0s 0000000 0s 0000000 0s 0000594 Access prohibited 00005A 00005 compare register 0 00005 00005 compare register ch 1 00005 OCU compare register ch 2 16 bit timer
57. ings in the pull up resistor setup register RDR4 are enabled when ports are set as inputs The RDR4 settings are ignored when ports are set as outputs Serial clock input output pin for extended I O serial interface 1 Only available when serial clock output is enabled for SCK1 General purpose I O port Data input for extended I O serial interface 2 Input operates continuously when the performing serial input Accordingly output to the pin from other functions that share this pin must be suspended unless performed intentionally Also can be used as the count clock A input to 8 16 bit up down counter timer 1 General purpose I O port Data output pin for extended I O serial interface 2 Only available when serial data output is enabled for SOT2 Also can be used as the count clock B input to 8 16 bit up down counter timer 1 General purpose I O port Serial clock input output pin for extended I O serial interface 2 Only available when serial clock output is enabled for SCK2 Also can be used as the control clock Z input to 8 16 bit up down counter timer 1 46 to 53 P60 to P67 ANO to AN7 General purpose ports Analog output pins for 0 and ch 1 of the 8 bit D A converter General purpose ports Port input is enabled when the analog input enable register ADER is set to the ports Analog inputs for the 8 10 bit A D converter Analog input
58. isabled in the DTP external interrupt enable register Interrupt flag The DTP external interrupt request register EIRR stores interrupt requests Processing selection Set El OS to be disabled ICR ISE 0 e Set EIOS to be enabled ICR ISE 1 Interrupt execution Jumps to interrupt handler routine after Neue automatic data transfer by 2 5 completes 2 5 support e Supports the extended intelligent I O service EIPOS 57 90520 520 Series TETTE Block diagram Detection level setting register ELVR Level Edge Pin Level Edge selector selector Level Edge selector Pin Level Edge selector INT2 Pin gt Level Edge selector Pin Level Edge selector Internal data bus Pin Level Edge selector Level Edge selector PUPS Te NIP Te SIP TT asco DTP external interrupt input R6 ER4 ER3 ERO detection circuit DTP external interrupt request register EIRR Interrupt request signal lev ew ee eee eee en Interrupt request signal
59. k diagram of analog input circuit model Analog input RON C MB90522A 523A 522B 523B Ron 2 2 approx 45 pF approx MB90F523B 2 6 approx C 28 pF approx Note The values listed are an indication only Error The relative error increases as AVRH AVRL becomes smaller MB90520A 520B Series 8 Electrical Characteristics for the D A Converter Parameter Resolution AVcc Voc 5 0 V 10 AVss Vss DVss 0 0 V Ta 40 C to 85 C Remarks Differential linearity error Absolute accuracy Linearity error Conversion time For load capacitance 20 Analog reference voltage Vss 3 0 Current consumption for reference voltage Stop mode Analog output impedance 9 Flash Memory Program Erase Parameter Sector erase time Chip erase time Word 16 bit width programming time Condition 25 Vcc 5 0 Remarks Excludes 00H programming prior erasure Excludes 00H programming prior erasure Excludes system level overhead Program Erase cycle Data hold time 93 90520 520 Series EXAMPLE CHARACTERISTICS Power supply current MB90523A Voc 25 External clock input lccs Vcc 2
60. l up option CMOS hysteresis input CMOS level output With standby control 1 Eeh Digital output Ich Digital output Hysteresis input lot 4 mA Standby control CMOS hysteresis input CMOS level output With standby control Continued MB90520A 520B Series Segment output pins Capacitor connection pin This is an N C pin on the MB90522A 90523 Analog power supply input protection circuit c R Vcc I Eeh Digital output Digital output 777 Vss lo 4 mA Hysteresis input Standby control Analog output CMOS hysteresis input CMOS level output CMOS output is not available when analog output is operating Also used as analog output Analog output has priority With standby control A D converter ref power supply input pin Incorporates power supply protection circuit Continued 15 90520 520 Series Circuit 1 Digital output her Digital output 777 Vss R loL 4 mA L Ww gt gt Hysteresis input Standby control Analog input Remarks CMOS hysteresis input CMOS level output Also used as analog input With standby control f Vcc 1 euni Digital output neg Digital output R 777 Vss loL 4 mA t W gt gt Hysteresis input Standby control Segment o
61. larly interrupt requests are also generated independently by each channel 46 Block diagram MB90520A 520B Series 16 bit freerun timer Timer data Y op TCDTO TCDT1 OF Prescaler 2 16 bit counter stop CLR Output compare register 0 Timer control status registers TCCSO TCCS1 7 9 Machine clock frequency OF Overflow Name for 16 freerun timer channel 1 wee StoP MODE our oua ouo Counter value output to input capture and output compare Output compare register 4 match signal Freerun timer Internal data bus overflow interrupt request Input capture 00 Pin i INOT IN10 Pin Input capture control status register 501 y en eere D J Input capture interrupt request Internal data bus 47 48 90520 520 Series Output compare Output compare control status registers OSC23 OSC67 Timer data registers HR compare p interrupt request me Lee TCDTO TCDT1 16 bit freerun timer 0 1 circuit 3 7 Internal data bus Outpu circui Output compare register 1
62. level RST Reset pin HST Hardware standby pin Serial data input pin Serial data output pin Serial clock input pin Input an H level during flash memory serial programming mode Uses the UART SCI in clock synchronous mode C pin Capacitor pin for power supply stabilization Connect an external capac of approx 0 1 Power supply voltage pins If the user system can provide the programming voltage 5 V 1095 do not need to connect to the flash microcontroller writer GND pin Connect to common GND with the flash microcontroller writer Overall configuration of connection between serial writer and MB90F523A Fujitsu standard serial on board programming uses a flash microcontroller writer made by YDC Host interface cable AZ221 gt RS232C writer serial MB90F523A B user system memory card Standard cable AZ210 Flash microcontroller Clock synchronous ES s l Can operate standalone Note Contact YDC for details of the functions and operation of the flash microcontroller writer AF220 AF210 AF120 or AF110 standard connection cable AZ210 and connectors 75 90520 520 Series Electrical Characteristics 1 Power supply voltage a Vss 6 0 Absolute Maximum Ratings Vss AVss 0 0 V Parameter Remarks Vss 6 0 Vss 6 0 Vss
63. lways counts the sub clock regardless of the settings in the clock selection register CKSC Clock timer functions Interval time e Selectable from the seven settings shown in the table below Clock timer size e 15 bit Clock supply Oscillation stabilization delay timer for sub clock and watchdog timer Source clock Sub oscillation clock divided by four SCLK Sub clock Interrupts Interval time overflow EI OS support e Not supported by the extended intelligent I O service EIOS Clock timer interval times Sub Clock Period Interval Time 29 SCLK approx 62 5 ms 2 SCLK approx 125 0 ms 2 SCLK approx 250 0 ms SCLK 122 us 212 5 approx 500 0 ms 2 3 SCLK approx 1 0 s 2 4 SCLK approx 2 0 s 216 SCLK approx 4 0 s SCLK Sub clock frequency The values enclosed in are the times for a sub clock frequency of 8 192 kHz Note that the sub oscillation clock is divided by four to generate the sub clock frequency The sub oscillation clock operates at 32 768 kHz Clock periods generated by clock timer Clock Supply Clock Period Oscillation stabilization delay timer 14 for sub clock 214 SCLK approx 2 0 s 210 SCLK approx 125 0 ms 2 3 SCLK approx 1 0 s Watchdog timer 2 4 SCLK approx 2 0 s 216 SCLK approx 4 0 s SCLK Sub clock frequency The values enclosed in are the times for a sub cl
64. m runaway The watchdog timer is a 2 bit counter that counts the clock signal from the timebase timer or clock timer Once started the watchdog timer must be cleared before the 2 bit counter overflows If an overflow occurs the CPU is reset Interval time for the watchdog timer HCLK Oscillation Clock 4 MHz SCLK Sub Clock 8 192 kHz Min Approx 3 58 ms Approx 14 33 ms Max Approx 4 61 ms Approx 18 30 ms Clock Period 21 211 HCLK 216 213 HCLK Clock Period Approx 0 438 s Approx 0 563 s 212 22 SCLK Approx 3 500 s Approx 4 500 s 215 212 SCLK Approx 57 23 ms Approx 73 73 ms 218 215 HCLK Approx 7 000 s Approx 9 000 216 213 SCLK Approx 458 75 ms Approx 589 82 ms 2 218 HCLK Approx 14 00 s Approx 18 00 217 214 SCLK The difference between the maximum and minimum watchdog timer interval times is due to the timing when the counter is cleared As the watchdog timer is a 2 bit counter that counts the carry up signal from the timebase timer or clock timer clearing the timebase timer when operating on HCLK or the clock timer when operating on SCLK lengthens the time until the watchdog timer reset is generated Watchdog timer count clock HCLK Oscillation clock WTC WDCS PCLK PLL clock SCLK Sub clock Count the clock timer output 1 Count the clock timer output Count t
65. me base timer mode SPL 1 clock mode SPL 1 and hardware standby mode MB90520A 520B Series P90 to 97 Standby control Controls stop mode SPL 1 time base timer mode SPL 1 clock mode SPL 1 Internal data bus PDR Port data register PDR read Segment pin output approval LCD Segment output and hardware standby mode Standby control SPL 1 35 90520 520 Series 2 Timebase Timer The timebase timer is an 18 bit freerun timer timebase timer counter that counts up synchronized with the main clock oscillation clock HCLK divided by 2 The timer can generate interrupt requests at a specified interval with four different interval time settings available Thetimer supplies the operating clock for peripheral functions including the oscillation stabilization delay timer and watchdog timer Timebase timer interval settings Internal Count Clock Period Interval Time 212 2 HCLK approx 1 024 ms 2 HCLK 0 5 us approx 4 096 ms 216 approx 16 384 ms 2 9 HCLK approx 131 072 ms HCLK Oscillation clock frequency The values enclosed in indicate the times for a clock frequency of 4 MHz Period of clocks supplied from timebase timer Peripheral Function Clock Period 210 approx 0 256 ms Oscillation stabilization delay 2 HCLK approx 2 0
66. me potential are connected together in the internal device design so as to prevent misoperation such as latch up connecting all Vcc and Vss pins appropriately minimizes unwanted radiation prevents misoperation of strobe signals due to increases in the ground level and keeps the overall output current rating Also ensure that the impedance of the Vcc and Vss connections to the power supply are as low as possible 18 90520 520 Series Connection of a bypass capacitor of approximately 0 1 uF between Vcc and Vss is recommended to prevent power supply noise Connect the capacitor close to the Vcc and Vss pins Crystal oscillator circuit Noise on the and X1 pins can be a cause of device misoperation Place the and pins crystal oscillator or ceramic oscillator and bypass capacitor to ground as close together as possible Also design the circuit board so that the 0 and X1 pin wiring does not cross other wiring Surrounding the 0 1 and XOA X1A pins with ground in the printed circuit board design is recommended to ensure stable operation Notes on using an external clock When using an external clock drive the pin only and leave the X1 pin open The figure below shows an example of how to use an external clock Example of how to use an external clock Open circuit FIL X0 X1 MB90520A 520B series Precautions when not using sub clock mode Connect an os
67. n event output is enabled for output compare unit 0 General purpose I O port Only available when waveform output from PG00 is disabled Output pin for 8 16 bit PPG timer 0 Only available when waveform output is enabled for PGOO 1 120 05 2 FPT 120P M13 General purpose port Only available when waveform output from PG01 is disabled Output pin for 8 16 bit PPG timer 0 Only available when waveform output is enabled for PGO1 Continued 90520 520 Series LQFP 120 QFP 1207 Pin Name Circuit Type Function General purpose I O ports Only available when waveform outputs from PG10 and PG11 are disabled The settings in the pull up resistor setup register RDR4 are enabled when ports are set as inputs The settings are ignored when ports are set as outputs Output pins for 8 16 bit PPG timer 1 Only available when waveform output is enabled for PG10 and PG11 General purpose I O port The settings in the pull up resistor setup register RDR4 are enabled when ports are set as inputs The RDR4 settings are ignored when ports are set as outputs UART SCI serial data input pin Input operates continuously when the UART is performing input Accordingly output to the pin from other functions that share this pin must be suspended unless performed intentionally General purpose I O port The settings in the pull up resistor setup regist
68. ne clock range is 4 MHz to 16 MHz PACKAGES 120 pin Plastic LQFP 120 pin Plastic QFP Continued FPT 120P M05 FPT 120P M13 FUJITSU 90520 520 Series Continued Sub clock 32 768 KHz operation available Minimum instruction execution time 62 5 ns for oscillation 4 MHz PLL clock setting x4 Vcc 5 0 V 16MB CPU memory space Internal 24 bit addressing Instruction set optimized for controller applications Rich data types bit byte word long word Extended addressing modes 23 types Enhanced signed multiplication and division instructions and RETI instruction Enhanced calculation precision using a 32 bit accumulator Instruction set designed for high level language C and multi tasking System stack pointer Enhanced pointer indirect instructions and barrel shift instructions Faster execution speed 4 byte instruction queue ROM mirror function 48 Kbytes of bank FF is mirrored in bank 00 Program patch function An address match detection function 2 x addresses Interrupt function 32 programmable interrupts with 8 levels Automatic data transmission function independent of CPU operation Extended intelligent I O service function 2 5 Up to 16 channels Low power consumption stand by modes Sleep mode CPU operating clock stops peripherals continue to operate Pseudo clock mode Only oscillation clock and timebase timer continue to operate Clock mode Main oscillati
69. ng flash memory MB90F523B For Vcc 5 internalfrequency 16 MHz sleep mode MB90522A 523A MB90F523B 522B 523B For Vcc 5 internalfrequency 8 MHz sleep mode MB90522A 523A MB90F523B 522B 523B For Vcc 5 internalfrequency 8 kHz sub clock mode 25 MB90522A 523A 522B 523B MB90F523B Continued 79 90520 520 Series Continued AVcc Vcc 5 0 V 10 AVss Vss DVss 0 0 V Ta 40 C to 85 C Parameter Pin Name Condition For Vcc 5 V internalfrequency 8 kHz sub sleep mode 25 Power supply For Voc 5 current internalfrequency 8 kHz clock mode 25 Sleep mode 25 Other than AVcc AVss C Vcc and Vss V0 V1 V1 V2 V2 V3 Input capacitance LCD divider resistor Output impedance for COMO to COMO to V1 to V3 5 0 V Output impedance for to 5 00 to SEG31 SEG31 to V3 COMO to SEGOO to SEG31 Current values are provisional and are subject to change without notice to allow for improvements to the char acteristics The power supply current is measured with an external clock leak current 80 MB90520A 520B Series 4 Characteristics 1 Reset and Hardware Standby Input Timings
70. ng or falling edge on the BIN pin and counts up or counts down Similarly reads the BIN pin input level on detect ing a rising or falling edge on the AIN pin and counts up or counts down Counter clear function Gate function 16 bit x 1 channel mode Timer mode 2 0 4 6 Machine clock frequency Up down count mode Phase difference count mode multiply by 2 Counts up on detecting speci fied edge on the AIN pin Counts down on detecting spec ified edge on the BIN pin Reads the AIN pin input level on detecting a rising or falling edge on the BIN pin and counts up or counts down Counter clear function Gate function Counter clear function Gate function Phase difference count mode multiply by 4 Reads the AIN pin input level on detecting a rising or falling edge on the BIN pin and counts up or counts down Similarly reads the BIN pin input level on detect ing a rising or falling edge on the AIN pin and counts up or counts down Counter clear function Gate function Other Functions Compare function Reload function Compare reload function Compare reload prohibit The direction of the previous count can be determined from the up down flag e Interrupt requests can be generated on the following conditions 1 Compare match 2 Underflow or overflow 3 Count direction change 49 90520 520 Series Block dia
71. ock frequency of 8 192 kHz Note that the sub oscillation clock is divided by four to generate the sub clock frequency The sub oscillation clock operates at 32 768 kHz 65 66 90520 520 Series Block diagram To watchdog timer Clock timer counter As imas eds OF Power on reset Counter Change to hardware standby mode clear circuit To oscillation stabilization Change to stop mode delay timer for sub clock Interval timer selector uL wpcs 506 WTIE WTOF WTR WTC2 WTC1 WTCO Clock timer control register WTC Clock timer interrupt Overflow SCLK Sub clock frequency MB90520A 520B Series 16 LCD Controller Driver The LCD controller driver can drive an LCD Liquid Crystal Display directly The LCD is driven by 4 common outputs and 32 segment outputs The output mode can be set to 1 2 1 3 or 1 4 duty LCD controller driver functions Divider resistor for LCD drive power Common outputs e Either the internal resistor approx 100 or an externally connected resistor can be selected e Max 4 outputs The corresponding pins cannot be used as ports when using an LCD Segment outputs e 32 outputs of these 24 pins can be used as I O ports in blocks of 8 pins Display data memory 16 bytes of RAM for internal dis
72. on clock stops sub clock and clock timer continue to operate Stop mode Main oscillation and sub clock both stop CPU intermittent operation mode Hardware stand by mode Change to stop mpde by operating hardware stand by pins Process CMOS technology ports General purpose ports CMOS input output 53 ports General purpose ports inputs with pull up resistors 24 ports General purpose I O ports Nch open drain outputs 8 ports Timers Timebase timer clock timer watchdog timer 1 channel each 8 16 timers 0 and 1 8 bit x 2 channels or 16 bit x 1 channel 16 bit reload timers 0 and 1 2 channels 16 bit timers 16 bit free run timers 0 and 1 2 channels 16 bit input capture 0 2 channels 2 channels per unit 16 bit output compare 0 and 1 8 channels 4 channels per unit 8 16 bit up down counter timers 0 and 1 8 bit x 2 channels or 16 bit x 1 channel Clock output function 1 channel Communications macro communication interface Extended I O serial interfaces 0 and 1 2 channels UART full duplex double buffered SCI Can also be used for synchronous serial transfer 1 channel MB90520A 520B Series External event interrupt control function DTP external interrupts 8 channels Can be set to detect rising edges falling edges levels or L levels Wake up interrupts 8 channels Detects 1 levels only Delayed interrupt generation module 1 channel for task switc
73. ounter timer 0 Extended serial interface 1 53 P54 DAO DA1 8 bit D A converter P60 67 ANO TINO OUTA TOTO OUT5 TIN1 OUT6 TOT1 OUT7 P70 P73 8 16 bit A D converter 16 bit reload timers 0 1 Output compare unit 1 P74 P77 COMO LCD control driver common output P80 P87 SEG16 SEG23 LCD control driver segment output P90 P97 SEG24 SEG31 LCD control driver segment output SEG8 SEG15 Notes LCD control driver segment output Port 9 contains general purpose ports with N ch open drain output circuits Connect an external pull up resistor when using port 9 pins as outputs Port 6 shares pins with the analog inputs When using port 6 as a general purpose port ensure that the corresponding analog input enable register ADER bits are set to 0 ADER is initialized to after a reset 30 MB90520A 520B Series Block diagrams 00 to 7 P10 to P17 Pull up resistor option connect disconnect setting Peripheral function input PDR Port data register read Internal data bus DDR write Standby control Controls stop mode SPL 1 time base timer mode SPL 1 clock mode SPL 1 and hardware standby mode Standby control SPL 1 P20 to P27 Peripheral function input PDR Por
74. play are provided Duty 1 2 1 3 or 1 4 can be selected Bias 1 3 only supported Drive clock Interrupts Either the oscillation clock HCLK or sub clock SCLK can be used e None EI OS support e Not supported by the extended intelligent I O service El2OS Bias ET and common output combinations 1 2 Duty Output Mode 1 3 Duty Output Mode 1 4 Duty Output Mode 1 3 bias COMO and COM outputs COMO to COM2 outputs COMO to outputs used used used 67 68 90520 520 Series Block diagram Common pin selection register LCDCMR LCDC control register 0 Internal il divider resistor Timing controller Prescaler Common EN driver Internal data bus AC conversion circuit Display data memory 16 bytes LCDC control register 1 LCR1 Controller Undefined bit HCLK Main clock Driver SCLK Sub clock V1 v2 v3 COMO COMI COM2 5 0 SEG1 SEG2 SEG29 SEG30 SEG31 MB90520A 520B Series 17 Communications Prescaler Supplies the clock to the dedicated baud rate generator used by the UART SCI and extended serial interfaces By dividing the machine clock to produce the clock supply to the dedicated baud rate generator the baud rate can be specified independently of the machine clock speed The communications
75. prescaler can divide the machine clock frequency by the following seven ratios to generate the clock supply to the dedicated baud rate generator and extended serial interface 9 2 0 3 9 4 0 5 9 6 0 7 4 8 Communications prescaler functions Function e Dedicated baud rate generator for the UART and the extended I O serial interface However the same clock is supplied to both peripherals Divided clock frequency 0 2 0 3 0 4 0 5 0 6 7 8 Machine clock frequency Clock supply Interrupts e None 5 support e Not supported by the extended intelligent I O service EIOS Note Asthe same output from the communications prescaler is supplied to both the UART 8 and the extended I O serial interface the transfer clock speed settings must be revised if the communications prescaler settings are changed Block diagram CDCR DIV3 DIV2 DIV1 DIVO Extended serial I O SMCS SMD2 SMDO 0008 1008 Communications prescaler SMR CS2 C50 0008 1005 UART Undefined Machine clock frequency 69 90520 520 Series 18 Address Match Detection Function fthe program address during program execution matches the value set in one of the detection address setting registers PADR the address match detection function replaces the instruction being executed with the INT9 instruction and executes the interrupt
76. pt circuit Continued MB90520A 520B Series LQFP 120 Pin Name QFP 120 2 Circuit Type Function General purpose I O port External trigger input to the 8 10 bit A D converter Input operates continuously when the 8 10 bit A D converter is performing input Accordingly output to the pin from other functions that share this pin must be suspended unless performed intentionally General purpose I O port General purpose I O port Output pin for clock monitor function The clock monitor is output when clock monitor output is enabled General purpose I O port Only available when waveform output from output compare 0 is disabled Event output pin for ch 0 of output compare unit 0 OCU Only available when event output is enabled for output compare unit 0 General purpose I O port Only available when waveform output from output compare 1 is disabled Event output pin for ch 1 of output compare unit 0 OCU Only available when event output is enabled for output compare unit 0 General purpose I O port Only available when waveform output from output compare 2 is disabled Event output pin for ch 2 of output compare unit 0 OCU Only available when event output is enabled for output compare unit 0 General purpose I O port Only available when waveform output from output compare 3 is disabled Event output pin for ch 3 of output compare unit 0 OCU Only available whe
77. r Underflow PCNT1 Ree PPG10 PPG1 underflow PPG output control circuit lt to PPGO MDO PPG11 PPGO underflow 5 from PPGO Timebase timer output HCLK 512 Peripheral clock 1 Peripheral clock 0 2 Peripheral clock 0 4 Peripheral clock 6 8 Peripheral clock 0 16 clock selector roses romeo orev er 01 output control register PPGOE signal Undefined Reserved Reserved bit HCLK Oscillation clock frequency Machine clock frequency 43 90520 520 Series 5 16 bit Reload Timers 0 and 1 With Event Count Function The 16 bit reload timers have the following functions The count clock can be selected from three internal clock and the external event clock Either software trigger or external trigger can be selected as the start signals for 16 bit reload timers 0 and 1 An interrupt to the CPU can be generated when an underflow occurs on 16 bit reload timer 0 1 This interrupt allows the timers to be used as interval timers Two different operation modes can be selected when an underflow occurs on 16 bit reload timer 0 1 one shot mode in which timer operation halts when an underflow occurs or reload mode in which the reload register value is loaded into the timer and counting continues Extended intelligent I O service 2 5 is supported The MB90520A 520B series con
78. remental conversion mode A D conversion is performed for one channel then halts until the next trigger After conver sion is performed for the end channel the next conversion is performed for the start chan nel and repeated this operation 61 62 90520 520 Series Block diagram gt Interrupt request output A D control status register ADCS Re BUSY INT INTE PAUS STS1 STSO STATIserveg MD1 MDO ANS2 JANS1 ANSO ANE2 JANE Amm Am 2 6 ADTG Trigger 2 Comparator Sample 8 p hold circuit Control circuit 5 channel AN3 1 selector AN2 AN1 AVRH AVRL ANO D A converter 55 PI Gate Cr od bcm pa oe os oa oe or ook TO Internal timer output Undefined Reserved Always set to 0 Machine clock Internal data bus MB90520A 520B Series 14 8 bit D A Converter The 8 bit D A converter performs R 2R D A conversion with 8 bit resolution Two D A converter channels with independent analog outputs are provided D A converter functions eThe settling time is 12 5 us This is independent of the machine clock D A conversion time Conversion method e R 2R conversion Resolution 8 bit Analog output pins Two output pins are provided Both pins can b
79. rforming synchronous or asyn chronous communications with external devices The interface provides bi directional communications in both clock synchronous and clock asynchronous modes Includes a master slave communication function multi processor mode Can generate interrupt requests at receive complete receive error detected and transmit complete timings Also supports El2OS UART SCI functions Data buffer Full duplex double buffered Transmission modes Clock synchronous with no start stop bit no parity bit e Clock asynchronous start stop sync Baud rate Can use dedicated baud rate generator Can use external clock input Can use clock supplied 16 bit reload timer 0 For machine clock speeds of 6 MHz 8 MHz 10 MHz 12 MHz and 16 MHz Available speeds for asynchronous communications 31250 bps 9615 bps 4808 bps 2404 bps and 1202 bps Available speeds for synchronous communications 1 Mbps 500 Kbps 250 Kbps 125 Kbps and 62 5 Kbps Number of data bits 7 bits when parity is used for asynchronous normal mode 8 bits when parity is not used Signal format Receive error detection Non return to zero NRZ format Framing errors not available in clock synchronous mode Overrun errors Parity errors not available in clock synchronous mode and multi processor mode Interrupt requests Receive interrupt Receive complete or receiv
80. s External reset input pin Hardware standby input pin General purpose ports The settings in the pull up resistor setup register RDRO are enabled when ports are set as inputs The RDRO settings are ignored when ports are set as outputs Event input pins for 0 to ch 6 of the DTP external interrupt circuit General purpose I O port The settings in the pull up resistor setup register RDRO are enabled when ports are set as inputs The RDRO settings are ignored when ports are set as outputs General purpose ports The settings in the pull up resistor setup register RDR1 are enabled when ports are set as inputs The settings are ignored when ports are set as outputs Event input pins for the wakeup interrupts General purpose ports Trigger input pins for input capture units ICU 0 and 1 Input operates continuously when channels 0 and 1 of input capture units ICU 0 and 1 are operating Accordingly output to the pins from other func tions that share this pin must be suspended unless performed intentionally General purpose I O port Also can be used as the count clock A input to 8 16 bit up down counter timer O General purpose I O port Also can be used as the count clock B input to 8 16 bit up down counter timer 0 General purpose I O port Also can be used as the control clock Z input to 8 16 bit up down counter timer 0 Event input pin for ch 7 of the DTP external interru
81. s for the LCD controller driver 8 54 94 Vcc Power supply input pins for the digital circuit 33 63 91 119 GND level power supply input pins for the digital circuit 42 Power supply input for the analog circuit Ensure that a voltage greater than AVcc is applied to Vcc before turning the analog power supply on or off H reference voltage for the A D converter Ensure that a voltage greater than AVRH is applied to AVcc before turning the power supply to this pin on or off L reference voltage for the A D converter GND level power supply input pin for the analog circuit H reference voltage for the D A converter Ensure that this voltage does not exceed Vcc 1 FPT 120P M05 2 FPT 120P M13 L reference voltage for the D A converter Apply the same voltage level as Vss 13 14 90520 520 Series I O CIRCUIT High speed oscillation feedback gt gt Clock input Standby control signal gt gt Clock input Standby control signal resistor Approx 1 Low speed oscillation feedback resistor Approx 10 R gt Hysteresis input Hysteresis input Pull up connect disconnect selection Digital output er Digital output Hysteresis input 10 4 mA Standby control Selectable pul
82. st from channel 1 s r lt gt Interrupt request Sc Counter control register 1 CCR1 H Pins and interrupt numbers 8 16 bit up down counter timer 0 AINO pin P24 AINO BINO pin P25 BINO ZINO pin P26 ZINO Compare match interrupt number 421 15 Interrupt number for underflow overflow interrupt count direction change interrupt 2 161 8 16 bit up down counter timer 1 AIN1 pin P50 AIN1 BIN1 pin P51 BIN1 ZIN1 pin P52 ZIN1 Compare match interrupt number 429 10 Interrupt number for underflow overflow interrupt count direction change interrupt 3 1 51 90520 520 Series 8 Extended I O Serial Interfaces 0 and 1 The extended I O serial interfaces are serial I O interfaces that perform clock synchronized data transfer The MB90520A 520B series contain two internal extended I O serial interface channels Either LSB first or MSB first data transmission format can be selected Extended serial interface functions Transmission direction Transmission mode e Transmit and receive can be handled simultaneously A setting is required to select transmit or receive Clock synchronous data transfer only Transmission clock Internal shift clock mode Uses the communications prescaler output clock e External shift clock mode Inputs the clock signal from SCK1 and SCK2 Transmission spee
83. ster PDR read e 2 o CRIORGUAGUREGNATUA RARER RAR RAR OA DR BU EURO CRUS nro Du E MEME Direction latch Nch DDR write 777 1 Standby control SPL 1 DDR read Standby control Controls stop mode SPL 1 time base timer mode SPL 1 clock mode SPL 1 and hardware standby mode P74 to P77 Common pin output approval LCD common output PDR Port data register 777 5 c FH gt fro 3 a gO Pin Direction latch Nch DDR write Standby control SPL 1 DDR read ee S CAM AD CD EE Standby control Controls stop mode SPL 1 time base timer mode SPL 1 clock mode SPL 1 and hardware standby mode 33 90520 520 Series P60 to 67 Analog input Internal data bus Standby control SPL 1 Standby control Controls stop mode SPL 1 time base timer mode SPL 1 clock mode SPL 1 and hardware standby mode 34 P80 to P87 to PA7 Segment pin output approval LCD Segment output a 0 I g t D SER Direction latch Nch DDR write U 777 Standby control SPL 1 DDR read Standby control Controls stop mode SPL 1 ti
84. t data register read Internal data bus 777 Standby control SPL 1 Standby control Controls stop mode SPL 1 time base timer mode SPL 1 clock mode SPL 1 and hardware standby mode 31 32 90520 520 Series P40 to P47 Pull up resistor option connect Peripheral function input disconnect setting PDR Port data register Peripheral function output approval PDR read Internal data bus Standby control Controls stop mode SPL 1 time base timer mode SPL 1 clock mode SPL 1 and hardware standby mode Peripheral function is equivalent to of peripheral function P30 to P37 P50 to P52 P70 to P73 Peripheral function input PDR Port data register Peripheral function output Peripheral function output approval Direction latch Internal data bus DDR write Standby control SPL 1 DDR read Standby control Controls stop mode SPL 1 time base timer mode SPL 1 clock mode SPL 1 and hardware standby mode Peripheral function is equivalent to of peripheral function MB90520A 520B Series 53 54 D A analog pin output approval D A analog output PDR Port data regi
85. t voltage to P97 All output pins other than P90 Vcc 4 5 V lou 2 0 mA L level output voltage All output pins Vcc 4 5 V lo 2 0 mA Input leak current to P97 Open drain output leak current P90 to P97 output pins All output pins other than P90 Vcc 5 5 V Vss Vi Vcc to P07 Pull up P10 to P17 resistor P40 to P47 MDO MD1 Pull down resistor Power supply current For Vcc 5 V internal frequency 16 MHz normal operation MB90522A 523A MB90F523B MB90522B 523B Continued MB90520A 520B Series Parameter Power supply current AVcc Voc 5 0 V 10 AVss Vss DVss 0 0 V Ta 40 C to 85 Pin Name Condition For Vcc 5 internalfrequency 8 MHz normal operation MB90522A 523A MB90F523B MB90522B 523B For 5 internalfrequency 16 MHz A D operation progress MB90522A 523A MB90F523B MB90522B 523B For Vcc 5 V internalfrequency 8 MHz A D operation in progress MB90522A 523A MB90F523B MB90522B 523B For Vcc 5 internalfrequency 16 MHz D A operation in progress MB90522A 523A MB90F523B MB90522B 523B For Vcc 5 V internalfrequency 8 MHz D A operation progress MB90522A 523A MB90F523B MB90522B 523B Writing or erasi
86. tains two 16 bit reload timer channels 16 bit reload timer operation modes Count Clock Internal clock 3 clocks available Start Trigger Software trigger Operation when an Underflow Occurs One shot mode Reload mode External trigger One shot mode Reload mode Event clock Software trigger External trigger Interval times for the 16 bit reload timers Count Clock Internal clock Count Clock Period 21 0 125 us One shot mode Reload mode One shot mode Reload mode Example Interval Times 0 125 us to 8 192 ms 23 0 5 us 0 5 us to 32 768 ms 25T 2 0 us 2 0 us to 131 1 ms Event clock 23 or longer 0 5 us or longer Note The values enclosed in and the example interval times are for a machine clock frequency of 16 MHz T is the machine cycle and is 1 machine clock frequency 44 MB90520A 520B Series Block diagram Internal data bus 16 bit reload register Reload signal Reload control circuit 16 bit timer register Clock pulse detection circuit Wait signal Output to internal peripheral functions Clear trigger GLK 22 Output signal Clock Di generation selector 1 circuit External clock EEE Select signal Internal clock control circuit Operation control circuit
87. ter Port 6 A D converter 111111118 00001 00001Du OCU compare register ch 5 16 bit timer 00001 Access prohibited 00001Fu Wakeup interrupt enable register Wakeup interrupts 000000008 Continued Address 000020 Abbreviated Register Name MB90520A 520B Series Register Name Serial mode register 000021u 000022u Serial control register Serial input data register Serial output data register 000023u Serial status register Peripheral Name Initial Value 00000000 0000010 0s 00001 00 000024 000025 Serial mode control status register 1 000026u Serial data register 1 Extended I O serial interface 1 XXXX 000 0s 0000001 0s 000027u 000028u 000029u Communication prescaler control register Serial mode control status register 2 00002 Serial data register 2 Communication prescaler register Extended serial interface 2 OXXX 111 15 XXXX 000 0s 0000001 0s 00002Bu Access prohibited 00002 00002Du 00002 00002 OCU control status register ch 45 OCU control status register ch 67 16 bit timer 0000 00 00000 0000 00 00000 000030 DTP interrupt enable re
88. timers Number of channels 1 Can be used in 2 x 8 bit channel mode Can generate a pulse waveform output with specified period and 0 to 10095 duty ratio Number of channels 1 Can be used in 2 x 8 bit channel mode External event inputs 6 channels Reload compare function 8 bit x 2 channels Clock monitor Clock output frequency Machine clock 2 to machine clock 23 Delayed interrupt generation module Interrupt generation module for task switching Used by REALOS DTP External interrupts Input channels 8 Generates interrupts to the CPU on rising edges falling edges with input H level or L level Can be used for external event interrupts and to activate El2OS Wakeup interrupts Input channels 8 Triggered by L level 8 10 bit A D converter successive approximation type 8 bit D A converter R 2R type Number of channels 8 Resolution 8 bit or 10 bit selectable Conversion can be performed sequentially for multiple consecutive channels Single shot conversion mode Converts specified channel once only Continuous conversion mode Repeatedly converts specified channel Intermittent conversion mode Converts specified channel then halts temporarily Number of channels 2 Resolution 8 bit UART SCI Number of channels 1 Clock synchronous transfer 62 5 Kbps to 1 Mbps Clock asynchronous transfer 1202 bps to 31250 bps Supports bi directional and m
89. tion change 4 0000 5 8 16 bit PPG timer 1 counter borrow DTP6 DTP7 external interrupt 6 external interrupt 7 Output compare 1 OCU ch 4 ch 5 match FFFF9CH 8 Clock timer FFFF944 0000 6 0000B7 Output compare 1 OCU ch 6 ch 7 match FFFF90 16 bit freerun timer 1 overflow 0000B8 8 16 bit up down counter timer 1 compare match 88 8 16 bit up down counter timer 1 overflow up down direction change 4 0000B9 Input capture 0 ICU capture FFFF804 Input capture 1 ICU capture FFFF7C 0000 Output compare 0 ch 0 match 78 Output compare 0 OCU ch 1 match FFFF744 0000 Priority Continued Continued MB90520A 520B Series EOS Interrupt Vector Interrupt Control Register Bu oe Support No Address ICR Address 10 Output compare 0 2 match FFFF70 Output compare 0 OCU ch 3 match 0000 UART SCI receive complete 16 bit reload timer 0 FFFF68 FFFF64 0000BDu UART SCI send complete FFFF60 16 bit reload timer 1 FFFF5Cu 0000 Flash memory FFFF58x Delayed interrupt generation module Supported X Not supported Supported includes El2OS stop function FFF
90. to P87 SEG16 to SEG23 P90 P91 to P97 SEG24 SEG25 to SEG31 General purpose ports Only available when the LCD controller driver control register is set to the ports LCD segment output pins for the LCD controller driver Only available when the LCD controller driver control register is set to the segment outputs General purpose ports Support up to lo 10 mA Only available when the LCD controller driver control register is set to the ports LCD segment output pins for the LCD controller driver Only available when the LCD controller driver control register is set to the segment outputs 17 to 24 SEGO to SEG7 LCD segment 00 to 07 pins for the LCD controller driver 25 to 32 PAO to PA7 to SEG15 1 120 05 2 FPT 120P M13 12 General purpose ports Only available when the LCD controller driver control register is set up to the ports LCD segment 08 to 15 pins for the LCD controller driver Only available when the LCD controller driver control register is set to the segment outputs Continued MB90520A 520B Series Continued LQFP 120 QFP 120 2 Pin Name Circuit Type Function 34 C Capacitor connection pin for stabilizing power supply Connect an external ceramic capacitor of approximately 0 1 uF If operat ing at 3 3 V or lower connect to Vcc 82 to 85 VO to V3 Power supply input pin
91. utput common output CMOS hysteresis input CMOS level output Also used as segment output pin With standby control only available when segment output is not operating Vcc Pch r Open drain rz vss lo 10 mA MW Ju gt Hysteresis input Standby control Segment output CMOS hysteresis input N ch open drain output Also used as segment output pin With standby control only available when segment output is not operaing Reference voltage pin for LCD controller 90520 520 Series HANDLING DEVICES Take note of the following points when handling devices Do not exceed maximum rated voltage to prevent latch up Supply voltage stability Power on precautions Power supply pins Crystal oscillator circuit Notes on using an external clock Precautions when not using sub clock mode Treatment of unused pins Treatment of N C pins Treatment of pins when A D converter is not used Sequence for connecting and disconnecting the A D converter power supply and analog input pins Shared use of general purpose ports and LCD controller driver SEG COM pins Conditions when output from ports 0 and 1 is undefined Initialization Notes on using the DIV A Ri and DIVW A RWi instructions Notes on using REALOS Device Handling Precautions Do not exceed maximum rated voltage to prevent latch up Latch up occurs in CMOS ICs if a voltage greater t

Download Pdf Manuals

image

Related Search

FUJITSU SEMICONDUCTOR MB90520A/520B Series handbook

Related Contents

    ASRock X58 SuperComputer motherboard Manual      Canon EOS 40Dcamera Manual          

Copyright © All rights reserved.
DMCA: DMCA_mwitty#outlook.com.