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FUJITSU SEMICONDUCTOR MB90495G Series handbook

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1. E Level Level i ui edge edge INT7 selector selector Ex Level Level i edge edge INT6 selector selector m Level m Level E i m edge edge INT5 selector selector 8 Ej o Bin Level INT4 selector selector DTP external interrupt input detection circuit ER4IER3 Eno DTP external interrupt condition register EIRR Interrupt request Interrupt request signal signal DTP external interrupt enable register ENIR 51 52 MB90495G Series sn 10 8 10 bit A D Converter The 8 10 bit A D converter converts analog voltage to 8 or 10 bit digital values by means of RC successive approximation conversion The input signal can be selected from an 8 channel analog input pin set Select a software trigger internal timer output or external trigger as the start trigger Functions of the 8 10 A D Converter Converts analog voltage input voltage input to the analog input pins to 8 bit or 10 bit digital values A D conversion The 8 10 bit A D converter has the following features Single channel A D conversion time is a minimum of 6 12 us including sampling time Single channel sampling time is a
2. 0 1 2 3 4 5 6 7 8 9 10 11 12 Ta 25 C Vcc 4 5 V Vo V 01 2 3 4 5 6 7 8 9 lo mA 10 11 12 85 MB90495G Series MB90497G lcc 25 C external clock operation f internal operation frequency 45 40 35 16 MHz 30 lt 10 MHz 20 f 8 MHz 15 19 apu ME n f 4 MHz OS MHz 0 I i i 3 0 4 0 5 0 6 0 7 0 Vcc V lccs Vcc 25 C external clock operation f internal operation frequency 16 14 f 16 MHz 12 10 10 MHz 8 1 8 MHz 6 4 a f 4 MHz Ea 0 1 1 3 0 4 0 5 0 6 0 7 0 Vcc V Continued 86 MB90495G Series Continued Ta 25 C external clock operation f internal operation frequency f 8 kHz 10 Ta 25 C external clock operation f internal operation frequency f 8 kHz V Continued 87 MB90495G Series sn
3. to to XXXXXXXXB XXXXXXXXB to 25 26 MB90495G Series Continued Register Address Abbreviation 003 48 to 003 Register Name Data register 1 Access 003 50 to 003C57u Data register 2 003 58 to 003 5 Data register 3 003 60 to 003C67u 003 68 to 003 6 Data register 4 Data register 5 003 70 to 003 77 Data register 6 003 78 to 003C7Fu Data register 7 Resource Name CAN controller Initial Value XXXXXXXXs to XXXXXXXXs to XXXXXXXXs to to to to to XXXXXXXXB 003 80 to 003CFFu system reserved area 003D00u 003001 Control status register R W 003002 003D03u Display last
4. Erase Program cycle MB90495G Series B EXAMPLE CHARACTERISTICS MB90F497G F498G lcc Vcc Ta 25 C external clock operation f internal operation frequency 45 40 f 16 MHz 30 z se 10 MHz f 8 MHz 20 15 10 an IAME f 2 MHz 5 o 0 0 4 0 5 0 6 0 7 0 Ta 25 C external clock operation f internal operation frequency 16 14 12 16 MHz 10 T E 8 9 10 MHz f 8 MHz 6 f 4 MHz 2 5 MHz 0 3 0 4 0 5 0 6 0 7 0 Vcc V Continued 83 MB90495G Series sn Continued Ta 25 C external clock operation f internal operation frequency f 8 kHz uA Ta 25 C external clock operation f internal operation frequency f 8 kHz Iccus uA wo 4 0 5 0 6 0 7 0 Vcc V Continued 84 Continued Vcc mV MB90495G Series snvnw lccr 25 C external clock operation f internal operation frequency T 6 f 8 kHz 5 T 4 5 3 0 1 1 1 3 0 4 0 5 0 6 0 7 0 Vcc V Vcc loH Vo lot 25 C Vcc 4 5 V
5. 5 Ec 1 m 18 70 0 40 736 016 GF Hrm 5514 008 8 009 XL aaa heiaht NDEX Gene height O 100039 JL ood 10 20 008 0 25 2338 1 1 2050 20 010 068 UR 047 008 Stand off f UTC AUS uA La 0 10 004 2003 FUJITSU LIMITED F64013S c 5 5 Dimensions in mm inches Note The values in parentheses are reference values Continued 90 MB90495G Series snvnw Continued 64 pin plastic LQFP Note 1 These dimensions not include resin protrusion FPT 64P M09 Note 2 Pins width and pins thickness include plating thickness Note 3 Pins width do not include tie bar cutting remainder T 14 00 0 20 551 008 SQ 2 12 00 0 10 472 004 SQ 0 145 0 055 0057 0022 HRHRHRRRHHRRHRH ad O AI 0 10 004 HH Details of A part 020 r E Mo
6. 24 bit Detection address configuration register 0 24 bit Detection address configuration register 1 Comparator Internal data bus PACSR Address detection control register PACSR Reserved Make sure this is always set to 01 Re Re Re Re Re Re INT9 instruction INT9 interrupt generation Address latch Stores value of address output to internal data bus Address detection control register PACSR Set this register to enable prohibit interrupt output when an address match is detected Detection address configuration register PADRO PADR1 Configure an address with which to compare the address latch value 59 60 MB90495G Series 14 ROM Mirror Function Selection Module The ROM mirror function selection module configures ROM internal data arrayed inside bank FF to be readable by accessing bank 00 ROM Mirror Function Selection Module Block Diagram Address Internal data bus ROM mirror function selection register ROMM Fere mere e Address area Accessing Bank FF through ROM Mirror Function 004000H ROM mirror area FC0000H FE0000H FF0000H FF4000H FFFFFFH MB90V495G MB90F498G MB90F497G Bank FF MB90497G Area corresponding to ROM mirror Y Y MB90495G Series snvnw 15 512 K 1 M bit Fla
7. HAV ELAV LOdd SId vv eodd 9ld ZNW LSd SLAV EDdd ZId 9NV 9Sd 91V ONLL OZd SNV SSd A LLY OLOL LZd 81V LNLL CZd 6LW LLOL S2d ZNW 2Sd 02 2 1 184 L2W SLNI SZd ONV OSd Z2W 9LNI 9Zd ZLNI Z9d EZY ZLNI ZZd e LINI L9d oujaiiIcoleoozrerzzr xx er E o S ge EE cOGOOSS 85455 peg Eg c On aoa PE 64 09 64 09 PIN DESCRIPTION Pin Name P61 Circuit Type MB90495G Series snvrn Description General purpose I O port Functions as external interrupt input pin Set this to input port P62 INT2 General purpose I O port Functions as external interrupt input pin Set this to input port P50 to P57 to AN7 General purpose I O port Functions as analog input port of A D converter This is enabled if analog input configuration is permitted Vcc power input pin of A D converter Reference voltage input pin for the A D converter This voltage must not exceed Vcc and AVcc Reference voltage is fixed to AVss Vss power input pin of A D converter General purpose I O port Functions as external interrupt input pin Set this to input port Low speed oscillation pin Perform pull down processing if not connected to an oscillator Low speed oscillation pin Set to o
8. FUJITSU SEMICONDUCTOR 16 bit Proprietary Microcontroller CMOS F2MC 16LX MB90495G Series MB90497G F497G F498G V495G DESCRIPTION The MB90495G Series is a general purpose high performance 16 bit microcontroller It was designed for devices like consumer electronics which require high speed real time process control This series features an on chip full CAN interface In addition to being backwards compatible with the 2 family architecture the instruction set has been ex panded to add support for high level language instructions expanded addressing mode and enhanced multiply divide and bit processing instructions A 32 bit accumulator is also provided making it possible to process long word 32 bit data The MB90495G Series peripheral resources include on chip 8 10 bit A D converter UART SCI 0 1 8 16 bit PPG timer 16 bit timer 16 bit free run timer input capture 0 1 2 3 ICU and CAN controller is abbreviation for Fujitsu Flexible Microcontroller F2MC is a registered trademark of Fujitsu Limited FEATURES Models that support 125 C Clock Built in PLL clock multiplier circuit Choose 1 2 oscillation clock or x1 to x4 multiplied oscillation clock for a 4 MHz oscillation clock 4 to 16 MHz machine PLL clock Continued PACKAGES 64 pin plastic QFP 64 pin plastic LQFP 64 06 64 09 FUJITS
9. gt gt i x b ib b b b x b FFFF88 Input capture 2 load Input capture 3 load x 0000 9 Reserved Reserved 7 0000BA 7 Reserved 78 Reserved FFFF74u 0000 7 Reserved 7 16 bit reload timer 1 FFFF6CH 0000BC UART1 reception complete 8 UART1 transmission complete x x FFFF64n 0000BD 7 Priority 3 Highest Continued MB90495G Series Continued EPOS Interrupt Vector Interrupt Register Interrupt Condition P Compatible Number Address ICR Address UARTO reception complete FFFF60u 0000BE UARTO transmission complete FFFF5Cu Flash memory FFFF58x 0000 1 Delayed interrupt generation module FFFF54u Lowest O Available x Not available Available EI OS halt function supplied A Available for interrupt conditions not shared by ICR 1 The interrupt level is the same for peripheral devices sharing the ICR register Peripheral devices that share the ICR register and use the extended intelligent I O service only utilize one set If one side of a peripheral device sharing the ICR register is set to extended intelligent I O service the other side cannot use interrupts 2 Only the 16 bit reload timer is compatibl
10. Vrst Vor 1LSB 1022 V Vor Voltage for transition from digital output 000 to 001 Vest Voltage for transition from digital output to 3FFu 7 Notes on Using A D Converter Select the output impedance value for the external circuit of analog input according to the following conditions External circuit output impedance values of about 5 or lower are recommended If external capacitors are used a capacitance of several thousand times the internal capacitor value is recom mended in order to minimize the effect of voltage distribution between the external and internal capacitor If the output impedance of the external circuit is too high the sampling time for analog voltages may not be sufficient sampling period 2 00 us machine clock of 16 MHz Model Analog Input Circuit Analog input R d MB90F497G MB90F498G MB90V495G R 3 2 Cz 30 pF MB90497G R 2 6 28 pF Note The figures given here are the suggested values About Error The smaller the absolute value of AVR AVss the greater the relative error 81 MB90495G Series 82 8 Flash Memory Program Erase Characteristics Parameter Condition Remarks Excludes 00H programming prior erasure Sector erase time Ta 25 C Excludes 00H programming prior Chip erare time Vcc 5 0 V erasure Word 16 bit width programming time Excludes system level overhead
11. 000012 Port 2 direction register R W 000000005 000013 000014 Port 3 direction register Port 4 direction register R W R W 000000005 XXX 0 0 0 0 Os 000015 Port 5 direction register R W 000000005 000016 Port 6 direction register R W XXXX 0 0 0 05 000017 to 00001 system reserved area 00001Bu Analog input enable register R W 8 10 bit A D converter 111111118 00001 to 00001Fu 000020 SMRO system reserved area Serial mode register 0 0000214 SCRO Serial control register 0 000022 SIDRO SODRO Serial input data register 0 Serial output data register 0 000023 SSRO Serial status register 0 0000244 CDCRO Communication prescaler control register 0 000025 5 50 Serial edge selection register 0 000000005 000001005 0001 05 0 XXX 111 18 XXXXXXX 08 000026 SMR1 Serial mode register 1 0000274 SCR1 Serial control register 1 0000284 SIDR1 SODR1 Serial input data register 1 Serial output data register 1 000000005 000001005 Continued Continued Address 000029 Register Abbreviation Register Name Serial status register 1 MB90495G Series Access R W Resource Name Initial Value 000010008 00002
12. 78 MB90495G Series snvnw 5 A D Converter Vcc AVcc 5 0 Vt54 Vss AVss 0 0 V 3 0 V lt AVR AVss Ta 40 C to 125 C Vcc AVcc 5 0 V 10 Vss AVss 0 0 V 3 0 V lt AVR AVss Ta 40 C to 105 C Parameter Pin Name Resolution Total error Nonlinearity error Differential linearity error Zero transition voltage ANO to AN7 1 LSB AVR 1024 Full scale transition voltage ANO to AN7 Conversion time 66 tcp Machineclock Sampling period 32 top of 16 MHz Analog port input current ANO to Analog input voltage ANO to AN7 AVss Reference voltage AVR AVss 3 0 AVcc AVcc Power supply current Reference voltage supply AVR current AVR Inter channel variation ANO to AN7 Current Vcc AVcc AVR 5 0 V when A D converter is not operating and CPU is halted 79 MB90495G Series 6 A D Converter Glossary Resolution Analog changes that are identifiable with the A D converter Linearity error The deviation of the straight line connecting the zero transition point 00 0000 0000 00 0000 0001 with the full scale transition point 11 1111 1110 lt 11 1111 1111 from actual conversion characteristics Differentiallinearity error The deviation of input voltage needed to change the output code by 1 LSB from the ideal value Total error The difference between the a
13. 3 tcr 2 20 5 tce 2 60 RD valid data input RD AD15 to ADOO 2 60 RD f data hold time RD AD15 to ADOO 0 RD 4 gt ALE T time RD ALE 16 2 15 RD f address valid time RD A23 to A16 16 2 10 Valid address CLK T time RD J gt CLKT time A23 to A16 AD15 to ADOO CLK tcp 2 20 tcp 2 20 ALE 4 2 RD J time 16 2 15 MB90495G Series snvnw Bus read timing CLK tAVLL HILLAX 24 V ALE 0 8V tAVRL gt lt tRLRH 2 4V RD 0 8V A23 to A16 lt 24V 0 8 Vcc 0 8 Vcc AD15 to ADOO Address 0 8V 0 2 Vcc 0 2 Vcc 73 MB90495G Series 6 Bus Write Timing Vcc 5 0 1096 Vss 0 0 V Ta 40 C to 105 C Parameter Pin Name Remarks A23 to A16 Valid Address WR J time AD15 to ADOO WR 15 WR pulse width WR 3 tce 2 20 Valid data output gt WR T time AD15 to ADOO WR 3 tce 2 20 WR T data hold time AD15 to ADOO WR 20 WR 7 address valid time A23 to A16 WR tce 2 10 WR T gt ALE f time tce 2 15 WR T gt CLK f time tce 2 20 tWLCH 24V CLK tWHLH 24V ALE WR WRL WRH A23 to A16 AD15 to ADOO Address Write data 74 MB9
14. 8 Internal clock fcP MHz External clock fc MHz 12 16 Relationship between external clock frequency and internal operation clock frequency x1 2 no multiplication AC characteristics are specified by the following reference voltage values Input Signal Waveform Hysteresis Input Pin Output Signal Waveform Output Pin 69 MB90495G Series 2 Clock Output Timing Vcc 5 0 V 5 Vss AVss 0 0 V Ta 40 C to 125 C Vcc 5 0 V 10 Vss AVss 0 0 V Ta 40 C to 105 C Value Parameter Symbol Condition Unit Cycle time tcvc 62 5 CLK T gt CLK 5 3 Reset Input Timing Parameter Condition Normal mode Stop mode Reset input time Oscillator oscillation time Watch mode 16 tcp Subclock mode Subsleep mode Oscillator oscillation time is the time to reach 90 amplitude For a crystal oscillator this is a few to several dozen ms for a FAR ceramic oscillator this is several hundred us to a few ms and for an external clock this is 0 ms Stop mode Watch mode Subclock mode Subsleep mode tRSTL RST N 0 2 Vcc 0 2 90 of Internal operation Oscillator oscillation time 16 tcp P gt ii Oscillation stabilize standby time Instruction execution Internal reset 70 Parameter Symb
15. Interrupt flag Stored in bit DIRR RO EIOS Does not support extended intelligent I O service Delayed Interrupt Generation Module Block Diagram Internal data bus DIRR Undefined Interrupt request latch Delayed interrupt request generation cancel register Delayed interrupt request generation cancel register DIRR Interrupt lt gt request signal 5 Interrupt R request latch This latch stores the delayed interrupt request generation cancel register setting generates cancels delayed interrupt requests Generates or cancels delayed interrupt requests Interrupt number Below is the interrupt number used by the delayed interrupt generation module Interrupt number 42 2An 49 MB90495G Series 9 DTP External Interrupts The DTP external interrupt transmits interrupt requests or data transfer requests generated by peripheral devices to the CPU generates external interrupt request and starts the extended intelligent I O service EIPOS DTP External Interrupt Functions Outputs interrupt requests from external peripheral devices to the CPU using the same procedure as for periph eral functions and generates external interrupts or starts the extended intelligent I O service EIPOS If the interrupt control register is configured to prohibit the extended intelligent I O service EI2OS ICR ISE 0 then the external interrupt feature bec
16. Subclock 8 192 kHz Notes the count clock of the watchdog timer is set to time base timer output overflow signal then clearing the time base timer could make it take longer to reset the watchdog f you are using a subclock as the machine clock make sure to select watch timer output by setting the watchdog timer clock source selection bit WDCS of the watch timer control register WTC to 0 Approx 18 432 s 217 4 214 SCLK 37 MB90495G Series 38 Watchdog Timer Block Diagram Watchdog timer control register WDTC Watch timer control register WTC WAST ERST SRST Dos M timer Launch Reset generation Go to sleep mode Counter Counter 2 bit Watchdog Go to time base clearcontrol clock reset timer mode circuit Selector generation circuit To internal reset counter generation circuit Go to watch mode Go to stop mode Time base timer counter Main clock 1 2 HCLK 2 x 22 x 28 x 29 x 210 x 211 212 x 213 2141 215 x 216 x 217 x lt 218 Clock counter HCLK Oscillation clock SCLK Subclock MB90495G Series 4 16 bit I O Timer The 16 bit I O timer is a complex module comprising one 16 bit free run timer and two input capture units 4 input pins Clock interval input signals and pulse widths can be measured based on the 16 bit free run timer 16 bit I O Timer Configuration
17. CMOS output 49 Timer Time base timer watch timer watchdog timer 1 channel 8 16 bit PPG timer four 8 bit channels or two 16 bit channels 16 bit reload timer 2 channels 16 bit I O timer 16 bit free run timer 1 channel 16 bit input capture ICU 4 channels Generates interrupt requests by latching onto the count value of the 16 bit free run timer with pin input edge detection Continued MB90495G Series snvnw Continued CAN Controller 1 channel CAN specifications conform to versions 2 0A and 2 08 8 on chip message buffers Forwarding rate 10 Kbps to 1 Mbps with 16 MHz machine clock UARTO SCI UART1 SCI 2 channels All with full duplex double buffer Use clock asynchronous or clock synchronous serial forwarding DTP external interrupt 8 channels module for launching extended intelligent I O service 2 5 and generating external interrupts through external output Delayed interrupt generation module Generates interrupt requests for switching tasks 8 10 bit A D converter 8 channels Switch between 8 bit and 10 bit resolution Launch through external trigger input Conversion time 6 13 us with 16 MHz machine clock including sampling time Program batch function 2 address pointer ROM correction Clock output function MB90495G Series PRODUCT LINEUP Part Number Paarmeter Feature Classification MB90F497G MB90497G MB90F498G MB90V495G FLASH
18. Continued 25 C external clock operation f internal operation frequency 7 1 8 2 6 4 3 5 9 3 2 1 0 i 3 0 4 0 5 0 6 0 7 0 Vcc V Vcc Vo lot Ta 25 C Vcc 2 4 5 V 25 C Vcc 4 5 V 1000 1000 900 900 800 800 700 700 t z 600 S 600 gt 500 9 500 8 7 400 400 300 300 200 200 100 100 0 0 012 3 4 5 6 7 8 9 10 11 12 012 3 4 5 6 7 8 9 10 11 12 loH mA lot mA 88 ORDERING INFORMATION Part Number MB90F497GPF MB90497GPF MB90F498GPF MB90F497GPFM MB90497GPFM MB90F498GPFM Package 64 pin plastic QFP 64 06 64 pin plastic LQFP 64 09 MB90495G Series Remarks 89 MB90495G Series PACKAGE DIMENSIONS 64 pin plastic QFP Note 1 These dimensions do not include resin protrusion 64 06 Note 2 Pins width and pins thickness include plating thickness Note 3 Pins width do not include tie bar cutting remainder 24 70 0 40 972 016 T a 20 00 0 20 787 008 0 17 0 06 8 007 002
19. FFBFFFH 7BFFFH 7C000H SA4 16 Kbytes FFFFFFH 7FFFFH If a parallel write is writing data to Flash memory the write address corresponds to the CPU address If a general purpose writer is used to write delete this address is written to over 62 MB90495G Series ELECTRICAL CHARACTERISTICS 1 Absolute Maximum Ratings Vss AVss 0 V Parameter Remarks Vss 6 0 Power supply voltage Vss 6 0 Voc AVcc Vss 6 0 AVcc 2 AVR Input voltage Vss 6 0 Output voltage Vss 6 0 Maximum clamp current cLAMP 2 0 Total maximum clamp current 20 L level maximum output current lou 15 L level average output current loLav L level maximum total output current L level average total output current H level maximum output current H level average output current loHav H level maximum total output current level average total output current Ylouav Power consumption Operating temperature Storage temperature 1 2 537 4 5 6 AVcc and AVR shall never exceed Vcc Also AVR shall never exceed AVcc Vi and Vo shall never exceed Vcc 0 3 V However if the maximum current to from an input is limited by some means with external components the IcLamp rating supersedes the Vi rating The rating for the maxim
20. SCI Number of channels 1 Clock synchronous forwarding 62 5 Kbps to 2 Mbps Clock asynchronous forwarding 1 202 bps to 62 500 bps Transmission can be performed by two way serial transmission or by master slave connection UART1 SCI Number of channels 1 Clock synchronous forwarding 62 5 Kbps to 2 Mbps Clock asynchronous forwarding 9 615 bps to 500 Kbps Transmission can be performed by two way serial transmission or by master slave connection Compliant with CAN specification versions 2 0A and 2 0B Send receive message buffers 8 Forwarding bit rate 10 Kbps to 1 Mbps with 16 MHz machine clock PACKAGES AND CORRESPONDING PRODUCTS MB90F497G MB90497G MB90F498G 64 06 O 64 09 O available x not available Note See Package Dimensions for details PRODUCT COMPARISON Memory Size When evaluating with evaluation chips and other means take careful note of the different between the evaluation chip and the chip actually used Take particular note of the following While the MB90V495G does not feature an on chip ROM the dedicated development tool can be used to achieve operation equivalent to a product with built in ROM Therefore the ROM size is configured by the development tool On the MB90V495G the 4000 to FFFFFFu image is only visible in the 00 bank and the 0000 to FF3FFFu is only visible in the FE and FF banks configurable
21. The 16 bit I O timer is made of the following modules One 16 bit free run timer Two input capture units each unit having 2 input pins 16 bit I O Timer Function 1 16 bit free run timer function The 16 bit free run timer consists of a 16 bit up counter a time counter control status register and prescaler The 16 bit up counter counts up in synchronization with a fraction of the machine clock The count clock can be set to one of eight fractions of the machine clock The external clock signals input to the 16 bit free run timer clock input pin FRCK can be used as the count clock Interrupts can be generated in response to counter value overflows Interrupts launch the extended intelligent I O service EOS The count value of the 16 bit free run timer can be cleared to 0000 by either a reset or software clear via the timer count clear bit TCCS CLR The count value of the 16 bit free run timer is output to the input capture and used as the base time for capture operation 2 Input Capture Function When the input capture detects that an external signal edge has been input to an input pin it stores the count value of the 16 bit free run timer in the input capture data register for the point at which the edge was detected The input capture consists of an input capture register corresponding to four I O pins an input capture control status register and an edge detection circuit When an e
22. The memory access modes of the MB90495G Series can be set to single chip mode internal ROM external bus mode and external ROM external bus mode 1 Memory Allocation of the MB90495G The MB90495G Series has 24 bit internal address bus and 24 bit external address bus output enabling it to access up to 16 Mbytes of external access memory The enable disable time of the ROM mirror function is shown graphically in the memory 2 Memory Map map 000000H 0000C0H 000100H Address 1 002000H Address 2 010000H Address 3 FFFFFFH Product MB90V495G MB90F497G Single chip mode ROM mirror function available Periphery ROM space image of bank FF ROM space Internal access memory External access memory DI Access prohibited Address 1 001900 000900 Address 2 Internal ROM External bus mode Periphery RAM space Register n Extention IO space ROM space image of bank FF ROM space 0040004 0040004 External ROM External bus mode Periphery RAM space Register B Extention IO space ee Address 3 0000 FF0000u MB90497G 000900 004000 FF0000u MB90F498G 000900 004000 Addresses 1 and 3 are product specific 0000 Note When the internal ROM is operational the ROM data in the upper address of bank 00 o
23. system reserved area 00002 Communication prescaler control register 1 R W 0 XXX 0 0 0 Os 00002 to 00002 system reserved area DTP external interrupt enable register DTP external interrupt condition register 000033 Detection level configuration register DTP external interrupt 000000008 0000000 0s 0000000 0s 000034 000035 000036 000037 A D control status register A D data register 8 10 bit A D converter 0000000 0s 000000005 XXXXXXXXB 00101 000038 to 00003 system reserved area 000040 PPGO operation mode control register R W 0000414 PPG1 operation mode control register R W 000042 000043 PPGO 1 count clock selection register system reserved area R W 8 16 bit PPG timer 0 1 0X000 XX 0X00000 18 000000 000044 PPG2 operation mode control register R W 000045 PPG3 operation mode control register R W 000046 PPG2 3 count clock selection register R W 8 16 bit PPG timer 2 3 0X000 XX 18 0X00000 000000 000047 to 00004 system reserved area 000050 000051 Input capture data register 0 000052 000053 Input capture data register 1 000054 000055
24. 1 1 1s 0000 Interrupt control register 14 0000011 18 0000BFu Interrupt control register 15 000001118 0000 0 to system reserved area 0000FFu 001 Detection address configuration R W register 0 lower Detection address configuration R W register 0 mid 001 2 Detection address configuration R W register 0 upper ROM correction 001FF3 Detection address configuration R W function register 1 lower Detection address configuration R W register 1 mid 001FF5 Detection address configuration R W register 1 upper 0039001 TMRO 16 bit timer register 0 003901 TMRLRO 16 bit reload register 0 AME E OOOO Address Register Name Access Resource Name Initial Value 0039021 TMR1 16 bit timer register 1 U 003903 TMRLR1 16 bit reload register 1 RW 16 bit reload timer 1 XXXXXXXX amp 003904 to system reserved area 00390Fu 003910 PPGO reload register L R W 003911 PPGO reload register R W XXXXXXXXs 003912u PPG1 reload register L R W 003913 PPG1 reload register H R W XXXXXXXXs 003914 PPG2 reload register L R W 003915 PPG2 reload register R W XXXXXXXXs 003916 PP
25. C output voltage pins Voc 4 75 V 105 lt Ta lt 125 C Vcc 5 5 V Input leakage All output Vss lt Vi current pins Voc 5 25 V Vss Vi lt Vcc 5 0 V Internal 16 MHz operation Normal mode 5 0 V Internal 16 MHz operation Flash memory write mode Vcc 5 0 V Internal 16 MHz operation Flash memory delete mode 5 0 V Internal 16 MHz operation Sleep mode Ta 40 C to 105 C 105 Ta 125 MB90497G MB90F497G MB90F498G MB90F497G MB90F498G MB90F497G MB90F498G MB90497G MB90F497G MB90F498G Continued 66 MB90495G Series snvnw Continued Vcc 5 0 V 5 Vss AVss 0 0 V Ta 40 C to 125 C Vcc 5 0 V 10 Vss AVss 0 0 V TA 40 C to 105 C Parameter Pin Condition 5 0 V Internal 2 MHz operation Timer mode Remarks MB90497G MB90F497G MB90F498G Vcc 5 0 V Internal 8 kHz operation Subclock operation mode TA 25 MB90497G MB90F497G MB90F498G Vcc 5 0 V Internal 8 kHz operation Subclock sleep mode Ta 25 MB90497G MB90F497G MB90F498G Vcc 5 0 V Internal 8 kHz operation Clock mode Ta 25 C MB90497G MB90F497G MB90F498G Input Capacity Otherthan Vcc or Vss Vcc 5 0 V Stop mode Ta 25 C MB90497G MB90F4
26. Fujitsu or any third party or does Fujitsu warrant non infringement of any third party s intellectual property right or other right by using such information Fujitsu assumes no liability for any infringement of the intellectual property rights or other rights of third parties which would result from the use of information contained herein The products described in this document are designed developed and manufactured as contemplated for general use including without limitation ordinary industrial use general office use personal use and household use but are not designed developed and manufactured as contemplated 1 for use accompanying fatal risks or dangers that unless extremely high safety is secured could have a serious effect to the public and could lead directly to death personal injury severe physical damage or other loss 1 nuclear reaction control in nuclear facility aircraft flight control air traffic control mass transport control medical life support system missile launch control in weapon system or 2 for use requiring extremely high reliability i e submersible repeater and artificial satellite Please note that Fujitsu will not be liable against you and or any third party for any claims or damages arising in connection with above mentioned uses of the products Any semiconductor devices have an inherent chance of failure You must protect against injury damage or loss from such failures by incorporat
27. Input capture control status register 000056 000057 Timer counter data register 16 bit I O timer XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB 0000000 0s 000000005 000000008 0000000 Os Continued 21 MB90495G Series sn Continued Register Abbreviation 000058 00000000 Timer counter control status register 000059 0 00005Au Input capture data register 2 16 bit timer 00005 Input capture data register 3 00005 00005 to system reserved area 000065 000066 R W 00000000s TMCSRO 16 bit reload timer 0 0000671 R W 00 Os Timer control status register 000068 R W 00000000s TMCSR1 16 bit reload timer 1 000069u R W XXXXO 0 0 05 00006A to system reserved area 00006 Address Register Name Access Resource Name Initial Value 00006 ROM mirror function selection register w ROM mirror function yyyyyyy 1 selection module 0000704 to system reserved area 00007 000080 Message buffer valid register R W CAN controller 0000000 0s 000081 system reserved area 0000824 Send request register R W CAN controller 10000000 0s 0000834 system reserved area 0000844 Send cancel register CAN
28. Send shift register Send start Serial output data register0 205 receive error generation signal Internal data bus Communi cations prescaler control register Serial Serial mode registerO edge selection register to CPU PE ORE FRE RDRF TDRE Serial control Serial status register0 RIE TIE 55 MB90495G Series UART1 Block Diagram Send start detection circuit circuit Reception bit counter Reception parity counter Send bit counter Send parity counter Send shift register Re ception ends Serial output data register1 Control bus Dedicated baud rate generator Send clock 16 bit reload timer1 Clock selector Reception clock Reception Send Pi control circuit control circuit in 4 SOKI Start bit Reception lt gt interrupt request output lt gt Send interrupt request output Send start 205 receive error generation signal Internal data bus 12 MD1 PEN Communi MDO cations Serial 2 prescaler mode zu control AID control register1 RST register1 REC register SCKE RXE SOE TXE to CPU 56 MB90495G Series snvnw 12 CAN Controller CAN Controller Area Network is a
29. controller 00000000s 0000854 system reserved area 000086 Send complete register R W CAN controller 0000000 Os 000087 system reserved area 0000884 Reception complete register R W CAN controller 10000000 0s 0000894 system reserved area 00008A Reception RTR register R W CAN controller 0000000 Os 00008 system reserved area 00008 Reception overrun register R W CAN controller 000000005 000080 system reserved area Reception complete interrupt enable 00008 register R W CAN controller 00000000s Continued 22 Continued Address 00008 to 00009Du Register Abbreviation Register Name Access Resource Name Initial Value MB90495G Series system reserved area 00009 Address detection control register R W ROM correction function 0000000 Os 00009 Delayed interrupt request generate cancel register Delayed interrupt generation module XXXXXXX 0 0000A0u 0000 1 Low power consumption mode control register Clock selection register R W Low power consumption modes 0001100 Os 111111008 0000 2 to 0000 4 system reserved area 0000A5u Auto ready function selection register Ww 0000A6u High address control register 0000A7u Bus control signal selection register External access 0011 0 Os 00000
30. lower than Vss is applied to an input or output pin with other than mid or high current resistance or voltage exceeding the rating is applied across Vcc and Vss Latch ups can dramatically increase the power supply current causing thermal breakdown of the device Make sure that you do not exceed the maximum rated value of your device in order to prevent a latch up When turning the analog power supply on or off make sure that the analog power voltage AVcc AVR and analog input voltages do not exceed the digital voltage Vcc Handling Unused Pins Leaving unused input pins open may cause malfunctions and latch ups permanently damaging the device Prevent this by connecting it to a pull up or pull down resistor of no less than 2 Leave unused output pins open in output mode or if in input mode handle them in the same as input pins Notes on Using External Clock When using the external clock drive pin only and leave pin X1 unconnected See below for an example of external clock use Example External Clock Use X0 MB90495G Series Open r2 Notes on Not Using Subclock If you do not connect pins and X1A to an oscillator use pull down handling on the pin and leave the X1A pin open Power Supply Pins If your product has multiple Vcc or Vss pins pins of the same potential are internally connected in the device in order to avoid abnormal operation in
31. minimum of 2 0 us RC type successive approximation with sampling and hold circuits is used for conversion Select 8 or 10 bit resolution Analog input pins can use up to 8 channels A D conversion results are stored in the A D data register allowing them to be used to generate interrupts Interrupt requests launch the Use the EI2OS to prevent dropped data even with continuous A D con version Select software internal timer output or external trigger falling edge as the start trigger With machine clock operating at 16 MHz Conversion Modes of the 8 10 bit A D Converter Conducts A D conversion for each channel in turn from the start channel to the end Single conversion mode When A D conversion of the end channel is completed the A D conversion function halts Conducts A D conversion for each channel in turn from the start channel to the end channel When A D conversion of the end channel is completed the function returns to the start channel and continues A D conversion Continuous conversion mode Suspends each channel and conducts A D conversion one at a time When A D Stop conversion mode conversion of the end channel is completed the function returns to the start channel and repeats the A D conversion and channel stop MB90495G Series 8 10 bit A D Converter Block Diagram A D control ADCS Output interrupt request status register R
32. 00 Os 0000000 or 0000100 0000A8u 0000A9u Watchdog timer control register Time base timer control register Watchdog timer Time base timer XXXXX 1 1 18 1 0 0000 Watch timer control register Watch timer 100010008 0000 to 0000 system reserved area 0000 Flash memory control status register R W 512 Kbit flash memory 000X000 Os 0000 system reserved area 0000 0000 1 Interrupt control register 00 Interrupt control register 01 R W 0000 2 Interrupt control register 02 0000B3u Interrupt control register 03 000084 Interrupt control register 04 0000B5u Interrupt control register 05 Interrupt controller 0000B6u Interrupt control register 06 0000B7u Interrupt control register 07 0000B8u Interrupt control register 08 0000B9u Interrupt control register 09 0000 Interrupt control register 10 000001 000001 000001 000001 000001 000001 000001 000001 000001 000001 000001 Continued 23 MB90495G Series sn Continued Register Abbreviation 0000BBH ICR11 Interrupt control register 11 R W 0000011 18 0000 12 Interrupt control register 12 R W 000001 1 1s 0000BDu Interrupt control register 13 Interrupt controller 0 0000
33. 0495G Series 7 Ready Input Timing 5 0 1096 Vss 0 0 V Ta 40 C to 105 C 45 RDY setup time tnvus RDY hold time tRYHH Note Use the automatic ready function if the setup time for the falling edge of the RDY signal is not sufficient Ready Input timing CLK ALE RD WR tRYHS RDY 0 8 0 8 Vcc Unweighted RDY Weighted 1 cycle 0 2 Vcc 8 Hold Timing Voc 5 0 Vt10 Vss 0 0 V Ta 40 C to 105 C Pin in floating status HAK J time T gt pin valid time Note It will take at least 1 cycle from the time the HRQ pin is loaded until the HAK changes Hold Timing HAK Each pin 75 MB90495G Series 76 9 UART Timing Parameter Serial clock cycle time Pin Name SCK1 SCK J SOT delay time SCK1 5011 Valid SIN gt SCK T SCK1 SIN1 SCK T gt valid SIN hold time SCK1 SIN1 Vcc 5 0 V 5 Vss 0 0 V Ta 40 C to 125 C Vcc 5 0 V 10 Vss 0 0 V Ta 40 C to 105 C Condition Internal shift clock mode output pin C 80 pF 1 TTL Remarks Serial clock H pulse width Serial clock L pulse width SCK1 SCK1 SCK SOT delay time SCK1 5011 Valid SIN gt SCK T SCK1 SIN1 SCK T gt valid SIN hold time See 1 Clock Timing for details abou
34. 1 in ex ternal bus mode these pins function as general purpose ports Functions as event input pin of TINO reload timer 0 Set this to input port Output pin of external address bus A16 Only valid when the bits of high address control register HACR are set to 0 in external bus mode General purpose I O port When the bits of high address control register HACR are set to 1 in ex ternal bus mode these pins function as general purpose I O ports Functions as event output pin of TOTO reload timer 0 Only valid if output configuration enabled Output pin of external address bus A17 Only valid when the bits of high address control register HACR are set to 0 in external bus mode General purpose I O port When the bits of high address control register HACR are set to 1 in ex ternal bus mode these pins function as general purpose I O ports Functions as event input pin of TIN1 reload timer 1 Set this to input port Output pin of external address bus A18 Only valid when the bits of high address control register HACR are set to 0 in external bus mode General purpose I O port When the bits of high address control register HACR are set to 1 in ex ternal bus mode these pins function as general purpose I O ports Functions as event output pin for TOT1 reload timer 1 Only valid if output configuration enabled Output pi
35. 97G MB90F498G Pull up Resistor ST Pull down Resistor This is when using the external clock as the power supply current test condition MD2 67 68 MB90495G Series 4 AC Characteristics 1 Clock Timing Parameter Clock frequency Pin Name XO X1 Vcc 5 0 V 5 Vss AVss 0 0 V Ta 40 C to 125 C Vcc 5 0 V 10 Vss AVss 0 0 V Ta 40 C to 105 C Remarks X1A Clock Cycle Time XO X1 X1A Input clock pulse width Pwet X0 Duty ratio should be around 30 to 70 Input clock rising falling time tcn tcr When external clock used Internal operation clock frequency fcp When oscillation circuit used When subclock used Internal operation clock cycle time tcp When using oscillation circuit When subclock used X0 X1 Clock Timing X0 tHCYL PWH PwL tcF MB90495G Series PLL guaranteed operation range Relationship between internal operating clock frequency and power supply voltage MB90F497G MB90F498G MB90497G guaranteed operation range Ta 40 C to 105 C MB90F497G MB90F498G MB90497G guaranteed operation range 105 C lt TA lt 125 Power supply voltage Vcc V 15 3 Internal clock fcP MHz
36. AN transmission output pin Only valid if output configuration enabled General purpose I O port CAN reception input pin Set this to input port 11 MB90495G Series I O CIRCUIT TYPE Circuit x bb Clock input lt Standby control signal R AW gt Hysteresis input Remarks High speed oscillation feedback resistor 1 MQ approx Low speed oscillation feedback resistor 10 MQ approx Hysteresis input with pull up Pull up Resistor 50 kQ approx gt Hysteresis input Vcc h 1 Digital output h Digital output Nch Hysteresis input Standby control Hysteresis input CMOS hysteresis input CMOS level output Standby control available Digital output ch Digital output R 777 lo 4 mA Hysteresis input Standby control Analog input 12 CMOS hysteresis input CMOS level output Doubles as analog input pin Standby control available Continued MB90495G Series Continued Hysteresis input with pull down R Pull down Resistor 50 approx gt H isi except FLASH device 13 14 MB90495G Series HANDLING DEVICES Make sure you do not exceed the maximum rated values in order to prevent latch up CMOS IC chips may suffer latch up if a voltage higher than Vcc or
37. G3 reload register L R W 003917 PPG3 reload register H R W XXXXXXXXs 003918 to system reserved area 003 00 to RAM general purpose RAM 003COFu Continued 24 MB90495G Series snvnw Continued Address 003 10 to 0030131 Register Abbreviation Register Name ID register 0 Access Resource Name 003 14 to 003 17 ID register 1 0030181 to 003C1Bu ID register 2 003 1 to 003C1Fu 003 20 to 003 23 ID register 3 ID register 4 003 24 to 003C27u ID register 5 003 28 to 003 2 ID register 6 003 2 to 003 2 ID register 7 CAN controller 003 30 003 31 DLC register 0 003C32u 003 33 003 34 003 35 DLC register 1 DLC register 2 003 36 003C37u DLC register 3 003 38 003C39u DLC register 4 003 003 3 DLC register 5 003 3 DLC register 6 003 DLC register 7 003 40 to 003 47 Data register 0 Initial Value to XXXXXXXXB to to to XXXXXXXXB to to
38. MB90495G Series Pin Block Diagram for Port 0 single chip mode iea read o i a 2 HOHE HM Pin gl irection x DDR write L 1 Standby control SPL 1 DDR read Standby control control stop mode SPL 1 time base timer mode SPL 1 and watch mode SPL 1 Port 0 register single chip mode The port 0 register contains the port 0 data register PDRO and the port 0 direction register DDRO The bits making up the register are in a one to one relation to the port 0 pin Compatibility between port 0 register and pin Related register bit and corresponding pin PDRO DDRO bit7 516 bit5 bit4 bit3 bit2 bit bitO Port 0 Corresponding pin 31 32 MB90495G Series Block Diagram for Pins of Ports 1 2 3 and 4 single chip mode Peripheral device Peripheral device output Port data register f Peripheral device output enabled 1 Pch Port direction register Direction latch Internal data bus Nch 777 Standby control SPL 1 Standby control control stop mode SPL 1 time base timer mode SPL 1 and watch mode SPL 1 Port 1 register single chip mode The port1 register contains the port 1 data register PDR1 and the port 1 direction regis
39. ROM Mask ROM FLASH ROM Product Evaluated ROM Size 64 Kbytes 128 Kbytes RAM Size 2 Kbytes 6 Kbytes Process CMOS Package LQFP64 width 0 65 mm QFP64 width 1 0 mm PGA256 Operating Power Emulator power supply 4 5 V to 5 5 V CPU Functions 351 8 bit 16 bit Number of instructions Instruction bit length Instruction length 1 to 7 bytes Data bit length 1 bit 8 bit 16 bit Minimum execution time 62 5 ns with 16 MHz machine clock Interrupt processing time minimum 1 5 with 16 MHz machine clock Low power consumption Standby Mode Sleep mode watch mode time base timer mode stop mode CPU intermittent mode I O Ports Time base timer General purpose ports CMOS output 49 18 bit free run counter Interrupt interval 1 024 ms 4 096 ms 16 834 ms 131 072 ms with 4 MHz oscillation clock Watchdog timer Reset generation intervals 3 58 ms 14 33 ms 57 23 ms 458 75 ms with 4 MHz oscillation clock 16 bit free run timer 16 bit Number of channels 1 Interrupts from overflow generation Timer Input capture Number of channels 4 Maintenance of free run timer value through pin input rising falling or both edg es 16 bit reload timer Number of channels 2 16 bit reload timer operation Count clock interval 0 25 us 0 5 us 2 0 us with 16 MHz machine clock External event count enabled Watc
40. U MB90495G Series sn Continued Select subclock behavior 8 192 kHz Minimum instruction execution time 62 5 ns operating with 4 MHz oscillation clock and x 4 PLL clock 16 MByte CPU memory space 24 bit internal addressing External access possible through selection of 8 16 bit bus width external bus mode Optimum instruction set for controller applications Wealth of data types Bit Byte Word Long Word Wealth of addressing modes 23 different modes Enhanced signed multiply divide instructions and RETI instruction functions Enhanced high precision arithmetic employing 32 bit accumulator Instruction set supports high level programming language C and multitasking Employs system stack pointer Enhanced indirect instructions with all pointer types Barrel shift instructions Improved execution speed 4 byte instruction queue Powerful interrupt feature Powerful 8 level 34 condition interrupt feature CPU independent automated data forwarding Extended intelligent I O service feature 5 maximum 16 channels Low power consumption Standby Mode Sleep mode CPU operation clock stopped Time base timer mode oscillation clock and subclock time base timer and watch timer only operational Watch mode subclock and watch timer only operational Stop mode oscillation clock and subclock stopped CPU intermittent operation mode Process CMOS technology Ports Generic I O ports
41. auer error check Sar end buffer eneration circuit Fi LEIR 58 13 ROM Correction Function In the case that the address of the instruction after the one that a program is currently processing matches the address configured in the detection address configuration register the program forces the next instruction to be processed into an INT9 instruction and branches to the interrupt process program Since processing can be conducted using INT9 interrupts programs can be repaired using batch processing Overview of the ROM Correction Function MB90495G Series snvnw The address of the instruction after the one that a program is currently processing is always stored in an address latch via the internal data bus ROM correction constantly compares the address stored in the address latch with the one configured in the detection address configuration register If the two compared addresses match the CPU forcibly changes this instruction into an INT9 instruction and executes an interrupt processing program There are two detection address configuration registers PADR0 and PADR1 Each register provides an interrupt enable bit This allows you to individually configure each register to enable prohibit the generation of interrupts when the address stored in the address latch matches the one configured in the detection address configuration register ROM Correction Block Diagram Address latch
42. ck and supplies a count clock to the 16 bit up counter One of four machine clock fractions can be selected by setting the timer counter control status register TCCS Timer Counter Register TCDT This is a 16 bit up counter It is possible to read the current counter value of the 16 bit free run timer by reading this counter The counter can be set to an arbitrary value by writing to it while stopped Timer Counter Control Status Register TCCS TCCS selects the divide ratio of a machine clock executes software clear of counter values and enables or disables counter operation Also TCCS confirms and clears an overflow generation flag and enables or disables interruption Input Capture Block Diagram MB90495G Series IN3 Pin Input capture data register 3 IPCP3 i l T l i Input capture data register 2 2 l l 2 44 2 l T l Input capture control status register C ICS23 Input capture interrupt request Input capture control status register EGnEGtoEGOIEGO waww 501 INO Edge detection circuit Internal data bus 41 MB90495G Series sn 5 16 bit Reload Timer The functions of the 16 bit reload timer are as follows Choose one of three internal cloc
43. cluding latch up However you should make sure to connect the pins external power and ground lines in order to lower unneeded emissions prevent abnormal operation of strobe signals due to a rise in ground levels and maintain total output current within rated levels Take care to connect the Vcc and Vss pins of MB90495G Series devices to power lines via the lowest possible impedance It is recommended that you connect a bypass capacitor of approximately 0 1 uF between Vcc and Vss near MB90495G Series device pins Crystal Oscillator Circuit Noise in the vicinity of XO and X1 pins could cause abnormal operations in MB90495G Series devices Make sure to provide bypass capacitors via the shortest possible distance from X0 and X1 pins crystal oscillators ceramic resonators and ground lines In addition design your printed circuit boards so as to keep and X1 wiring from crossing other wiring if at all possible Itis strongly recommended that you provide printed circuit board artwork surrounding and X1 pins within a grand area as this should stabilize operation MB90495G Series snvnw A D Converter and Analog Input Initiation Sequence Make sure to power up the A D converter and analog input pins ANO to AN7 after turning on digital power Voc Turn off digital power after turning off the A D converter power supply and analog inputs In this case make sure that the voltage of AVR does no
44. ctual value and the theoretical value which includes zero transition error full scale transition error linearity error and differential linear ity error Total error Actual conversion characteristics 3FD I 1 LSB x N 1 0 5 LSB Digital output Actual conversion 002 DI characteristics i Ideal characteristics AVss AVR Analog input 1 LSB x 1 0 5 LSB Total error of digital output N 1LSB LSB E AVR AVss 1 LSB ideal value 1024 V Vor ideal value AVss 0 5 LSB V Vest ideal value AVR 1 5 LSB V The voltage to transition digital output from N 1 to N Continued 80 MB90495G Series Continued Linearity error Differential linearity error Ideal 3FF characteristics Actual conversion TSB X N 1 N 1 Actual conversion characteristics 3FD actual P measurement eS tual 8 004 S 2 2 003 I 15 Actual conversion AN characteristics measurement NT actual measurement 002 Ideal characteristics 001 characteristics actual measurement AVss AVR AVss AVR Analog input Analog input Linearity error of digital output N LSB 1 LSB V N 1 T Differential linearity error of digital output N TLSB 1 LSB LSB
45. d Timer Block Diagram Internal data bus 16 bit reload register Reload signal Reload control circuit 16 bit timer register Count clock generation circuit 3 Valid clock Wait signal Prescaler determination 9 circuit Clear Machine Output to on chip peripheral functions Output control circuit Output signal control Clock generation circuit selector circuit a External L ell clock Select signal Internal clock Select function esee ps rh Timer control status register TMCSR lt gt Output interrupt request 43 44 MB90495G Series 6 Watch Timer The watch timer is a 15 bit free run counter that counts up in synchronization with the subclock Eight different intervals can be selected and interrupt requests generated for each interval time Supplies a timer for subclock oscillation stabilization standby and an operational clock for the watchdog timer The subclock is always the count clock regardless of the clock selection register CKSCR setting nterval timer feature When the interval time set by the interval time selection bits WTC WTC2 to WTCO is reached the clock timer generates an overflow in the bits corresponding to the interval time of the watch timer counter and sets the overflow flag bit WTC WTOF 1 Interrupts arising fro
46. dge is detected either rising falling or both can be selected An interrupt request can be generated to the CPU when an input signal edge is detected Interrupts launch the extended intelligent I O service El OS Since the input capture has four pairs of input pins and input capture data registers it can measure up to 4 phenomena Block Diagram of 16 bit Timer Internal data bus 16 bit free run timer Input capture Dedicated bus 16 bit free run timer The counter value of the 16 bit free run timer is used as the base time of the input capture Input capture Input capture detects rising falling and both edges for external signals input to input pins and stores the counter value of the 16 bit free run timer Interrupts can be generated in response to input signal edge detection 39 40 MB90495G Series Block Diagram of 16 bit Free run Timer Output count value to input capture Timer counter data register TCDT 16 bit free run timer Internal data bus Timer counter control status register TCCS Re STOP served ana Free run timer interrupt request Machine clock OF overflow Note The 16 bit I O timer contains one 16 bit free run timer The interrupt request number of the 16 bit free run timer is as follows Interrupt request number 19 134 Prescaler Takes a fraction of the machine clo
47. e BUSY INT INTE PAUSSTSISTSOJSTATI MD1 MDO ANS2 ANST ANSOANE2ANE1 ANEO 2 6 Decoder Selector Comparator AN7 Sample and AN6 hold circuit Control circuit AN5 AN4 Analog AN3 channel selector AN1 AVR ANO AVcc D A converter AVss 5 A D data register 09 os 07 06 04 ps oe po ADCR TO Reserved Internal timer output Undefined Make sure this is always set to 01 Machine clock Internal data bus 53 MB90495G Series 11 UARTO 1 The UART is general purpose serial data communications interface for synchronous or asynchronous com munication with external devices The UART has a clock synchronous clock asynchronous two way communications feature Also supplies a master slave communications feature multi processor mode It can be used only master side Interrupts can be generated upon send complete receive complete or reception error detection Supports extended intelligent I O service EIPOS UARTO 1 Functions Functions Data Buffer Full duplex double buffer Clock synchronous no start stop or parity bit Transfer mode Clock asynchronous start stop synchronization Select from 8 dedicated baud rate generators Baud Rate External clock input possible Clock supplied f
48. e code These codes also cannot be accessed through commands Flash memory write delete t is not possible to simultaneously write to and read from flash memory When writing to or deleting from flash memory first copy the program residing in flash memory into RAM then execute the program copied into RAM This will allow you to write to flash memory MB90495G Series sn List of Flash Memory Registers and Reset Values Flash memory control on 7 6 5 4 3 2 1 0 status register FMCS 2 21212 0 bee Undefined Sector Architecture of 512 K 1 M bit Flash memory Sector architecture 512 Kbit flash memory When accessing from the CPU SAO to SA3 are arrayed in the Bank FF register 1 Mbit flash memory When accessing from the CPU SAO is arrayed in the Bank FE register SA1 to SA4 are arrayed in the Bank FF register Sector Architecture of 512 K 1 M bit Flash Memory 512 Kbit Flash Memory CPU Addresses Writer Address FF0000H 70000 SAO 32 Kbytes FF7FFFH 77FFFH FF8000H 78000H 1 8 Kbytes FF9FFFu 79FFFH 7A000H SA2 8 Kbytes FFBFFFH 7BFFFH 7 000 SA3 16 Kbytes FFFFFFH 7FFFFH 1 Mbit Flash Memory CPU Addresses Writer Address 60000H SAO 64 Kbytes FEFFFFH 6FFFFH FF0000H 700001 SA1 32 Kbytes FF7FFFH 77FFFH FF8000H 78000H SA2 8 Kbytes FF9FFFu 79FFFH 7A000H SA3 8 Kbytes
49. e with EIOS Since PPG does not support EI OS if you use with the 16 bit reload timer prohibit interrupts by PPG 3 Priority if two or more interrupts with the same level are generated simultaneously 29 MB90495G Series PERIPHERAL RESOURCES Port 1 Overview General purpose parallel I O ports can be used as the I O ports The MB90495G Series has 7 ports 49 Each port doubles as a peripheral device I O pin 1 I O Port Features ports output data to I O pins and load signals input to them by means of the port data register Additionally the port direction register DDR sets the I O direction of the I O pins at the bit level Below is a description of each pin s function and the peripheral device that shares it PortO Port 1 Port 2 Port 3 Port 4 Port 5 Port 6 general purpose port doubles as external address data bus pin general purpose I O port doubles as PPG timer output input capture input and external address data bus pin general purpose I O port doubles as reload timer I O external interrupt input pin and external address bus pin general purpose I O port doubles as UARTO I O free run timer and A D converter startup trigger general purpose I O port doubles as UART1 I O and CAN controller transmit receive pin general purpose port doubles as analog input pin general purpose I O port doubles as external interrupt input pin
50. eset values 0 The reset value of this bit is 0 1 The reset value this bit is 1 X The reset value of this bit is undefined System reserved area contains system internal addresses and cannot be used 27 MB90495G Series 28 E INTERRUPT CONDITIONS AND INTERRUPT VECTOR REGISTER Interrupt Condition Reset EPOS Compatible Interrupt Vector Interrupt Register Number Address FFFFDCnu ICR Address INT 9 instruction Exception processing FFFFD4 Can controller reception complete RX FFFFDOu Can controller reception complete TX Node status transition NS FFFFCCu 000080 7 Reserved Reserved 8 4 0000 1 External interrupt 1 Time base timer FFFFBCH 0000B2x 16 bit reload timer 0 8 10 bit A D converter 0000B3u 16 bit free run timer overflow External interrupt INT2 INT3 FFFFACH 000084 Reserved PPG timer ch0 ch1 underflow 4 0000 5 Input capture 0 load External interrupt INT4 INT5 FFFF9CH 0000B6u Input capture 1 load PPG timer ch2 ch3 underflow 94 0000B7u External interrupt INT6 INT7 FFFF90 Watch timer FFFF8CH 0000B8u Reserved
51. event register system reserved area R W CAN controller 0 XXXX 0 0 18 0 0 XXX 0 0 0s 0 00 XX 0 0 Os 003004 003005 Receive transmit error counter R 003D06u 003007 Bit timing register 003D08u IDE register CAN controller 0000000 Os 0000000 0s 1111111 1s 11111115 003D09u system reserved area 0 Transmit RTR register R W CAN controller 0000000 0s 003 system reserved area 003D0Cx Remote frame reception standby register R W CAN controller XXXXXXXXs 003D0Dx system reserved area 003D0E Transmit complete interrupt enable register R W CAN controller 000000008 Continued Continued Address 0 Register Abbreviation MB90495G Series Register Name Access system reserved area Resource Name Initial Value 003010 003011 Acceptance mask selection register R W CAN controller 003D12u 003D13u system reserved area 003014 003017 003018 00301 Acceptance mask register 0 R W Acceptance mask register 1 CAN controller to to XXXXXXXXs 00301 to 003FFFH system reserved area Explanation of r
52. f the F2MC 16LX is visible in animage This is called the ROM mirror function and takes advantage of the small C compiler model With the F2MC 16LX the lower 16 bit address of bank FF and the lower 16 bit address of bank 00 are identical to one another This allows the ROM internal table to be referenced without specifying a far pointer For example say the address 00 000 is accessed In actuality the address inside ROM will be accessed However as the ROM space in bank FF exceeds 48 Kbytes the entire space cannot be viewed on bank 00 s image And so since 4000 to FFFFFFxH ROM data will be visible on the 004000 to OOFFFFu image save the ROM data table in the 4000 to FFFFFFe space 19 20 MB90495G Series B I O MAP Address 000000 Register Abbreviation Register Name Port 0 data register Access Resource Name Initial Value XXXXXXXXB 0000014 Port 1 data register 000002 Port 2 data register XXXXXXXXB 000003 Port 3 data register XXXXXXXXB 000004 Port 4 data register XXXXXXXXB 000005 000006 Port 5 data register Port 6 data register R W XXXXXXXXB XXXXXXXXB 000007 to 00000 system reserved area 000010 Port 0 direction register R W 000000005 000011 Port 1 direction register R W 000000005
53. h Time base timer output 512 HCLK 4 Peripheral clock 1 6 o Peripheral clock 2 6 1 o Peripheral clock 4 6 Peripheral clock 8 6 o Peripheral clock 16 0 o Reserved HCLK 9 Undefined Reserved bit Oscillation clock frequency Machine clock frequency Interrupt output from 8 16 bit PPG timer 0 is merged with interrupt request output from PPG Count clock selector 3 Pulse selector Operation mode control signal PPGO underflow PPG1 underflow to PPG1 PPGO PPG output control circuit Select signal esses emos PPGO 1 count clock selection register PPGO1 timer 1 into a single interrupt via an OR circuit 47 48 MB90495G Series Block Diagram of 8 16 Bit PPG Timer1 H level side data bus Level side data bus S PPGC1 reload PRLH1 register side Operation PPG1 operation mode control register ma eel L served mode control signal PPG1 temporary buffer PRLBH1 Reload selector CIR Select signal L H selector Initial count value Cf 4 Reload i PPG1 down counter 1 PCNT1 Invert output latch PPG1 underflow CK 7 PPG output control circuit to PPGO 7 MDO PPGO underflow 5 from PPGO Time base timer o
54. h timer 15 bit free run counter Interrupt intervals 31 25 ms 62 5 ms 12 ms 250 ms 500 ms 1 0 s 2 05 with 8 192 kHz subclock 8 16 bit PPG timer Number of channels 2 two 8 bit channels can be used Two 8 bit or one 16 bit channel PPG operation possible Free interval free duty pulse output possible Count clock 62 5 ns to 1 us with 16 MHz machine clock The 52 dipswitch setting when using the MB2145 507 emulation baud For details see the MB2145 507 hardware manual 2 7 Emulator Power Pin Continued Continued Part Number Parameter Delayed interrupt generation module MB90495G Series MB90F497G MB90497G MB90F498G MB90V495G Module for delayed interrupt generation switching tasks Used in real time OS DTP external interrupt circuit Number of inputs 8 Starting by rising edge falling edge H level input or L level input external interrupts or extended intelligent I O service EITOS can be used 8 10 bit A D converter Number of channels 8 Resolution set 10 bit or 8 bit Conversion time 6 13 us with 16 MHz machine clock including sampling time Continuous conversion of multiple linked channels possible up to 8 channels can be set One shot conversion mode converts selected channel only once Continuous conversion mode converts selected channel continuously Stop conversion mode converts selected channel and suspends operation repeatedly UARTO
55. hannel module can yield the following behavior 8 bit PPG output 2 channel independent operation mode 16 bit PPG output operation mode 8 8 bit PPG output operation mode The MB90495G Series features two on chip 8 16 bit PPG timers This section describes the functions of PPGO 1 PPG2 3 has the same functions as PPGO 1 8 16 bit PPG Timer Functions The 8 16 bit PPG timer is made up of four 8 bit reload registers PRLHO PRLLO PRLH1 PRLL1 and two PPG down counters PNTO PCNT1 Since you can set each output pulse to H or L width independently the interval and duty ratio of each pulse can be set to an arbitrary value Select one of 6 internal clocks as the count clock Interrupt requests can be generated for each interval time allowing the timer to be used as an interval timer The use of an external circuit allows the timer to be used as a D A converter PPGO reload register PRLHO H level side PRLLO L level side PPGO temporary buffer 0 PRLBHO Reload register Select signal Tee poo MB90495G Series Block Diagram of 8 16 Bit PPG Timer 0 H level side data bus L level side data bus PPGO operation mode control register PPGCO Output interrupt request L H selector Initial count value Underflow Reload PPGO down counter PCNTO CLK 5 Invert PPGO output latc
56. ided from the pins so that incomplete operation may result Note that if the B input is applied during power on the power supply is provided from the pins and the resulting supply voltage may not be sufficient to operate the power on reset Care must be taken not to leave the B input pin open Note that analog system input output pins other than the A D input pins LCD drive pins comparator input pins etc cannot accept B signal input Sample recommended circuits Protective diode Vcc Limiting resistance B input OV to 16 V 7 If used exceeding Ta 105 C be sure to contact us for reliability limitations WARNING Semiconductor devices can be permanently damaged by application of stress voltage current temperature etc in excess of absolute maximum ratings Do not exceed these ratings MB90495G Series snvnw 2 Recommended Operating Conditions Vss AVss 0 0 V Parameter Remarks During normal operation Ta 40 C to 105 C Power supply voltage During normal operation 105 C Ta lt 125 C Maintaining stop operation state Smoothing capacitor 21 Operating temperature T 1 Use a ceramic capacitor or one with approximately the same frequency characteristics The bypass capacitor of the Vcc pin should have a greater capacity than Cs See the figure below for details about connecting a smooth capacito
57. ing safety design measures into your facility and equipment such as redundancy fire protection and prevention of over current levels and other abnormal operating conditions If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Law of Japan the prior authorization by Japanese government will be required for export of those products from Japan F0306 FUJITSU LIMITED Printed in Japan
58. ks or an external event clock as the count clock Choose a software or external launch trigger Aninterruptcan be sentto the CPU in response to an underflow generated by the 16 bittimer register Interrupts can be used to utilize the timer as an interval timer When an underflow is generated by the 16 bit timer register TMR select one shot mode where TMR counter operation is halted or reload mode where the 16 bit reload register value is reloaded and TMR count operation continues Supports extended intelligent I O service EIPOS The MB90495G Series features two on chip 16 bit reload timer channels 16 bit Reload Timer Operation Mode Count Clock Launch Trigger Software trigger Internal clock mode External trigger Operation in Case of Underflow One shot mode Reload mode Event count mode Software trigger One shot mode Internal Clock Mode Reload mode Set the count clock selection bits of the timer control status register TMCSR CSL1 0 to 008 018 or 108 to set the 16 bit reload timer to internal clock mode In internal clock mode the timer counts down in synchronization with the internal clock Set the count clock selection bits of the timer control status register TMCSR CSL1 CSLO to select one of three count clock intervals Select software triggered or externally triggered edge detection launch 42 MB90495G Series 16 bit Reloa
59. m overflows are enabled WTC WTIE 1 an interrupt request is generated when the overflow flag bit is set WTC WTOF 1 Select from one of the following 8 watch timer intervals Clock Timer Interval Times 25 SCLK 31 25 ms 23 SCLK 62 5 ms 2 0 SCLK 125 ms 2 SCLK 250 ms 2 SCLK 500 ms 2 3 SCLK 1 0 s 2 4 SCLK 2 0 s 2 5 SCLK 4 0 s SCLK 122 us SCLK Subclock frequency Figures in parentheses are a sample calculation with the subclock running at 8 192 kHz MB90495G Series Watch Timer Block Diagram gt watchdog timer Watch timer counter Power on reset Counter EOM To subclock oscillation clear circuit stabilization standby time Go to hardware standby Go to stop mode timer selector see wre mor wre reer Watch timer control register WTC Watch timer interrupt lt gt OF Overflow SCLK Subclock Notes The actual interrupt request number generated by the watch timer is as follows Interrupt request number 28 1 Watch timer counter 15 bit up counter using the subclock SCLK as its count clock Counter clear circuit This circuit clears the watch timer counter 45 MB90495G Series 7 8 16 Bit PPG The 8 16 bit PPG timer is a 2 channel reload timer module PPGO PPG1 capable of arbitrary synchronization and pulse output of duty ratio Combining the 2 c
60. n for external address bus A19 Only valid when the bits of high address control register HACR are set to 0 in external bus mode Continued 10 MB90495G Series Pin Name P24 to P27 INT4 to INT7 A20 to A23 Circuit Type Description General purpose I O port When the bits of high address control register HACR are set to 1 in ex ternal bus mode these pins function as general purpose I O ports Functions as external interrupt input pin Set this to input port Output pin for external address bus A20 to A23 Only valid when the bits of high address control register HACR are set to 0 in external bus mode Power supply 0 V input pin General purpose I O port Only enabled in single chip mode UARTO serial data output pin Only valid if UARTO serial data output configuration is enabled Address latch authorization output pin Only enabled during external bus mode General purpose I O port Only enabled in single chip mode UARTO serial clock I O pin Only valid if UARTO serial clock I O configuration is enabled Lead strobe output pin Only enabled during external bus mode General purpose I O port UARTO serial data input pin Set this to input port Write strobe output pin for lower 8 bit of data bus Only valid if WRL pin output is enabled in external bus mode General purpose I O p
61. of Port 6 Pins Internal data bus Port data register PDR PDR read Direction latch DDR write Peripheral device input MB90495G Series Pa Nch E DDR read Standby control control stop mode SPL 1 time base timer mode SPL 1 and watch mode SPL 1 Standby control SPL 1 Port 6 register The port 6 register contains the port 6 data register PDR6 and the port 6 direction register DDR6 The bits making up the register are in a one to one relationship with the port 6 pins Port 6 Register and Corresponding Pins PDR6 DDR6 Related register bit and corresponding pin Corresponding pin 35 36 MB90495G Series sn 2 Time base Timer The time base timer is an 18 bit free run counter time base counter for counting up in synchronization with the main clock 1 2 main oscillation clock Four interval times are available and interrupt requests can be generated for each interval time The time base timer also has a function for supplying timers for oscillation stabilize standby time and operating clocks for peripheral devices nterval timer feature When the time base timer counter reaches the interval set by the interval time selection bits TBTC TBC1 it generates an overflow TBTC 1 and interrupt request f the interrupt
62. of Undefined Output from Ports 0 1 with RST pin set to H Time in standby for oscillation to stabilize Time in standby for step down circuit to stabilize Vcc power supply pin PONR power on reset signal RST external asynchronous reset signal RST internal reset signal Oscillation clock signal mf L KA internal operating clock A signal KB internal operating clock B signal 1 Step down circuit stabilization standby time 217 oscillation clock frequency with 16 MHz oscillation clock frequency about 8 19 ms 2 Oscillation stabilization standby time 2 8 oscillation clock frequency with 16 MHz oscillation clock frequency about 16 36 ms Figure 2 Timing Chart of High Impedance State for Ports 0 1 when RST pin is L Time in standby for oscillation to stabilize Step down circuit stabilization standby time Vcc power supply pin RST external asynchronous reset signal RST internal reset signal F LL Oscillation clock signal UUUUHUVUUUL KA internal operation clock A signal KB internal operating clock signal PORT port output signal PONR power on reset signal High impedance 1 Step down circuit stabilization standby time 2 oscilla
63. ol Condition Win Power supply rising time 05 MB90495G Series 4 Power on Reset Vcc 5 0 V 5 Vss 0 0 V Ta 40 C to 125 C Vcc 5 0 V 10 Vss AVss 0 0 V Ta 40 C to 105 C ms Power supply cutoff time torr Voc 1 ms Due to repeated operations Vcc toFF Sudden changes in the power supply voltage may cause a power on reset To change the power supply voltage while the device is in operation it is recommended that you raise the voltage at a steady rate in order to suppress fluctuations see figure below In this case perform this operation when the PLL clock is not being used If however the voltage falling speed is no more than 1 V s itis permissible to perform this operation while using the PLL clock It is recommended that you keep the rising 3V speed to no more than 50 mV ms RAM data hold period 71 MB90495G Series 5 Bus Read Timing Vcc 5 0 10 Vss 0 0 V Ta 40 C to 105 C 72 Parameter ALE pulse width Pin Name ALE tcp 2 20 Remarks Valid address gt ALE 4 time ALE A23 to A16 AD15 to ADOO tcr 2 20 ALE address valid time ALE AD15 to ADOO 1 2 15 Valid address gt RD J time A23 to A16 AD15 to ADOO RD tcp 15 Valid address Valid data input RD pulse width A23 to A16 AD15 to ADOO RD
64. omes valid and the process branches into interrupt processing If the EIPOS is enabled ICR ISE 1 then the DTP function becomes valid and the automatically transmits data and after transmitting data a specified number of times branches into interrupt processing Overview of DTP External Interrupts External interrupt DTP functions Input pins Interrupt condition 8 INTO to INT7 Each pin sets individually in the detection level configuration register ELVR level rising edge falling edge input H level input Interrupt numbers 15 OFu 20 14 24 18x 27 1B Interrupt control The DTP external interrupt enable register ENIR enables or prohibits interrupt request output Interrupt flag Interrupt conditions stored by DTP external interrupt condition register EIRR Process selection Processing 50 Set El OS to prohibited ICR ISE 0 Set EI OS to enabled ICR ISE 1 After the EIOS conducts automated data Branch to external interrupt process forwarding the specified number of times branches to interrupt processing MB90495G Series SS DTP External Interrupt Block Diagram Detection level configuration register ELVR fente eoe ae ue merani 241 pem EA
65. on development tool On the MB90F497G F498G 497G the FF4000x to FFFFFFu image is visible in the 00 bank and the 0000 to is visible only in the FF bank MB90495G Series PIN ASSIGNMENTS 64 06 TOP VIEW 100 204 80QV ONI 0Ld 60QV LNI L Ld OLQV ENI 2ld LLQV ENI Eld cLQOV OOdd r Ld ELOW LOdd Sld 914 Ld 91 0 1 024 21 0101 1 4 81 1 264 6L V LLOL Ecd 1 91 SSA 31Y 0LOS 0 d PO5 ADO5 P04 AD04 P03 AD03 1 PO2 ADO2 PO1 ADO1 26 00 32 6 06 oan E LNI 9d VIX VOX O LNI 09d SSAV ZNV 4Sd 9NV 9Sd SNV SSd ENY Sd CNY CSd LNW LSd cANI C9d LLNI L9d 4 XX giz I 5 silt 92 553540 LGESRLLH OZoomp 9 epee GI 9 e 06 64 MB90495G Series QN gt lt lt lt lt lt lt lt lt 85 82 aE n a n n nn nn gt xx gt x e e 80QV ONI O Ld VIX 60QV INI L Ld VOX OLQV 2NI Z Ld OLNI 09d LLOV ENI E Ld SSAV 0
66. one to one relationship with the port 3 pins Port 3 Register and Corresponding Pins Related register bit and corresponding pin CKE RYE HDE ECSR Corresponding pin P31 P30 Port 4 register The port4 register contains the port 4 data register PDR4 and the port 4 direction register DDR4 The bits making up the register are in a one to one relationship with the port 4 pins Port 4 Register and Corresponding Pins Related register bit and corresponding pin DDR4 bit4 bit3 bit2 bit bitO Corresponding pin P44 P43 P42 P41 40 Port 4 33 MB90495G Series Block Diagram of Port 5 Pins Analog input Pch Internal data bus 777 Standby control SPL 1 Standby control control stop mode SPL 1 time base timer mode SPL 1 and watch mode SPL 1 34 Port 5 register The port 5 register contains the port 5 data register PDR5 the port 5 direction register DDR5 and the analog input enable register ADER Theanalog data enable register ADER enables or disables the input of analog signals by the analog input pin The bits making up the register are in a one to one correspondence with the pins of port 5 Port 5 Register and Corresponding Pins Port Name Related register bit and corresponding pin PDR5 DDR5 ADER Corresponding pin Block Diagram
67. ort Write strobe output pin for upper 8 bit of data bus Only valid if external bus mode 16 bit bus mode WRH pin output enabled General purpose I O port Hold reguest input pin Only valid if hold input is enabled in external bus mode General purpose I O port Hold addressing output pin Only valid if hold input is enabled in external bus mode Power supply 5 V input pin Capacity pin for power stabilization Please connect to an approximately 0 1 uF ceramic capacitor Continued MB90495G Series Continued Pin Name Circuit Type Description General purpose I O port Functions as an external clock input pin for a FRCK 16 bit free run timer Set this to input port External ready input pin Only valid if external ready input is enabled in external bus mode General purpose I O port Functions as A D converter external trigger input pin Set this to input port External clock output pin Only valid if external clock output is enabled in external bus mode General purpose I O port UART1 serial data input pin Set this to input port General purpose I O port UART1 serial clock I O pin Only valid if UART1 clock I O configuration is enabled General purpose I O port UART1 serial data output pin Only valid if UART1 serial data output configuration is enabled General purpose I O port C
68. pen if not connected to an oscillator General purpose I O port Functions as external interrupt input pin Set this to input port Input pin for specifying operation mode External reset input pin Input pin for specifying operation mode Input pin for specifying operation mode High speed oscillation pin High speed oscillation pin Power supply 0 V input pin POO to P07 ADOO to AD07 General purpose I O port Only enabled in single chip mode I O pin for the lower 8 bit of the external address data bus Only enabled during external bus mode P10 to P13 INO to IN3 ADOS to AD11 General purpose port Only enabled in single chip mode Functions as trigger input pin for input capture channels 0 to 3 Set this to input port I O pin for upper 4 bit of external address data bus Only enabled during external bus mode Continued MB90495G Series Continued Pin Name P14 to P17 PPGO to PPG3 AD12 to AD15 Circuit Type Description General purpose I O port Only enabled in single chip mode Functions as output pin of PPG timer 01 23 Only valid if output configu ration is enabled I O pin for upper 4 bit of external address data bus Only enabled during external bus mode P20 TINO 16 General purpose I O port When the bits of high address control register HACR are set to
69. peration clock TQ Prescaler Bit timing clock 1 segment imer segment BTR 85 CSR HALT Node status Node status p 1 suspend transition interrupt gt transition send generation circuit interrupt signal tion circuit receive 510 Error error control circuit overload Send receive BVALR Big sena sequence buffer Send buffer Send determination buffer circuit Data Acceptance counter filter control circuit Send Re ID circuit DLC ception selection DLC Arbitration lost Bit error Staff error Sait CRC error end buffer Frame error Output 1 ACK error driver Pin Tx TRTRR RFWTR Send shift Staffing register TCR Set clear send buffer or CRC ACK i en generation generation TIER send com jete interrupt complete Send DLC circuit circuit W CRC error Set reception buffer signa Receive RCR u 5 DLC CRC generation Reception complete eception interrupt generation circuit completo eas Reception buffer 22 Reception signa i i lii RRTRR Set clear send buffer shift register Destaffing Set reception staffing error ROVRR buffer Select ID check Y ANBO 0 Acceptance Reception buffer Arbitration t determination lost Arbitration check AMR1 filter circuit Bit error Bit error check ky ri Reception buffer DLCR7 ACK error p to 0187 RAM address Reception
70. r to the Cs 2 If used exceeding Ta 105 be sure to contact us for reliability limitations C Pin Connection Diagram Cs WARNING The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device All of the device s electrical characteristics are warranted when the device is operated within these ranges Always use semiconductor devices within their recommended operating condition ranges Operation outside these ranges may adversely affect reliability and could result in device failure No warranty is made with respect to uses operating conditions or combinations not represented on the data sheet Users considering application outside the listed conditions are advised to contact their FUJITSU representatives beforehand 65 MB90495G Series sn 3 DC Characteristics Vcc 5 0 V 5 Vss AVss 0 0 V TA 40 C to 125 C Vcc 5 0 V 10 Vss AVss 0 0 V Ta 40 C to 105 C Parameter Pin Name Condition Remarks CMOS H level hysteresis input input pin voltage MD input pin T CMOS L level hysteresis 0 2 input input pin voltage MD input pin Vss 0 3 Vcc 4 5 V o o H level All output 40 mA Ta 40 to 105 output voltage pins Voc 4 75 V 105 Ta lt 125 C Voc 4 5 V o o level All output 4 0 mA Ta 40 C to 105
71. rom internal timer 16 bit reload timer available 7 bit asynchronous normal mode only 8 bit Signal method Non Return to Zero NRZ Framing error Reception Error Detection Overrun error Parity error not available in operation mode 1 multi processor mode Data length Receive interrupt reception complete reception error detected Interrupt Requests Send interrupt send complete Both send and receive support extended intelligent I O service EI2OS Master Slave Communications Function 1 to n master to slave communication available can only be used as master In multiprocessor mode Note During clock synchronous forwarding just the data is forwarded with no stop or start bit appended 54 UARTO Block Diagram MB90495G Series Control bus Reception lt gt interrupt Dedicated baud rate request output generator Send clock lt gt Send interrupt 1 reguest output 16 bit reload timerO Clock selector Reception clock Reception Send Pin control circuit control circuit ach Start bit detection circuit Reception bit counter Reception parity counter ee 5 Reception shift register Re Serial input 6 data registerO 97 Reception status determination circuit ception U Send start circuit Sendbit U counter Send parity counter
72. s due to overflow generation are enabled TBTC TBIE 1 when an overflow is generated TBTC 1 an interrupt is generated Select from the following 4 time base timer intervals Time base timer interval times Count Clock Interval Time 2 HCLK approx 1 0 ms 2 4 HCLK approx 4 1 ms 2 HCLK approx 16 4 ms 2 HCLK 0 5 2 HCLK approx 131 1 ms HCLK oscillation clock The number in parentheses for 4 MHz oscillation clock operation Time base Timer Block Diagram gt To PPG timer watchdog timer Time base timer counter OF To clock controller oscillation stabilize standby time selector Power on Reset Stop Mode Clear counter CKSCR MCS 1 gt 0 1 circuit CKSCR SCS 0 gt 1 2 Interval Timer selector Clear TBOF Set TBOF Re 2221 1112 TBR TBC1 TBCO Time base timer control register TBTC Time base timer interrupt signal lt gt OF overflow HCLK oscillation clock 1 Switch machine clock from main clock to PLL clock 2 Switch machine clock from subclock to main clock See below for the actual interrupt request number of the time base timer Interrupt request number 16 10x 3 Watchdog Timer The watchdog timer is a 2 bit timer used as a count clock for the timer based or watch timer MB90495G Series
73. serial communications protocol conforming to CAN version 2 0 A and B Sending and receiving is available in standard and extended frame format Can Controller Features The CAN controller format conforms to CAN versions 2 0 A and B Sending and receiving is available in standard and extended frame format Supports automated data frame formatting through remote frame reception Baudrate 10 Kbps to 1 Mbps When using at 1 Mbps the machine clock must be operated at 8 MHz or more Data Transmission Baud Rates Machine clock Baud rate Max 16 MHz 1 Mbps 12 MHz 1 Mbps 1 Mbps 500 Kbps 250 Kbps Supplies 8 send receive message buffers Sending and receiving available in standard frame format ID 11 bit and extended frame format ID 29 bit Message data can be set to 0 to 8 bytes Possible to configure a multi level message buffer The CAN controller has two built in acceptance masks each of which can be setto a different mask for reception message IDs The two acceptance masks can receive in standard or extended frame format Configure four types of partial masks with full bit compare full bit mask and acceptance mask register 0 1 57 MB90495G Series CAN Controller Block Diagram EI2OS 16LX Bus CPU gt O
74. sh Memory Overview There are three methods available for writing deleting data to from flash memory 1 Parallel writer 2 Serial dedicated writer 3 Program runtime write delete Overview of 512 K 1 M bit flash memory 512 Kbit flash memory is arrayed in bank on the CPU memory 1 Mbit flash memory is arrayed in bank to on the CPU memory map The flash memory interface circuit provides read and program access from the CPU Since instructions from the CPU are carried out via the flash memory interface circuit flash memory can be overwritten at the implementation level This allows you to efficiently improve programs and data Features of 512 K 1 M bit Flash Memory 512 Kbit flash memory 64 KWords x 8 bit 32 KWords x 16 bit 16 Kbyte 8 Kbyte 8 Kbyte 32 Kbyte sector architecture e 1 Mbit flash memory 128 KWords x 8 bit 64 KWords 16 bit 16 Kbyte 8 Kbyte 8 Kbyte 32 Kbyte 64 Kbyte sector architecture e Auto program algorithm Embedded Algorithm same as MBM29LV200 On chip delete suspend delete resume functions Data polling write delete completion detection through toggle bit Write delete completion detection from CPU overwrite Sector specific deletion available sectors can be combined as desired Write delete iterations minimum 10 000 Embedded Algorithm is a trademark of Advanced Micro Device Notes There is no function to read the manufacture or devic
75. snvnw If the counter is not cleared within the interval time it resets the CPU Watchdog Timer Function The watchdog timer is a timer counter used to deal with runaway programs Once the watchdog timer is launched it is necessary to keep clearing its counter within the specified interval If the specified interval passes without the watchdog timer counter being cleared the CPU will be reset This feature is called the watchdog timer The watchdog timer interval traces back to the clock interval input as the count clock A watchdog reset is generated for the smallest to largest times Theclock source output destination is set by the watchdog clock selection bit of the watch timer control register WTC WDCS The watchdog timer interval is set time base timer output selection bit watch timer output selection bit of the watchdog timer control register WDTC WT1 WTO Watchdog Timer Intervals Minimum Approx 3 58 ms Approx 14 33 ms Maximum Approx 4 61 ms Approx 18 3 ms Clock Interval 214 211 HCLK 216 213 HCLK Minimum Approx 0 457 s Approx 3 584 s Maximum Approx 0 576 s Approx 4 608 s Clock Interval 212 29 SCLK 215 212 SCLK Approx 57 23 ms Approx 73 73 ms 218 215 HCLK Approx 7 168 s Approx 9 216 s 216 213 SCLK Approx 458 75 ms Approx 589 82 ms 221 218 HCLK Approx 14 336 s HCLK oscillation clock 4 MHz SCLK
76. t exceed AVcc it is permissible to turn off analog and digital power simultaneously Connecting Unused A D Converter Pins If you are not using the A D converter set unused pins to AVcc AVR Vcc AVss Vss Notes for Powering Up Ensure that the voltage step up time between 0 2 V and 2 7 V at power up is no less than 50 us in order to prevent malfunction in the built in step down circuit Initialization The device contains built in registers which are only initialized by a power on reset Cycle the power supply to initialize these registers Stabilizing the Power Supply Make sure that the Vcc power supply voltage is stable Even at the rated operating Vcc power supply voltage large sudden changes in the voltage could cause malfunctions As a standard for stable power supply keep Vcc ripples peak to peak value at commercial power frequencies 50 Hz to 60 Hz to no more than 10 of the power supply voltage and momentary surges caused by switching the power supply and other events to more than 0 1 V ms If Output from Ports 0 1 Becomes Undefined After power is turned on if the RST pin is set to H during step down circuit stabilization standby during power on reset ports 0 and 1 output will be undefined If the RST pin is set to ports 0 and 1 will go into a high impedance state Take careful note of the timing of events outlined in figures 1 and 2 MB90495G Series Figure 1 Timing Chart
77. t tce internal operating clock cycle time SCK1 SIN1 Notes AC ratings are for CLK synchronous mode is the load capacitor value connected to pins while testing Eternal shift clock mode outputpin C 80 pF 1 TTL MB90495G Series Internal shift clock mode SCK SOT SIN External shift clock mode SCK SOT SIN 0 2 Vcc 0 2 Vcc 77 MB90495G Series 10 Timer Input Timing Voc 5 0 V 5 Vss 0 0 V Ta 40 C to 125 C Vcc 5 0 1096 Vss 0 0 V Ta 40 C to 105 C Value Parameter Symbol Condition Unit Min Max t TINO TIN1 FRCK Input pulse width 4 tcp ns INO to IN3 1 Timer Input Timing TINO TIN1 INO to INS FRCK 11 Timer Output Timing Vcc 5 0 5596 Vss 0 0 V Ta 40 to 125 C Vcc 5 0 V 10 Vss 0 0 V TA 40 to 105 C Parameter Symbol Condition TOTO TOT1 Timer Output Timing 2 4 V CLK TOTO TOT1 24V PPGO to PPG3 0 8 V 12 Trigger Input Timing Vcc 5 0 V 5 Vss 0 0 V Ta 40 C to 125 C Vcc 5 0 V410 Vss 0 0 V Ta 40 C to 105 C Value Parameter Symbol Condition Unit Input pulse width in INTO to INT7 sss idis Trigger Input Timing INTO to INT7 ADTG
78. ter DDR1 The bits making up the register are in a one to one relationship with the port 1 pins Port 1 Register and Corresponding Pins Related register bit and corresponding pin PDR1 DDR1 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bitO Port 1 Corresponding pin P17 P16 P15 P14 P13 P12 P11 P10 MB90495G Series snvnw Port 2 register The port2 register contains the port 2 data register the port 2 direction register DDR2 and the high address control register HACR The high address control register HACR enables or disables the output of external addresses A16 to A23 When the register enables the output of the external addresses the port can not be used as a peripheral device and a general purpose I O port The bits making up the register are in a one to one relationship with the port 2 pins Port 2 Register and Corresponding Pins Related register bit and corresponding pin PDR2 DDR2 HACR Corresponding pin Port 3 register The port3 register contains the port 3 data register PDR3 and the port 3 direction register DDR3 The bus control signal selection register ECSR enables or disables the input and output of external bus control signals WRL WRH HRQ HAK RDY CLK When the register enables the input and output of the external bus control signals the port can not be used as a peripheral device and a general purpose port The bits making up the register are in a
79. tion clock frequency with 16 MHz oscillation clock frequency about 8 19 ms 2 Oscillation stabilization standby time 2 8 oscillation clock frequency with 16 MHz oscillation clock frequency about 16 38 ms MB90495G Series Caution on Operations during PLL Clock Mode If the PLL clock mode is selected in the microcontroller it may attempt to continue the operation using the free running frequency of the automatic oscillating circuit in the PLL circuitry even if the oscillator is out of place or the clock input is stopped Performance of this operation however cannot be guaranteed Support for 125 C If used exceeding Ta 105 C be sure to contact us for reliability limitations 18 MB90495G Series BLOCK DIAGRAM X0 X1 RST X1A SOT SCK1 SIN1 SOTO SCKO SINO AVss ANO to AN7 AVR ADTG Clock control circuit Watch timer ROM FLASH Prescaler UART1 a Prescaler CPU F2MC 16LX Core Internal data bus 8 UARTO 8 10 bit A D converter 8 ch 16 bit free run timer Input capture 4 ch 16 bit PPG timer 2 ch CAN DTP external interrupt circuit 16 bits reload timer 2 ch External bus FRCK INO to INS PPGO to RX TX INTO to INT7 TINO TIN1 TOTO TOT1 ADOO to 015 A16 to A23 ALE RD WRL WRH HRQ HAK RDY CLK MEMORY MB90495G Series
80. um output current is the peak value of one of the corresponding pins The standard for computing average output current is the average current output from one of the corresponding pins over a period of 100 ms the average value is taken by multiplying operating current by operational rate The standard for computing average total output current is the average current output from all of the corre sponding pins over a period of 100 ms the average value is taken by multiplying operating current by operational rate Applicable to pins POO to P07 P10 to P17 P20 to P27 P30 to P37 P40 to P44 P50 to P57 P60 to P63 Use within recommended operating conditions Use at DC voltage current The B signal should always be applied a limiting resistance placed between the B signal and the microcontroller The value of the limiting resistance should be set so that when the B signal is applied the input current to the microcontroller pin does not exceed rated values either instantaneously or for prolonged periods Note that when the microcontroller drive current is low such as in the power saving modes the B input potential may pass through the protective diode and increase the potential at the Vcc pin and this may affect other devices Continued 63 64 MB90495G Series Continued Note that if a B signal is input when the microcontroller power supply is off not fixed at 0 V the power supply is prov
81. unting height 0 25 010 INDEX 0 8 gi 4 C o B 0 50 0 20 0 10 0 10 020 008 004 004 0 60 0 15 Stand off 0 651 026 0 3240 05 0243 008 gt 013 002 0 13 005 69 2003 FUJITSU LIMITED F64018S c 3 5 Dimensions in mm inches Note The values in parentheses are reference values MB90495G Series sn FUJITSU LIMITED All Rights Reserved The contents of this document are subject to change without notice Customers are advised to consult with FUJITSU sales representatives before ordering The information such as descriptions of function and application circuit examples in this document are presented solely for the purpose of reference to show examples of operations and uses of Fujitsu semiconductor device Fujitsu does not warrant proper operation of the device with respect to use based on such information When you develop equipment incorporating the device based on such information you must assume any responsibility arising out of such use of the information Fujitsu assumes no liability for any damages whatsoever arising out of the use of the information Any information in this document including descriptions of function and schematic diagrams shall not be construed as license of the use or exercise of any intellectual property right such as patent right or copyright or any other right of
82. utput 512 HCLK Peripheral clock 1 6 Peripheral clock 2 0 Peripheral clock 4 6 Peripheral clock 8 6 Peripheral clock 16 9 oue clock Select Gam PPGO 1 count clock selection register 01 Output interrupt request lt gt pes pepon Undefined Reserved Reserved bit HCLK Oscillation clock frequency Machine clock frequency Interrupt output from 8 16 bit PPG timer 1 is merged with interrupt request output from PPG timer 0 into a single interrupt via an OR circuit MB90495G Series 8 Delayed Interrupt Generation Module The delayed interrupt generation module generates interrupts for switching tasks This module can be used to generate hardware interrupts from the software Overview of the Delayed Interrupt Generation Module Use the delayed interrupt generation module to generate or cancel hardware interrupts from the software Overview of the Delayed Interrupt Generation Module Functions and Control Interrupt Condition When the RO bit of the delayed interrupt request generation cancel register is set to 1 DIRR 1 Generate interrupt request When the RO bit of the delayed interrupt request generation cancel register is set to 0 DIRR 0 Cancel interrupt request Interrupt number 42 2An Interrupt control There is no enable setting from the register

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