ST PM6681A handbook
Contents
1. PM6681A Figure 10 Standby mode input battery Figure 11 Voltage reference vs load current vs input voltage current 1 2325 SHDN high 1 2320 ENS and ENS low Sas V5SW GND w 2 1 2310 n nc 1 2305 4 ul di 1 2300 nc 1 2295 4 1 2290 3 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 0 20 40 60 80 100 INPUT VOLTAGE V LOAD CURRENT uA Figure 12 OUT1 3 3 V switching Figure 13 OUT2 1 8 V switching frequency frequency 250 SkP 12V 300 PQ SKIP 24V 250 SKIP 24V SKIP 32V SKIP Q 32v NO AUD SKIP Q 12V 5 200 NO AUD SKP Q 12V NOAUD SKIP Q24V 450 NO AUD SKP Q 24V NOAUD SKIP 32V E NO AUD SKP 32V PAM Q12V 100 PAM 12V PWM AV 50 PWM O AV PWM 32V B PWM 32V 0 01 0 10 1 00 10 00 0 01 0 10 100 im Load current A Load current A Figure 14 OUT1 3 3 V load regulation Figure 15 OUT2 1 8 V load regulation gt SKP Q 12V 3330 SKIP2. VREF Internal 1 237 V high accuracy voltage reference It can deliver 50 pA Bypass to SGND with a 100 nF capacitor to reduce noise 7 47 Functional block diagram PM6681A 3 Figure 3 Functional block diagram Functional block diagram REFERENCE GENERATOR ADJUSTABLE LINEAR REGULATOR SMPS CONTROLLER PHASE2 CSENSE2 COMP2 VIN 5V LINEAR REGULATOR LDOS LDOS ENABLE O V58W FB1 OUT1 OUT1 SMPS BOOT1 CONTROLLER HGATE1 O PHASE CSENSE1 COMP1 LGATE1 PGOOD1 STARTUP LDOS ENABLE CONTROLLER TERMIC FAULT TERMIC CONTROLLER 8 47 PM6681A Maximum ratings 4 Maximum ratings Table 3 Absolute maximum ratings Parameter Value Unit V5SW LDO5 to PGND 0 3 to 6 V VIN to PGND 0 3 to 36 HGATEx and BOOTx to PHASEx 0 3 to 6 V PHASEx to PGND 0 6 1 to36 V CSENSEx to PGND 0 6 to 42 V CSENSEx to BOOTx 6 to 0 3 V LGATEx to PGND 0 3 9 to LDO5 40 3 V FBx COMPx SKIP FSEL VREF to SGND LDO FB 0 3 to Vcc 0 3 V PGND to SGND 0 3 to 0 3 V SHDN PGOODx OUTx VCC ENx to SGND 0 3 to 6 V Power dissipation at Ta 25 C 2 8 W Maximum withstanding voltage range test condition VIN 1000 V CDF AEC Q100 002 human body model acceptance criteria normal performance Other pins 2000 1 PHASE to PGND up to 2 5 V fort lt 10 ns 2 LGATE
3. e Place all the sensitive analog signals feedbacks voltage reference and current sense paths on the bottom side of the board or in an inner layer Isolate them from the power top side with a signal ground layer SGND Connect the SGND and PGND plans only in one point a multiple via connection is preferable to a 0 ohm resistor connection near the PGND device pin Place the device on the top or on the bottom size and connect the exposed pad and the SGND pins to the SGND plan see Figure 44 Figure 44 Current paths ground connection and driver traces layout Reduce the AC current paths SGND plan inner layer 1 Device top layer Multiple vias between SGND plan and PGND plan I 4 1 SGND connection to SGND plan Exposed pad connection to SGND Signal traces Top layer PG B pjan SGND p Bottom layer 42 47 SZ PM6681A Layout guidelines As general rule make the high side and low side drivers traces wide and short The high side driver is powered by the bootstrap circuit It s very important to place capacitor CBOOT and diode DBOOT as near as possible to the HGATE pin for example on the layer opposite to the device Route HGATE and PHASE traces as near as possible in order to minimize the area between them The Low side gate driver is powered by the 5 V linear regulator output Placing PGND and LGATE pins near the low side MOSFETS reduces the length of the traces and the crosstal
4. 8 3V 20V 3 3V 290KHz 24V 0 45 2 5 8 2uH We choose standard value L 8 2 uH Ali max 1 16 A O Vin 24 V ILams 2 53 A 39 47 Design guidelines PM6681A Ipeak 2 5 A 0 58 A 3 08 A OUT2 l gAp 2 5 A 35 ripple current 1 8V 24V 1 8V 425KHz 24V 0 35 2 5 4 76uH We choose standard value L 4 7 uH Alt max 0 89 A O Vin 24 V lLams 2 513 A Ipeak 2 5 A 0 443 A 2 943 A 9 8 2 Output capacitor selection We would like to have an output ripple smaller than 25 mV OUT1 POSCAP 4TPE150MI OUT2 POSCAP 6TPE220M 9 8 3 Power MOSFETs OUT1 High side STS5NF60L Low side STS7NF60L OUT2 High side STS5NF60L Low side STS7NF60L 9 8 4 Current limit OUT1 min Al I vatey MIN l oap max 5 4 12A 4 12A HcsENsE 100uA 16 25mO 6700 Let s assume the maximum temperature Tmax 75 C in Rps on calculation OUT2 4 2A 1 Al min ILvatley Min lL oap max aumn 40 47 kr PM6681A Design guidelines 9 8 5 9 8 6 9 8 7 9 8 8 100uA 16 25mQ 6800 HcsENsE Let s assume Tmax 75 C in Rps on calculation Input capacitor Maximum input capacitor RMS current is about 1 1 A Then Icinrms gt 1 1 A We can put two 10 uF ceramic capacitors with lis 1 5 A Synchronous rectifier OUT1 Schottky diode STPS1L40M OUT2 Schottky diode STPS1L40M Integrator loop Refer to Figure 40 OUT1 The ripple
5. 197 PM6681A Dual synchronous step down controller with adjustable LDO Features m 0 9 3 3V LDO adjustable delivers 100 mA 6 V to 36 V input voltage range Adjustable output voltages peak current 5 V LDO delivers 100 mA peak current 1 237 V 1 reference voltage available No Rgense current sensing using low side MOSFETS Ros on Negative current limit Soft start internally fixed at 2 ms Soft output discharge Latched UVP Not latched OVP Selectable pulse skipping at light loads Selectable minimum frequency 33 kHz in pulse skip mode 5 mW maximum quiescent power Independent Power Good signals W Output voltage ripple compensation VFQFPN 32 5 mm x 5 mm Description PM6681A is a dual step down controller specifically designed to provide extremely high efficiency conversion with lossless current sensing technique The constant on time architecture assures fast load transient response and the embedded voltage feed forward provides nearly constant switching frequency operation An embedded integrator control loop compensates the DC voltage error due to the output ripple Pulse skipping technique increases efficiency at very light load Moreover a minimum switching frequency of 33 kHz is selectable to avoid audio noise issues The PM6681A provides a selectable switching frequency allowing three different Applications values of switching frequencies for the two switching sections The out
6. skP Q24V n SKIP 4V se 70 SKIP 32V 70 di SKIP 32V gt 60 NO AUD SKIP 12V 60 NO AUD SKIP 12V 50 NOAUD SKP Q24V 2 50 NO AUD SKIP 24V 24 NOAUD SKP Q3 40 NOAUD SKIP 32V E 30 PWM Q 12V 30 PWM O 12V PWM Q 24V A PWM 24V q Il Pwe o EL PWM 32V 0 001 010 0 100 1 000 10 000 0 001 0 010 0 100 1 000 1 Load current A Load current A Figure 6 PWM no load battery current Figure 7 No audible skip no load vs input voltage battery current vs input voltage 45 00 _ 5 50 lt 40 00 E E E 35 00 Linput E 5 00 Linput ui 30 00 u 450 x x oe 25 00 u oc I EXT5V 2200 SKIP 5V PWM mode 5 400 E 4 gt gt es HEXTSV 23504 SKIP VREF NA SKIP mode 5 00 3 00 TT 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 INPUT VOLTAGE V INPUT VOLTAGE V Figure 8 Skip no load battery current Figure 9 Shutdown mode input battery vs input voltage current vs input voltage 0 90 30 00 n 25 00 0 60 20 00 030 SKIP GND skip mode 1500 5 040 gt O 030 9 1000 SHDN low 5 020 2 ENS and ENS low amp 010 z 50 V5SW GND 7 0 00 0 00 E 3 3 3 3 3 3 3 4 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 INPUT VOLTAGE V INPUT VOLTAGE V 13 47 Typical operating characteristics
7. 1 SGND the signal ground plan of the power supply The signal ground plan and the power ground plan must be connected together in one point near the PGND pin 2 COMP2 DC voltage error compensation pin for the switching section 2 Frequency selection pin It provides a selectable switching frequency 3 FSEL allowing three different values of switching frequencies for the switching sections 5 47 Pin settings PM6681A Table 2 Pin functions continued N Pin Function Enable input for the switching section 2 The section 2 is enabled applying a voltage greater than 2 4 V to this pin 4 EN2 The section 2 is disabled applying a voltage lower than 0 8 V When the section is disabled the high side gate driver goes low and Low Side gate driver goes high If both EN1 and EN2 pins are low and SHDN pin is high the device enters in standby mode Shutdown control input The device switch off if the SHDN voltage is lower than the device off threshold shutdown mode 5 SHDN The device switch on if the SHDN voltage is greater than the device on threshold The SHDN pin can be connected to the battery through a voltage divider to program an undervoltage lockout In shutdown mode the gate drivers of the two switching sections are in high impedance high Z Feedback input for the switching section 2 This pin is connected to a 6 FB2 resistive voltage divider from OUT2 to PGN
8. 24V gt SKIP 32V 2 3325 S NO AUD SKP Q 12V 9 3320 NOAUD SKIP 24V 2 3315 NOAUD SKIP 32V mai NIU E PAM 12V 3310 PAM AV 3305 Pgs 0001 0010 0100 1000 10 000 Load current A 1 820 SKIP Q 12V 1 815 gt SKIP 24V SKIP 32V 23 2 1 805 NO AUD SKIP 12V 1 800 NO AUD SKIP 24V NO AUD SKIP 32V Output Voltage 17 PAM 12V 1 790 PWM 24V PAM 32V 0 001 0 010 0 100 1 000 Load current A 10 000 14 47 7 PM6681A Typical operating characteristics Figure 16 LDO5 vs output current Figure 17 LDO vs output current 4 9890 4 9880 4 9870 4 9860 4 9850 4 9840 4 9830 4 9820 4 9810 4 9800 4 9790 LDO OUPUT VOLTAGE V 0 10 20 30 40 50 60 70 80 90 100 LOAD CURRENT mA 3 3400 3 3390 3 3380 3 3370 3 3360 3 3350 3 3340 3 3330 3 3320 LDO OUTPUT VOLTAGE V 3 3310 3 3300 20 30 40 50 60 70 80 90 100 LOAD CURRENT mA Figure 18 SHDN OUT1 LDO and LDO5 power up Figure 19 OUT1 OUT2 LDO and LDO5 power up a 1
9. 0 25 0 3 D 4 85 5 5 15 D2 See exposed pad variations 2 E 4 85 5 5 15 E2 See exposed pad variations 2 e 0 5 L 0 3 0 4 0 5 ddd 0 05 Table 19 Exposed pad variations D2 E2 Min Typ Max Min Typ Max 2 90 3 10 3 20 2 90 3 10 3 20 1 VFQFPN stands for thermally enhanced very thin fine pitch quad flat package no lead Very thin A 1 00 mm Max 2 Dimensions D2 and E2 are not in accordance with JEDEC r PM6681A Package mechanical data Figure 45 Package dimensions SEATING PLANE AS feb Lu 1 1 il 24 PIN 1 ID ur i R 0 20 32 25 b L e BOTTOM VIEW ky 45 47 Revision history PM6681A 12 46 47 Revision history Table 20 Document revision history Date Revision Changes 02 Nov 2006 1 Initial release 03 Jun 2008 2 p status promoted from Target specification to 26 Jun 2008 3 Updated Figure 1 on page 4 Figure 27 on page 16 Figure 16 and Figure 17 on page 15 PM6681A Please Read Carefully Information in this document is provided solely in connection with ST products STMicroelectronics NV and its subsidiaries ST reserve the right to make changes corrections modifications or improvements to this document and the products and services described herein at any time without notice All ST products are sold pursuant to ST s terms and conditions of sale Purchasers are solely responsible for the choi
10. 9 5 7 to 31 Coilcraft MLC 0 7 to 4 5 13 6 to 17 3 11 5 to 26 TDK RLF12560 1 to 10 7 5 to 14 4 7 5 to 18 5 Output capacitor The selection of the output capacitor is based on the ESR value Rout and the voltage rating rather than on the capacitor value Cout The output capacitor has to satisfy the output voltage ripple requirements Lower inductor value can reduce the size of the choke but increases the inductor current ripple Al Since the voltage ripple VrippLEout IS given by Equation 17 VrippLEout Rout X Al A low ESR capacitor is required to reduce the output voltage ripple Switching sections can work correctly even with 20 mV output ripple However to reduce jitter noise between the two switching sections it s preferable to work with an output voltage ripple greater than 30 mV If lower output ripple is required a further compensation network is needed see Closing the integrator loop paragraph Finally the output capacitor choice deeply impacts on the load transient response see Load transient response paragraph Below there is a list of some capacitor manufacturers 31 47 Design guidelines PM6681A Table 12 Output capacitor manufacturer Manufacturer Series deed value Rated voltage V ESR max m9 SANYO ia c 100 to 470 2 5 to 6 3 12 to 65 Panasonic SPCAP UD UE 100 to 470 2 to 6 3 7 to 18 9 4 Input capacitors selection In a buck topology converter the curren
11. PM6681A Figure 36 Current waveforms in current limit conditions Maximum load current is current DC current limit maximum load influenced by the inductor current ripple Inductor current Valley current threshold Being fixed the valley threshold the greater the current ripple is greater the DC output current is The valley current limit can be set with resistor Resense Equation 7 Rps on sensing technique R _ Roson X Lvalley CSENSE VU s CSENSE Where Icsense 100 HA Ros on is the drain source on resistance of the low side switch Consider the temperature effect and the worst case value in Rpgion calculation The accuracy of the valley current threshold detection depends on the offset of the internal comparator AVorr and on the accuracy of the current generator Alcsense Equation 8 Alvary _ Alcsense n AVorr 100 ARcsense ARsns l valley lcsENsE Rosense 2 lcsENsE CSENSE Rens Where Rgns is the sensing element Rps on PM66814 provides also a fixed negative peak current limit to prevent an excessive reverse inductor current when the switching section sinks current from the load in PWM mode This negative current limit threshold is measured between PHASE and SGND pins comparing the magnitude drop on the PHASE node during the conduction time of the low side MOSFET with an internal fixed voltage of 120 mV The negative valley current limit INEG if the device works in PWM mod
12. compromise between the transient response time the efficiency the cost and the size is to choose the inductor value in order to maintain the inductor ripple current Al between 20 and 50 of the maximum output current l oAp max The maximum Al occurs at the maximum input voltage With this considerations the inductor value can be calculated with the following relationship Equation 13 L Vin Vour Vour fsw X Al Vin where fs is the switching frequency V n is the input voltage Vour is the output voltage and AIL is the selected inductor ripple current In order to prevent overtemperature working conditions inductor must be able to provide an RMS current greater than the maximum RMS inductor current I rms Equation 14 Al max luRMs iowa 12 Where Al may is the maximum ripple current PM6681A Design guidelines 9 3 Equation 15 Al _ Vinmax Vour x Vour max Toy xL Vin max If hard saturation inductors are used the inductor saturation current should be much greater than the maximum inductor peak current Ipea Equation 16 Al max Ipeak ILoaD max 2 Using soft saturation inductors it s possible to choose inductors with saturation current limit nearly to Ipeak Below there is a list of some inductor manufacturers Table 11 Inductor manufacturer Manufacturer S ries Inductor value RMS current Saturation current uH A A Coilcraft SER1360 1108 6 to
13. is a list of some possible low side MOSFETS 33 47 Design guidelines PM6681A Table 15 Low side MOSFET manufacturer Manufacturer Type Rps on MO es Rated reverse voltage V ST STS17NF3LL 5 5 0 047 30 ST STS25NH3LL 3 5 0 011 30 Dual N channel MOSFETS can be used in applications with a maximum output current of about 3 A Below there is a list of some MOSFET manufacturers Table 16 Dual MOSFET manufacturer Manufacturer Type Rps on MQ Gate charge nC Rated reverse voltage V ST STS8DNH3LL 25 10 30 ST STS4DNF60L 65 32 60 A rectifier across the low side MOSFET is recommended The rectifier works as a voltage clamp across the synchronous rectifier and reduces the negative inductor swing during the dead time between turning the high side MOSFET off and the synchronous rectifier on It can increase the efficiency of the switching section since it reduces the low side switch losses A Schottky diode is suitable for its low forward voltage drop 0 3 V The diode reverse voltage must be greater than the maximum input voltage Vinmax minimum recovery reverse charge is preferable Below there is a list of some Schottky diode manufacturers Table 17 Schottky diode manufacturer Manufacturer Series Forward voltage Rated reverse voltage Reverse current V V uA ST STPS1L30M 0 34 30 0 00039 ST STPS1L20M 0 37 20 0 000075 9 6 Closing the
14. is smaller than 40mV then the virtual ESR network is required Cint 1 NF Ca 47 pF Rinr 1 KO C 25 6nF R 36 KQ RI 3 kQ OUT2 The ripple is smaller than 40mV then the virtual ESR network is required Cint 1 nF Cg 110 pF Rint 1 KQ C 5 6 nF R 22 KQ R12 8 3 kQ Output feedback divider Refer to Figure 32 OUT1 R1 10 KQ R2 6 8 kO OUT2 R1 11 KQ R2 1 8 KQ 41 47 Layout guidelines PM6681A 10 Layout guidelines The layout is very important in terms of efficiency stability and noise of the system It is possible to refer to the PM6681A demonstration board for a complete layout example For good PC board layout follows these guidelines e Placeonthe top side all the power components inductors input and output capacitors MOSFETs and diodes Refer them to a power ground plan PGND If possible reserve a layer to PGND plan The PGND plan is the same for both the switching sections e AC current paths layout is very critical see Figure 44 The first priority is to minimize their length Trace the LS MOSFET connection to PGND plan with or without current sense resistor RSENSE as short as possible Place the synchronous diode D near the LS MOSFET Connect the L8 MOSFET drain to the switching node with a short trace e Place input capacitors near HS MOSFET drain It is recommended to use the same input voltage plan for both the switching sections in order to put together all input capacitors
15. mA 4 9 5 0 5 1 V LDOS line regulation 6 V lt VIN lt 36 V I_po5 20 mA 0 004 V ILDos LDOS current limit Vi pos gt UVLO 270 330 400 mA Under voltage lockout of ULVO LDOS 3 94 4 4 13 V LDO linear regulator 4 5 V lt V5BSW lt 5 5 V Vi po LDO linear output voltage 0 5 mA lt lj po lt 50 mA 0 887 10 905 0 923 V LDO FB connected to LDO ky 11 47 Electrical characteristics PM6681A Table 6 Electrical characteristics Vin 24 V Ty 25 C unless otherwise specified continued Symbol Parameter Test condition Min Typ Max Unit ILDO LDO current limit 170 220 270 mA liporg Input bias current 1 0 1 UA High and low gate drivers HGATEx high state pull up 2 0 3 HGATE driver on resistance HGATEx low state pull down 1 6 2 7 Q LGATEx high state pull up 1 4 2 1 LGATE driver on resistance LGATEx low state pull down 0 8 1 2 PGOOD pins UVP OVP protections Both SMPS sections with OVP Over voltage threshold respect to VREF OUT1 5 V 112 116 120 96 OUT2 3 3 V UVP Under voltage threshold 65 68 71 Upper threshold 107 110 113 96 VFB VREF PGOOD1 2 1 an ower thresho 88 91 94 VFB VREF IpgooD1 2 PGOOD leakage current VPGoop1 2 forced to 5 5 V 1 uA VPGoop1 2 output low voltage Isink 4 MA 150 250 mV Power management pins SMPS disabled level 1 0 8 EN1 2 V SMPS
16. 00 vidi 1 00 vidiv 1 00 rai 1 00 Vidiv 2 0000 V 4 0000 V 3 0000 V 2 0000 V 1 00 msi Normal 299V 1 00MS 100 MS sfEdge Positive Figure 20 OUT1 3 3 V load transient 0to2A Figure 21 OUT2 1 8 V load transient 0to2A a imebase 44 4 ug Trigger gj 20 0 Vidiy 100 mai 1 00 Aldi 20 0 psidiv Stop 1 684 80 00 V orc 1 5000 1200 oouo ilese E Pois 15 47 Typical operating characteristics PM6681A 16 47 Figure 22 3 3 V soft start 1 load Figure 23 1 8 V soft start 0 6 load Figure 24 OUT123 3V soft end no load Figure 25 OUT2 1 8 V soft end no load Figure 26 OUT1 3 3 V soft end 0 8 Q load Figure 27 OUT2 1 8 V soft end 0 6 O load 7 PM6681A Typical operating characteristics Figure 28 3 3 V no audible skip mode Figure 29 1 8 V no audible skip mode our 17 47 Device description PM6681A 7 7 1 18 47 Device description The PM6681A is a dual step down controller dedicated to provide logic voltages for industrial automation application and notebook computer It is based on a constant on time control architecture This type of control offers a very fast load transient response with a minimum external component count A typical application circuit is shown in Figure 1 The PM66814 regul
17. D to adjust the output voltage from 0 9 V to 3 3 V 7 LDO Adjustable internal regulator output It can be set from 0 9 V to 3 3 V LDO pin can provide a 100 mA peak current Output voltage sense for the switching section 2 This pin must be directly 8 OUT2 nb connected to the output voltage of the switching section Bootstrap capacitor connection for the switching section 2 It supplies the 9 BOOT2 high side gate driver 10 HGATE2 High side gate driver output for section 2 This is the floating gate driver output Switch node connection and return path for the high side driver for the 11 PHASE2 section 2 It is also used as negative current sense input Positive current sense input for the switching section 2 This pin must be connected through a resistor to the drain of the synchronous rectifier 12 CSENSE2 z E Rps on sensing to obtain a positive current limit threshold for the power supply controller 13 LGATE2 Low side gate driver output for the section 2 14 PGND Power ground This pin must be connected to the power ground plan of the power supply 15 LGATE1 Low side gate driver output for the section 1 Feedback input for the adjustable internal linear regulator This pin is 16 LDO FB connected to a resistive voltage divider from LDO to SGND to adjust the output voltage from 0 9 V to 3 3 V Internal 5 V regulator bypass connection If V5SW is connected to OUTS or to an external 5 V supply and V5SW is 17 V5SW great
18. OMP pin is given by Equation 28 C u INT _ VRIPPLE VRIPPLEout X Qu m VriPPLEout X 4 INT Lit Where VRIPPLEout is the output ripple and q is the attenuation factor of the output ripple If the ripple is very small lower than approximately 30 mV a further compensation network named virtual ESR network is needed This additional part generates a triangular ripple that is added to the ESR output voltage ripple at the input of the integrator network The complete control schematic is represented in Figure 40 Figure 40 Virtual ESR network COMP PIN VOLT AGE TNODE VOLTAGE OUTPUT VOLTAGE Pa oh sa COMP ui c E PWM INT Comparator Vr Vi OUT Re FB D AEE AMO00519v1 The T node voltage is the sum of the output voltage and the triangular waveform generated by the virtual ESR network In fact the virtual ESR network behaves like a further equivalent ESR Resp A good trade off is to design the network in order to achieve an Resp given by Equation 29 R _ VRIPPLE R ESR AI out L PM6681A Design guidelines where Al is the inductor current ripple and VRIPPLE is the overall ripple of the T node voltage It should be chosen higher than approximately 30 mV The new closed loop gain depends on Cinr In order to ensure stability it must be verified that Equation 30 m Vr NI
19. RE NOT SPECIFIED AS AUTOMOTIVE GRADE MAY ONLY BE USED IN AUTOMOTIVE APPLICATIONS AT USER S OWN RISK Resale of ST products with provisions different from the statements and or technical features set forth in this document shall immediately void any warranty granted by ST for the ST product or service described herein and shall not create or extend in any manner whatsoever any liability of ST ST and the ST logo are trademarks or registered trademarks of ST in various countries Information in this document supersedes and replaces all information previously supplied The ST logo is a registered trademark of STMicroelectronics All other names are the property of their respective owners 2008 STMicroelectronics All rights reserved STMicroelectronics group of companies Australia Belgium Brazil Canada China Czech Republic Finland France Germany Hong Kong India Israel Italy Japan Malaysia Malta Morocco Singapore Spain Sweden Switzerland United Kingdom United States of America www st com 47 47 4
20. T Sixt Vout Where Equation 31 f 2n x Cout Rror where Rror is the sum of the ESR of the output capacitor Rout and the equivalent ESR given by the virtual ESR network Resp Moreover CNT must meet the following condition Equation 32 k 20 Cout XRror T gt kxfz Where k is a free design parameter greater than 3 and determines the minimum integrator capacitor value Cinr Equation 33 C must be selected as shown Equation 34 C gt 5x Cint R must be chosen in order to have enough ripple voltage on integrator input Equation 35 L Bare Regen x C R1 can be selected as follows 37 47 Design guidelines PM6681A Equation 36 ub 1 R1 EIE B 1 Cxnxf Example OUT 1 5 V fsw 290 kHz L 2 5 uH Cout 330 uF with Rout 12 mQ We design Resp 12 MO We choose Cyr 1 nF by equations 31 34 and C 47 pF Rinr 1 KO by eq 28 29 C 5 6 nF by Eq 35 Then R 36 kO eq 36 and R1 3 kQ eq 37 9 7 Other parts design e VIN filter A VIN pin low pass filter is suggested to reduce switching noise The low pass filter is shown in the next figure Figure 41 VIN pin filter R o VIN At 4 AM00520V1 Typical components values are R 3 9 Q and C 4 7 uF e VCC filter A VCC low pass filter helps to reject switching commutations noise Figure 42 Inductor current waveforms 38 47 PM6681A Design g
21. also to an external 5 V supply LDOS regulator turns off and LDOS is supplied externally If V5SW is connected to ground the internal 5 V regulator is always on and supplies LDOS output PM6681A Device description Table 8 V5SW multifunction pin V5SW Description GND The 5 V linear regulator is always turned on and supplies LDOS output Switching 5 V The 5 V linear regulator is turned off when the voltage on V5SW is above 4 8 V and output LDO5 output is supplied by the switching 5 V output External 5 V The 5 V linear regulator is turned off when the voltage on V5SW is above 4 8 V and supply LDO5 output is supplied by the external 5 V The adjustable linear regulator is supplied by LDOS output It turns on after LDO5 power up sequence It can provide up to 100 mA peak current Set up the feedback resistor divider according to the following formula to regulate a voltage from 0 9 V to 3 3 V Equation 12 down R LDO V m where LDO is the desired output voltage Vr 0 9 V is the internal reference voltage and Rup and Rgown are the resistors of the feedback divider as shown in Figure 38 Figure 38 LDO linear regulator AM00517v1 Bypass LDO5 and LDO output with 1 10 uF ceramic capacitor and a 4 7 uF tantalum capacitor ESR gt 2 Q 27 47 Device description PM6681A 7 10 28 47 Power up sequencing and operative modes Let s consider SHDN EN1 and EN 2 low
22. at the beginning The battery voltage is applied as input voltage The device is in shutdown mode When the SHDN pin voltage is above the shutdown device on threshold 1 5 V typ the controller begins the power up sequence All the latched faults are cleared LDO5 undervoltage control is blanked for 4 ms and the internal regulator LDOS turns on If the LDOS output is above the UVLO threshold after this time the device enters in standby mode and the adjustable internal linear regulator LDO is turned on The switching outputs are kept to ground by turning on the low side MOSFETs When EN1 and EN2 pins are forced high the switching sections begin their soft start sequence Table 9 Operative modes Mode Conditions Description Run SHDN is high Switching regulators are enabled internal linear ENT EN2 pins are high regulators outputs are enabled Internal linear regulators active LDOS is always on In Standby Hs eius low standby mode LGATE1 LGATEZ pins are forced high P 9 while HGATE1 HGATEZ pins are forced low Shutdown SHDN is low All circuits off PM6681A Monitoring and protections 8 8 1 8 2 8 3 8 4 Monitoring and protections Power Good signals The PM6681A provides three independent Power Good signals one for each switching section PGOOD1 PGOOD2 PGOOD1 PGOOD2 signals are low if the output voltage is out of 10 of the designed set point or during the soft start standby and shut
23. ates two adjustable output voltages OUT1 and OUT2 The switching frequency of the two sections can be adjusted to three different values In order to maximize the efficiency at light load condition a pulse skipping mode can be selected The PM6681A includes also a 5 V linear regulator LDO5 that can power the switching drivers If the output OUT1 regulates 5 V in order to maximize the efficiency in higher consumption status the linear regulator can be turned off and their outputs can be supplied directly from the switching outputs Moreover the PM66814 includes also a linear regulator with an output voltage adjustable from 0 9 V to 3 3 V It can provide 100 mA of peak current The PM6681A provides protection versus overvoltage undervoltage and overtemperature as well as Power Good signals for monitoring purposes An external 1 237 V reference is available Constant on time PWM control If the SKIP pin is tied to 5 V the device works in PWM mode Each power section has an independent on time control The PM6681A employees a pseudo fixed switching frequency constant on time COT controller as core of the switched mode section Each power section has an independent COT control The COT controller is based on a relatively simple algorithm and uses the ripple voltage due to the output capacitor s ESR to trigger the fixed on time one shot generator In this way the output capacitor s ESR acts as a current sense resistor providing the appropriate
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25. d PHASE pins work respectively as supply and return rails for the HS driver The low side driver uses the internal LDOS output for the supply rail and PGND pin as return rail An important feature of the gate drivers is the adaptive anti cross conduction protection which prevents high side and low side MOSFETs from being on at the same time When the 25 47 Device description PM6681A 7 9 26 47 high side MOSFET is turned off the voltage at the phase node begins to fall The low side MOSFET is turned on when the voltage at the phase node reaches an internal threshold When the low side MOSFET is turned off the high side remains off until the LGATE pin voltage goes approximately under 1 V The power dissipation of the drivers is a function of the total gate charge of the external power MOSFETs and the switching frequency as shown in the following equation Equation 11 Pariver Variver Q x fsw Where Variver is the 5 V driver supply Reference voltage and bandgap The 1 237 V typ internal bandgap voltage is accurate to 1 over the temperature range It is externally available VREF pin and can supply up to 100 uA and can be used as a voltage threshold for the multifunction pins FSEL and SKIP to select the appropriate working mode Bypass VREF to ground with a 100 nF minimum capacitor If VREF goes below 0 87 V typ the system detects a fault condition and all the circuitry is turned off A toggle on the input vol
26. down mode Thermal protection The PM6681A has a thermal protection to preserve the device from overheating The thermal shutdown occurs when the die temperature goes above 150 C In this case all internal circuitry is turned off and the power sections are turned off after the discharge mode A power on reset or a toggle on the SHDN pin is necessary to restart the device Overvoltage protection When the switching output voltage goes over the OVP threshold about 116 of its nominal value the low side MOSFET turns on The L8 MOSFET is kept on until the output voltage returns under the OVP threshold Undervoltage protection When the switching output voltage is below 70 of its nominal value a latched undervoltage protection occurs In this case the switching section is immediately disabled and both switches are open The controller enters in soft end mode and the output is eventually kept to ground turning low side MOSFET on The undervoltage circuit protection is enabled only at the end of the soft start Once an overvoltage protection has been detected a toggle on SHDN EN1 EN2 pin or a power on reset is necessary to clear the undervoltage fault and starts with a new soft start phase Table 10 Protections and operatives modes Mode Conditions Description LGATE1 LGATE2 pin is forced high until the output voltage is over the OVP threshold LDO5 remains active LGATE1 LGATE2 is forced high after the soft end mode LDO5 r
27. e is given by Equation 9 24 47 SZ PM6681A Device description 7 7 7 8 soft start and soft end Each switching section is enabled separately by asserting high EN1 EN2 pins respectively In order to realize the soft start at the startup the overcurrent threshold is set 25 of the nominal value and the undervoltage protection see related sections is disabled The controller starts charging the output capacitor working in current limit The overcurrent threshold is increased from 25 to 100 of the nominal value with steps of 25 every 700 us typ After 2 8 ms typ the undervoltage protection is enabled The s oft start time is not programmable A minimum capacitor Cinr is required to ensure a soft start without any overshoot on the output Equation 10 6uA IL valley AL 4 2 Cir Cou Figure 37 Soft start waveforms Switching Current limit threshold EN1 EN2 When a switching section is turned off EN1 EN2 pins low the controller enters in soft end mode The output capacitor is discharged through an internal 18 Q P MOSFET switch when the output voltage reaches 0 3 V the low side MOSFET turns on keeping the output to ground The soft end time also depends on load condition Gate drivers The integrated high current drivers allow to use different power MOSFETs The high side driver MOSFET uses a bootstrap circuit which is indirectly supplied by LDOS output The BOOT an
28. emains active Exit by a power on reset or toggling SHDN or ENT EN2 Overvoltage OUT1 OUT2 gt 115 of protection the nominal value Undervoltage OUT1 OUT2 70 96 of the protection nominal value Thermal shutdown All circuitry off Exit by a POR on VIN or toggling TJ 150 C SHDN 29 47 Design guidelines PM6681A 9 9 1 9 2 30 47 Design guidelines The design of a switching section starts from two parameters e Input voltage range in notebook applications it varies from the minimum battery voltage Vinmin to the AC adapter voltage Vinmax e Maximum load current it is the maximum required output current l oAp max Switching frequency It s possible to set 3 different working frequency ranges for the two sections with FSEL pin table 1 Switching frequency mainly influences two parameters e Inductor size for a given saturation current and RMS current greater frequency allows to use lower inductor values which means smaller size e Efficiency switching losses are proportional to frequency High frequency generally involves low efficiency Inductor selection Once that switching frequency is defined inductor selection depends on the desired inductor ripple current and load transient performance Low inductance means great ripple current and could generate great output noise On the other hand low inductor values involve fast load transient response A good
29. enabled level m 2 4 Frequency selection range Low level 1 0 5 ESEL Middle level 1 1 0 ibo Hag 1 Vipos High level 0 8 Pulse skip mode 1 0 5 1 Vipos SKIP Ultrasonic mode 1 0 15 V 1 Vipos PWM mode 0 8 Ven1 2 0to5V 1 V KIP Oto5V 1 Input leakage current uA Vaupu 0t05 V 1 Vesp 0 t0 5 V 1 1 by design 12 47 577 PM6681A Typical operating characteristics 6 Typical operating characteristics FSEL GND 200 300 kHz SKIP GND skip mode V5SW EXT5 V external 5 V power supply connected input voltage VIN 24 V SHDN EN1 and EN2 high OUT1 3 3 V OUT2 1 8 V no load LDO 3 3 V LDO FB divider 5 6 k and 15 k unless specified Figure 4 Efficiency vs current load Figure 5 Efficiency vs current load OUT1 3 3V Efficiency OUT2 1 8V Efficiency a SKP 12V 100 SKIP Q 12V n
30. ent doesn t cross the zero and the device works in the same way as in PWM mode and the frequency is fixed to the nominal value Figure 33 PWM and pulse skip mode inductor current PWM mode Pulse skip mode Low side on Inductor current Tont Ton2 Low side off AMO00515v1 Figure 33 shows inductor current waveforms in PWM and SKIP mode In order to keep average inductor current equal to load current in SKIP mode some switching cycles are skipped When the output ripple reaches the regulated voltage Vreg a new cycle begins The off cycle duration and the switching frequency depend on the load condition As a result of the control technique losses are reduced at light loads improving the system efficiency No audible skip mode If SKIP pin is tied to VREF a no audible skip mode with a minimum switching frequency of 33 kHz is enabled At light load condition If there is not a new switching cycle within a 30 us typ period a no audible skip mode cycle begins Figure 34 No audible skip mode Inductor current No audible skip mode 30us PM6681A Device description 7 6 The low side switch is turned on until the output voltage crosses about Vreg 1 Then the high side MOSFET is turned on for a fixed on time period Afterwards the low side switch is enabled until the inductor current reaches the zero crossing threshold This keeps the switching frequency higher than 33
31. er than 4 9 V the LDOS regulator shuts down and the LDOS pin is directly connected to OUT5 through a 3 W max switch If VESW is connected to GND the LDOS linear regulator is always on if the device is not in shutdown mode 6 47 572 PM6681A Pin settings Table 2 Pin functions continued N 18 Pin LDO5 Function 5 V internal regulator output It can provide up to 100 mA peak current LDOS pin supplies embedded low side gate drivers and an external load 19 VIN Device supply voltage input and battery voltage sense A bypass filter 4 W and 4 7 uF between the battery and this pin is recommended 20 CSENSE1 Positive current sense input for the switching section 1 This pin must be connected through a resistor to the drain of the synchronous rectifier Rps on Sensing to obtain a positive current limit threshold for the power supply controller 21 PHASE1 Switch node connection and return path for the high side driver for the section 1 It is also used as negative current sense input 22 HGATE1 High side gate driver output for section 1 This is the floating gate driver output 23 BOOT1 Bootstrap capacitor connection for the switching section 1 It supplies the high side gate driver 24 SKIP Pulse skipping mode control input If the pin is connected to LDO5 the PWM mode is enabled If the pin is connected to GND the p
32. integrator loop The design of external feedback network depends on the output voltage ripple If the ripple is higher than approximately 30 mV the feedback network Figure 39 is usually enough to keep the loop stable 34 47 ky PM6681A Design guidelines Figure 39 Circuitry for output ripple compensation COMP PIN VOLTAGE OUTPUT VOLTAGE AMO00518v1 The stability of the system depends firstly on the output capacitor zero frequency The following condition should be satisfied Equation 24 k fon gt K Tout 2nxC xR out out where k is a design parameter greater than 3 and Roy is the ESR of the output capacitor It determinates the minimum integrator capacitor value Cj Equation 25 Om Vr Cr gt x where gm 50 us is the integrator trans conductance In order to ensure stability it must be also verified that Equation 26 Vr x Vour m Cor gt Dr xt T X Tout In order to reduce ground noise due to load transient on the other section it is recommended to add a resistor Rin and a capacitor Cg that together with Cinr realize a low pass filter see Figure 39 The cutoff frequency four must be much greater 10 or more times than the switching frequency of the section 35 47 Design guidelines PM6681A 36 47 Equation 27 1 Cint x Cin Cur Crit Rint 2nx four x Due to the capacitive divider Cint Cri the ripple voltage at the C
33. itching frequency increases as a function of the load current Standard switching frequency values can be selected for both sections by connecting pin FSEL to SGND VREF or LDOS pin The following table shows the typical switching frequencies that can be obtained as a function of the programmed output voltage The measures are referred to switching sections with 2 A load 12 V input voltage and working in continuous conduction mode Table 7 FSEL pin selection typical switching frequency Fsw OUT1 1 5 V kHz Fsw OUT2 1 05 V kHz FSEL GND 200 325 FSEL VREF 290 425 FSEL LDO5 390 590 ky 19 47 Device description PM6681A 7 2 7 3 20 47 Constant on time architecture Figure 31 shows the simplified block diagram of a constant on time controller A minimum off time constrain 350 ns typ is introduced to allow inductor valley current sensing on synchronous switch A minimum on time 130 ns is also introduced to assure the start up switching sequence PM6681A has a one shot generator for each power section that turns on the high side MOSFET when the following conditions are satisfied simultaneously the PWM comparator is high the synchronous rectifier current is below the current limit threshold and the minimum off time has timed out Once the on time has timed out the high side switch is turned off while the synchronous Switch is turned on according to the anti cross conduction circuitry
34. k noise between the two sections The linear regulator output LDOS is referred to SGND as long as the reference voltage Vref Place their output filtering capacitors as near as possible to the device Place input filtering capacitors near VCC and VIN pins It would be better if the feedback networks connected to COMP FB and OUT pins are referred to SGND in the same point as reference voltage Vref To avoid capacitive coupling place these traces as far as possible from the gate drivers and phase switching paths Place the current sense traces on the bottom side If low side MOSFET Rps on sensing is enabled use a dedicated connection between the switching node and the current limit resistor RcsENsE 43 47 Package mechanical data PM6681A 11 44 47 Package mechanical data In order to meet environmental requirements ST offers these devices in ECOPACK9 packages These packages have a lead free second level interconnect The category of second Level Interconnect is marked on the package and on the inner box label in compliance with JEDEC Standard JESD97 The maximum ratings related to soldering conditions are also marked on the inner box label ECOPACK is an ST trademark ECOPACK specifications are available at www st com Table 18 VFQFPN32 5 x 5 x 1 0 mm pitch 0 50 Databook mm Dim Min Typ Max A 0 8 0 9 1 A1 0 0 02 0 05 A3 0 2 0 18
35. kHz As a consequence of the control the regulated voltage can be slightly higher than Vreg up to 1 96 If due to the load the frequency is higher than 33 kHz the device works like in skip mode No audible skip mode reduces audio frequency noise that may occur in pulse skip mode at very light loads keeping the efficiency higher than in PWM mode Current limit The current limit circuit employs a valley current sensing algorithm During the conduction time of the low side MOSFET the current flowing through it is sensed The current sensing element is the low side MOSFET on resistance Figure 35 Figure 35 Rps on Sensing technique RCSENSE CSENSE Rbs on AMO0516v1 An internal 100 uA current source is connected to CSENSE pin and determines a voltage drop on Rcsense If the voltage across the sensing element is greater than this voltage drop the controller doesn t initiate a new cycle A new cycle starts only when the sensed current goes below the current limit Since the current limit circuit is a valley current limit the actual peak current limit is greater than the current limit threshold by an amount equal to the inductor ripple current Moreover the maximum output current is equal to the valley current limit plus half of the inductor ripple current Equation 6 Al lLoap Max livalley E The output current limit depends on the current ripple as shown in Figure 36 23 47 Device description
36. management When the negative input voltage at the PWM comparator Figure 31 which is a scaled down replica of the output voltage see the external R1 R2 divider in Figure 32 reaches the valley limit determined by internal reference Vr 0 9 V the low side MOSFET is turned off according to the anti cross conduction logic once again and a new cycle begins Figure 31 Constant on time block diagram Toff min CSENSE Positive Current Limit COMP Vr Zero cross C OUT w Comp gt AMOOS13v1 Output ripple compensation and loop stability In a classic constant on time control the system regulates the valley value of the output voltage and not the average value as shown in Figure 30 In this condition the output voltage ripple is source of a DC static error To compensate this error an integrator network can be introduced in the control loop by connecting the output voltage to the COMP1 COMP2 for the OUT1 and OUT2 sections respectively pin through a capacitor CINT as in Figure 32 572 PM6681A Device description Figure 32 Circuitry for output ripple compensation COMP PIN VOLTAGE OUTPUT VOLTAGE PWM Comparator VCwr OUT R2 Ri AMO00514v1 The integrator amplifier generates a current proportional to the DC errors between the FB voltage and Vr which decreases the output vol
37. mas rx cm RR Xa een 40 9 8 5 Input capacitor sx sa ssa de xm mm as dus dun xar edens 41 9 8 6 Synchronous rectifier 41 9 8 7 Integrator loop 41 9 8 8 Output feedback divider 41 10 Layout guidelines iius eR RRRECAE X 3 eee eed Rd ha nas 42 11 Package mechanical data 44 12 Revision history uuo so ge un nun T C CR nun 46 y 3 47 Simplified application schematic PM6681A 1 Simplified application schematic Figure 1 Application schematic 4 47 SZ PM6681A Pin settings 2 Pin settings 2 1 Connections Figure 2 Pin connection top view v v lt o Q Q E S8 a 8 8 8 132 131 127 na I 1 l rsa uud l SGND SKIP COMPS i BOOT1 re i HGATE1 EN2 l PHASE1 i PM6681A SHDN l CSENSE1 FB2 VIN LDO LDO5 OUT2 V5SW 3 o i a o 9 o 5 2 2 Functions Table 2 Pin functions N Pin Function Signal ground Reference for internal logic circuitry It must be connected to
38. put voltages OUT1 m Embedded computer system and OUT2 can be adjusted from 0 9 V to 5 V and m FPGA system power from 0 9 V to 3 3 V respectively The device us provides also 2 LDOs 5 V fixed and 0 9 V 3 3 V m industrial applications on 24 V adjustable m High performance and high density DC DC modules m Notebook computer Table 1 Order codes Order codes Package Packaging PM6681A VFQFPN 32 5 mm x 5 mm Tray PM6681ATR exposed pad Tape and reel June 2008 Rev 3 1 47 www st com Contents PM6681A Contents 1 Simplified application schematic 4 2 Pin SGUINGS svi Tr ce eect a a biais 5 2 1 Connections yeu cnc ewe UR A ee ae Nes SAR ele eee ee eee 5 2 2 Functions 5 3 Functional block diagram 8 4 Maximum ratings lt cssccccs 00 en 9 5 Electrical characteristics 10 6 Typical operating characteristics 13 7 Device description mu 22cm RREREEREEE A REX RE RETE 18 7 1 Constant on time PWM control 18 7 2 Constant on time architecture 20 7 8 Output ripple compensation and loop stability 20 7 4 Pulse skip mode s ua ecce RR ERR ERR ERES EDU wee pened 21 7 5 No audible skip Mode 5s b kr ss da pad RE ER EA 22 7 8 CEM DTE ruo nuire Reg dise i
39. r p acad rides ar dede acit A Ed 23 7 7 soft start and soft end 25 fo BUB CHUBIS passou des efa dd een edu camden RE 25 7 9 Internal linear regulators 26 7 10 Power up sequencing and operative modes 28 8 Monitoring and protections 29 8 1 Power good signals 5244 oix RS Rc E dei da ind EA dit 29 8 2 Thermal protection ssa 40 48 20 RARE REX EC REC essa ia RE PAR dd 29 8 3 Overvollage protection a ius ed ddseRERISI rRePReRESBRPR PERS 29 8 4 Undervoltage protection 2 ssp RR EE RRESZESDRER EGRE ERE ee 29 2 47 SZ PM6681A Contents 9 Design guidelines 4 3 8 8 RR date dde en e RC ads 30 9 1 Switching frequency sss ke RR eve eda have a dr ae ana ans 30 9 2 Inductor selection D en pias UES eels 30 93 Outputcapacitor are Ro LITE CHOR RR EE phe vanes 31 9 4 Input capacitors selection sus ima matr FR pads aaa 32 9 5 Power MOSFETS ee he boi eak IE eana eoa atra sinos E 32 9 6 Closing the integrator loop 34 9 7 Other parts design 38 9 8 Design example xs4 cres 4x ae Be na teen 39 9 8 1 Inductor selection 39 9 8 2 Output capacitor selection 40 9 8 3 Power MOSFEIS seas ga vee Ferd AC eh doe wa ates RORIS X 40 9 8 4 C rrent limil so
40. ramp signal to the PWM comparator On time one shot duration is directly proportional to the output voltage sensed at the OUT1 OUT2 pins and inversely proportional to the input voltage sensed at the VIN pin as follows Equation 1 Vout T K on Vin This leads to a nearly constant switching frequency regardless of input and output voltages When the output voltage goes lower than the regulated voltage Vreg the on time one shot generator directly drives the high side MOSFET for a fixed on time allowing the inductor current to increase after the on time an off time phase in which the low side MOSFET is turned on follows Figure 30 shows the inductor current and the output voltage waveforms in PWM mode PM6681A Device description Figure 30 Constant on time PWM control AM00512v1 Inductor current Output voltage Vreg Tor Toff t The duty cycle of the buck converter in steady state is Equation 2 D Vout Vin The PWM control works at a nearly fixed frequency few Equation 3 Vout a m gt p Ton Kon X Vout on Vin As mentioned the steady state switching frequency is theoretically independent from battery voltage and from output voltage Actually the frequency depends on parasitic voltage drops that are present during the charging path high side switch resistance inductor resistance DCR and discharging path low side switch resistance DCR As a result the sw
41. t that flows into the input capacitor is a pulsed current with zero average value The input RMS current of the two switching sections can be roughly estimated as follows Equation 18 Icinams yD xl x 1 D4 Da x13 x 1 Da Where D1 D2 are the duty cycles and l1 I2 are the maximum load currents of the two sections Input capacitor should be chosen with an RMS rated current higher than the maximum RMS current given by both sections Tantalum capacitors are good in term of low ESR and small size but they occasionally can burn out if subjected to very high current during the charge Ceramic capacitors have usually a higher RMS current rating with smaller size and they remain the best choice Below there is a list of some ceramic capacitor manufacturers 9 5 32 47 Table 13 Input capacitor manufacturer Manufacturer Series Capacitor value uF Rated voltage V Tayio yuden UMK432 X5506MM T 10 50 TDK C3225X5R1E106M 10 25 Power MOSFETs Logic level MOSFETs are recommended since low side and high side gate drivers are powered by LDOS Their breakdown voltage VBRpss Must be higher than Vinmax In notebook applications power management efficiency is a high level requirement The power dissipation on the power switches becomes an important factor in switching selections Losses of high side and low side MOSFETs depend on their working conditions The power dissipation of the high side MOSFET is given b
42. tage power on reset or a toggle on SHDN pin is necessary to restart the device An internal divider of the bandgap provides a voltage reference Vr of 0 9 V This voltage is used as reference for the linear and the switching regulators outputs The overvoltage protection the undervoltage protection and the Power Good signals are referred to Vr Internal linear regulators The PM6681A has two linear regulators providing respectively 5 V LDO5 and an adjustable voltage LDO at 2 accuracy High side drivers low side drivers and MOSFETs of internal circuitry are supplied by LDO5 output through VCC pin an external RC filter may be applied between LDO5 and VCC The linear regulator can provide an average output current of 50 mA and a peak output current of 100mA Bypass LDOS output with a minimum 1 uF ceramic capacitor and a 4 7 uF tantalum capacitor ESR gt 2 Q If the 5 V output goes below 4 V the system detects a fault condition and all the circuitry is turned off A power on reset or a toggle on SHDN pin is necessary to restart the device V5SW pin allows to keep the 5 V linear regulator always active or to enable the internal bootstrap switch over function if the 5 V switching output is connected to V5SW when the voltage on V5SW pin is above 4 8 V an internal 3 0 O max P channel MOSFET switch connects V5SW pin to LDOS pin and simultaneously LDO5 shuts down This configuration allows to achieve higher efficiency V5SW can be connected
43. tage in order to compensate the total static error including the voltage drop on PCB traces In addition CINT provides an AC path for the output ripple In steady state the voltage on COMP1 COMP2 pin is the sum of the reference voltage Vr and the output ripple see Figure 32 In fact when the voltage on the COMP pin reaches Vr a fixed Ton begins and the output increases For example we consider Vout 5 V with an output ripple of AV 50 mV Considering Cinr gt gt Crit the Cint DC voltage drop VCINT is about 5 V Vr 25 mV 4 125 V Cint assures an AC path for the output voltage ripple Then the COMP pin ripple is a replica of the output ripple with a DC value of Vr 25 mV 925 mV For more details about the output ripple compensation network see the paragraph Closing the integrator loop in the design guidelines In steady state the FB pin voltage is about Vr and the regulated output voltage depends on the external divider Equation 4 7 4 Pulse skip mode If the SKIP pin is tied to ground the device works in skip mode At light loads a zero crossing comparator truncates the low side switch on time when the inductor current becomes negative In this condition the section works in discontinuous conduction mode The threshold between continuous and discontinuous conduction mode is ky 21 47 Device description PM6681A 7 5 22 47 Equation 5 ILOAD SKIP LE ToN x For higher loads the inductor curr
44. tion soft start ramp time 2 3 5 ms Current limit and zero crossing comparator Icsense Input bias current limit 1 90 100 110 uA Comparator offset VcsENsE VPGND 6 6 mV Zero crossing comparator offset aa VPGND VPHASE d 11 mV Fixed negative current limit threshold VpaNp VPHASE eo B 10 47 y PM6681A Electrical characteristics Table 6 Electrical characteristics Vin 24 V Ty 25 C unless otherwise specified continued Symbol Parameter Test condition Min Typ Max Unit On time pulse width FSEL to GND 575 680 785 OUT1 3 3 V OUT 1 8 V 195 230 265 lade FSEL to VREF 390 460 530 Ton SUR SALE OUT 3 3 V ns OUT2 18V 145 175 205 FSEL to LDO5 285 340 395 OUT1 3 3 V OUT 1 8 V 110 135 160 OFF time Minimum off time ToFFMN VIN 24 V 350 500 ns Voltage reference VREF Voltage accuracy 4V VMipos 5 5 V 1 224 1 236 1 249 V Load regulation 100 uA lt Iperf lt 100 HA 4 4 mV Undervoltage lockout fault threshold Falling edge of REF 0 95 mV Integrator FB Voltage accuracy 891 909 mV FB Input bias current 1 0 1 UA COMP Over voltage clamp Normal mode 250 m COMP Under voltage clamp 150 Line regulation Both SMPS 6 V lt Vin lt 36 V 1 1 96 LDOS linear regulator 6 V VIN 36 V Vi pos LDOS linear output voltage 0 lt lj pos lt 50
45. uidelines 9 8 9 8 1 Typical components values are R 47 Q and C 1 uF e VREF capacitor A 10 nF to 100 nF ceramic capacitor on VREF pin must be added to ensure noise rejection e LDOS5 output capacitors Bypass the output of each linear regulator with 1 uF ceramic capacitor closer to the LDO pin and a 4 7 uF tantalum capacitor ESR 2 O In most applicative conditions a 4 7 uF ceramic output capacitor can be enough to ensure stability e Bootstrap circuit The external bootstrap circuit is represented in the next figure Figure 43 Bootstrap circuit CO PHASE The bootstrap circuit capacitor value Cgoor Must provide the total gate charge to the high side MOSFET during turn on phase A typical value is 100 nF The bootstrap diode D must charge the capacitor during the off time phases The maximum rated voltage must be higher than Vinmax A resistor Rgoor on the BOOT pin could be added in order to reduce noise when the phase node rises up working like a gate resistor for the turn on phase of the high side MOSFET Design example The following design example considers an input voltage from 7 V to 16 V The two switching outputs are OUT1 1 5 V and OUT2 1 05 V and must deliver a maximum current of 5 A The selected switching frequencies are about 290 kHz for OUT1 section and about 425 kHz for OUT2 section see Table 1 Inductor selection OUT1 lj oAp 2 5 A 45 ripple current
46. ulse skip mode is enabled If the pin is connected to VREF the pulse skip mode is enabled but the switching frequency is kept higher than 33 kHz No audible pulse skip mode 25 EN1 Enable input for the switching section 1 The section 1 is enabled applying a voltage greater than 2 4 V to this pin The section 1 is disabled applying a voltage lower than 0 8 V when the section is disabled the high side gate driver goes low and low side gate driver goes high 26 PGOOD1 Power Good output signal for the section 1 This pin is an open drain output and when the output of the switching section 1 is out of 10 of its nominal value It is pulled down 27 PGOOD2 Power Good output signal for the section 2 This pin is an open drain output and when the output of the switching section 2 is out of 10 of its nominal value It is pulled down 28 FB1 Feedback input for the switching section 1 This pin is connected to a resistive voltage divider from OUT1 to PGND to adjust the output voltage from 0 9 V to 5 5 V 29 OUT1 Output voltage sense for the switching section 1 This pin must be directly connected to the output voltage of the switching section 30 COMP1 DC voltage error compensation pin for the switching section 1 31 VCC Device supply voltage pin It supplies all the internal analog circuitry except the gate drivers see LDO5 Connect this pin to LDO5 32
47. x to PGND up to 1 V fort 40 ns Table 4 Thermal data Symbol Parameter Value Unit TsrG Storage temperature range 50 to 150 C Rinsa Thermal resistance junction to ambient 35 C W Ty Junction operating temperature range 40 to 125 C Ta Operating ambient temperature range 40 to 85 C Table 5 Recommended operating conditions Value Symbol Parameter Test condition Unit Min Typ Max VIN Input voltage range LDOS in regulation 5 5 36 V VCC IC supply voltage 4 5 5 5 V Me maximum operating 55 V ky 9 47 Electrical characteristics PM6681A 5 Electrical characteristics Table 6 Electrical characteristics Vin 24 V Ty 25 C unless otherwise specified Symbol Parameter Test condition Min Typ Max Unit Supply section Turn on voltage threshold 4 8 4 9 V Vvssw Turn off voltage threshold 4 6 4 75 V Hysteresis 20 50 mV LDOS internal bootstra Rps on 2 E P V5SW gt 4 9 V 1 8 3 Q switch resistance OUTx OUTx discharge mode 18 25 Q On resistance OUTx OUTx discharge mode ne 0 2 0 35 0 6 V Synchronous rectifier turn on level Operating power FBx gt VREF Vref in regulation P consumption V5WS to 5 V i i Ish zn current sunk by SHDN connected to GND 20 30 pA IN Isb an current sunk by ENx to GND V5SW to GND 250 380 pA IN Shutdown section Device on threshold 1 2 1 5 1 7 V VSHDN Device off threshold 0 8 0 85 0 9 soft start sec
48. y Equation 19 PpHighside F conduction Pswitching PM6681A Design guidelines Maximum conduction losses are approximately Equation 20 Vour 2 Peonduction Rpson x u lLoAp max INmin where Rps on is the drain source on resistance of the high side MOSFET Switching losses are approximately Equation 21 Al Al Vin X Loan max E x ton X few Vin x ligAp max t x tor X fsw Pswitching 2 2 where ton and toff are the switching times of the turn off and turn off phases of the MOSFET As general rule high side MOSFETs with low gate charge are recommended in order to minimize driver losses Below there is a list of possible choices for the high side MOSFET Table 14 High side MOSFET manufacturer Manufacturer Type Gate charge nC Rated reverse voltage V ST STS12NH3LL 10 30 ST STS17NH3LL 18 30 The power dissipation of the low side MOSFET is given by Equation 22 Ppi owSide F conduction Maximum conduction losses occur at the maximum input voltage Equation 23 V OUT 2 Peonduction E Rpson x E lLoap max INmax Choose a synchronous rectifier with low Ros on When high side MOSFET turns on the fast variation of the phase node voltage can bring up even the low side gate through its gate drain capacitance CRSS causing cross conduction problems Choose a low side MOSFET that minimizes the ratio Cass Cas Cas Ciss Cass Below there
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