ST PM6680A handbook
Contents
1. anos anos anos us Is fo fo auos no 5 xd MSSA es os men Je fo fo la n anos anos IT x P auos 9 5 lt 3 mz 2 auos angs angs zey _ an 28822 zaoo9d rav odi szo 184 190099 d 8 nars Oop i eis PONO ii 84 DJ oir D 512 190094 zu us 919 sc Z 29190 ONS 8i sto eine Eon 2100 E anos anos uno jz uno 294 MSSA gt er 60 a4 Is lasnaso v RUN TH 52 FT ele za n 198 3 f C ha tawo Td s ET ss 7 ew eu b H en H T m 7219H 2 men Y Y vr 5 21008 ss om 5 uno 88 9 8 90 ele 21009 k e uoo8 NEN QNOd A Il DANIS anos auos Wik Nod QNO9d Nos Nos vo 9 21008 zr now ik zo 192. LOAD CURRENT uA um Figure 17 OUT1 3 3V load transient 02A Figure 18 OUT2 1 8V load transient 02A jin 14 48 PM6680A Typical operating characteristics Figure 19 3 3 V soft start 10 load Current limit 3 5A Figure 20 1 8 V soft start 0 60 load Current limit 3 5A Figure 21 OUT1 3 3 V soft end no load Figure 22 OUT2 1 8 V soft end no load 500 ETT Figure 23 OUT1 3 3 soft end 0 8 load Figure 24 OUT2 1 8 V soft end 0 6 load 15 48 Typical operating characteristics PM6680A Figure 25 3 3 V no audible skip mode Figure 26 1 8 V no audible skip mode E li i WM et 16 48 Application schematic PM6680A Application schematic 6 Simplified application schematic Figure 27 anos
3. 1 403 T 1948 10 19 S9921 QNS9S pue 31V9H esojo lt _ woyjog 298 3 ISNISI 1 apis NEL ast Id GN9d uano Oy do ue 43 48 Design guidelines PM6680A 44 48 As general rule make the high side and low side drivers traces wide and short The high side driver is powered by the bootstrap circuit It s very important to place capacitor CBOOT and diode DBOOT as near as possible to the HGATE pin for example on the layer opposite to the device Route HGATE and PHASE traces as near as possible in order to minimize the area between them The Low side gate driver is powered by the 5 V linear regulator output Placing PGND and LGATE pins near the low side MOSFETs reduces the length of the traces and the crosstalk noise between the two sections The linear regulator output LDO5 is referred to SGND as long as the reference voltage Vref Place their output filtering capacitors as near as possible to the device Place input filtering capacitors near VCC and VIN pins It would be better if the feedback networks connected to COMP FB and OUT pins are referred to SGND in the same point as reference voltage Vref To avoid capacitive cou
4. i1008 A M i E 17 48 Device description PM6680A 7 7 1 18 48 Device description The PM6680A is a dual step down controller dedicated to provide logic voltages for industrial automation applications It is based on a Constant On Time control architecture This type of control offers a very fast load transient response with a minimum external component count A typical application circuit is shown in Figure 3 The PM6680A regulates two adjustable output voltages OUT1 and OUT2 The switching frequency of the two sections can be adjusted to 200 300 kHz 300 400 kHz or 400 500 kHz respectively In order to maximize the efficiency at light load condition a pulse skipping mode can be selected The PM6680A includes also a 5 V linear regulator LDO5 that can power the switching drivers If the output OUT1 regulates 5 V in order to maximize the efficiency in higher consumption status the linear regulator can be turned off and their outputs can be supplied directly from the switching outputs The PM6680A provides protection versus overvoltage undervoltage and over temperature as well as power good signals for monitoring purposes An external 1 237 V reference is available Constant on time PWM control If the SKIP pin is tied to 5 V the device works in PWM mode Each power section has an independent on time control The PM6680A employees a pseudo fixed switching
5. 18 20 22 24 26 28 30 SKIP 5V PWM mode 3 3 36 INPUT VOLTAGE V INPUT VOLTAGE V 12 48 PM6680A Typical operating characteristics Figure 7 No audible skip no load battery Figure 8 Standby mode input battery current current vs input voltage vs input voltage 240 SS zaL L LUExmM p 200 LLL EN1 and low 180 SKIPZVREF no audible skip mode 1 60 m 140 2 120 1 00 16 18 20 22 2 26 28 30 32 3 36 6 18 20 22 24 26 28 30 32 34 36 INPUT VOLTAGE V INPUT VOLTAGE V Figure 9 Shutdown mode input battery current vs input voltage Figure 10 1005 vs output current SHDN low EN1 and EN2 low 16 18 20 22 24 26 20 30 32 4 36 INPUT VOLTAGE V 4 9890 4 9880 4 9870 4 9860 4 9850 gt 49840 4 9830 4 9820 4 9810 4 9800 4 9790 LINEAR OUPUT VOLTAGE 0 10 20 30 40 50 60 70 80 90 LOAD CURRENT mA 100 Figure 11 OUT1 3 3 V switching frequency Figure 12 OUT2 1 8 V switching frequency fsw kHz 12V 5 Q 24V SKP Q 32V NO AUD SKP 12V NO AUD SKP 24V NOAUD SKP 32V PWM 12V PWM Q 24V Q 32V
6. 6680 Dual synchronous step down controller with adjustable output voltages plus LDO Features 6 V to 36 V input voltage range Adjustable output voltages 5V LDO delivers 100 mA peak current 1 237 V 1 reference voltage available externally Current sensing using low side MOSFETs Rps on Valley current sensing Soft start internally fixed at 2ms Soft output discharge Latched OVP and UVP Selectable pulse skipping at light loads Selectable minimum frequency 33 kHz in pulse skip mode 5mW maximum quiescent power Independent power good signals Output voltage ripple compensation Thermal shutdown Applications Table 1 Embedded computer system FPGA system power Industrial applications on 24 V High performance and high density DC DC modules Device summary VFQFPN 32 5X5 Description PM6680A is a dual step down controller specifically designed to provide extremely high efficiency conversion with loss less current sensing technique The constant on time architecture assures fast load transient response and the embedded voltage feed forward provides nearly constant switching frequency operation An embedded integrator control loop compensates the DC voltage error due to the output ripple Pulse skipping technique increases efficiency at very light load Moreover a minimum switching frequency of 33 kHz is selectable to avoid audio noise issues The PM6680A provides a selectable switching
7. The T node voltage is the sum of the output voltage and the triangular waveform generated by the virtual ESR network In fact the virtual ESR network behaves like a further equivalent ESR A good trade off is to design the network in order to achieve an Resp given by Equation 28 VRIPPLE _ R R ESR Al out where AIL is the inductor current ripple and is the overall ripple of the T node voltage It should be chosen higher than approximately 30 mV The new closed loop gain depends on In order to ensure stability it must be verified that Equation 29 Where 37 48 Design guidelines PM6680A 38 48 Equation 30 1 tz 21x Cout where is the sum of the ESR of the output capacitor Rout and the equivalent ESR given by the virtual ESR network RESR Moreover must meet the following condition Equation 31 k fsw gt Kx fz 2nx Cout Where k is a free design parameter greater than 3 and determines the minimum integrator capacitor value Equation 32 C must be selected as shown Equation 33 gt 5 Cint R must be chosen in order to have enough ripple voltage on integrator input Equation 34 R1 can be selected as follows Equation 35 o Riga y 2 1 Cxnx amp Example OUT1 1 5 V fgsw 290 kHz L 2 5 uH Cout 330 uF with Rout lt 12 We design Resp 12 We choose
8. 0 10 Load current A 1 00 10 00 300 SKP 12V 250 SKP 24V 200 SKP 32V NO AUD SKP Q 12V 150 NOAUD SKP 24V E 100 NO AUD SKP 32V PWM 12V 50 PWM Q 24V PWMQ 32V 0 0 01 0 10 1 00 10 00 Load current A 13 48 Typical operating characteristics PM6680A Figure 13 OUT1 3 3 V load regulation Figure 14 OUT2 1 8 V load regulation SKP Q 12V 3 330 SKP Q 24V SKP Q 32V NO AUD SKIP 12V 3320 AUD SKP 24V S 3315 NO AUD SKIP 32V 5 PWM Q 12V 3310 PWM 24V 3 305 PWM 32V 0 0001 0 010 0100 1000 10 000 Load current A 1 1 skP 12v 1815 skP 24V Sie skeesv 3 NOAUD SKP 12V 1805 NOAUD SKIP 24V 5 SKP Q 32V B un NO AUD SKIP 32 5 PwMQ 12 1795 PWM 24V 1790 we 0001 0 010 0100 1 000 10000 Load current A Figure 15 Voltage reference vs load current Figure 16 OUT1 OUT2 and 1005 Power Up 12325 _ 12820 212315 2212310
9. 1 NF by equations 30 33 and 47 pF Rint 1 by eq 27 28 C 5 6 nF by Eq 34 Then R 36 eq 34 and R1 eq 35 ky PM6680A Design guidelines 9 7 Other parts design e VIN filter A VIN pin low pass filter is suggested to reduce switching noise The low pass filter is shown in the next figure Figure 38 VIN pin filter VIN Input voltage E EN 100pF Typical components values R 3 9 and C 4 7 uF e VCC filter A VCC low pass filter helps to reject switching commutations noise Figure 39 Inductor current waveforms Typical components values 47 and C 1yF e VREF capacitor A 10nF to 100nF ceramic capacitor VREF pin must be added to ensure noise rejection 1005 output capacitors Bypass the output of each linear regulator with 1 uF ceramic capacitor closer to the LDO pin and a 4 7uF tantalum capacitor ESR 2 In most applicative conditions 4 7 uF ceramic output capacitor can be enough to ensure stability Bootstrap circuit The external bootstrap circuit is represented in the next figure 39 48 Design guidelines PM6680A Figure 40 Bootstrap circuit The bootstrap circuit capacitor value must provide the total gate charge to the high side MOSFET during turn on phase A typical value is 100 nF The bootstrap diode D must charge the capacitor during the
10. 23 405 Curentlimit d dad 24 77 Softstartand soft end 25 28 3916 dIVelS x xa RO dean RE e a UR Re 26 7 9 Reference voltage and bandgap 27 7 10 Internal linear regulator 27 7 11 Power up sequencing and operative 5 28 8 Monitoring and protections 29 2 48 y PM6680A Contents 9 Design guidelines 30 9 1 Switching frequency 30 9 2 Inductor selection 30 93 Outputcapacitor isois esa iamen cies CHOR IR Eoo 31 9 4 Input capacitors selection 32 9 5 Power MOSFETS ese theta d pea rd i Eb 33 9 6 Closing the integratorloop 35 9 7 Otherparts design 39 9 8 Design example 40 10 Package mechanical data 45 11 REVISION history 47 3 48 Block diagram PM6680A Block diagram Figure 1 Functional block diagram VIN REFERENCE GENERATOR LINEAR REGULATOR LDO5 ENABLE ouT1 SMPS SMPS
11. CONTROLLER CONTROLLER STARTUP CONTROLLER LEVEL SHIFTER OCSENS COMP1 5 lt LDO5 ENABLE TERMIC CONTROLLER E1 4 48 X Pin settings PM6680A Pin settings Connections 2 1 Pin connection through top view Figure 2 190099 290094 184 LLANO Ido JOA 33 U GND1 COMP2 lt 2 FSEL SHDH FE2 SGNEO LGATE1 PGND LGATE2 CSENS2 PHASE2 HGATE2 OOT 5 48 Pin settings PM6680A 2 2 Functions Table 2 Pin functions N Pin Function Signal ground Reference for internal logic circuitry It must be connected to the 1 SGND1_ ground plan of the power supply The signal ground plan and the power ground plan must be connected together in one point near the PGND pin 2 COMP2 DC voltage error compensation pin for the switching section 2 Frequency selection pin It provides a selectable switching frequency allowing three 3 FSEL n i different values of switching frequencies for the switching sections Enable input for the switching section 2 The section 2 is enabled applying a voltage greater than 2 4 V to this pin 4 The section 2 is disabled applying a voltage lower than 0 8 V When the section is disabled the High Side gate driver goes low and Low Side gate driver goes high If
12. If due to the load the frequency is higher than 33 kHz the device works like in skip mode No audible skip mode reduces audio frequency noise that may occur in pulse skip mode at very light loads keeping the efficiency higher than in PWM mode 23 48 Device description PM6680A 7 6 Current limit The current limit circuit employs a valley current sensing algorithm During the conduction time of the low side MOSFET the current flowing through it is sensed The current sensing element is the low side MOSFET on resistance Figure 33 Figure 33 Rsense sensing technique An internal 100 pA current source is connected to CSENSE pin and determines a voltage drop on RCSENSE If the voltage across the sensing element is greater than this voltage drop the controller doesn t initiate a new cycle A new cycle starts only when the sensed current goes below the current limit Since the current limit circuit is a valley current limit the actual peak current limit is greater than the current limit threshold by an amount equal to the inductor ripple current Moreover the maximum DC load is equal to the valley current limit plus half of the inductor ripple current Equation 6 Al Max ES The output current limit depends on the current ripple as shown in Figure 34 Figure 34 Current waveforms in current limit conditions Current DC current limit maximum load Inductor cur
13. lt 50 mA 4 9 5 0 5 1 V 6V lt V 36 V lt VIN lt 1005 line regulation 1005 20 0 004 V ILDO5 1005 current limit VLDO5 gt UVLO 270 330 400 mA Under voltage lockout of ULVO 1005 3 94 4 4 13 V 2 By demoboard test 10 48 PM6680A Electrical characteristics Table 5 Electrical characteristics continued TA 40 to 125 C unless otherwise specified All parameters at operating temperature extremes are guaranteed by design and statistical analysis not production tested Symbol Parameter Test condition Min Typ Max Unit High and low gate drivers HGATE HGATEx high state pullup 2 0 3 Q driver on resistence low state pulldown 1 6 2 7 Q LGATE LGATEx high state pullup 1 4 2 1 Q driver on resistance LGATEx low state pulldown 0 8 1 2 Q PGOOD pins UVP OVP protections Both SMPS sections with o OVP Over voltage threshold respect to VREF 112 116 120 UVP Under voltage threshold 65 68 71 96 Upper threshold VFB VREF 107 110 113 7o PGOOD1 2 ower thresho VFB VREF 58 91 a IPGOOD1 2 PGOOD leakage current VPGOOD1 2 forced to 5 5 V 1 VPGOOD1 2 Output low voltage ISink 4 mA 150 250 mV Thermal shutdown Tspn Shutdown temperature 150 Power management pins SMPS disabled level 0 8 EN1 2 V SMPS enabled level 2 4 Low level 3 0 5 3 VLDO
14. I nang min I za p max I Equation 39 255500 10044 Let s assume the maximum temperature Tmax 75 in calculation We choose standard value Resgwse 560 OUT2 Equation 40 min nang miN 1 max 2 057 41 48 Design guidelines PM6680A 42 48 Equation 41 EM 5500 Let s assume Tmax 75 C Rpson calculation We choose standard value Rosense 560 Input capacitor Maximum input capacitor RMS current is about 1 084 A Then gt 1 084 We put two 10 uF ceramic capacitors with Irms 1 5 A Synchronous rectifier OUT1 Shottky diode STPS1L40M OUT2 Shottky diode STPS1L40M Integrator loop Refer to figure 14 OUT1 The ripple is smaller than 40 mV then the virtual ESR network is required 1 5 47 pF Rint 1 1 OUT2 The ripple is smaller than 40 mV then the virtual ESR network is required 71 5 nF 247 pF Rint 820 Output feedback divider Refer to figure 6 OUT1 R1 10 R2 27 OUT2 R1 10 R2 10 Layout guidelines The layout is very important in terms of efficiency stability and noise of the system It is possible to refer to the PM6680A demoboard for a complete layout example For good PC board layout follows these guidelines Place on the top side all the power components inductors input and output capacitors MOSFETs
15. independent from input voltage and from output voltage Actually the frequency depends on parasitic voltage drops that are present during the charging path high side switch resistance inductor resistance DCR and discharging path low side switch resistance DCR As a result the switching frequency increases as a function of the load current Standard switching frequency values can be selected for both sections by pin FSEL as shown in the following table Table 6 FSEL pin selection typical switching frequency FswG OUT 3 3 V kHz FswG OUT 1 8 V kHz FSEL GND 195 335 FSEL VREF 295 440 FSEL LDO5 390 600 19 48 Device description PM6680A 7 2 20 48 Constant on time architecture Figure 29 shows the simplified block diagram of a constant on time controller A minimum off time constrain 350 ns typ is introduced to allow inductor valley current sensing on synchronous switch A minimum on time 130 ns is also introduced to assure the start up switching sequence PM6680A has a one shot generator for each power section that turns on the high side MOSFET when the following conditions are satisfied simultaneously the PWM comparator is high the synchronous rectifier current is below the current limit threshold and the minimum off time has timed out Once the on time has timed out the high side switch is turned off while the synchronous switch is turned on according to the anti cross c
16. inductor must be able to provide an RMS current greater than the maximum RMS inductor current Ris Equation 13 Al max 12 Where Al may is the maximum ripple current PM6680A Design guidelines 9 3 Equation 14 Vinmax Vout x Vour Al fot SW Vinmax If hard saturation inductors are used the inductor saturation current should be much greater than the maximum inductor peak current Ipeak Equation 15 Al max oap max Using soft saturation inductors it s possible to choose inductors with saturation current limit nearly to Ipeak Below there is a list of some inductor manufacturers Table 10 Inductor manufacturer Inductor value RMS current Saturation current Manufacturer Series uH A A COILCRAFT MSS1038 1 5 to 22 2 85 to 7 85 2 9 to 8 30 COILCRAFT MSS7341 3 3 to 22 1 7 to 3 95 1 3 to 3 5 WURTH TPC 1 to 22 uH 2 7 t08 2 6 to 9 5 Output capacitor The selection of the output capacitor is based on the ESR value Rout and the voltage rating rather than on the capacitor value Cout The output capacitor has to satisfy the output voltage ripple requirements Lower inductor value can reduce the size of the choke but increases the inductor current ripple AIL Since the voltage ripple is given by Equation 16 Rout X Al A low ESR capacitor is required to reduce t
17. to realize the soft start at the startup the overcurrent threshold is set 25 of the nominal value and the undervoltage protection see related sections is disabled The controller starts charging the output capacitor working in current limit The overcurrent threshold is increased from 25 to 100 of the nominal value with steps of 25 every 700 us typ After 2 8 ms typ the undervoltage protection is enabled The soft start time is not programmable A minimum capacitor is required to ensure a soft start without any overshoot on the output Equation 10 gt Lvalley 4 2 C out 25 48 Device description PM6680A 7 8 26 48 Figure 35 Soft start waveforms Switching output Current limit threshold EN1 EN2 Time When switching section is turned off EN1 EN2 pins low the controller enters in soft end mode The output capacitor is discharged through an internal 18 p MOSFET switch when the output voltage reaches 0 3 V the low side MOSFET turns on keeping the output to ground The soft end time also depends on load condition Gate drivers The integrated high current drivers allow to use different power MOSFETs The high side driver MOSFET uses bootstrap circuit which is indirectly supplied by LDO5 output The BOOT and PHASE pins work respectively as supply and return rails for the HS driver The low side driver uses the internal LDO5 output for the s
18. 5 FSEL Frequency selection range Middle level 10 1 5 V High level 9 7 Pulse skip mode 3 0 5 3 VLDO5 SKIP PWM mode 1 0 15 V Ultrasonic mode 3 005 0 8 VEN1 2 0 1 to5V VSKIP 0 1 Input leakage current to5V VSHDN 0 5 1 VFSEL 0 to 5 V 1 3 By design 677 11 48 Typical operating characteristics PM6680A 5 Typical operating characteristics FSEL GND 200 300 kHz SKIP GND skip mode VSSW EXTS5V external 5 V power supply connected input voltage VIN 24 V SHDN EN1 and EN2 high OUT1 3 3 V 2 1 8 V no load unless specified Figure 3 OUT1 3 3 V efficiency Figure 4 OUT2 1 8 V efficiency SKP 12 SKP 12V SKP 24V SKP Q 24V 5 32V SKP 32V PNO AUD SKIP 12V gt NO AUD SKIP 12V 2 NO AUD SKIP 24V NO AUD SKP 24V NOAUD SKPQ3N 2 NO AUD SKP 32V 12V PWM Q 12V PWM Q 24V PWM Q 24V PWM Q 32V Q 32V 0 001 0 010 0 100 1 000 10 000 0 001 0 010 0 100 1 000 10 000 Load current A Load current A Figure 5 PWM no load battery current vs Figure 6 Skip no load battery current vs input voltage input voltage 16
19. DO5 is always Standby T low In Standby mode LGATE1 LGATE2 pins are forced 9 high while HGATE 1 HGATE 2 pins are forced low Shutdown SHDN is low All circuits off PM6680A Monitoring and protections 8 Monitoring and protections Power good signals The PM6680A provides two independent power good signals one for each switching section PGOOD1 PGOOD2 PGOOD1 PGOOD2 signals are low if the output voltage is out of 10 of the designed set point or during the soft start standby and shutdown mode Thermal protection The PM6680A has a thermal protection to preserve the device from overheating The thermal shutdown occurs when the die temperature goes above 150 In this case all internal circutry is turned off and the power sections are turned off after the discharge mode A power on reset or a toggle on the SHDN pin is necessary to restart the device Overvoltage protection When the switching output voltage is about 115 of its nominal value a latched overvoltage protection occurs In this case the synchronous rectifier immediately turns on while the high side MOSFET turns off The output capacitor is rapidly discharged and the load is preserved from being damaged The overvoltge protection is also active during the soft start Once an overvoltage protection has been detected a toggle on SHDN EN1 EN2 pins or a power on reset is necessary to exit from the latched state Undervolt
20. E2 Low side gate driver output for the section 2 14 PGND Power ground This pin must be connected to the power ground plan of the power supply 15 LGATE1 Low side gate driver output for the section 1 Signal ground for analog circuitry It must be connected to the signal ground plan of 16 SGND2 the power supply 6 48 ky PM6680A Pin settings Table 2 Pin functions continued Function Internal 5 V regulator bypass connection If VSSW is connected to OUTS or to an external 5 V supply and V5SW is greater 17 V5SW than 4 9 V the LDOS regulator shuts down and the LDO5 pin is directly connected to OUT5 through a max switch If VSSW is connected to GND the 1005 linear regulator is always on 18 1005 internal regulator output It can provide up to 100 mA peak current LDO5 supplies embedded low side gate drivers and an external load 19 VIN Device supply voltage input and battery voltage sense A bypass filter 4 and 4 7 uF between the battery and this pin is recommended Positive current sense input for the switching section 1 This pin must be connected 20 CSENSE1 through a resistor to the drain of the synchronous rectifier Roson sensing to obtain a positive current limit threshold for the power supply controller Switch node connection and return path for the high side driver for the section 1 1 is 21 PHASE1 also used as negat
21. T As general rule high side MOSFETS with low gate charge are recommended in order to minimize driver losses Below there is a list of possible choices for the high side MOSFET Table 13 High side MOSFET manufacturer Manufacturer Type Gate charge nC Rated reverse voltage V The power dissipation of the low side MOSFET is given by Equation 21 Ppiowside Peonduction Maximum conduction losses occur at the maximum input voltage 33 48 Design guidelines PM6680A Equation 22 V OUT 2 m 2 INmax Choose a synchronous rectifier with low Rpgon When high side MOSFET turns on the fast variation of the phase node voltage can bring up even the low side gate through its gate drain capacitance causing cross conduction problems Choose a low side MOSFET that minimizes the ratio Ciss Cnss Below there is a list of some possible low side MOSFETs Table 10 Low side MOSFET manufacturer Crass Rated reverse volta ge Manufacturer Type R ACT yp DSon Cas V ST STS7NF60L VC11 19 0 0625 60 Dual n channel MOSFETS can be used in applications with a maximum output current of about 3 A Below there is a list of some MOSFET manufacturers Table 14 Dual MOSFET manufacturer Manufacturer Type Roson 2 bi voltage ST STS4DNF60L 50 15 60 A rectifi
22. age protection When the switching output voltage is below 70 of its nominal value a latched undervoltage protection occurs In this case the switching section is immediately disabled and both switches are open The controller enters in soft end mode and the output is eventually kept to ground turning low side MOSFET on The undervoltage circuit protection is enabled only at the end of the soft start Once an overvoltage protection has been detected a toggle on SHDN EN1 EN2 pin or a power on reset is necessary to clear the undervoltage fault and starts with a new soft start phase Table 9 Protections and operatives modes Mode Conditions Description LGATE1 LGATE2 pin is forced high LDO5 remains active Exit by a power on reset or toggling SHDN or EN1 EN2 LGATE1 LGATE2 is forced high after the soft end mode LDO5 remains active Exit by a power on reset Overvoltage OUT1 OUT2 gt 115 of the protection nominal value Undervoltage OUT1 OUT2 lt 70 of the protection nominal value or toggling SHDN or ENT EN2 Thermal All circuitry off Exit by a POR on VIN or toggling shutdown 15096 SHDN 29 48 Design guidelines PM6680A 9 9 1 9 2 30 48 Design guidelines The design of a switching section starts from two parameters e Input voltage range in notebook applications it varies from the minimum battery voltage VINmin to the AC adapter voltage Vinmax e Maximum load current it is
23. and diodes Refer them to a power ground plan PGND If possible reserve a layer to PGND plan The PGND plan is the same for both the switching sections AC current paths layout is very critical see Figure 41 The first priority is to minimize their length Trace the LS MOSFET connection to PGND plan as short as possible Place the synchronous diode D near the LS MOSFET Connect the LS MOSFET drain to the switching node with a short trace Place input capacitors near HS MOSFET drain It is recommended to use the same input voltage plan for both the switching sections in order to put together all input capacitors Place all the sensitive analog signals feedbacks voltage reference current sense paths on the bottom side of the board or in an inner layer Isolate them from the power top side with a signal ground layer SGND Connect the SGND and PGND plans only in one point a multiple vias connection is preferable to a 0 ohm resistor connection near the PGND device pin Place the device on the top or on the bottom size and connect the exposed pad and the SGND pins to the SGND plan see Figure 41 Design guidelines PM6680A Current paths ground connection and driver traces layout Figure 41 Je e usd 8183 99243 ped pesodx3 GNOS ANOS ANOS
24. both EN1 and EN2 pins are low and SHDN pin is high the device enters in standby mode Shutdown control input The device switch off if the SHDN voltage is lower than the device off thershold Shutdown mode 5 SHDN The device switch on if the SHDN voltage is greater than the device on threshold The SHDN pin can be connected to the battery through a voltage divider to program an undervoltage lockout In shutdown mode the gate drivers of the two switching sections are in high impedance high Z 6 NC Not connected 7 FB2 Feedback input for the switching section 2 This pin is connected to a resistive voltage divider from OUT2 to PGND to adjust the output voltage from 0 9 V to 3 3 V Output voltage sense for the switching section 2 This pin must be directly connected 8 OUT2 Md to the output votage of the switching section Bootstrap capacitor connection for the switching section 2 It supplies the high side 9 BOOT2 gate driver 10 HGATE2 gate driver ouput for section 2 This is the floating gate driver output Switch node connection and return path for the high side driver for the section 2 1 is 11 PHASE2 also used as negative current sense input Positive current sense input for the switching section 2 This pin must be connected 12 CSENSE2 through a resistor to the drain of the synchronous rectifier Rogon sensing to obtain a positive current limit threshold for the power supply controller 13 LGAT
25. dance with JEDEC 45 48 Package mechanical data PM6680A Figure 42 Package dimensions SEATING PLANE pee 0 16 4 10 2 C b 2 P 4 3 D 5 vl PIN 1 ID mc R 0 20 32 25 L 02 pee BOTTOM VIEW 46 48 ky PM6680A Revision history 11 Revision history Table 18 Document revision history Date Revision Changes 12 Oct 2006 1 Initial release 17 Dec 2007 2 Added Section 5 Typical operating characteristics on page 12 and Section 9 Design guidelines on page 30 47 48 PM6680A Please Read Carefully Information in this document is provided solely in connection with ST products STMicroelectronics NV and its subsidiaries ST reserve the right to make changes corrections modifications or improvements to this document and the products and services described herein at any time without notice All ST products are sold pursuant to ST s terms and conditions of sale Purchasers are solely responsible for the choice selection and use of the ST products and services described herein and ST assumes no liability whatsoever relating to the choice selection or use of the ST products and services described herein No license express or implied by estoppel or otherwise to any intellectual property right
26. directly connected 29 OUT ae to the output votage of the switching section 30 1 DC voltage error compensation pin for the switching section 1 31 vce Device supply voltage pin It supplies all the internal analog circuitry except the gate drivers see LDO5 Connect this pin to LDO5 32 VREF Internal 1 237 V high accuracy voltage reference It can deliver 50 pA Bypass to SGND with a 100 nF capacitor to reduce noise 7 48 Electrical data PM6680A 3 3 1 3 2 8 48 Electrical data Maximum rating Table 3 Absolute maximum ratings Parameter Value Unit V5SW 1005 to PGND 0 3 to 6 V VIN to PGND 0 3 to 36 V HGATEx and BOOTx to PHASEx 0 3 to 6 V PHASEx to PGND 0 6 0 1036 V CSENSEx to PGND 0 6 to 42 V CSENSEx to BOOTx 6 to 0 3 V LGATEx to PGND 0 3 to 1005 0 3 V FBx COMPx SKIP FSEL VREF to SGND1 SGND2 0 3 to Vec 0 3 V PGND to SGND1 SGND2 0 3 to 0 3 SHDN PGOODx OUTx VCC ENx to SGND1 SGND2 0 3 to 6 V Power Dissipation at T 25 C 2 8 W Maximum withstanding Voltage range test condition VIN 1000 CDF AEC Q100 002 Human Body Model acceptance V criteria Normal Performance Other pins 2000 1 PHASE to PGND up to 2 5 V fort 10 ns 2 LGATEx to PGND upto 1 V fort lt 40 ns Thermal data Table 4 Thermal data Symbol Parameter Value Unit Riha Thermal resistance junction to ambie
27. ected to very high current during the charge Ceramic capacitors have usually a higher RMS current rating with smaller size and they remain the best choice Below there is a list of some ceramic capacitor manufacturers Table 12 Input capacitor manufacturer Manufacturer Series Capacitor value uF Rated voltage V TAYIO YUDEN UMK325BJ106KM T 10 50 TAYIO YUDEN GMK325BJ106MN 10 35 PM6680A Design guidelines 9 5 Power MOSFETS Logic level MOSFETs are recommended since low side and high side gate drivers are powered by LDO5 Their breakdown voltage VBRpss must be higher than Vinmax In notebook applications power management efficiency is a high level requirement The power dissipation on the power switches becomes an important factor in switching selections Losses of high side and low side MOSFETs depend on their working conditions The power dissipation of the high side MOSFET is given by Equation 18 PpHighside F conduction Pswitching Maximum conduction losses are approximately Equation 19 QUT x max Peonduction where RDSon is the drain source on resistance of the high side MOSFET Switching losses are approximately Equation 20 Al Al Vin 1 max a ton X f x ligAp max p X fow Pswitching 2 2 where ton and are the switching times of the turn on and turn phases of the MOSFE
28. ent limit 1 90 100 110 offset VCSENSE VPGND 6 6 mV Zero crossing comparator offset VPHASE 1 11 mV Fixed negative current _ limit threshold VPHASE 169 mv 1 25 to 125 C ky 9 48 Electrical characteristics PM6680A Table 5 Electrical characteristics continued TA 40 C to 125 C unless otherwise specified All parameters at operating temperature extremes are guaranteed by design and statistical analysis not production tested Symbol Parameter Test condition Min Typ Max Unit Minimum on time OUT1 3 3 V 595 700 805 FSEL to GND OUT2 1 8 190 225 260 1 3 3 V 400 470 545 On time pulse width Vin 24 V FSELto VREF ns OUT2 1 8 V 145 170 200 OUT1 3 3 V 300 355 410 FSELtoLDO5 OUT2 1 8 V 105 125 145 Minimum off time TOFFMIN Q Vin 24 V 350 500 ns Voltage reference Voltage accuracy 4V VLDO5 5 5 V 1 224 1 236 1 249 V VREF Load regulation 100 pA lt IREF lt 100 pA 4 4 mV Undervoltage lockout fault threshold Falling edge of REF 0 95 mV PWM comparator FB Voltage accuracy 909 900 909 mV FB Input bias current 0 1 Normal mode 250 COMP Over voltage clamp Pulse skip mode 60 mV COMP Under voltage clamp 150 Line regulation Both SMPS 6V lt Vy lt 36 2 1 96 1005 linear regulation 6V Vin lt 36 V LDOS linear output voltage 0 lt 005
29. er across the low side MOSFET is recommended The rectifier works as a voltage clamp across the synchronous rectifier and reduces the negative inductor swing during the dead time between turning the high side MOSFET off and the synchronous rectifier on It can increase the efficiency of the switching section since it reduces the low side switch losses A shottky diode is suitable for its low forward voltage drop 0 3 V The diode reverse voltage must be greater than the maximum input voltage Vinimax A minimum recovery reverse charge is preferable Below there is a list of some shottky diode manufacturers Table 15 Schottky diode manufacturer Forward voltage Rated reverse Reverse current V voltage V uA ST 0 5 40 21 STPS1L40M 34 48 677 PM6680A Design guidelines 9 6 Closing the integrator loop The design of external feedback network depends on the output voltage ripple If the ripple is higher than approximately 30 mV the feedback network Figure 36 is usually enough to keep the loop stable Figure 36 Circuitry for output ripple compensation COMP PIN VOLTAGE Vr OUTPUT VOLTAGE The stability of the system depends firstly on the output capacitor zero frequency The following condition should be satisfied Equation 23 k few gt Kx 5G out out where k is a design parameter greater than 3 and Rout is the ESR of the output capacitor It determinates the mi
30. frequency Constant On Time COT controller as core of the switched mode section Each power section has an independent COT control The COT controller is based on a relatively simple algorithm and uses the ripple voltage due to the output capacitor s ESR to trigger the fixed on time one shot generator In this way the output capacitor s ESR acts as a current sense resistor providing the appropriate ramp signal to the PWM comparator On time one shot duration is directly proportional to the output voltage sensed at the OUT1 OUT2 pins and inversely proportional to the input voltage sensed at the VIN pin as follows Equation 1 V 24 Viu This leads to a nearly constant switching frequency regardless of input and output voltages When the output voltage goes lower than the regulated voltage Vreg the on time one shot generator directly drives the high side MOSFET for a fixed on time allowing the inductor current to increase after the on time an off time phase in which the low side MOSFET is turned on follows Figure 28 shows the inductor current and the output voltage waveforms in PWM mode PM6680A Device description Figure 28 Constant ON time PWM control Output The duty cycle of the buck converter in steady state is Equation 2 p Vout Vin The PWM control works at a nearly fixed frequency few Equation 3 As mentioned the steady state switching frequency is theoretically
31. frequency allowing three different values of switching frequencies for the two switching sections The output voltages OUT1 and OUT2 can be adjusted from 0 9 V to 5 V and from 0 9 V to 3 3 V respectively Order codes PM6680A PM6680ATR Package VFQFPN 32 5X5 exposed pad Packaging Tube Tape and reel December 2007 Rev 2 1 48 www st com Contents PM6680A Contents 1 Block di gram ss sisama gon UR e mon a 3 2 Pin SGUINGS oed 4 2 1 Connections ex cose C RR RON i SA Ru RARE RR 4 2 2 FUNCIONS on 5 3 Electrical data 8 3 1 Ma xim m rating Rape RR RO ERI ed pd E ces 8 3 2 Thermal data 8 4 Electrical characteristics 9 5 Typical operating characteristics 12 6 Application schematic 17 7 Device description 18 7 1 Constant On time PWM 18 7 2 Constant On time architecture 20 7 3 Output ripple compensation and loop stability 21 7 4 Pulse Skip M dE uoo dime 22 7 5 No audible skip
32. he output voltage ripple Switching sections can work correctly even with 20 mV output ripple However to reduce jitter noise between the two switching sections it s preferable to work with an output voltage ripple greater than 30 mV If lower output ripple is required a further compensation network is needed see Closing the integrator loop paragraph Finally the output capacitor choice deeply impacts on the load transient response see Load transient response paragraph Below there is a list of some capacitor manufacturers 31 48 Design guidelines PM6680A 9 4 32 48 Table 11 Output capacitor manufacturer Manufacturer Series value Rated voltage V ESR max SANYO bogus 10010470 2 5 to 6 3 12 to 65 PANASONIC SPCAP UD UE 100 to 470 2 to 6 3 7 to 18 Input capacitors selection In a buck topology converter the current that flows into the input capacitor is a pulsed current with zero average value The input RMS current of the two switching sections can be roughly estimated as follows Equation 17 1 0 0 x5 x 1 D3 Where D1 D2 are the duty cycles and 11 I2 are the maximum load currents of the two sections Input capacitor should be chosen with an RMS rated current higher than the maximum RMS current given by both sections Tantalum capacitors are good in term of low ESR and small size but they occasionally can burn out if subj
33. ive current sense input 22 HGATE1 High side gate driver ouput for section 1 This is the floating gate driver output 23 Bootstrap capacitor connection for the switching section 1 It supplies the high side gate driver Pulse skipping mode control input If the pin is connected to LDO5 the PWM mode is enabled 24 SKIP e Ifthe pin is connected to GND the pulse skip mode is enabled If the pin is connected to VREF the pulse skip mode is enabled but the switching frequency is kept higher than 33 kHz No audible puse skip mode Enable input for the switching section 1 The section 1 is enabled applying a voltage greater than 2 4 to this pin 25 EN1 e The section 1 is disabled applying a voltage lower than 0 8 V When the section is disabled the High Side gate driver goes low and Low Side gate driver goes high Power Good ouput signal for the section 1 This pin is an open drain ouput and when 26 PGOOD1 the ouput of the switching section 1 is out of 10 of its nominal value It is pulled down Power Good ouput signal for the section 2 This pin is an open drain ouput and when 27 PGOOD2 the ouput of the switching section 2 is out of 10 of its nominal value It is pulled down 28 FB1 Feedback input for the switching section 1 This pin is connected to a resistive voltage divider from OUT1 to PGND to adjust the output voltage from 0 9 V to 5 5 V Output voltage sense for the switching section 1 This pin must be
34. lies LDO5 output Table 7 V5SW multifunction pin V5SW Description GND The 5 V linear regulator is always turned on and supplies LDO5 output Switching 5 V The 5 V linear regulator is turned off when the voltage on V5SW is above 4 8 V and output the LDOS output is supplied by the switching 5 V output External 5 V The 5 V linear regulator is turned off when the voltage on V5SW is above 4 8 V and supply 1005 output is supplied by the external 5 V 27 48 Device description PM6680A 7 11 28 48 Power up sequencing and operative modes Let us consider SHDN EN1 and 2 low at the beginning An external voltage is applied as input voltage The device is in shutdown mode When the SHDN pin voltage is above the shutdown device on threshold 1 5 V typ the controller begins the power up sequence All the latched faults are cleared LDO5 undervoltage control is blanked for 4 ms and the internal regulator 1005 turns on If the 1005 output is above the UVLO threshold after this time the device enters in standby mode The switching outputs are kept to ground by turning on the low side MOSFETs When EN1 and EN2 pins are forced high the switching sections begin their soft start sequence Table 8 Operatives modes Mode Conditions Description Run SHDN is high Switching regulators are enabled internal linear EN1 EN2 pins are high regulators outputs are enabled Internal Linear regulators active L
35. ltage and Vr which decreases the output voltage in order to compensate the total static error including the voltage drop on PCB traces In addition provides an AC path for the output ripple In steady state the voltage on COMP1 COMP2 pin is the sum of the reference voltage Vr and the output ripple see Figure 30 In fact when the voltage on the COMP pin reaches Vr a fixed Ton begins and the output increases For example we consider Vout 5 V with an output ripple of AV 50 mV Considering gt gt the DC voltage drop VCjyr is about 5 V Vr 25 mV 4 125 V assures an AC path for the output voltage ripple Then the COMP pin ripple is a replica of the output ripple with a DC value of Vr 25 mV 925 mV For more details about the output ripple compensation network see the Chapter 9 6 Closing the integrator loop on page 35 in the Design guidelines 21 48 Device description PM6680A 7 4 22 48 Pulse skip mode If the SKIP pin is tied to ground the device works in skip mode At light loads a zero crossing comparator truncates the low side switch on time when the inductor current becomes negative In this condition the section works in discontinuous conduction mode The threshold between continuous and discontinuous conduction mode is Equation 5 ILOAD SKIP Sa x For higher loads the inductor current doesn t cross the zero and the device works in the same wa
36. nimum integrator capacitor value Equation 24 Cir gt 24 x n where gm 50 us is the integrator transconductance 35 48 Design guidelines PM6680A 36 48 In order to ensure stability it must be also verified that Equation 25 Vr gt V TX OUT In order to reduce ground noise due to load transient on the other section it is recommended to add a resistor and a capacitor that together with realize low pass filter see figure 13 The cutoff frequency must be much greater 10 or more times than the switching frequency of the section Equation 26 1 x Ciit Rint 2 four x Due to capacitive divider the ripple voltage the COMP pin is given by Equation 27 C INT VRIPPLE VniPPLEout X C G VRIPPLEout X d INT Vit Where gout is the output ripple and q is the attenuation factor of the output ripple If the ripple is very small lower than approximately 30 mV a further compensation network named virtual ESR network is needed This additional part generates a triangular ripple that is added to the ESR output voltage ripple at the input of the integrator network The complete control schematic is represented in Figure 37 PM6680A Design guidelines Figure 37 Virtual ESR network COMP pin voltage T node voltage Output voltage ANC INI
37. nt 35 C W Storage temperature range 40 to 150 Ty Junction operating temperature range 40 to 125 SZA PM6680A Electrical characteristics 4 Electrical characteristics Table 5 Electrical characteristics 40 C to 125 C unless otherwise specified All parameters at operating temperature extremes are guaranteed by design and statistical analysis not production tested Symbol Parameter Test condition Min Typ Max Unit Supply section VIN Input voltage range Vout Vref 1005 in regulation 5 5 36 V Voc IC supply voltage 4 5 5 5 V Vyssw Turn ON voltage threshold 4 8 4 9 V Turn OFF voltage threshold is s y Hysteresis 20 50 mV Vvssw Maximum operating range 5 5 V LDOS Int tst Rps on pa ua 9095 V5SW gt 4 9 1 8 3 Q switch resistance OUTx OUTx discharge Mode 18 25 Q On resistance OUTx OUTx discharge Mode 0 2 0 36 0 6 V Synchronous rectifier Turn on level Operating power FBx gt Vref in regulation Fin consumption V5WS to 5V my Ish current sunk by SHDN connected to GND 20 30 uA IN Isb current sunk by to GND VSSW to GND 190 250 uA IN Shutdown section Device ON threshold 1 2 1 5 1 7 V VSHDN Device OFF threshold 0 8 0 85 0 9 V Soft start section Soft start ramp time 2 3 5 ms Current limit and zero crossing comparator Input bias curr
38. off time phases The maximum rated voltage must be higher than ViNmax A resistor on the BOOT pin could be added in order to reduce noise when the phase node rises up working like a gate resistor for the turn on phase of the high side MOSFET 9 8 Design example The following design example considers an input voltage from 16 V to 32 V the typical value is 24 V The two switching outputs are OUT1 3 3 V and OUT2 1 8 V and must deliver maximum current of 2 5 A The selected switching frequencies are about 290 kHz for OUT1 section and about 440 kHz for OUT2 section see Table 6 1 Inductor selection OUT1 ILOAD 2 5 A 45 ripple current Equation 36 _ 3 37 24V 3 37 290K Hz 24V 0 45 2 5 We choose standard value L 8 2 uH Ali 1 16 VIN 24 V 2 523 2 5 0 58 3 83 OUT2 ILOAD 2 5 A 35 ripple current 40 48 PM6680A Design guidelines Equation 37 1 8 20V 1 8V 425KHiz 24V 0 35 2 5 ps We choose standard value L 4 7 uH 0 886 A 24 V 2 523 2 5 0 58 3 83 2 Output capacitor selection We would like to have an output ripple smaller than 25 mV OUT1 POSCAP 4TPE150MI OUT2 POSCAP 6TPE220M 3 Power MOSFETs OUT1 High side STSBNF60L Low side STS7NF60L OUT2 High side STSBNF60L Low side STS7NF60L 4 Current limit OUT1 Equation 38 Al mi
39. onduction circuitry management When the negative input voltage at the PWM comparator Figure 29 which is a scaled down replica of the output voltage see the external R1 R2 divider in Figure 29 reaches the valley limit determined by internal reference Vr 0 9 V the low side MOSFET is turned off according to the anti cross conduction logic once again and a new cycle begins Figure 29 Constant on time block diagram Positive Current Limit Toff min COMP 1 Anti cross Min Freq Counter Zero cross omp SKIP VREF In steady state the FB pin voltage is about Vr and the regulated output voltage depends on the external divider Equation 4 OUT 1 m 4 PM6680A Device description 7 3 Output ripple compensation and loop stability In a classic constant on time control the system regulates the valley value of the output voltage and not the average value as shown in Figure 28 this condition the output voltage ripple is source of a DC static error To compensate this error an integrator network can be introduced in the control loop by connecting the output voltage to the COMP1 COMP2 for the OUT1 and OUT2 sections respectively pin through a capacitor as in Figure 30 Figure 30 Circuitry for output ripple compensation COMP PIN Vr OUTPUT VOLTAGE The integrator amplifier generates a current proportional to the DC errors between the FB vo
40. or service described herein and shall not create or extend in any manner whatsoever any liability of ST ST and the ST logo are trademarks or registered trademarks of ST in various countries Information in this document supersedes and replaces all information previously supplied The ST logo is a registered trademark of STMicroelectronics All other names are the property of their respective owners 2007 STMicroelectronics All rights reserved STMicroelectronics group of companies Australia Belgium Brazil Canada China Czech Republic Finland France Germany Hong Kong India Israel Italy Japan Malaysia Malta Morocco Singapore Spain Sweden Switzerland United Kingdom United States of America www st com Q 48 48
41. pling place these traces as far as possible from the gate drivers and phase switching paths Place the current sense traces on the bottom side Using It is recommended to use a dedicated connection between the switching node and the current limit resistor RcsENsE PM6680A Package mechanical data 10 Note Package mechanical data In order to meet environmental requirements ST offers these devices in packages These packages have Lead free second level interconnect The category of second Level Interconnect is marked on the package and on the inner box label in compliance with JEDEC Standard JESD97 The maximum ratings related to soldering conditions are also marked on the inner box label ECOPACK is an ST trademark ECOPACK specifications are available at www st com Table 16 VFQFPN 5x5 mechanical data mm Dim Min Typ Max A 0 80 0 90 1 00 A1 0 0 02 0 05 A3 0 20 b 0 18 0 25 0 30 4 85 5 00 5 15 D2 See exposed pad variations 1 E 4 85 5 00 5 15 E2 See exposed pad variations 1 e 0 50 L 0 30 0 40 0 50 ddd 0 05 1 Dimensions D2 amp E2 are not in accordance with JEDEC Table 17 Exposed pad variations D2 E2 Min Typ Max Min Typ Max 2 90 3 10 3 20 2 90 3 10 3 20 1 VFQFPN stands for Thermally Enhanced Very thin Fine pitch Quad Flat Package No lead Very thin 1 00 mm Max 2 Dimensions D2 amp E2 are not in accor
42. rent Valley current limit 24 48 ky PM6680A Device description 7 7 Being fixed the valley threshold the greater the current ripple is greater the DC output current is The valley current limit can be set with resistor RCSENSE Equation 7 Hps on valley R CSENSE Icsense Where Icsense 100 RDSon is the drain source on resistance of the low side switch Consider the temperature effect and the worst case value in RDSon calculation The accuracy of the valley current threshold detection depends on the offset of the internal comparator and on the accuracy of the current generator AlcsENsE Equation 8 AI I Lvalley AI CSENSE i AVorr x100 di AR sys I R Lvalley CSENSE CSENSE CSENSE CSENSE SNS Where RSNS is the sensing element RDSon PM6680A provides also a fixed negative peak current limit to prevent an excessive reverse inductor current when the switching section sinks current from the load in PWM mode This negative current limit threshold is measured between PHASE and SGND pins comparing the magnitude drop on the PHASE node during the conduction time of the low side MOSFET with an internal fixed voltage of 120 mV The negative valley current limit if the device works in PWM mode is given by Equation 9 Soft start and soft end Each switching section is enabled separately by asserting high EN1 EN2 pins respectively In order
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44. the maximum required output current l Switching frequency It s possible to set 3 different working frequency ranges for the two sections with FSEL pin Table 6 Switching frequency mainly influences two parameters e Inductor size for a given saturation current and RMS current greater frequency allows to use lower inductor values which means smaller size e Efficiency switching losses are proportional to frequency High frequency generally involves low efficiency Inductor selection Once that switching frequency is defined inductor selection depends on the desired inductor ripple current and load transient performance Low inductance means great ripple current and could generate great output noise On the other hand low inductor values involve fast load transient response A good compromise between the transient response time the efficiency the cost and the size is to choose the inductor value in order to maintain the inductor ripple current Al between 20 and 50 of the maximum output current l oAp max The maximum Al occurs at the maximum input voltage With this considerations the inductor value can be calculated with the following relationship Equation 12 L Vin Vout x Vour Lo x Al Vin where fsw is the switching frequency Viy is the input voltage is the output voltage and Al is the selected inductor ripple current In order to prevent overtemperature working conditions
45. upply and PGND pin as return rail An important feature of the gate drivers is the adaptive anti cross conduction protection which prevents high side and low side MOSFETs from being on at the same time When the high side MOSFET is turned off the voltage at the phase node begins to fall The low side MOSFET is turned on when the voltage at the phase node reaches an internal threshold When the low side MOSFET is turned off the high side remains off until the LGATE pin voltage goes approximatively under 1 V The power dissipation of the drivers is a function of the total gate charge of the external power MOSFETs and the switching frequency as shown in the following equation Equation 11 Variver Where Variver is the 5 V driver supply PM6680A Device description 7 9 7 10 Reference voltage and bandgap The 1 237 V typ internal bandgap voltage is accurate to 1 96 over the temperature range It is externally available VREF pin and can supply up to 100 pA and can be used as a voltage threshold for the multifunction pins FSEL and SKIP to select the appropriate working mode Bypass VREF to ground with a 100 nF minimum capacitor If VREF goes below 0 87 V typ the system detects a fault condition and all the circuitry is turned off A toggle on the input voltage power on reset or a toggle on SHDN pin is necessary to restart the device An internal divider of the bandgap provides a
46. voltage reference Vr of 0 9 V This voltage is used as reference for the linear and the switching regulators outputs The overvoltage protection the undervoltage protection and the power good signals are referred to Vr Internal linear regulator The PM6680A has an internal linear regulator providing 5 V LDO5 at 2 accuracy High side drivers low side drivers and most of internal circuitry are supplied by LDO5 output through VCC pin an external RC filter may be applied between LDO5 and VCC The linear regulator can provide an average output current of 50 mA and a peak output current of 100 mA Bypass 005 output with a minimum ceramic capacitor and a 4 7 uF tantalum capacitor ESR 2 2 If the 5 V output goes below 4 V the system detects a fault condition and all the circuitry is turned off A power on reset or a toggle on SHDN pin is necessary to restart the device V5SW pin allows to keep the 5 V linear regulator always active or to enable the internal bootstrap switchover function if the 5 V switching output is connected to VSSW when the voltage on V5SW pin is above 4 8 V an internal 3 0 O max p channel MOSFET switch connects V5SW pin to 1005 and simultaneously LDO5 shuts down This configuration allows to achieve higher efficiency V5SW can be connected also to an external 5 V supply 1005 regulator turns off and 005 is supplied externally If V5SW is connected to ground the internal 5 V regulator is always on and supp
47. y as in PWM mode and the frequency is fixed to the nominal value Figure 31 PWM and pulse skip mode inductor current PWM mode Pulse skip mode Low side on Inductor current Figure 31 shows inductor current waveforms in PWM and SKIP mode In order to keep average inductor current equal to load current in SKIP mode some switching cycles are skipped When the output ripple reaches the regulated voltage Vreg a new cycle begins The off cycle duration and the switching frequency depend on the load condition As a result of the control technique losses are reduced at light loads improving the system efficiency PM6680A Device description 7 5 No audible skip mode If SKIP pin is tied to a no audible skip mode with a minimum switching frequency of 33 kHz is enabled At light load condition If there is not a new switching cycle within a 30 us typ period a no audible skip mode cycle begins Figure 32 No audible skip mode Inductor current No audible skip mode The low side switch is turned on until the output voltage crosses about Vreg 1 Then the high side MOSFET is turned on for a fixed on time period Afterwards the low side switch is enabled until the inductor current reaches the zero crossing threshold This keeps the switching frequency higher than 33 kHz As a consequence of the control the regulated voltage can be slightly higher than Vreg up to 1
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