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FUJITSU SEMICONDUCTOR MB90435 Series handbook

1. Continued TOP VIEW O GQ O 0 0 OO O GO O O 5 gt gt 4 gt 5 4 4 4 gt 4 gt 4 lt G O f o lt TO 0 O O O O O gt m 0 D D D O D D gt gt lt gt gt gt gt lt gt xn Q 5 9 lt O 6 O 62 00 00 00 00 00 00 00 00 gt P22 A18 1 75 RST P23 A19 2 74 7 P24 A20 3 73 6 P25 A21 4 72 P95 P26 A22 5 71 P94 P27 A23 6 70 P93 INT3 P30 ALE 7 69 P92 INT2 P31 RD 8 68 P91 INT1 Nss 9 67 P90 INTO P32 WRL WR 10 66 P87 TOT1 P33 WRH 11 65 P86 TIN1 P34 HRQ 12 64 P85 OUT1 P35 HAK 13 63 0 P36 RDY 4 62 P83 PPG3 P37 CLK 15 61 P82 PPG2 P40 SOTO 6 60 P81 PPG1 P41 SCKO 7 59 P80 PPGO P42 SINO 18 58 P77 OUT3 IN7 P43 SIN1 19 57 P76 OUT2 IN6 P44 SCK1 20 56 P75 IN5 Vcc 21 55 P74 IN4 P45 SOT1 22 54 P73 IN3 P46 SOT2 23 53 P72 IN2 P47 SCK2 24 52 P71 IN1 25 51 P70 INO x 9 r
2. Address Register Abbreviation Access Resource name Initial value Serial mode register 1 SMR1 0000000 0s Serial control register 1 SCR1 000001008 Serial output data register SODRI 06000006 Serial status register 1 SSR1 00001 008 UART1 prescaler control register U1CDCR Serial Edge select register SES1 Prohibite Serial I O prescaler SCDCR Serial mode control register SMCS Serial mode control register SMCS 2 0000001 Os Serial data register SDR Serial Edge select register SES2 External interrupt enable register ENIR 0000000 0s External interrupt request register EIRR XXXXXXXXs External Interrupt External interrupt level register ELVR 0000000 0 External interrupt level register ELVR 0000000 0 A D control status register 0 ADCSO 0000000 0 A D control status register 1 ADCS1 0000000 08 A D data register 0 ADCRO XXXXXXXXs A D data register 1 ADCR1 00001 _ PPGO operation mode control register PPGCO 16 bir Programmable 0 000 18 PPG1 operation mode control register PPGC1 Pulse 0 0000015 0 1 clock selection register 1 u O Prohibited 2 operation mode control register PPGC2 R W Programmable 0 000 15 operation mode control register PPGC3 R W Pulse 0 88 PPG2 3 Clock Selection Register PPG23 RW Genere 100000 x Prohibited 400 PPG4 ope
3. 0 Gq QI QI QI C co 0 C c gt cO co co CO C sb SE 8 9 9 6 25 95289 99 gt AK 555555338 55 5 757 EAH 5 Pu a dq 88888 5 0 100 05 MB90435 Series PIN DESCRIPTION PinNo Circuit type Function LQFP 80 82 X0 A 81 83 X1 Oscillation High speed crystal oscillator input pins Low speed crystal oscillator input pins For the one clock 78 system parts perfom external pull down processing Oscillation Low speed crystal oscillator input pins For the one clock 77 79 X1A system parts leave it open 75 77 RST External reset request input pin 50 52 HST Hardware standby input pin P00 to PO7 General port with programmable pull up This function is enabled in the single chip mode 83 to 90 85 to 92 n OPE nm e AD00 to ADO7 pins for 8 ower bits of the externa address data bus This function is enabled when the external bus is enabled General I O port with programmable pull up This function is P10 to P17 enabled in the single chip mode 91 to 98 93 to 100 EE 08 to AD15 pins or8 igher bits of the externa address data bus This function is enabled when the external bus is enabled General I
4. FUJITSU SEMICONDUCTOR DATA SHEET 0 07 13727 1 16 bit Proprietary Microcontroller CMOS F2MC 16LX MB90435 Series MB90437L 438 F438L MB90439 S 439 S V540G DESCRIPTION The MB90435 series with FLASH ROM is specially designed for industrial applications The instruction set by F2MC 16LX CPU core inherits an AT architecture of the F MC family with additional instruction sets for high level languages extended addressing mode enhanced multiplication division instruc tions and enhanced bit manipulation instructions The micro controller has a 32 bit accumulator for processing long word data The MB90435 series has peripheral resources of 8 10 bit A D converters UART SCI extended I O serial interfaces 8 16 bit timer I O timer input capture ICU output compare OCU 2 stands for FUJITSU Flexible Microcontroller FEATURES Clock Embedded PLL clock multiplication circuit Operating clock PLL clock can be selected from divided by 2 of oscillation or one to four times the oscillation Minimum instruction execution time 62 5 ns operation at oscillation of 4 MHz four times the oscillation clock Vcc of 5 0 V Subsystem Clock 32 kHz Continued PACKAGES 100 pin Plastic QFP 100 pin Plastic LQFP FP T 100P M06 FP T 100P M05 FUJITSU MB90435 Series Instruction set to optimize controller appl
5. 25 Input capacity Cin Other than AVcc AVss AVRH C Vcc Vss The power supply current testing conditions are when using the external clock 890435 Series 4 AC Characteristics 1 Clock Timing MB90F438L S 437L 438L S Vcc 3 5 V to 5 5 V Vss AVss 0 0 V Ta 40 C to 105 C MB90F439 439 V540G Vcc 5 0 V 10 Vss AVss 0 0 V Ta 40 C to 105 C Parameter Oscillation frequency Symbol fc Pin name name Vcc 5 0 10 Vcc 4 5 MB90F438L S 437L S 438L S Oscillation cycle time tcv Vcc 5 0 10 Vcc 4 5 MB90F438L S 437L S 438L S tLeyL Input clock pulse width Duty ratio is about 30 to 70 Input clock rise and fall time tcn tcr When using external clock When using main clock Machine clock frequency When using sub clock When using main clock Machine clock cycle time When using sub clock Clock Timing 33 MB90435 Series Guaranteed PLL operation range Guaranteed operation range MB90F439 S 439 S V540G operation range m 5 5 Power supply voltage Vcc S 3 5 Guaranteed PLL operation range MB90F438L S 437L
6. MB90F438L 437 438 5 Maintain RAM data in stop mode Smooth capacitor Operating temperature Use a ceramic capacitor or a capacitor of better 4 AC characteristics The Vcc Capacitor should be greater than this capacitor WARNING The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device All of the device s electrical characteristics are warranted when the device is operated within these ranges Always use semiconductor devices within their recommended operating condition ranges Operation outside these ranges may adversely affect reliability and could result in device failure No warranty is made with respect to uses operating conditions or combinations not represented on the data sheet Users considering application outside the listed conditions are advised to contact their FUJITSU representatives beforehand C Pin Connection Diagram Cs 3 DC Characteristics MB90F438L 437 438L S Vcc 3 5 V to 5 5 Vss AVss 0 0 V Ta 40 C to 105 Parameter Input H voltage Pin name name CMOS hysteresis input pin Condition MB90435 Series Vcc 3 MB90F439 439 V540G Vcc 5 0 V 10 Vss AVss 0 0 V Ta 40 C to 105 C Remarks TTL input pin MD input pin Vcc 3 Input voltage CMOS hysteresis
7. 10 Timer Input Timing MB90F438L S 437L 5 438L S Vcc 3 5 V to 5 5 V Vss AVss 0 0 V TA 40 C to 105 C MB90F 4339 S 439 S V540G Vcc 5 0 V 10 Vss AVss 0 0 V Ta 40 to 105 C Parameter Symbol name Condition Mi uns Remarks TINO 10 1 Input pulse width tmr TINO TU 4 tcp ns Timer Input Timing 11 Timer Output Timing MB90F438L S 437L 5 438 S Vcc 3 5 V to 5 5 V Vss AVss 0 0 V TA 40 C to 105 C MB90F 4339 S 439 S V540G Vcc 5 0 V 10 Vss AVss 0 0 V Ta 40 to 105 C Value Parameter name Condition nts TOTO to TOT1 Timer Output Timing Le V CLK 24V TOUT 0 8V 45 MB90435 Series 12 Trigger Input Timing MB90F438L S 437L 438L S Vcc 3 5 V to 5 5 V Vss AVss 0 0 V Ta 40 C to 105 C MB90F 439 S 439 S V540G Vcc 5 0 V 10 Vss AVss 0 0 V Ta 40 C to 105 C Parameter Symbol Condition Kemana Min Max PT tren INTO to INT7 5 Under nomal operation Trigger Input Timing E idi cu Vcc 46 5 A D Converter Electrical Characteristics MB90435 Series Vcc AVcc 5 0 10 Vss 0 0 V 3 0 V lt AVRH AVRL Ta 40
8. MB90435 Series 1 PIN ASSIGNMENT e 9 66 2 9 O N O O 5 5 5545554044 44 025 z gt lt lt S D 5 ooo BR 5 5 0 100 06 TOP VIEW 5 5 8 5 5 8 5 5 6 5 5 8 8 5 8 gt gt 68 s 000 OR amp 2 0 lt lt lt 1111 11111 111111 11111 11111 11111 11 11 5 5 amp 5 8 5 5 8 5 8 8 G 8 885 P20 A16 17 21 17 2 O X1A P22 A18 3 PAO P23 A19 4 RST P24 A20 5 P97 P25 A21 6 P96 P26 A22 7 P95 P27 A23 8 P94 P30 ALE 9 P93 INT3 P31 RD 10 P92 INT2 Vss 11 P91 INT1 P32 WRL WR 12 P90 INTO P33 WRH 13 P87 TOT1 P34 HRQ 14 P86 TIN1 P35 HAK 15 P85 OUT1 P36 RDY 16 P84 OUTO P37 CLK 17 P83 PPG3 P40 SOTO 18 P82 PPG2 P41 SCKO 19 P81 PPG1 P42 SINO 20 P80 PPGO P43 SIN1 21 P77 OUT3 IN7 P44 SCK1 22 P76 OUT2 IN6 23 P75 IN5 P45 SOT1 24 P74 IN4 P46 SOT2 25 P73 IN3 P47 SCK2 26 P72 IN2 27 P71 IN1 P50 SIN2 28 P70 INO P51 INT4 29 HST P52 INT5 30 2 Continued MB90435 Series 1
9. 20 2 10 16 2 15 2 20 Bus Timing Write CLK ALE A16 to A23 ADOO to 015 tAVWL lt tWLCH 24V Address TWLWH tDVWH tWHLH 24V Write data 41 MB90435 Series 7 Ready Input Timing MB90F438L S 437L 438 S Vcc 3 5 V to 5 5 V Vss AVss 0 0 V Ta 40 C to 105 C MB90F439 439 5 V540G 5 0 10 Vss AVss 0 0 V 40 C to 105 C Parameter Symbol name Condition Note If the RDY setup time is insufficient use the auto ready function Ready Input Timing CLK ALE RD WR RDY no WAIT is used RDY When WAIT is used 1 cycle 42 MB90435 Series 8 Hold Timing MB90F438L S 437L S 438 S 8 5 V to 5 5 Vss AVss 0 0 V 40 C to 105 90 439 S 439 V540G Vcc 5 0 V 10 Vss AVss 0 0 V Ta 40 C to 105 C Parameter Symbol name Condition Pin floating gt HAKJtime HAK Ttime Pin valid time HAK Note There is more than 1 cycle from the time HRQ is read to the time the HAK is changed Hold Timing HAK gom Each pin 9 UARTO 1 Serial I O Timing MB90F438L S 437L S 438 S
10. 16 bit Output Compare 4 channels 16 bit Input Capture 8 channels 8 16 bit Programmable Pulse Generator 4 channels 32 kHz Sub clock External Interrupt 8 channels Can be programmed edge sensitive or level sensitive External bus interface External access using the selectable 8 bit or 16 bit bus is enabled external bus mode Ports Virtually all external pins be used as general purpose I O All push pull outputs and schmitt trigger inputs Bit wise programmable as input output or peripheral signal Supports automatic programming Embeded Algorithm Write Erase Erase Suspend Erase Resume commands A flag indicating completion of the algorithm Number of erase cycles 10 000 times Data retention time 10 years Boot block configuration Erase can be performed on each block Block protection by externally programmed voltage 1 Under development 2 If the one clock system is used equip and X1A with clocks from the tool side 3 Itis setting of DIP switch S2 when Emulator pod MB2145 507 is used Please refer to the MB21 45 507 hardware manual 2 7 Emulator specific Power Pin about details 4 Embedded Algorithm is a trade mark of Advanced Micro Devices Inc 5 OPERATING VOLTAGE RANGE Products MB90F 4339 S 439 S V540G Flash Memory Operation guarantee range 4 5 V to 5 5 V 8904381 S 437L S 438 3 5 V to 5 5 V
11. C to 105 C Parameter Resolution Conversion error L Nonlinearity error Differential nonlinearity error Zero transition voltage ANO to AN7 AVRL 3 5 LSB AVRL 0 5 LSB AVRL 4 5 LSB Full scale transition voltage ANO to AN7 AVRH 6 5 LSB AVRH 1 5 LSB AVRH 4 1 5 LSB Compare time Sampling time 352 tcp Internal frequency 16 MHz Internal frequency 16 MHz Analog port input current ANO to AN7 1 Vcc 5 0 V 1 Analog input voltage range ANO to AN7 AVRL AVRH Reference voltage range AVRH AVRL 2 7 AVcc AVRL 7 Power supply current AVcc AVcc Reference voltage supply current AVRH Flash device Mask ROM AVRH Offset between input channels When not using an A D converter this is the current Vcc ANO to AN7 AVcc AVRH 5 0 V when the CPU is stopped Note The functionality of the A D converter is only guaranteed for VCC 5 0 V 10 also for MB90F438L S 437 S 438L S 47 MB90435 Series A D Converter Glossary Resolution Analog changes that are identifiable with the A D converter Linearity error The deviation of the straight line connecting the zero transition point 00 0000 0000 00 0000 0001 with the full scale transition point 11 1111 1110 lt 11 1111 1111
12. 001008 Watch timer control register WTC Watch Timer 1 8 ABu to AD Prohibited Flash memory control status register Flash only otherwise reserved FMCS Flash Memory 000X000 0s AFu Interrupt control register 00 Prohibited ICROO 1 Interrupt control register 01 ICRO1 2 Interrupt control register 02 ICRO2 Interrupt control register 03 ICRO3 4 Interrupt control register 04 ICRO4 5 Interrupt control register 05 Interrupt control register 06 15305 ICRO6 73 Interrupt control register 07 ICRO7 B8u Interrupt control register 08 ICRO8 9 Interrupt control register 09 ICRO9 Interrupt control register 10 ICR10 BBu BCu Interrupt control register 11 Interrupt control register 12 ICR11 ICR12 BDu Interrupt control register 13 ICR13 Interrupt control register 14 ICR14 BFu Interrupt control register 15 ICR15 Interrupt controller 000001118 000001118 000001118 000001118 0000011 18 0000011 1s 000001118 0000011 18 000001118 000001118 000001118 000001118 000001118 0000011 1s 0000011 18 000001118 to FFu Address 1 Register Program address detection register 0 External Abbreviation Access 1 Program address detection re
13. 8 5 V to 5 5 V Vss AVss 0 0 V Ta 40 C to 105 90 439 S 439 S V540G 5 0 V 10 Vss AVss 0 0 V Ta 40 C to 105 C Parameter Symbol Condition unis omar Serial clock cycle time 15 SCKO to SCK2 SCKO to SCK2 SOTO to SOT2 Internal clock opera SCKO to 502 output pins are Valid SIN SCKT tivsH SINO to SIN2 C 80 pF 1 TTL SCKO to SCK2 SINO to SIN2 Serial clock H pulse width 8 to SCK2 Serial clock L pulse width SCKO to SCK2 SCKO to SCk2 External clock oper SOTO to SOT2 ation output pins are SCKO to SCK2 80 pF 1 TTL SIN0 to SIN2 SCKO to SCK2 SINO to SIN2 5064 3507 delay time tsLov SCKT Valid SIN hold time tsHix 5064 3507 delay time tsLov Valid SINGSCKT tivsH SCKT Valid SIN hold time tsHix Notes e AC characteristic in CLK synchronized mode is load capacity value of pins when testing e For tce Machine clock cycle time refer to 1 Clock Timing 43 44 MB90435 Series Internal Shift Clock Mode SCK SOT SIN 0 8 Vcc 0 2 Vcc tiVSH tSHIX 0 8 Vcc 0 2 Vcc External Shift Clock Mode SCK SOT SIN HISLSH P 0 2 Vcc 0 2 Vcc a 1551 MB90435 Series
14. LSB Differential linearity error _ V u i of digital N TLSB 1 LSB LSB 1 LSB Vrsr 1022 Vor Voltage at transition of digital output from 0003 to 0010 Vest Voltage at transition of digital output from to Notes on Using A D Converter Select the output impedance value for the external circuit of analog input according to the following conditions Output impedance values of the external circuit of 15 or lower are recommended When capacitors are connected to external pins the capacitance of several thousand times the internal capacitor value is recommended to minimized the effect of voltage distribution between the external capacitor and internal capacitor Note When the output impedance of the external circuit is too high the sampling period for analog voltages may not be sufficient sampling period 4 00 us 9 machine clock of 16 MHz Equipment of analog input circuit model 5 Analog input 3 2 Max The smaller the AVRH AVRL the greater the error would become relatively 30 pF Max Error 49 50 MB90435 Series 1 6 Flash Memory Program Erase Characteristics Parameter Sector erase time Chip erase time Word 16 bit width programming time Condition 25 C Vcc 5 0 V ma Excludes 00x programming prior erasure MB90F438L S Excludes 00 pr
15. S 438L Guaranteed PLL operation range MB90F439 S 439 S V540G 1 5 8 16 Machine clock MHz External clock frequency and Machine clock frequency 16 Machine clock 12 fce MHz A 8 4 8 16 External clock fc MHz 34 MB90435 Series 1 AC characteristics are set to the measured reference voltage values below Input signal waveform Output signal waveform Hysteresis Input Pin Output Pin 2 4 mama 0 8 V c 35 MB90435 Series 2 Clock Output Timing MB90F438L S 437 438L S Vcc 3 5 V to 5 5 V Vss AVss 0 0 V Ta 40 C to 105 C MB90F439 S 439 S V540G Vcc 5 0 V 10 Vss AVss 0 0 V Ta 40 C to 105 C Parameter Symbol name Condition min wax at ee 71 CLK 3 Reset and Hardware Standby Input Timing MB90F438L S 437L 438 S Vcc 3 5 V to 5 5 V Vss AVss 0 0 V Ta 40 C to 105 C 90 439 S 439 V540G Vcc 5 0 V 10 Vss AVss 0 0 V Ta 40 C to 105 C ES name Remarks Parameter Symbol Under normal operation Oscillation time of In stop mode oscillator 4 tcp Pseudo timer mode 199 MB90437L 438 S Reset input time Pseudo timer mode 4 top Other than MB90437L S 438L S In sub clock mode sub sleep mode and watc
16. are used for creating a power on reset Some registers in the device are initialized only upon a power on reset To initialize these register turn on the power supply using the above values Ae Vcc V 0 2V 0 2 V 0 2 tOFF Sudden changes in the power supply voltage may cause a power on reset To change the power supply voltage while the device is in operation it is recommended to raise the voltage smoothly to suppress fluctuations as shown below In this case change the supply voltage with the PLL clock not used If the voltage drop is 1 V or fewer per second however you can use the PLL clock T is recommended to keep the rising speed of the supply voltage RAM data being held at 50 mV ms or slower 38 5 Bus Timing Read MB90435 Series MB90F438L 437L 438 S Vcc 3 5 V to 5 5 V Vss AVss 0 0 Ta 40 C to 105 C MB90F439 439 S V540G Vcc 5 0 V 10 Vss AVss 0 0 V Ta 40 C to 105 C Parameter ALE pulse width Valid address ALE time Symbol TLHLL name ALE 16 to A23 ADOO 5 ALEJ Address valid time ALE 000 5 Valid address RDtime 16 toA23 ADOO to AD15 RD Valid address Valid data input 16 to 23 000 5 RD pulse width RD RDJ Valid data input RDT Data hold time
17. input pin 0 2 Vcc TTL input pin MD input pin Output H voltage All output pins Vcc 4 5 V lou 4 0 mA Output L voltage All output pins Vcc 4 5 V lo 4 0 mA Input leak current Pull up resistance to P07 P10 to P17 P20 to P27 P30 to P37 RST Vcc 5 5 V Vss gt Vi lt Vcc Pull down resistance MD2 Continued 31 32 MB90435 Series Continued Parameter Sym bol Pin name name Condition MB90F438L S 437L 438L S Voc 3 5 V to 5 5 V Vss AVss 0 0 V Ta 40 C to 105 C MB90F439 439 V540G Vcc 5 0 V 10 Vss AVss 0 0 V 40 C to 105 C x Remarks Power supply current lccr lccue Internal frequency 16 MHz At normal operating Internal frequency 16 MHz At Flash programming erasing Flash device Internal frequency 16 MHz At sleep mode 5 0V 1 Internal frequency 2 MHz At pseudo timer mode MB90F348L 5 MB90437L 5 438L S Internal frequency 8 kHz At sub operation Ta 25 C MB90F438L S Mask ROM Flash device Internal frequency 8 kHz At sub sleep Ta 25 C Internal frequency 8 kHz At timer mode Ta 25 C At stop Ta 25 C At hardware standby mode
18. register specifies a port 41 to 44 48 to 46 Analog input pins for the 8 10 bit A D converter This function is enabled when the analog input enable register specifies A D P56 General I O port This function is always enabled Event input pin for the 16 bit reload timers 0 Set the TINO corresponding Port Direction Register to input if this function is used Continued 10 name P57 TOTO Circuit type MB90435 Series 1 ma General I O port This function is enabled when the 16 bit reload timers 0 disables the output Output pin for the 16 bit reload timers 0 This function is enabled when the 16 bit reload timers 0 enables the output 51 to 56 53 to 58 P70 to P75 INO to IN5 General I O ports This function is always enabled Trigger input pins for input captures ICUO to ICU5 Set the corresponding Port Direction Register to input if this function is used P76 P77 OUT2 OUT3 IN6 IN7 General I O ports This function is enabled when the OCU disables the waveform output Event output pins for output compares OCU2 and OCUS This function is enabled when the OCU enables the waveform output Trigger input pins for input captures ICU6 and ICU7 Set the corresponding Port Direction Register to input and disable the OCU waveform output if this function is used 61 to 64 P80 to P83 PPGO to PPG3 Gene
19. tRHDx RD 000 5 RD 5 000 DJ ALETtime tRHLH RD ALE Address valid time RD A16 to 3 Valid address CLKTtime tavcH 16 to A23 000 to AD15 CLK RDJ CLKkTtime tRLCH RD CLK ALEJ RDJtime ALE RD Condition 10 2 20 10 2 0 tcp 2 5 tcr 5 5 tcp 2 60 3 tce 2 20 3 09 2 0 2 15 10 2 0 10 2 0 10 2 0 2 5 39 MB90435 Series Bus Timing Read CLK ALE M tRLRH V tAVLL gt A16 to A23 40 MB90435 Series 6 Bus Timing Write MB90F438L 437 438 Vcc 3 5 V to 5 5 V Vss AVss 0 0 V Ta 40 C to 105 C MB90F439 439 S V540G Vcc 5 0 V 10 Vss AVss 0 0 V Ta 40 C to 105 C Parameter Valid address gt WR Itime WR pulse width Symbol twLwH name 16 to A23 ADOO to AD15 WR WR Valid data output 2WRTtime tovwH ADOO to AD15 WR RT Data hold time twHbx ADOO to AD15 WR RT 4Address valid time twHax 16 to A23 WR WRT gt ALETtime tWHLH WR ALE WRT CLK Ttime WR CLK Condition 6 2 20 Remarks 6 2 20
20. this operation however cannot be guaranteed 18 MB90435 Series BLOCK DIAGRAM XO X1 X1A Clock RST Controller HST RAM 2 K 4 K 6 K 8 6 ROM Flash 64K 128 K 256 K ROM only SCKO SINO SCK1 SCI SIN1 SCK2 SIN2 AVcc AVss ANO to AN7 10 bit A D AVRH Converter ch 8 AVRL ADTG F2MC 16LX CPU FMC 16 Bus 16 bit Timer 16 bit Input Capture 8 ch 16 bit Output Compare 4 ch 8 16 bit PPG 4 ch 16 bit Reload Timer 2 ch External Bus Interface External Interrupt 8 ch INO 5 IN6 OUT2 IN7 OUTS OUTO OUT1 PPGO to PPG3 TINO TIN1 TOTO TOT1 000 to AD15 A16 to A23 ALE RD WRL WRH HRQ HAK RDY CLK INTO to INT7 MEMORY MAP The memory space of the MB90435 Series is shown below MB90435 Series MB90V540G MB90F437L S MB90F438L S 438L S MB90F439 S 439 S FFFFFFH FFFFFFH FFFFFFH FFFFFFH ROM ROM ROM ROM FF bank FF bank FF bank FF bank FFOOOOH FFOOOOH FFOOOOH FFOOOOH FEFFFFH FEFFFFH FEFFFFH ROM ROM ROM FE bank FE bank FE bank FEOOOOH FEOOOOH FDFFFFH FDFFFFH ROM ROM FD bank FD bank FDOOOOH External FDOOOOH FCFFFFH FCFFFFH ROM External ROM FC bank FC bank OOFFFFH OOFFFFH ROM ROM OOFFFFH ROM OOFFFFH ROM Image of Image of Image of Image of 0
21. 04000H FF bank 004000H FF bank 004000H FF bank 004000H FF bank 003FFFH 003FFFH 003FFFH 003FFFH Peripheral Peripheral Peripheral Peripheral 003900H 003900H 003900H 003900H 002000H 002000H 002100H 001 5 0018FFH 001505 ROM correction 0010FFH 0008FFH RAM 2 4 000100H 0001001 000100H 000100H 0000BFH 0000BFH 0000BFH Peripheral Peripheral Peripheral Peripheral 000000H 000000 000000 000000 Under development Note The high order portion of bank 00 gives the image of the FF bank ROM to make the small model of the C compiler effective Since the low order 16 bits address are the same the table in ROM can be referenced without using the far specification in the pointer declaration For example an attempt to access 00 000 accesses the value at FFC000u in ROM The ROM area in bank FF exceeds 48 Kbytes and its entire image cannot be shown in bank 00 The image between FF4000n FFFFFFais visible in bank 00 while the image between FF0000 and FF3FFFa is visible only in bank FF 19 20 MB90435 Series I O Address Register Port 0 data register Port 1 data register Abbreviation Access Resource name Initial value XXXXXXXXs XXXXXXXXs Port 2 data register XXXXXXXXs Port 3 data register XXXXXXXXs Port 4 data register XXXXXXXXs Port 5 data register XXXXXXXXs 07 Port 6 data register Port 7 data register PDR7 XXXXXXXX
22. 31 25 K 62 5 K 125 K 500 K 1 Mbps at System clock 16 MHz A D Converter 10 bit or 8 bit resolution 8 input channels Conversion time 26 3 us per one channel Continued 890435 Series Continued Features MB90F438L S F439 S MB90V540G 438L S 439 S Operation clock frequency fsys 2 1575 23 fsys 25 fsys System clock frequency Supports External Event Count function Signals an interrupt when overflow Supports Timer Clear when a match with Output Compare Channel 0 Operation clock freq fsys 22 fsys 24 fsys 2 15 5 25 fsys System clock freq Signals an interrupt when a match with 16 bit Timer Four 16 bit compare registers A pair of compare registers can be used to generate an output signal Rising edge falling edge or rising amp falling edge sensitive Four 16 bit Capture registers Signals an interrupt upon external event Supports 8 bit and 16 bit operation modes Eight 8 bit reload counters Eight 8 bit reload registers for L pulse width Eight 8 bit reload registers for H pulse width A pair of 8 bit reload counters can be configured as one 16 bit reload counter or as 8 bit prescaler plus 8 bit reload counter 4 output pins Operation clock freq fsys fsys 2 fsys 2 fsys 23 fsys 2 or 128 us fosc 4 MHz fsys System clock frequency fosc Oscillation clock frequency Sub clock for low power operation 16 bit Reload Timer 2 channels 16 bit I O Timer
23. 37LSPFV 100 5 MB90438LPFV MB90438LSPFV MB90439PFV MB90439SPFV 56 PACKAGE DIMENSIONS MB90435 Series 1 100 pin Plastic QFP 100 06 23 90 0 40 941 016 Note Pins width pins thickness include plating thickness 008 c INDEX 0 65 026 0 32 0 05 4 5 0 10 004 Ex 17 90 0 40 O 705 016 E 14 00 0 20 551 008 d ES LES Details of A part EG Li 30015 10 251010 am f N 035002 2001 FUJITSU LIMITED F100008S c 4 4 mor al 0 13 005 06 00700 0 80 0 20 0 25 0 20 0315 008 010 008 0 88 0 15 Stand off 035 006 Dimensions in mm inches 100 pin Plastic LQFP 100 5 Note Pins width and pins thickness include plating thickness 2000 FUJITSU LIMITED F100007S 3c 5 14 0010 101 55t12 004 50 ES S 0 08 003 Deta
24. Capture Register 1 IPCP1 391 Input Capture Register 2 IPCP2 3911 Input Capture Register 2 IPCP2 3916 Input Capture Register 3 IPCP3 391Fu Input Capture Register 3 IPCP3 3920 Input Capture Register 4 IPCP4 3921 Input Capture Register 4 IPCP4 39220 Input Capture Register 5 IPCP5 39238 Input Capture Register 5 IPCP5 39240 Input Capture Register 6 IPCP6 39258 Input Capture Register 6 IPCP6 39268 Input Capture Register 7 IPCP7 3927 Input Capture Register 7 IPCP7 Reserved Continued Input Capture 0 1 Input Capture 2 3 Input Capture 4 5 Input Capture 6 7 Di D D D D D D D D D D D D D Dd 24 MB90435 Series Continued Address Register Abbreviation Access Resource name Initial value 39288 Output Compare Register 0 OCCPO 3929 Output Compare Register 0 OCCPO XXXXXXXXs Output Compare 0 1 392 Output Compare Register 1 OCCP1 XXXXXXXXs 392 Output Compare Register 1 XX
25. FAOn External Interrupt INT4 INT5 FFFF9Cu Input Capture 1 FFFF98u 8 16 bit PPG 2 3 FFFF94u External Interrupt INTG INT7 FFFF90u Watch Timer FFFF8CH 8 16 bit PPG 4 5 FFFF88x Input Capture 2 3 3 FFFF84n 8 16 bit PPG 6 7 3 FFFF80n Output Compare 0 3 FFFF7Cu Output Compare 1 3 FFFF78u Input Capture 4 5 3 FFFF74u Output Compare 2 3 Input Capture 6 7 3 FFFF70u 16 bit Reload Timer 1 3 FFFF6CH UART 0 RX FFFF68x UART 0 TX 3 FFFF64u UART 1 RX 3 FFFF60n UART 1 TX 5 FFFF58x Delayed interrupt FFFF54u ICROO 0000B0 ICRO1 000081 ICRO2 000082 ICRO3 000053 ICRO4 000084 15305 000085 ICRO6 000086 ICRO7 000087 ICRO8 0000B8 ICR09 0000B9 ICR10 0000 16111 0000 ICR12 0000008 ICR13 000080 16 14 0000058 ICR15 0000 MB90435 Series 1 The interrupt request flag is cleared by the EOS interrupt clear signal 2 The interrupt request flag is cleared by the EI2OS interrupt clear signal A stop request is available Notes e The interrupt request flag is not cleared by the EIOS interrupt clear signal For a peripheral module with two interrupt causes for a single interrupt number both interrupt request flags are cleared by the El OS interrupt clear signal e At the end of EIPOS the EI OS clear signal will be asserted for all t
26. O port with programmable pull up In external bus P20 to P27 mode this function is valid when the corresponding bits in the external address output control register HACR are set to 1 99106 1108 8 bit output pins for A16 to A23 at the external address bus In A16 to A23 external bus mode this function is valid when the correspond ing bits in the external address output control register HACR are set to O 3 General I O port with programmable pull up This function is P30 7 enabled in the single chip mode Address latch enable output pin This function is enabled ALE when the external bus is enabled 3 General I O port with programmable pull up This function is P31 10 enabled in the single chip mode BM Read strobe output pin for the data bus This function is enabled when the external bus is enabled General I O port with programmable pull up This function is P32 enabled in the single chip mode or when the WR WRL pin output is disabled 10 12 WRL Write strobe output pin for the data bus This function is enabled when both the external bus and the WR WRL pin output are enabled WRL is write strobe output pin for the WR lower 8 bits of the data bus in 16 bit access WR is write strobe output pin for the 8 bits of the data bus in 8 bit access Continued MB90435 Series Circuit anton P
27. XXXXXXs 392Cu Output Compare Register 2 OCCP2 XXXXXXXXs 392Du Output Compare Register 2 OCCP2 R W Output Compare 2 3 392 Output Compare Register 3 OCCP3 R W XXXXXXXXs 392Fu Output Compare Register 3 OCCP3 R W XXXXXXXXs 3930 10 Reserved 39FFu 00 to 33004 to 90008 to 90008 to 3DFFu 3E00 to Read write notation R W Reading and writing permitted Reserved Reserved Reserved Reserved Reserved Read only W Write only Initial value notation 0 Initial value is 0 1 Initial value is 1 X Initial value is undefined Note Any write access to reserved addresses in I O map should not be performed A read access to reserved addresses results in reading X 25 MB90435 Series 1 INTERRUPT MAP Interrupt vector Interrupt control register Interrupt cause Number Address Number Address Reset 08 FFFFDCH INT9 instruction 09 FFFFD8u Exception 4 Reserved FFFFDOu Reserved FFFFCCu Reserved 8 Reserved 4 External Interrupt 1 Time Base Timer FFFFBCu 16 bit Reload Timer 0 FFFFB8x 8 10 bit A D Converter 4 Timer External Interrupt INT2 INT3 FFFFACH Serial I O FFFFA8x 8 16 bit PPG 0 1 FFFFA4H Input Capture 0 3 FFF
28. c Ta 425 C ICCH1 uA lccH1 Voc STOP Ta 25 C 53 54 MB90435 Series Power supply current MB90F439 Icc Vcc Ta 25 Z ae 12 MHz Fd ul 8 MHz Voc V 14 12 Ices Vcc 25 C ICTS Vcc 600 500 25 C 400 300 uA 200 100 Voc V 300 250 200 ICCL uA 5 100 50 Ta 25 C MB90435 Series uA Voc Ta 25 vcc V IccT uA Vcc Ta 25 Vcc V 100 ICCH2 nA IccH2 Vcc hardware standby Ta 25 C 4 5 6 7 Voc V ICCH1 uA Vcc STOP Ta 25 55 MB90435 Series 1 ORDERING INFORMATION Part number Package 02222 Remarks MB90F438LPF MB90F438LSPF MB90F439PF MB90F439SPF MB90437LPF 100 pin Plastic QFP MB90437LSPF 100 06 MB90438LPF MB90438LSPF MB90439PF MB90439SPF MB90F438LPFV MB90F438LSPFV MB90F439PFV MB90F439SPFV MB90437LPFV 100 pin Plastic LQFP MB904
29. chnology I O port General purpose I O ports 81 ports Timer Watchdog timer 1 channel 8 16 bit PPG timer 8 16 bit x 4 channels 16 bit re load timer 2 channels 16 bit I O timer 16 bit free run timer 1 channel Input capture 8 channels Output compare 4 channels Extended I O serial interface 1 channel UART 0 With full duplex double buffer 8 bit length Clock asynchronized or clock synchronized with start stop bit transmission can be selectively used Continued 890435 Series 1 Continued UART 1 With full duplex double buffer 8 bit length Clock asynchronized or clock synchronized serial extended I O serial can be used External interrupt circuit 8 channels A module for starting an extended intelligent I O service 05 and generating an external interrupt which is triggered by an external input Delayed interrupt generation module Generates an interrupt request for switching tasks 8 10 bit A D converter 8 channels 8 10 bit resolution can be selectively used Starting by an external trigger input Conversion time 26 3 us External bus interface Maximum address space 16 Mbytes Package QFP 100 LQFP 100 Embedded Algorithm is a trade mark of Advanced Micro Devices Inc MB90435 Series PRODUCT LINEUP MB90F438L S F439 MB90V540G Features CPU F2MC 16LX CPU System clock On chip PLL clock multiplier x1 x2 x3 x4 1 2 when PLL st
30. des the B input potential may pass through the protective diode and increase the potential at the Vcc pin and this may affect other devices Note that if B signal is input when the microcontroller current is off not fixed at 0 V the power supply is provided from the pins so that incomplete operation may result Note that if the B input is applied during power on the power supply is provided from the pins and the resulting supply voltage may not be sufficient to operate the power on result Continued MB90435 Series Continued Care must be taken not to leave the B input pin open Note that analog system input output pins other than the A D input pins LCD drive pins comparator input pins etc cannot accept B signal input Sample recommended circuits Input Output Equivalent circuits diode Limiting 1 een resistance W B input 0 V to 16 V Note Average output current operating current x operating efficiency WARNING Semiconductor devices can be permanently damaged by application of stress voltage current temperature etc in excess of absolute maximum ratings Do not exceed these ratings 29 30 MB90435 Series 2 Recommended Conditions Vss AVss 0 0 V Parameter Symbol Min T Units Remarks Under normal operation MB90F439 439 V540G Power supply voltage Under normal operation
31. from actual conversion characteristics Differential linearity error The deviation of input voltage needed to change the output code by 1 LSB from the theoretical value Total error The total error is defined as a difference between the actual value and the theoretical value which includes zero transition error full scale transition error and linearity error Total error Digital output lt Actual conversion characteristics Theoretical characteristics AVRL AVRH Analog input AVRH AVRL 1024 Vor Theoretical value AVRL 0 5 LSB V 1 LSB Theoretical value V Vest Theoretical value 1 5 LSB 1158 4 1 05188 oo Total error for digital output N TLSB Vnr Voltage at a transition of digital output from 1 to Continued 48 MB90435 Series Continued Linearity error Differential linearity error Theorential characteristics conversion value 1 LSB x N 1 N 1 Actual conversion value measured value 8 8 Actual conversion 8 measured value characteristics 5 N 1 measured value Theoretical Acturel characteristics turel conversion measured value AVRL AVRH AVRL AVRH Analog input Analog input Linearity error of _ Vnt 1 LSB x N 1 LSB digital output N 7 1
32. gister 0 1 2 Program address detection register 0 1FF3H Program address detection register 1 1 4 Program address detection register 1 1 5 Program address detection register 1 Resource name Address Match Detection Function Initial value Continued 23 MB90435 Series Address Register Abbreviation Access Resource name Initial value 3900 Reload 0 XXXXXXXXs 3901 Reload H PRLHO 16 bit Programmable Pulse 39025 Reload L PRLL1 Generator 0 1 00000606 3903 Reload H PRLH1 XXXXXXXXs 3904 Reload L 2 3905 Reload PRLH2 16 bit Programmable Pulse 3906 Reload PRLL3 Generator 2 3 20000606 39074 Reload H PRLH3 3908 Reload 4 3909 Reload 4 16 bit Programmable Pulse 3909 Reload PRLL5 Generator 4 5 390Bu Reload H PRLH5 XXXXXXXXs 39008 Reload 6 3900 Reload H PRLH6 16 bit Programmable Pulse 390 Reload L PRLL7 Generator 6 7 00000606 390 Reload H PRLH7 XXXXXXXXs 39104 to 3917u 3918 Input Capture Register 0 IPCPO 3919 Input Capture Register 0 IPCPO 3918 Input Capture Register 1 IPCP1 391Bu Input
33. gister 1 reload register 1 4 XXXXXXXXs Output compare control status register 0 0650 Output Compare 0000 0 Os Output compare control status register 1 OCS1 0 1 000008 Output compare control status register 2 OCS2 Output Compare 000 0 08 Output compare control status register 3 OCS3 2 3 000008 5Cu to 6Bu Prohibited 608 Timer Counter Data register TCDT 0000000 Os 6Du Timer Counter Data register TCDT Timer 0000000 0 6 Timer Counter Control status register TCCS 0000000 Os ROM mirror function selection register ROMM ROM Mirror 70H to 7FH Reserved 80 to 8 Reserved 909 to 9Du Prohibited Program address detection C panies Match 9 control status register PACSR R W 2 0000000 Os unction Delayed interrupt release register DRR R W Delayed Interrupt 08 Os AOH Low power mode control register LPMCR R W yos boda 0001100 0s Atu Clock selection register CKSCR R W pol 111111005 Continued Continued Address 2 to 4 Register Abbreviation Prohibited MB90435 Series Resource name Initial value Abu Automatic ready function select register ARSR External address output control register HACR 7 8 Bus control signal selection register Watchdog Timer control register ECSR WDTC External Memory Access Watchdog Timer 0011 008 000000008 XXXXX 1 1 18 9 Time Base Timer Control register TBTC Time Base Timer 1
34. h mode Hardware standby input time tusr Under normal operation tcp represents one cycle time of the machine clock Oscillation time of oscillator is time that amplitude reached the 90 In the crystal oscillator the oscillation time is between several ms to tens of ms In FAR ceramic oscillator the oscillation time is between handreds of us to several ms In the external clock the oscillation time is 0 ns Any reset can not fully initialize the Flash Memory if it is performing the automatic algorithm 36 MB90435 Series Under normal operation Pseudo timer mode Sub clock mode Sub sleep mode Watch mode WA TRSTL tHSTL RST HST 0 2 Vcc In stop mode tRSTL RST N ARM Vcc 0 2 90 of amplitude Internal operation clock m 4 tcP gt Oscillation time of Oscillati m oscillator scillation setting time Internal reset Instruction execution 37 MB90435 Series 4 Power On Reset MB90F438L S 437 S 438L S Vcc 3 5 V to 5 5 V Vss AVss 0 0 V Ta 40 C to 105 C MB90F439 S 439 S V540G Vcc 5 0 V 10 Vss AVss 0 0 V Ta 40 C to 105 C EA e Parameter Symbol name Condition min max Power off time Due to repetitive operation Vcc must be kept lower than 0 2 before power on Notes The above values
35. he AVcc power supply is applied before the Vcc voltage Latch up may increase the power supply current drastically causing thermal damage to the device For the same reason care must also be taken in not allowing the analog power supply voltage AVcc AVRH to exceed the digital power supply voltage 2 Handling unused pins Leaving unused input pins open may result in misbehavior or latch up and possible permanent damage of the device Therefor they must be pulled up or pulled down through resistors In this case those resistors should be more than 2 kQ Unused bi directional pins should be set to the output state and can be left open or the input state with the above described connection 3 Using external clock To use external clock drive pin only and leave 241 pin unconnected Below is a diagram of how to use external clock MB90435 Series 7 ld x1 4 Use of the sub clock Use one clock system parts when the sub clock is not used In that case pull down the and leave the pin X1A open When using two clock system parts a 32 kHz oscillator has to be connected to the XOA and X1A pins 5 Power supply pins Vcc Vss In products with multiple Vcc or Vss pins the pins of a same potential are internally connected in the device to avoid abnormal operations including latch up However you must connect the pins to an external power and a ground line to lower the electro magnetic emissi
36. he Extended I O serial interface This SOT2 function is enabled when the Extended I O serial interface enables the serial data output General I O port This function is enabled when the Extended dii I O serial interface disables the clock output Serial clock pulse I O pin for the Extended I O serial interface SCK2 This function is enabled when the Extended I O serial interface enables the Serial clock output P50 General I O port This function is always enabled Serial data input pin for the Extended I O serial interface Set SIN2 the corresponding Port Direction Register to input if this function is used P51 to P54 General I O port This function is always enabled 27 to 30 29 to 32 External interrupt request input pins for INT4 to INT7 Set the INT4 to INT7 corresponding Port Direction Register to input if this function is used P55 General I O port This function is always enabled Trigger input pin for the A D converter Set the corresponding 918 Port Direction Register input if this function is used General I O port This function is enabled when the analog P60 to P63 28 input enable register specifies a port 36 to 39 38 to 41 Analog input pins for the 8 10 bit A D converter This function is ANE ANA enabled when the analog input enable register specifies A D General I O port The function is enabled when the analog P64 to P67 i input enable
37. he interrupt flags assigned to the same interrupt number If one interrupt flag starts the EIPOS and the meantime another interrupt flag is set by a hardware event the later event is lost because the flag is cleared by the EI2OS clear signal caused by the first event So it is recommended not to use the EI OS for this interrupt number If EOS is enabled EOS is initiated when one of the two interrupt signals in the same interrupt control register ICR is asserted This means that different interrupt sources share the same EI OS Descriptor which should be unique for each interrupt source For this reason when one interrupt source uses the EIOS the other interrupt should be disabled 28 MB90435 Series ELECTRICAL CHARACTERISTICS 1 Absolute Maximum Ratings Parameter Power supply voltage Symbol Vss 6 0 Vss AVss 0 0 V Vss 0 Vss 0 Vcc AVcc AVcc gt AVRH AVRL AVRH AVRL Input voltage Vss 6 0 Output voltage Maximum clamp current IcLAMP Vss 0 Total maximum clamp current XI L level max output current L level avg output current lo loLav L level max overall output current Llo L level avg overall output current H level max output current loH H level avg output current level max overall output current H level avg overall output curre
38. ications Rich data types bit byte word long word Rich addressing mode 23 types Enhanced signed multiplication division instruction and RETI instruction functions Enhanced precision calculation realized by the 32 bit accumulator Instruction set designed for high level language C language and multi task operations Adoption of system stack pointer Enhanced pointer indirect instructions Barrel shift instructions Program patch function for two address pointers Enhanced execution speed 4 byte Instruction queue Enhanced interrupt function 8 levels 34 factors Automatic data transmission function independent of CPU operation Extended intelligent I O service function EOS Embedded ROM size and types Mask ROM 64 Kbytes 128 Kbytes 256 Kbytes Flash ROM 128 Kbytes 256 Kbytes Embedded RAM size 2 Kbytes 4 Kbytes 6 Kbytes 8 Kbytes evaluation chip Flash ROM Supports automatic programming Embedded Algorithm TM Write Erase Erase Suspend Resume commands A flag indicating completion of the algorithm Hard wired reset vector available in order to point to a fixed boot sector in Flash Memory Erase can be performed on each block Block protection with external programming voltage Low power consumption stand by mode Sleep mode mode in which CPU operating clock is stopped Stop mode mode in which oscillation is stopped CPU intermittent operation mode Clock mode Hardware stand by mode Process 0 5 um CMOS te
39. ies Circuit type Diagram UE P ch Analog input R HYS input Wy x Remarks CMOS level output CMOS Hysteresis input Analog input R HYS input bii R Pull down LE een TTL level input jn HYS input Hysteresis input Pull down Resistor 50 kQ approx except FLASH devices CMOS level output CMOS Hysteresis input TTL level input FLASH devices in FLASH writer mode only Continued Continued MB90435 Series Circuit type Diagram Pull up ON OFF select signal Vcc P ch P ch Ha HYS input j x Remarks CMOS level output CMOS Hysteresis input Programmable pull up resistor 50 kQ approx D wn select signal P ch a P ch Pull up ON OFF 777 HYS input TTL level input CMOS level output CMOS Hysteresis input TTL level input FLASH devices in FLASH writer mode only Programmable pull up resistor 50 kQ approx 15 MB90435 Series HANDLING DEVICES 1 Preventing latch up CMOS IC chips may suffer latch up under the following conditions A voltage higher than Vcc or lower than Vss is applied to an input or output pin A voltage higher than the rated voltage is applied between Vcc and Vss T
40. ils of A pat s 4020 4008 TES INDEX 0 10 0 10 d ES di nu 004 004 s i Stand off i an 1111101110011111 0203 08 025 010 00 060015 cm T 008 602 0 081009 s Dimensions in mm inches 57 MB90435 Series 1 FUJITSU LIMITED All Rights Reserved The contents of this document are subject to change without notice Customers are advised to consult with FUJITSU sales representatives before ordering The information and circuit diagrams in this document are presented as examples of semiconductor device applications and are not intended to be incorporated in devices for actual use Also FUJITSU is unable to assume responsibility for infringement of any patent rights or other rights of third parties arising from the use of this information or circuit diagrams The products described in this document are designed developed and manufactured as contemplated for general use including without limitation ordinary industrial use general office use personal use and household use but are not designed developed and manufactured as contemplated 1 for use accompanying fatal risks or dangers that unless extremely high safety is secured could have a serious effect to the public and could lead directly to death personal injury severe physical damage or other loss 1 nuclear reacti
41. in name Function LQFP type General I O port with programmable pull up This function is P33 enabled in the single chip mode external bus 8 bit mode or when WRH pin output is disabled 11 13 Write strobe output pin for the 8 higher bits of the data bus WRH This function is enabled when the external bus is enabled when the external bus 16 bit mode is selected and when the WRH output pin is enabled General port with programmable pull up This function is P34 enabled in the single chip mode or when the hold function is 12 14 disabled HRQ Hold request input pin This function is enabled when both the external bus and the hold functions are enabled General I O port with programmable pull up This function is P35 enabled in the single chip mode or when the hold function is 13 15 disabled HAK Hold acknowledge output pin This function is enabled when both the external bus and the hold functions are enabled General port with programmable pull up This function is P36 enabled in the single chip mode or when the external ready 14 16 function is disabled RDY Ready input pin This function is enabled when both the external bus and the external ready functions are enabled General I O port with programmable pull up This function is P37 enabled in the single chip mode or when the CLK output is 15 17 H disabled CLK CLK output pin This function is enabled when both the external bus and CLK outputs are enabled Ge
42. neral I O port This function is enabled when UARTO P40 16 18 G disables the serial data output SOTO Serial data output pin for UARTO This function is enabled when UARTO enables the serial data output General I O port This function is enabled when UARTO P41 17 45 disables serial clock output SCK0 Serial clock I O pin for 10 This function is enabled when UARTO enables the serial clock output P42 General port This function is always enabled 18 20 G Serial data input pin for UARTO Set the corresponding Port SINO ips Direction Register to input if this function is used P43 General I O port This function is always enabled 19 21 5 Serial data input pin for UART1 Set the corresponding Port SIN1 ip Pm Direction Register to input if this function is used Continued MB90435 Series Circuit type name MEE General I O port This function is enabled when UART1 Det disables the clock output Serial clock pulse I O pin for UART1 This function is pM enabled when UART1 enables the serial clock output General I O port This function is enabled when UART1 pas disables the serial data output Serial data output pin for UART1 This function is enabled when Sen 00371 enables the serial data output General port This function is enabled when the Extended 555 serial interface disables the serial data output Serial data output pin for t
43. nt You Y loHav Power consumption Operating temperature Hl Flash device Mask ROM Storage temperature 1 AVcc AVRH AVRL should not exceed Vcc Also AVRH AVRL should not exceed AVcc and AVRL does not 2 3 4 D 6 exceed AVRH Vi and Vo should not exceed Vcc 0 3 V Vi should not exceed the specified ratings However if the maximum current to from an input is limited by some means with external components the Icuame rating supercedes the Vi rating The maximum output current is a peak value for a corresponding pin Average output current is an average current value observed for a 100 ms period for a corresponding pin Total average current is an average current value observed for a 100 ms period for all corresponding pins e Applicable to pins POO to P07 P10 to P17 P20 to P27 P30 to P37 P40 to P47 P50 to P57 P60 to P67 P70 to P77 P80 to P87 P90 to P97 PAO Use within recommended operating conditions Use at DC voltage current The B signal should always be applied with a limiting resistance placed between the B signal and the microcontroller The value of the limiting resistance should be set so that when the B signal is applied the input current to the microcontroller pin does not exceed rated values either instantaneously or for prolonged periods Note that when the microcontroller drive current is low such as in the power saving mo
44. ogramming MB90F439 S prior erasure Excludes system level overhead Erase Program cycle MB90435 Series EXAMPLE CHARACTERISTICS H level output voltage L level output voltage VoL IOL Vcc 4 5 V 25 C Vcc 4 5 V Ta 25 C 5 0 9 Wr 4 5 08 i 0 7 3 5 0 6 _ 3 gt gt 0 5 25 3 gt gt 4 2 0 3 1 5 1 0 2 0 5 0 1 0 0 0 2 4 6 8 10 0 4 6 8 10 loH MA mA level input voltage level input voltage Hysterisis inpiut Vin 6 Ta 25 C Vin VJ 51 52 MB90435 Series Power supply current 90439 Icc Vcc Ta 25 C m Ta 25 C 40 16 MHz fcp 16 MHz 35 10 30 rom 12 MHz 8 25 lt lt E 20 6 8 15 4 10 2 5 0 0 5 6 7 2 3 4 5 6 7 Vcc V Vcc V Icts Vcc Ta 25 C Ta 25 C 600 100 90 500 80 70 400 60 lt lt 300 50 9 40 200 30 20 100 10 0 0 4 5 6 7 2 4 5 6 7 Vcc V Vcc V 890435 Series Ta 25 C Vcc V lccr Vc
45. on control in nuclear facility aircraft flight control air traffic control mass transport control medical life support system missile launch control in weapon system or 2 for use requiring extremely high reliability i e submersible repeater and artificial satellite Please note that Fujitsu will not be liable against you and or any third party for any claims or damages arising in connection with above mentioned uses of the products Any semiconductor devices have an inherent chance of failure You must protect against injury damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy fire protection and prevention of over current levels and other abnormal operating conditions If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Law of Japan the prior authorization by Japanese government will be required for export of those products from Japan 0207 FUJITSU LIMITED Printed in Japan
46. on level to prevent abnormal operation of strobe signals caused by the rise in the ground level and to conform to the total current rating Make sure to connect Vcc and Vss pins via the lowest impedance to power lines is recommended to provide a bypass capacitor of around 0 1 uF between Vcc and Vss pins near the device MB90435 16 MB90435 Series 6 Pull up down resistors MB90435 Series does not support internal pull up down resistors except PortO Port3 pull up resistors Use external components where needed 7 Crystal Oscillator Circuit Noises around or X1 pins may be possible causes of abnormal operations Make sure to provide bypass capacitors via the shortest distances from X1 pins crystal oscillator or ceramic resonator and ground lines and make sure to the utmost effort that lines of oscillation circuits do not cross the lines of other circuits It is highly recommended to provide a printed circuit board artwork surrounding and X1 pins with a ground area for stabilizing the operation 8 Turning on Sequence of Power Supply to A D Converter and Analog Inputs Make sure to turn on the A D converter power supply AVcc AVRH AVRL and analog inputs ANO to AN7 after turning on the digital power supply Vcc Turn off the digital power after turning off the A D converter supply and analog inputs In this case make sure that the voltage does not e
47. onverter This power supply must be turned on or off while a voltage higher than or equal to AVcc is applied to Vcc Power supply Power supply pin for the A D Converter Power supply External reference voltage input pin for the A D Converter This power supply must be turned on or off while a voltage higher than or equal to AVRH is applied to AVcc Power supply External reference voltage input pin for the A D Converter Input pins for specifying the operating mode The pins must be directly connected to Vcc or Vss Input pin for specifying the operating mode The pin must be directly connected to Vcc or Vss Power supply stabilization capacitor pin It should be connect ed externally to an 0 1 uF ceramic capacitor Input pin for power supply 5 0 V 1 FPT 100P M06 2 FPT 100P M05 12 Input pin for power supply 0 0 I O CIRCUIT MB90435 Series Circuit type Diagram Hard soft standby control Clock input Remarks High speed oscillation feedback resistor 1 MO approx Low speed oscillation feedback resistor 10 MQ approx wee Pull up R HYS input AW Hysteresis input Pull up resistor 50 kQ approx HYS input Hysteresis input ES input CMOS level output CMOS Hysteresis input Continued 13 14 MB90435 Ser
48. op Minimum instruction exection time 62 5 ns 4 MHz osc PLL x 4 Mask ROM MB90437L S 64 Kbytes MB90438L S 128 Kbytes MB90439 S 256 Kbytes Flash memory MB90F438L S 128 Kbytes MB90F439 S 256 Kbytes External MB90437L S 2 Kbytes MB90438L S 4 Kbytes MB90439 S 6 Kbytes MB90F438L S 4 Kbytes MB90F439 S 6 Kbytes 8 Kbytes Clocks MB90437L 438L 439 Two clocks system MB90437LS 438LS 439S One clock system MB90F438L F439 Two clocks system MB90F438LS F439S One clock system Two clocks system Operating voltage range 5 Temperature range 40 C to 105 C Package QFP100 LQFP100 PGA 256 Emulator specify power supply Nan None UARTO Full duplex double buffer Support asynchronous synchronous with start stop bit transfer Baud rate 4808 5208 9615 10417 19230 38460 62500 500000 bps asynchronous 500 K 1 M 2 Mbps synchronous at System clock 16 MHz UART1 SCI Full duplex double buffer Asynchronous start stop synchronized and CLK synchronous communication Baud rate 1202 2404 4808 9615 19230 31250 38460 62500 bps asynchronous 62 5 K 125 K 250 K 500 K 1 M 2 Mbps synchronous at 6 8 10 12 16 MHz Serial Transfer can be started from MSB or LSB Supports internal clock synchronized transfer and external clock synchronized transfer Supports positive edge and nagative edge clock synchronization Baud rate
49. ral I O ports This function is enabled when 8 16 bit PPG disables the waveform output Output pins for 8 16 bit PPGs This function is enabled when 8 16 bit PPG enables the waveform output P84 P85 OUTO OUT1 General I O ports This function is enabled when the OCU disables the waveform output Waveform output pins for output compares 0 and OCU1 This function is enabled when the OCU enables the waveform output P86 10 1 General I O port This function is always enabled Input pin for the 16 bit reload timers 1 Set the corresponding Port Direction Register to input if this function is used General I O port This function is enabled when the 16 bit Poe reload timers 0 disables the output B B n Output pin for the 16 bit reload timers 1 This function is enabled when the 16 bit reload timers 1 enables the output P90 to P93 General I O port This function is always enabled 67 to 70 69 to 72 External interrupt request input pins for INTO to INT3 Set the INTO to INT3 corresponding Port Direction Register to input if this function is used 71 73 P94 D General port Continued 11 MB90435 Series Continued Circuit name type Function General I O port General I O port General I O port 0 0 0 General I O port Power supply Power supply pin for the A D C
50. ration mode control register PPGC4 R W 16 bit Programmable 0 000 18 41 PPG5 operation mode control register PPGC5 R W Pulse 0 0000015 421 4 5 clock selection register PPG45 RAW s 43H Prohibited 440 PPG6 operation mode control register PPGC6 R W 16 bit Programmable 0 000 18 45H PPG7 operation mode control register PPGC7 R W Pulse 0 1 46 PPG6 7 clock selection register PPG67 RW 7 Continued 21 22 MB90435 Series Address Register Abbreviation Access Resource name Initial value 47n to 4 Prohibited 408 Input capture control status register 1 ICSO1 Input Capture 0 1 10000000 Os 408 Input capture control status register 3 ICS23 Input Capture 2 3 0 0 0 0 0 0 Os 4 Input capture control status register 4 5 ICS45 Input Capture 4 5 0 0 0 00 0 0 05 4 3 Input capture control status register 7 ICS67 Input Capture 6 7 0 0 000 0 0 05 Timer control status register 0 TMCSRO 0000000 0s Timer control status register 0 TMCSRO ___0000s8 TMRO 16 bit Reload Timer register 0 reload register 0 TMRLRO Timer 0 Timer register O reload 00000006 Timer control status register 1 TMCSR1 0000000 0s Timer control status register 1 TMCSR1 __ _000 0s 1 16 bit Reload Timer register 1 reload register 1 TMRLR1 Timer 1 Timer re
51. s XXXXXXXXs 08 Port 8 data register PDR8 XXXXXXXXs 09u Port 9 data register PDR9 XXXXXXXXs OAH Port A data register PDRA 084 to 03 Reserved 108 Port 0 direction register Port 1 direction register DDRO 0000000 Os 0000000 Os Port 2 direction register 0000000 Os Port 3 direction register 0000000 Os Port 4 direction register 0000000 Os Port 5 direction register 0000000 Os Port 6 direction register Port 7 direction register DDR7 Port 7 0000000 Os 0000000 Os Port 8 direction register DDR8 Port 8 0000000 Os Port 9 direction register DDR9 Port 9 0000000 Os Port A direction register DDRA Port A Analog Input Enable register ADER Port 6 A D 111111118 Port 0 pull up control register Port 1 pull up control register PUCRO PUCR1 Port 0 0000000 0 0000000 0 Port 2 pull up control register PUCR2 0000000 Os Port 3 pull up control register PUCR3 0000000 Os Serial Mode Control Register 0 UMCO Serial Status Register 0 USRO Serial input data register 0 Serial output data register 0 UIDRO UODRO Rate and data register 0 URDO 0000010 0 0001000 0 XXXXXXXXs 0000000 Continued MB90435 Series
52. xceed AVRH or AVcc turning on off the analog and digital power supplies simulta neously is acceptable 9 Connection of Unused Pins of A D Converter Connect unused pins of A D converter to AVcc Vcc AVss AVRH Vss 10 N C Pin The N C internally connected pin must be opened for use 11 Notes on Energization To prevent the internal regulator circuit from malfunctioning set the voltage rise time during energization at 50 us or more 0 2 V to 2 7 V 12 Initialization In the device there are internal registers which are initialized only by a power on reset To initialize these registers please turn on the power again 13 Directions of DIV A Ri and DIVW A RWi instructions In the Signed multiplication and division instructions DIV A Ri and DIVW A the value of the corresponding bank register DTB ADB USB SSB is set in 00x If the values ofthe corresponding bank registers DTB ADB USB SSB are set to other than 00x the remainder by the execution result of the instruction is not stored in the register of the instruction operand 14 Using REALOS The use of EI OS is not possible with the REALOS real time operating system 15 Caution on Operations during PLL Clock Mode If the PLL clock mode is selected the microcontroller attempt to be working with the self oscillating circuit even when there is no external oscillator or external clock input is stopped Performance of

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