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FUJITSU SEMICONDUCTOR MB90420G/5G (A) Series handbook

1. OONOON 0O 0NOOCO 00 0NOOCO 0 00 00NO 0000 00NO 00 Note For an explanation of a to d referto Table 4 Number of Execution Cycles for Each Type of Addressing and Table 5 Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles 84 MB90420G 5G A Series Table 10 Increment and Decrement Instructions Byte Word Long Word 12 Instructions e Operation oe byte ear ear 1 byte eam eam 1 byte ear lt ear byte eam lt eam 1 word ear ear 1 word eam eam 1 word ear lt ear 1 word eam lt eam 1 long ear ear 1 long eam eam 1 long ear lt ear 1 long eam eam 1 O OP ON O N Note For an explanation of a to d referto Table 4 Number of Execution Cycles for Each Type of Addressing and Table 5 Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles Table 11 Compare Instructions Byte Word Long Word 11 Instructions Mnemonic Operation CMP A byte AH AL CMP A ear byte ear CMP A eam byte A eam
2. cn SEGO 1 SEG1 2 SEG2 3 SEG3 4 SEG4 5 SEG5 6 SEG6 7 SEG7 8 Vss 9 SEG8 10 SEG9 11 SEG10 12 SEG11 13 P36 SEG12 14 P37 SEG13 15 P40 SEG14 16 P41 SEG15 17 P42 SEG16 18 P43 SEG17 19 P44 SEG18 20 Vcc 21 P45 SEG19 22 P46 SEG20 23 P47 SEG21 24 C 25 IS IS G Q OQ Q GO O O G G UU lt lt lt lt b gt P gt Ub gt UUVUVU lt UUUTU Qduoc cmNo z cocooooooooo BH SESE mm 4 2222 2222 G G o KOSS N gt 100 05 92 V5S Sd 08 0X 6 SSA 82 VOX ZL YIX 18 oan 1NI Sd LXu LLNI LSd LXL ZLNI ZSd RST P56 SGO FRCK P55 RX0 54 0 DVss P87 PWM2M3 P86 PWM2P3 P85 PWM1M3 P84 PWM1P3 DVcc P83 PWM2M2 P82 PWM2P2 P81 PWM1M2 P80 PWM1P2 DVss P77 PWM2M1 P76 PWM2P1 P75 PWM1M1 P74 PWM1P1 DVcc P73 PWM2MO P72 PWM2P0 P71 PWM1MO P70 PWM1PO DVss MB90420G 5G A Series PIN DESCRIPTIONS Les Symbol E Description 80 82 X0 High speed oscillator input pin 81 83 X1 High speed oscillator output pin 78 80 X0A Eu 2 pin If no oscillator is connected apply 77 79 X1A oscillator output If no oscillator is connected leave 75
3. 2 A EE E wwe MOVW dir A MOVW addr16 A MOVW SP A MOVW RWi A MOVW ear A MOVW eam A MOVW io A MOVW RWi disp8 A MOVW RLi disp8 A MOVW RWi ear MOVW RWi eam MOVW ear RWi MOVW eam RWi MOVW RWi imm16 MOVW io imm16 MOVW ear imm16 MOVW eam imm16 MOVW AL AH MOVW A T word word word O O O ILI A N NS PO e e Co 9 word RWi lt ear word RWi eam R Nee word ear RWi word eam RWi word RWi imm16 word io imm16 word ear imm16 word eam imm16 lt O G O 0 0 0 ononnPn on OO ch OO ch ch bM zk bM bM sz O Och sch OO OCH 9 I word A AH XCHW A ear XCHW A eam XCHW RWi ear XCHW RWi eam ear eam MOVL A imm32 Ne i lt gt eam o MOVL ear MOVL eam A Note For an explanation of a to d refer to Table 4 Number of Execution Cycles for Each Type of Addressing and Table 5 Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles long ear A long eam
4. 1995 FUJITSU LIMITED F100007S 2C 3 Mouting height Details of A part 0 15 006 m 0 15 006 Details of B part 12 00 15 00 472 591 SE REF NOM INDEX ivi Rem no OTTER 5 0 50 0197 0 18003 gt 0 127 1002 07 2819 0 08003 5 N SG 2110 10 004 Nm STAND OFF r 10 50 0 20 020 008 NI Dimensions in mm inches MB90420G 5G A Series n FUJITSU LIMITED For further information please contact Japan FUJITSU LIMITED Corporate Global Business Support Division Electronic Devices Shinjuku Dai Ichi Seimei Bldg 7 1 Nishishinjuku 2 chome Shinjuku ku Tokyo 163 0721 Japan Tel 81 3 5322 3347 Fax 81 3 5322 3386 htip edevice fujitsu com North and South America FUJITSU MICROELECTRONICS INC 3545 North First Street San Jose CA 95134 1804 U S A Tel 1 408 922 9000 Fax 1 408 922 9179 Customer Response Center Mon Fri Z am 5 pm PST Tel 1 800 866 8608 Fax 1 408 922 9179 http www fujitsumicro com Europe FUJITSU MICROELECTRONICS EUROPE GmbH Am Siebenstein 6 10 D 63303 Dreieich Buchschlag Germany Tel 49 6103 690 0 Fax 49 6103 690 122 http www fujitsu fme com Asia Pacific FUJITSU MICROELECTRONICS ASIA PTE LTD 05 08 151 Lorong Chuan
5. 4 RX FFFFDO CANO TX NS OCH 0000 0 CAN1 RX CAN1 TX NS 4 0000B1u Input capture 0 DTP external interrupt ch 0 detected 0000 2 Reload timer 0 8 interrupt ch 1 detected 0000 3 Input capture 1 DTP external interrupt ch 2 detected FFFFACH 0000B4 Input capture 2 8 DTP external interrupt ch 3 detected 4 0000 5 Input capture 3 DTP external interrupt 4 5 detected FFFF9CH 0000B6k PPG timer 0 DTP external interrupt ch 6 7 detected 9 94 0000 7 PPG timer 1 9 Reload timer 1 FFFF8C 0000B8u PPG timer 2 88 Real time clock timer 84 0000 9 Free run timer over flow A D converter conversion end FFFF80 FFFF7C 0000 Free run timer clear FFFF78 Sound generator 74 0000BBu Time base timer FFFF701 Clock timer sub clock FFFF6CH 0000 UART 1 8 UART 1 TX FFFF644 0000BDu UART 0 RX UART 0 TX 00
6. 67 MB90420G 5G A Series _______________ _ __ RN AC ratings are defined for the following measurement reference voltage values Input signal waveform Output signal waveform Hysteresis input pin Output pin 68 MB90420G 5G A Series 2 Reset input Vcc 5 0 V 10 Vss AVss 0 0 V TA 40 C to 105 C NE Parameter Symbol ue Reset input time Reset input time time ren lt tor E tRSTL 0 6 Vcc 0 6 Vcc 3 Power on reset power on conditions Vss 0 0 V Ta 40 C to 105 C Parameter Conditions Power supply rise time Remarks Power supply start voltage Power supply attained voltage Power supply cutoff time For repeat operation Vcc Extreme variations in voltage supply may activate a power on reset As the illustration below shows when varying supply voltage during operation the use of a smooth voltage rise with suppressed fluctuation is recommended Also in this situation the PLL clock on the device should not be used however it is permissible to use the PLL clock during a voltage drop of 1mV s or less Vcc 5 0V 4 5 420G 425G series N 3 0 V 420GA 425GA series A rise slope of 50 mV or less is recommended RAM data hold Vss 69 MB90420G 5G A Series 70 4 UARTO UART1 timing Vcc 5 0 V 10 Vss AVss 0 0 V Ta
7. 17 MB90420G 5G A Series M DO A Y I O MAP Other than CAN Interface Address Register name Read write Peripheral function Initial value Port 0 data register R W XXXXXXXX Port 1 data register R W XXXXXX abled Port 3 data register R W Port 4 data register R W XXXXXXXX Port 5 data register R W XXXXXXXX Port 6 data register R W XXXXXXXX Port 7 data register R W XXXXXXXX Port 8 data register R W XXXXXXXX Port 9 data register R W Disabled Port 0 direction register DDR0 R W 00000000 Port 1 direction register DDR1 R W 000000 Disabled Port 3 direction register DDR3 R W Port 4 direction register DDR4 R W 00000000 Port 5 direction register DDR5 HAN 00000000 Port 6 direction register DDR6 R W Port 6 00000000 Port 7 direction register DDR7 R W Port 7 00000000 Port 8 direction register DDR8 R W Port 8 00000000 Port 9 direction register DDR9 R W Port 9 Analog input enable ADER R W Port 6 A D 11111111 Disabled A D control status register lower 00000000 A D control status register higher 00000000 A D data register lower XXXXXXXX A D data register higher 00101 XXX XXXXXXXX XXXXXXXX 00000000 00000000 Timer control status register lower 00000000 Compare clear register Timer data register 16 bit free run timer
8. FUJITSU SEMICONDUCTOR DATA SHEET DS07 13711 1E 16 Bit Original Microcontroller CMOS F MC 16LX MB90420G 5G A Series MB90423G 423GA F423G F423GA V420G MB90427G 427GA 428G 428GA F428G F428GA DESCRIPTIONS The FUJITSU MB90420G 5G A Series is a 16 bit general purpose high capacity microcontroller designed for vehicle meter control applications etc The instruction set retains the same AT architecture as the FUJITSU original FAMC 8L and F2MC 16L series with further refinements including high level language instructions expanded addressing mode enhanced signed multipler divider computation and bit processing In addition A 32 bit accumulator is built in to enable long word processing FEATURES 16 bit input capture 4 channels Detects rising falling or both edges 16 bit capture register x 4 Pin input edge detection latches the 16 bit free run timer counter value and generates an interrupt request 16 bit reload timer 2 channels 16 bit reload timer operation select toggle output or one shot output Event count function selection provided Continued PACKAGES Plastic QFP 100 pin Plastic LOFP 100 pin 100 06 100 05 MB90420G 5G A Series Clock timer main clock Operates directly from oscillator clock Compensates for oscillator deviation Read write enabled second minute hour register Signal interrupt 16 bit
9. 2 At For 16 MHz 1 66 x tor 4 125 us 3 Equivalent to conversion time per channel at Fce 16 MHz and selection of tsur 32 x tc and 1 32 x 4 Defined as supply current when Vcc AVcc 5 0 V with A D converter not operating and CPU in stop mode Notes The relative error increases as AVRH is reduced eThe output impedance rs on the external analog input circuit should be used as follows External circuit output impedance rs 5 max elf the output impedance on the external circuit is too great the analog voltage sampling time may be insufficient elf DC inhibitor capacitance is placed between the external circuit and input pin then a capacitance value several thousand times the value of the chip internal sampling capacitance CSH should be selected in order to suppress the effects of voltage division with CSH 73 MB90420G 5G A Series 74 Analog input equivalent circuit Microcontroller internal circuits Comparator Input pin AN7 S H circuit External circuits Analog channel selector lt Recommended and guide values for element parameters gt rs 5 or less approx 3 approx 25 pF Note These element parameters are intended as guidelines for reference and are not warranted for actual use MB90420G 5G A Series 2 Definition of terms Resoluti
10. Data register 7 8 bytes XXXXXXXX to XXXXXXXX 003ACOu to 7 003 to 003BC7u Data register 8 8 bytes XXXXXXXX to 003AC8u to 003 8 to 003BCFH Data register 9 8 bytes XXXXXXXX to XXXXXXXX Continued 29 MB90420G 5G A Series iS II I i iii iii Continued Address CAN0 CAN1 003BD0H to to Data register 10 8 bytes XXXXXXXX to XXXXXXXX 003AD7 003 07 003AD8 003 8 to to Data register 11 8 bytes XXXXXXXX to XXXXXXXX 003BDF 003BEOk to to Data register 12 8 bytes XXXXXXXX to XXXXXXXX 00 7 7 003 8 to to Data register 13 8 bytes XXXXXXXX to XXXXXXXX 003BEFk 003 to to Data register 14 8 bytes XXXXXXXX to XXXXXXXX 003AF74 003BF7H 8 003BF8H to to Data register 15 8 bytes XXXXXXXX to XXXXXXXX OO3AFFu 003 Register name Initial value 30 MB90420G 5G A Series INTERRUPT SOURCES INTERRUPT VECTORS AND INTERRUPT CONTROL REGISTERS Interrupt source Reset EPOS compatible Interrupt vector Interrupt control register Number 08 08H Address FFFFDCu ICR Address INT9 instruction 09 09H FFFFD8 Exception processing OAH
11. Hysteresis input CMOS high current output Hysteresis input LCDC output LCDC output MB90420G 5G A Series HANDLING DEVICES When handling semiconductor devices care must be taken with regard to the following ten matters Strictly observe maximum rated voltages prevent latchup Stable supply voltage Power on procedures Treatment of unused input pins Treatment of A D converter power supply pins Use of external clock signals Power supply pins Proper sequence of A D converter power supply analog input Handling the power supply for high current output buffer pins DVcc DVss Pull up pull down resistance Precautions when not using a sub clock signal Precautions for Handling Semiconductor Devices Strictly observe maximum rated voltages prevent latchup When CMOS integrated circuit devices are subjected to applied voltages higher than Vcc at input and output pins other than medium and high withstand voltage pins or to voltages lower than Vss or when voltages in excess of rated levels are applied between Vcc and Vss a phenomenon known as latchup can occur In a latchup condition supply current can increase dramatically and may destroy semiconductor elements In using semi conductor devices always take sufficient care to avoid exceeding maximum ratings Also care must be taken when power to analog systems is switched on or off to ensure that the analog power supply AVcc
12. Precautions for when not using a sub clock signal If the XOA and X1A pins are not connected to an oscillator apply pull down treatment to the XOA pin and leave the X1A pin open MB90420G 5G A Series 16 BLOCK DIAGRAM XO X1 X1A Clock control CPU RST circuit F2MC 16LX core o m P57 SGA x P56 SGO FRCK P55 RX0 P54 TX0 P53 INT3 P52 INT2 TX1 P51 INT1 RX1 P50 INTO ADTG POO SINO INT4 PO1 SOTO INT5 P02 SCKO INT6 POS SIN1 INT7 P04 SOT1 P05 SCK1 TRG PO6 PPGO TOT 1 PO7 PPG1 TIN1 P10 PPG2 P11 TOTO WOT P12 TINO INS P13 IN2 VV Reload timer m P14 IN1 0 1 P15 INO Real time Clock timer Free run timer 1 Evaluation device MB90V420G i No built in ROM i Built in RAM is 6 KB I Low voltage detector reset Interrupt controller Stepping motor Controller 0 1 2 3 A D converter 8 ch LCD controller driver P87 PWM2M3 P86 PWM2P3 P85 PWM1M3 P84 PWM1P3 P83 PWM2M2 P82 PWM2P2 P81 PWM1M2 P80 PWM1P2 P77 PWM2M1 P76 PWM2P1 P75 PWM1M1 P74 PWM1P1 P73 PWM2M0 P72 PWM2P0 P71 PWM1M0 P70 PWM1P0 P67 P60 AN7 ANO AVcc AVss AVRH P91 P90 SEG23 SEG22 P47 P40 SEG21 SEG14 P37 P36 SEG13 SEG12 SEG11 SEGO COMS3 COMO VO MB90420G 5G A Series MEMORY MAP Single chip mode with ROM mirror function 000000H Peripheral area RAM area 000
13. 4 when the result is zero 8 when an overflow occurs and 16 normally 6 a when the result is zero 9 a when an overflow occurs and 19 a normally 4 when the result is zero 7 when an overflow occurs and 22 normally 6 a when the result is zero 8 a when an overflow occurs and 26 a normally b when the result is zero or when an overflow occurs and 2 x b normally c when the result is zero or when an overflow occurs and 2 x c normally 8 when byte AH is zero and 7 when byte AH is not zero 4 when byte ear is zero and 8 when byte ear is not zero 5 a when byte eam is zero and 9 a when byte eam is not 0 8 when word AH is zero and 11 when word AH is not zero 4 when word ear is zero and 12 when word ear is not zero 5 a when word eam is zero and 13 a when word eam is not zero Note For an explanation of a to d referto Table 4 Number of Execution Cycles for Each Type of Addressing 86 and Table 5 Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles MB90420G 5G A Series Table 13 Signed Multiplication and Division Instructions Byte Word Long Word 11 Instructions Mnemonic Operation word AH byte AL Quotient byte AL Remainder byte word A byte ear Quotient byte A Remainder byte ear word A byte eam Quotient byte A Remainde
14. A 83 MB90420G 5G A Series III i iii iii Table 9 Addition and Subtraction Instructions Byte Word Long Word 42 Instructions Mnemonic Operation ADD A imm8 A imm8 ADD A dir A dir ADD A ear ADD A eam ADD ear A ADD eam A ADDC A ADDC A ear ADDC ADDDC SUB A imm8 SUB A dir SUB A ear SUB A eam SUB ear A SUB eam A SUBC A SUBC A ear SUBC SUBDC ADDW ADDW ADDW ADDW imm16 ADDW ear ADDW eam A ADDCW A ear ADDCW A eam SUBW A SUBW ear SUBW eam SUBW A imm16 SUBW ear SUBW SUBCW ear SUBCW A eam ADDL ear ADDL eam ADDL imm32 SUBL ear SUBL A eam 508 fimm32 oom t T TT A eam ear A oo WP ear C eam C H AL C decimal 1113 gt touno TETT NNNNNNNNN I NNNN Ton SO OO 00 0000 I T N r ear A eam A ear C m X amp AES wn 2 OOGO OOND WP ear A eam A p 2
15. 16 MHz 30 ii FFc 11 MHz 20 9 lt Fo 8 MHz 15 Fe 5MHz _ 1 NS Fc 4MHz 99 i 2 MHz 3 5 4 5 5 5 6 5 Vcc V Voc 25 C 3 5 3 2 Fc 16 MHZ 25 lt _______________ _ 1 _______________ 8 MHz 8 15 8 5 MHZ 1 4 MHz I 05 Fc 2 MHz 0 1 1 3 5 4 5 5 5 6 5 Vcc V Ta 25 C 900 Fe 16 MHz 800 11 MHz 700 Fc 8 MHz Fc 5 MHz x C 2 5 409 2 MHz 300 200 100 0 3 5 45 5 5 6 5 Vcc V Continued MB90420G 5G A Series Continued 5 uA IccT uA Fc 8 kHz 25 C 125 40 3 5 4 5 5 5 6 5 Voc V Fc 8 kHz Ta 125 C 25 Ta 40 4 5 5 5 6 5 Vcc V Fc 8 kHz Ta 125 C 25 40 3 5 4 5 5 5 6 5 Vcc V 77 MB90420G 5G A Series 78 INSTRUCTIONS 351 INSTRUCTIONS Table1 Explanation of Items in Tables of Instructions Meaning Mnemonic Upper case letters and symbols Represented as they appear in assembler Lo
16. Continued Parameter Large current output drive capacity variation 1 Pin name PWM1Pn PWM1Mn PWM2Pn PWM2Mn 0103 Conditions Vcc 4 5 V lou 30 0 mA maximum variation Remarks Large current output drive capacity variation 2 PWM1Pn PWM1Mn PWM2Pn PWM2Mn n 0to3 Vcc 4 5 V lou 30 0 mA maximum variation LCD divider resistance VO to V1 V1 to V2 V2 to V3 COMO to COMS output imped ance COMn n 2 0 to 3 SEGO to SEG3 output imped ance SEGn n 00 to 23 LCD leakage current VO to COMm m 00 to 23 SEGn n 00 to 23 4 Defined as maximum variation in with all channel 0 PWM1P0 PWM1M0 PWM2P0 PWM2M0 simul taneously ON Similarly for other channels 65 MB90420G 5G A Series i II ii i 4 AC Characteristics 1 Clock timing Voc 5 0 V 10 Vss DVss AVss 0 0 V 40 C to 105 Parameter Base oscillation clock frequency Fc Pinname X0 X1 Remarks Fic X0A X1A Base oscillation clock cycle time tcv XO X1 tLeyL XOA X1A Input clock pulse width Pw Pwet Use duty ratio of 40 to 60 as a guideline Input clock rise fall time tcr tcf With external clock signal Input operating clock frequency Using main clock
17. Main oscillator clock Sub second register CI Second Minute Hour EN counter counter counter CO INTEO INTO 41 MB90420G 5G A Series 6 PPG Timer The PPG timer consists of a prescaler one 16 bit down counter 16 bit data register with buffer for period setting and 16 bit compare register with buffer for duty setting plus pin control circuits The timer can output pulses synchronized with an externally input soft trigger The period and duty of the output pulse can be adjusted by rewriting the values in the two 16 bit registers 1 PWM function Programmable to output a pulse synchronized with a trigger Can also be used as a D A converter with an external circuit 2 One shot function Detects the edge of a trigger input and outputs a single pulse 3 Pin control e Set to 1 at a duty match priority Reset to 0 at a counter borrow event Has a fixed output mode to output a simple all L or H signal Polarity can be specified 4 16 bit down counter Select from four types of counter operation clocks Four internal clocks 6 6 4 6 16 6 64 Machine clock cycles The counter value can be initialized to at a reset or counter borrow event 5 Interrupt requests Timer startup Counter borrow event period match Duty match event Counter borrow event period match or duty match event
18. New Tech Park Singapore 556741 Tel 65 281 0770 Fax 65 281 0220 http www 1 50 Korea FUJITSU MICROELECTRONICS KOREA LTD 1702 KOSMO TOWER 1002 Daechi Dong Kangnam Gu Seoul 135 280 Korea Tel 82 2 3484 7100 Fax 82 2 3484 7111 F0012 FUJITSU LIMITED Printed in Japan All Rights Reserved The contents of this document are subject to change without notice Customers are advised to consult with FUJITSU sales representatives before ordering The information and circuit diagrams in this document are presented as examples of semiconductor device applications and are not intended to be incorporated in devices for actual use Also FUJITSU is unable to assume responsibility for infringement of any patent rights or other rights of third parties arising from the use of this information or circuit diagrams The contents of this document may not be reproduced or copied without the permission of FUJITSU LIMITED FUJITSU semiconductor devices are intended for use in standard applications computers office automation and other office equipments industrial communications and measurement equipments personal or household devices etc CAUTION Customers considering the use of our products in special applications where failure or abnormal operation may directly affect human lives or cause physical injury or property damage or where extremely high levels of reliability are demanded such as
19. yz S88 3858 Bdo339 590995 VUVSASMSARZAAZ OOGSEROG SUSAJ29zg999 OOS 9929239362z2z22 lt 22 2222002 12354990 ooczmo dm coo0 ooce o oo o o o cO cO cO cO 00 COM2 1 80 COM3 2 79 SEGO 3 78 P57 SGA SEG1 4 77 RST SEG2 5 76 P56 SGO FRCK SEG3 6 75 P55 RX0 SEG4 7 74 P54 TX0 SEG5 8 73 DVss SEG6 9 72 P87 PWM2M3 SEG7 10 71 P86 PWM2P3 Vss 11 70 P85 PWM1M3 SEG8 12 69 P84 PWM1P3 SEG9 13 68 DVcc SEG10 14 67 P83 PWM2M2 SEG11 15 66 P82 PWM2P2 P36 SEG12 16 65 P81 PWM1M2 P37 SEG13 17 64 P80 PWM1P2 P40 SEG14 18 63 DVss P41 SEG15 19 62 P77 PWM2M1 P42 SEG16 20 61 P76 PWM2P1 P43 SEG17 21 60 P75 PWM1M1 P44 SEG18 22 59 P74 PWM1P1 Vcc 23 58 DVcc P45 SEG19 24 57 P73 PWM2M0 P46 SEG20 25 56 P72 PWM2P0 P47 SEG21 26 55 P71 PWM1MO C 27 54 P70 PWM1PO P90 SEG22 28 53 DVss P91 SEG23 29 52 P53 INT3 vo 30 51 MD2 Q2 CO P I I I I IRI p LO GO O Q 4010 OO cO O SESESS 4 2222 222244 o gt 5 O FPT 100P M06 Continued MB90420G 5G A Series Continued TOP VIEW 9 UT va Sog 5525 5352506005 959902200290 dagdo9Eez z 709797 AA 888922e 233d382222 22225025 544445 0 co cO cO cO cO Qo
20. 00004 003 00 00007Fu 003D00H 003C01H 003D01H Receiving interrupt enable register Control status register 00000000 00 000 00000000 003 02 003D02u 003 03 003003 Last event indicator register 000 0000 003 04 003004 003 05 003 06 003D05H 003006 003C07 003D07 RX TX error counter Bit timing register 00000000 1111111 00000000 11111111 003C08 003008 003 09 003009 IDE register XXXXXXXX XXXXXXXX 003 003D0Au 003 00300 Transmission RTR register 00000000 00000000 003C0Cu 00300 003C0DH 008DODu Remote frame receiving wait register XXXXXXXX XXXXXXXX 003 00300 003C0FH 003DOFu Transmission interrupt enable register 00000000 00000000 Continued 25 MB90420G 5G A Series 26 Address CANO 003 10 1 003D10u 003 11 003011 003C12u 003D12u 003 13 003 14 003D13u 003014 003 15 003015 003 16 003 16 003 17 003D17u Register name Acceptance mask select register Acceptance mask register 0 Initial value XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXX XXXXXXXX 003 18 003018 003C19u 003C1Au 003D19
21. CAN Clock division control register 1 CDCR1 R W Prescaler 0 0000 40 4 Area reserved f Timer control status register 0 lower TMCSROL Timer control status register O high er TMCSROH TMR0 TMRLRO Timer register 0 Reload register 0 or CAN interface 0 16 bit reload timer 0 00000000 00000 XXXXXXXX XXXXXXXX Timer control status register 1 lower TMCSR1L Timer control status register 1 high er TMCSR1H TMR1 TMRLR1 Timer register 1 Reload register 1 16 bit reload timer 1 00000000 00000 XXXXXXXX XXXXXXXX Clock timer control register lower WTCRL Clock timer control register higher WTCRH Real time clock timer 000 000 00000000 Continued 19 MB90420G 5G A Series 20 Address Register name Symbol Read write Peripheral function Sound control register lower Sound control register higher Frequency data register Sound generator Amplitude data register Decrement grade register Tone count register Initial value 00000000 XXXXXXXX 00000000 XXXXXXXX XXXXXXXX Input capture register 0 Input capture 0 1 Input capture register 1 XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX Input capture register 2 Input capture 2 3 Input capture register 3 XXXXXXXX XXXXXXXX XXXXXXXX XXXXXX
22. FPT 100P M05 Remarks MB90420G 5G A Series PACKAGE DIMENSIONS Plastic QFP 100 pin FPT 100P M06 23 90 0 40 941 016 2 3 35 132 pe height 20 00 0 20 787 008 0 05 002 MIN STAND OFF 1 9 i 14 00 0 20 17 90 0 40 12 p E 16 30 0 40 551 008 705 016 642 016 ED ECH ECH enne o Le or or oT mm or oT EE or or EE 0 65 0256 TYP 0 30 0 10 fo 15 0 05 006 002 012 004 210 13 005 Details of A part 1 J minn b Geen 918 RI B part l AL 7 0 10 004 0 30 012 SE I 18 85 742 _ 0 18 007 0 80 0 20 80 0 22 30 0 40 878 016 0 53 021 MAX 031 008 _ 4 4 1994 FUJITSU LIMITED F100008 3C 2 Dimensions in mm inches Continued 97 MB90420G 5G A Series 98 Continued Plastic LQFP 100 FPT 100P M05 16 00 0 20 630 008 SQ gt 14 00 0 10 551 004 SQ 1 50 2010 Ber 059 08
23. PWM1P0 PWM1M0 PWM2PO PWM2MO Circuit type Description General purpose input output ports Stepping motor controller ch 0 output pins 57 to 60 62 to 65 59 to 62 64 to 67 P74 to P77 PWM1P1 PWM1M1 PWM2P1 PWM2M1 P80 to P83 PWM1P2 PWM1M2 PWM2P2 PWM2M2 General purpose input output ports Stepping motor controller ch 1 output pins General purpose input output ports Stepping motor controller ch 2 output pins 67 to 70 69 to 72 P84 to P87 PWM1P3 PWM1M3 PWM2P3 PWM2M3 General purpose input output ports Stepping motor controller ch 3 output pins P54 General purpose input output port CAN interface 0 TX output pin General purpose output port CAN interface 0 RX input pin General purpose input output port Sound generator SGO output pin Free run timer clock input pin 76 78 SGA General purpose input output port Sound generator SGA output pin 28 to 31 30 to 33 VO to V3 LCD controller driver reference power supply pins 56 66 58 68 DVcc High current output buffer with dedicated power supply input pins pin numbers 54 57 59 62 64 67 69 72 51 61 71 53 63 73 DVss High current output buffer with dedicated power supply GND pins pin numbers 54 57 59 62 64 67 69 72 32 34 AVcc A D converter dedicated power supply input pin 35 37 AVss A D con
24. XXXX XXXX Continued MB90420G 5G A Series Address CANO 003A76u CAN1 003B76u 003A77u 003B77u Register name DLC register 11 DLCR11 Initial value XXXX XXXX 003 78 003 78 003A79u 7 003B79u 003B7Au 003A7Bu 003B7Bu DLC register 12 DLC register 13 DLCR12 DLCR13 XXXX XXXX XXXX XXXX 003A7CH 003 7 7 003B7Du DLC register 14 DLCR14 XXXX XXXX 7 003 7 003A7Fu 003 80 to 003A87u 003B7F 003 80 to 003B87H DLC register 15 Data register 0 8 bytes DLCR15 XXXX XXXXXXXX to XXXXXXXX 003A88u to 003A8Fu 003 88 to 003B8FH Data register 1 8 bytes XXXXXXXX to XXXXXXXX 003A90u to 003A87H 003 90 to 003B97H Data register 2 8 bytes XXXXXXXX to XXXXXXXX 003A98u to 003A9Fu 003 98 to 003B9FH Data register 3 8 bytes XXXXXXXX to XXXXXXXX OO3AA0H to 00 7 003BA0H to 003BA7H Data register 4 8 bytes XXXXXXXX to XXXXXXXX 003AA8u to 00 00 10 00 7 003BA8H to 003BAFu 003BBOk to 003BB7 Data register 5 8 bytes Data register 6 8 bytes XXXXXXXX to XXXXXXXX XXXXXXXX to XXXXXXXX 00 8 to 003 8 to
25. port Peripheral function General purpose port Peripheral function PWM2M1 PWM2P1 PWM1P1 General purpose I O port Peripheral function General purpose I O port Peripheral function 33 MB90420G 5G A Series Continued bit6 bit5 SEG18 SEG16 P70 PWM2MO PWM1PO PWM2M3 PWM1P3 PWM2M2 PWM2P2 Note Port 6 also functions as an analog input pin When using this port as a general purpose port always write 0 to the corresponding analog input enable register ADER bit The ADER bit is initialized to 1 at reset 34 MB90420G 5G A Series 2 Block Diagrams Internal data bus Ports 0 1 3 4 5 7 8 9 Peripheral function output Peripheral function input PDR Port data register PDR read EE Peripheral function output enabled Direction latch DDR write DDR read Standby control SPL 1 or LCD output enabled Port 6 Analog input Internal data bus DDR write DDR read Standby control SPL 1 35 MB90420G 5G A Series 2 Watchdog Timer Time Base Timer Clock Timer The watchdog timer timer base timer and clock ti
26. 40 C to 105 Parameter Pin name Conditions Serial clock cycle time SCKO SCK1 SCKO SCK1 SOTO SOT1 Valid SIN to SCK rise SCKO SCK1 SCK rise to valid SIN hold time SINO SIN1 SCK fall to SOT delay time Internal shift clock mode output pin C 80 pF 1eTTL Serial clock H pulse width SCKO SCK1 Serial clock L pulse width SCK0 SCK1 SOTO SOT1 Valid SIN to SCK rise SCKO SCK1 SCK rise to valid SIN hold time SINO SIN1 SCK fall to SOT delay time Notes AC ratings are for CLK synchronous mode e CL is load capacitance connected to pin during testing Internal shift clock mode External shift clock mode output pin 80 pF 1eTTL SCK SOT 0 8 Vcc M 0 6 Vcc External shift clock mode 0 8 Vcc 0 6 Vcc 0 8 Vcc SCK La tsLsH 0 6 Vcc 0 6 Vcc SOT 0 8 Vcc SIN 0 6 Vcc 0 8 Vcc 0 6 Vcc MB90420G 5G A Series Vcc 5 0 V 10 Vss AVss 0 0 V TA 40 C to 105 C 5 Timer input timing Parameter Pin name Conditions i Remarks TINO TIN1 Input pulse width INO IN1 IN2 IN3 Timer input timing 0 8 Vcc 0 8 Vcc 0 6 Vcc TINO TIN1 0 6 Vcc INO Vcc 5 0 V 10 Vss AVss 0 0 V TA 40 C to 105 C 6 Trigger input ti
27. 45 MB90420G 5G A Series 2 Block diagram Request level setting register ELVR Internal data bus P50 INTO P51 INT1 P52 INT2 P53 INT3 Interrupt request number 16 10H 18 12H 20 148 22 16H 24 18H 26 1AH MB90420G 5G A Series 9 8 10 bit A D Converter The 8 10 bit A D converter has functions for using RC sequential comparator conversion format to convert analog input voltage into 10 bit or 8 bit digital values The input signal is selected from 8 channel analog input pins and the conversion start can be selected from three types by software 16 bit reload timer 1 or a trigger input from an external signal pin 1 8 10 bit A D converter functions The A D converter takes analog voltage signals input voltage input at analog input pins and converts these to digital values providing the following features Minimum conversion time is 6 13 us at machine clock frequency of 16 MHz including sampling time Minimum sampling time is 3 75 us at machine clock 16 MHz The conversion method is an RC sequential conversion in comparison with a sample hold circuit Either 10 bit or 8 bit resolution can be selected The analog input pin can select from 8 channels by a program setting At completion of A D conversion an interrupt request can be g
28. P80 P87 lotav2 70 77 P80 87 Other than 70 77 P80 P87 70 77 P80 87 L level average total output current Zlo au Other than P70 P77 P80 P87 Zlo aus P70 77 P80 87 H level maximum output current H level average output current 2 Other than P70 P77 P80 P87 2 2 louavi 3 P70 77 P80 87 Other than P70 P77 P80 P87 loHav2 3 P70 77 P80 87 H level maximum total output current Other than P70 P77 P80 P87 70 77 P80 87 H level average total output current Power consumption Other than P70 P77 P80 P87 24 P70 77 P80 87 Operating temperature Storage temperature 1 Care must be taken to ensure that AVcc and DVcc do not exceed Vcc at power on etc 2 Maximum output current is defined as the peak value of the current of any of the corresponding pins 3 Average output current is defined as the value of the average current flowing over 100 ms at any one of the corresponding pins The average value can be calculated from the formula of operating current times operating factor 4 Average total output current is defined as the value of the average current flowing over 100 ms at all of the corresponding pins The average value can be calculated from the formula of operating current times
29. Prefix code for accessing AD space Prefix code for accessing DT space Prefix code for accessing PC space Prefix code for accessing SP space Prefix code for no flag change Prefix code for common register bank 1 state 2 states 2 7 3 x pop count 2 x last register number to be popped 7 when rlst 0 no transfer register 3 29 3 x push count 3 x last register number to be pushed 8 when rlst 0 no transfer register 93 MB90420G 5G A Series 94 Table 22 Bit Manipulation Instructions 21 Instructions Mnemonic RG Operation MOVB A dir bp byte A lt dir bp b MOVB A addr16 bp byte A addr16 bp b MOVB A io bp byte io bp b bit dir bp b A bit b bit io bp b MOVB dir bp A MOVB addr16 bp A MOVB io bp A SETB dir bp SETB addri6 bp SETB io bp bit dir bp b 1 bit addr16 bp b lt 1 bit io bp b lt 1 CLRB dir bp CLRB addr16 bp CLRB io bp bit dir bp b 0 bit addr16 bp b 0 bit io bp b lt 0 BBC dir bp rel BBC addr16 bp rel BBC io bp rel Branch when dir bp b e Branch when addr16 b Branch when io bp b E BBS dir bp rel BBS addr16 bp rel BBS io bp rel Branch when dir bp b Branch when addr16 bp b 1 Branch when io bp b 1 OQ OQ Co SBBS addr16 bp rel Branch when add
30. to stack Note For an explanation of a to 9 referto Table 4 Number of Execution Cycles for Each Type of Addressing and Table 5 Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles 91 MB90420G 5G A Series Table 20 Branch 2 Instructions 19 Instructions Mnemonic RG B Operation LHJAH 1 S T N Z v RMW imm8 rel 3 0 0 Branch when byte z imm8 CWBNE A imm16 rel 41 10 0 Branch when word imm16 CBNE ear imm8 rel 4 2 11 0 Branch when byte zimm8 CBNE eam imm rel 4 3 0 b Branch when byte eam imm8 1 1 CWBNE ear imm16 rel 5 4 1 0 Branch when word ea zimm16 CWBNE eam ftimm16 rel 54 3 O Branch when word eam imm16 DBNZ ear rel 3 5 2 0 Branch when byte ear ear 1 and ear z 0 DBNZ eam rel 3 2 2x b Branch when byte eam eam 1 and eam 0 DWBNZ ear rel 3 2 0 Branchwhen word ear 1 and ear 0 DWBNZ eam 3 6 2 2x Branch when word eam eam 1 and eam 0 INT vct8 2 20 0
31. 6 Multiple channels can be set to start up at an external trigger or to restart during operation MB90420G 5G A Series 7 Block diagram Prescaler CK PSCT Load 16 bit down counter Start Machine clock Borrow PDUT PPG mask Enable Trigger input PO5 TRG Edge detection Soft trigger Inversion bit Interrupt selection Interrupt 43 MB90420G 5G A Series 7 Delayed Interrupt Generator Module The delayed interrupt generator module is a module that generates interrupts for task switching This module makes it possible to use software to generate cancel interrupt requests to the FAMC 16LX CPU Block diagram F2MC 16LX bus Delayed interrupt source generate delete decoder Source latch 44 MB90420G 5G A Series 8 DTP External Interrupt Circuit The DTP Data transfer peripheral external interrupt circuit is located between an externally connected periph eral device and the F2MC 16LX CPU and sends interrupt requests or data transfer requests generated from the peripheral device to the CPU thereby generating external interrupt requests or starting the expanded intelligent I O services EI OS 1 DTP external interrupt function The DTP external interrupt function uses a signal input from the DTP external interrupt pin as a startup source And it is accepted by the CPU by the same procedure as a
32. 7 Segment 16 x 8 bits driver LCDC control register H LCRH Controller Driver 54 MB90420G 5G A Series 13 Low voltage Program Looping Detection Reset Circuit The Low voltage detection reset circuit is a function that monitors power supply voltage in order to detect when a voltage drops below a given voltage level When a low voltage condition is detected an internal reset signal is generated The Program Looping detection reset circuit is a count clock with a 20 bit counter that generates an internal reset signal if not cleared within a given time after startup 1 Low voltage detection reset circuit Detection voltage 4 0V 0 3V When a low voltage condition is detected the low voltage detection flag LVRC LVRF is set to 1 and an internal reset signal is output Because the low voltage detection circuit continues to operate even in stop mode detection of a low voltage condition generates an internal reset and releases stop mode During an internal RAM write cycle an internal reset is generated after the completion of writing During the output of this internal reset the reset output from the low voltage detection circuit is suppressed 2 Program Looping detection reset circuit The Program Looping detection reset circuit is a counter that prevents program looping The counter starts automatically after a power on reset and must be continually cleared within a given time If
33. 8 byte imm8 AL A ear lt ear A eam lt eam A imm16 lt imm16 A ear A eam A imm32 lt lt ear lt eam lt imm32 0 1 0 0 0 1 0 0 2 0 0 Note For an explanation of a to d referto Table 4 Number of Execution Cycles for Each Type of Addressing and Table 5 Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles 85 MB90420G 5G A Series DVU A word AH byte AL DIVU A ear word Ay byte ear DIVU A eam word A byte eam DIVUW A ear long A word ear DIVUW eam long A word eam MULU A byte AH byte AL word A MULU A ear byte A byte ear word MULU byte A byte eam word A MULUW A word AH word AL long A MULUW A ear word ear long A MULUW A eam word A word eam long A Table 12 Multiplication and Division Instructions Byte Word Long Word 11 Instructions Mnemonic Operation Quotient byte AL Remainder byte AH Quotient byte A Remainder byte ear Quotient byte Remainder byte eam Quotient word A Remainder word ear Quotient word A Remainder word eam 8 when the result is zero 7 when an overflow occurs and 15 normally
34. Disabled Flash control register FMCS R W Flash interface 000X0XX0 Disabled Interrupt control register 00 000001 Interrupt control register 01 000001 Interrupt control register 02 000001 Interrupt control register 03 000001 Interrupt control register 04 000001 Interrupt control register 05 000001 Interrupt control register 06 000001 Interrupt control register 07 000001 Interrupt controller Interrupt control register 08 000001 Interrupt control register 09 000001 Interrupt control register 10 000001 Interrupt control register 11 000001 Interrupt control register 12 ICR12 R W 000001 Interrupt control register 13 ICR13 R W 000001 Interrupt control register 14 ICR14 R W 000001 Interrupt control register 15 ICR15 R W 000001 Disabled 21 MB90420G 5G A Series 22 Address Register name ROM correction address 0 Read write R W ROM correction address 1 R W ROM correction address 2 R W ROM correction address 3 R W 1FF5H ROM correction address 4 ROM correction address 5 HAN HAN Address match detection function Peripheral function Initial value XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 39004 to 391Fu Disabled 3920H 3921u PP
35. Instructions Mnemonic Operation RORC A byte A Right rotation with carry ROLC A byte A Left rotation with carry RORC ear byte ear Right rotation with carry RORC eam byte eam lt Right rotation with carry ROLC ear byte ear Left rotation with carry ROLC eam byte eam Left rotation with carry ASR A RO 1 byte A lt Arithmetic right barrel shift A RO LSR A RO 1 byte A lt Logical right barrel shift A RO LSL A RO 1 byte A lt Logical left barrel shift A RO ASRWA word A lt Arithmetic right shift A 1 bit LSRW A SHRW A word A lt Logical right shift A 1 bit LSLW A SHLW A word A lt Logical left shift A 1 bit ASRW A RO 1 word A Arithmetic right barrel shift A LSRW A RO 1 RO LSLW A RO 1 word A lt Logical right barrel shift A RO word Logical left barrel shift RO ASRL A RO long A Arithmetic right shift A RO LSRL A RO long A Logical right barrel shift A RO LSLL A RO long A Logical left barrel shift A RO 1 6 when RO is 0 5 RO in all other cases 2 6 when RO is 0 6 RO in all other cases Note For an explanation of a to d referto Table 4 Number of Execution Cycles for Each Type of Addressing and Table 5 Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles 90 MB90420G 5G A Series
36. PLL clock Using sub clock Input operating clock cycle time Frequency variability ratio locked Using main clock PLL clock Using sub clock The frequency variability ratio is the maximum proportion of variation from the set central frequency using a multiplier in locked operation 11 100 Central fo frequency X1 clock timing X0A X1A clock timing 66 MB90420G 5G A Series Range of warranted operation Relation between internal operating clock frequency and supply voltage MB90F428GA MB90428GA MB90427GA range of warranted operation 5 5 3 7 3 3 mm E L Warranted operation Supply voltage Vcc V IMB90F428G MB90428G MB90427G _ range of warranted operation 2 8 12 16 Internal clock frequency fcP MHz The MB90F428GA MB90F423GA MB90428GA MB90427GA and MB90423GA enter reset mode at supply voltage below 4 V 0 3 V Relation between oscillator clock frequency and internal operating clock frequency Internal operating clock frequency PLL clock Main clock Multiplier Multiplier Multiplier Multiplier x1 x2 x3 x4 SEET M 8MHz 12MHz 16MHz frequency Sample oscillator circuit Oscillator element Frequency C1 C2 manufacturer XO X1 SR i Ci C2 777 777
37. PPG 3 channels Output pins 3 external trigger input pin 1 Output clock frequencies fce fce 2 24 26 Delay interrupt Generates interrupt for task switching Interruptions to CPU can be generated deleted by software setting External interrupts 8 channels 8 channel independent operation Interrupt source setting available L edge to L edge L level H level A D converter 10 bit or 8 bit resolution x 8 channels input multiplexed Conversion time 6 13 us or less at fce 16 MHz External trigger startup available P50 INTO ADTG Internal timer startup available 16 bit reload timer 1 UART 2 channels Full duplex double buffer type Supports asynchronous synchronous transfer with start stop bits Internal timer can be selected as clock 16 bit reload timer 0 Asynchronous 4808 bps 5208 bps 9615 bps 10417 bps 19230 bps 38460 bps 62500 bps 500000 bps Synchronous 500 Kbps 1Mbps 2Mbps at fce 16 MHz CAN interface Conforms to CAN specifications version 2 0 Part A and B Automatic resend in case of error Automatic transfer in response to remote frame 16 prioritized message buffers for data and messages for data and ID Multiple message support Receiving filter has flexible configuration All bit compare all bit mask two partial bit masks Supports up to 1 Mbps CAN WAKEUP function connects RX internally to INTO LCD controller
38. Table 19 Branch 1 Instructions 31 Instructions Mnemonic Operation Branch when Z 2 o0000000000000000 D rel rel rel rel Branch when Branch when Branch when Branch when Branch when Branch when 2 2 SS Branch when V xor Branch when C or Branch when C or Branch unconditionally O O O O O O O O O O O word PC A word PC addr16 word PC ear word PC eam word PC ear PCB ear 2 word PC eam PCB eam 2 word PC ad24 0 to 15 PCB ad24 16 to 23 word PC lt ear word PC eam word PC addr16 Vector call instruction word PC lt ear 0 to 15 addr16 ear eam JMPP Gear 3 JMPP eam JMPP addr24 OO O00 OONO 00 CALL ear 4 CALL eam 3 CALL addr16 5 CALLV vct4 5 ear 6 lt eam 0 to 15 eam 16 to 23 lt addr0 to 15 CALLP eam A CALLP addr24 77 1 4 when branching 3 when not branching 2 b 3x c 8 Read word branch address 4 W Save word to stack R read word branch address 5 Save word to stack 6 W Save long word to W stack R read long word R branch address 7 Save long word
39. Timer control status register higher 0 00000 Continued 18 MB90420G 5G A Series Address Register name PPGO control status register lower PCNTLO Read write PPGO control status register higher PCNTHO Peripheral function Initial value 16 bit PPGO 00000000 0000000 PPG1 control status register lower PCNTL1 PPG1 control status register higher PCNTH1 16 bit PPG1 00000000 0000000 PCNTL2 PCNTH2 PPG2 control status register lower PPG2 control status register higher 16 bit PPG2 00000000 0000000 External interrupt enable ENIR External interrupt request EIRR External interrupt level lower ELVRL External interrupt level higher ELVRH External interrupt 00000000 XXXXXXXX 00000000 00000000 SMRO SCRO Serial mode register 0 Serial control register 0 SIDRO SODRO Input data register 0 Output data register 0 Serial status register 0 SSRO 00000 00 00000100 XXXXXXXX 00001000 Serial mode register 1 Serial control register 1 SCR1 SIDR1 SODR1 SSR1 Input data register 1 Output data register 1 Serial status register 1 R W 00000 00 00000100 XXXXXXXX 00001000 3CH Disabled Clock division control register 0 CDCR0 R W Prescaler 0 0000 CAN wake up control register CWUCR R W
40. aerospace systems atomic energy controls sea floor repeaters vehicle operating controls medical devices for life support etc are requested to consult with FUJITSU sales representatives before such use The company will not be responsible for damages arising from such use without prior approval Any semiconductor devices have inherently a certain rate of failure You must protect against injury damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy fire protection and prevention of over current levels and other abnormal operating conditions If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Control Law of Japan the prior authorization by Japanese government should be required for export of those products from Japan
41. an underflow event Thus underflow occurs when counting from the value Reload register setting 1 A selection of two counter operating modes are available In reload mode the counter is reset to the count value and continues counting after an underflow and in one shot mode the count stops after an underflow The counter can generate an interrupt when an underflow occurs and is compatible with the expanded intelligent I O services EIOS 1 16 bit Reload timer operating modes Clock mode Counter mode 16 bit reload timer operation Reload mode Soft trigger operation Internal clock mode External trigger operation One shot mode External gate input operation Event count mode Reload mode external clock mode One shot mode Soft trigger operation 2 Internal clock mode One of three input clocks is selected as the count clock and can be used in one of the following operations Soft trigger operation When 1 is written to the TRG bit in the timer control status register TMCSRO0 1 the count operation starts Trigger input at the TRG bit is normally valid with an external trigger input as well as an external gate input External trigger operation Count operation starts when a selected edge rising falling both edges is input at the TINO 1 pin External gate input operation Counting continues as long as the selected signal level L or is input at the TINO 1 pin 3 Event count mo
42. and lt eam and A imm8 or ear or eam lt ear or A am lt eam or A xor imm8 xor ear xor eam lt ear xor A lt eam xor A byte A not A byte ear not ear byte eam not eam ORW ORW ORW ORW ORW ORW XORW XORW XORW XORW XORW XORW NOTW NOTW NOTW A A imm16 A ear A eam ear A eam A A A imm16 A ear A eam ear A eam A A A imm16 A ear A eam ear A eam A omo OOh OO A ONO word A AH and A word A A and imm16 word A lt A and ear word A A and eam word ear lt ear and eam eam and A H or A or imm16 or ear or eam ear or A lt eam or A H xor A xor imm16 A xor ear xor eam lt ear xor A lt eam xor A word A lt not A word ear not ear word eam lt not eam DUD 3 253 22 22 lt Note For an explanation of a to d referto Table 4 Number of Execution Cycles for Each Type of Addressing and Table 5 Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles MB90420G 5G A Series Table15 Logical 2 Instructions Long Word 6 Instructions Mnemonic Operation long A A and ear long A A and eam long A A
43. compatible with expanded intelligent I O services Master slave type communication function multi processor mode 1 master to n slave communication enabled only master side supported Note The UART in clock synchronous transfer does not add start bits or stop bits but transfers data only Operating mode Normal mode Data length No par ity Parity 7 bit or 8 bit Synchronization Asynchronous Multi processor mode 8 1 Asynchronous Stop bit length 1 bit or 2 bit Normal mode Setting not available 8 Synchronous 1 indicates address data selection bit A D for communication control 2 In receiving only one stop bit is detected None 49 MB90420G 5G A Series 2 Block diagram Control bus Receiving lt interrupt signals Exclusive baud 39 27H rate generator lt 37 25 gt Sending clock Sending gt interrupt signals 16 bit Clock 40 28 gt o i reload timer selector Receiving Receiving Sending lt 38 26H gt 505 control control circuit circuit Pins eee 02 5 0 Start bit i lt 05 5 1 gt detection circuit Receiving bit i counter Receiving parity Sending parity Pin counter i counter Vern ere PO1 SOTO lt P04 SOT1 gt R
44. driver 1 channel Segment driver and command driver with direct LCD panel display drive capability Low voltage Program Looping detect reset 2 Automatic reset when low voltage is detected Program Looping detection function Stepping motor controller 4 channels High current output for all channels x 4 Synchronized 8 10 bit PWM for all channels x 2 Sound generator 8 bit PWM signal mixed with tone frequency from 8 bit reload counter PWM frequencies 62 5 kHz 31 2 kHz 15 6 kHz 7 8 kHz at fce 16MHz Tone frequencies 1 2 PWM frequency divided by reload frequency 1 Continued MB90420G 5G A Series Continued Input output ports Push pull output and Schmitt trigger input Programmable in bit units for input output or peripheral signals Flash memory Supports automatic programming Embeded Algorithm write erase erase pause erase resume instructions Flag indicates algorithm completion Minato Electronics flash writer Boot block configuration Erasable by blocks Block protection by external programming voltage 1 MB90420G A series has 2 channels built in MB90425G A series has 1 channel built in 2 Built in to MB90420GA 5GA series only Not built in to MB90420G 5G series Embeded Algorithm is a registered trademark of Advanced Micro Devices Inc MB90420G 5G A Series PRODUCT LINEUP e MB90420G A Series Parameter Configuration MB90V420G MB90F423G MB90F423GA MB904
45. normal hardware interrupt and can generate an external interrupt or start the expanded intelligent I O service 2 5 When the interrupt is accepted by the CPU if the corresponding expanded intelligent I O service EIPOS is prohibited the interrupt operates as an external interrupt function and branches to an interrupt routine If the EPOS is permitted the interrupt functions as a DTP function using El OS for automatic data transfer then branching to an interrupt routine after the completion of the specified number of data transfers External interrupt DTP function Input pins 8 pins P50 INTO to P53 INT3 POO INT4 to P03 INT7 Request level setting register ELVR sets the detection level or selected edge for each pin Interrupt sources level L level rising edge falling edge input Interrupt numbers 16 104 18 12h 20 144 22 16 24 184 26 1 H level L level input Interrupt control DTP interrupt enable register ENIR permits prohibits interrupt request output Interrupt flags DTP interrupt enable register EIRR stores interrupt sources Process selection When EI OS prohibited ICR ISE 0 When is enabled ICR ISE 1 EI OS performs automatic data transfer then after a specified number of cycles branches to an interrupt routine Branch to external interrupt processing Processing routine ICR Interrupt control register
46. operating factor WARNING Semiconductor devices can be permanently damaged by application of stress voltage current temperature etc in excess of absolute maximum ratings Do not exceed these ratings 61 MB90420G 5G A Series i ii ii 2 Recommended Operating Conditions Vss DVss AVss 0 0 V Parameter Remarks In normal operation MB90F428G F428GA MB90428G 428GA MB90427G 427GA Holding stop operation status MB90F428G MB90428G MB90427G Holding stop operation status MB90F428GA MB90428GA MB90427GA Use a ceramic capacitor or other capacitor of Smoothing equivalent frequency characteristics A capacitor smoothing capacitor on the Vcc pin should have a capacitance greater than Cs Power supply voltage Operating temperature For smoothing capacitor Cs connections see the illustration below C pin connection Vss DVss 55 Cs WARNING The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device All of the device s electrical characteristics are warranted when the device is operated within these ranges Always use semiconductor devices within their recommended operating condition ranges Operation outside these ranges may adversely affect reliability and could result in device failure No warranty is made with respect to uses operating conditions or combinations not repr
47. the given time interval elapses and the counter has not been cleared a cause such as infinite program looping is assumed and an internal reset signal is generated The internal reset generated form the Program Looping detection circuit has a width of 5 machine cycles Interval duration Number of oscillation clock cycles This value assumes an oscillation clock speed of 4 MHz During recovery from standby mode the detection period is the maximum interval plus 20 us This circuit does not operate in modes where CPU operation is stopped The Program Looping detection reset circuit counter is cleared under any of the following conditions 1 Writing 0 to the LVRC register CL bit 2 Internal reset 3 Main oscillation clock stop 4 Transition to sleep mode 5 Transition to time base timer mode or clock mode 6 Start of hold MB90420G 5G A Series 3 Block diagram Voltage comparator circuit Constant voltage Program Looping detection circuit Source Internal reset OF Noise canceller RESVO RESVO RESV1 RESV1 LVRF RESVO CPUF Low voltage detection reset control register LVRC Internal data bus 56 MB90420G 5G A Series 14 Stepping Motor Controller The stepping motor controller is composed of two PWM pulse generators four motor drivers and selector logic circuits The four motor drivers have a high output drive capacity and can be di
48. 00BEu Flash memory status 8 Delayed interrupt generator module x x O jP gt gt gt bib pb b gt gt bib bib XI x xix 54 0000 1 Priority 2 High MB90420G 5G A Series Compatible with EIPOS stop function Compatible Compatible when interrupt sources sharing ICR are not in use Not compatible Peripheral functions sharing the ICR register have the same interrupt level f peripheral functions sharing the ICR register are using expanded intelligent I O services one or the other x P O 2 cannot be used e When peripheral functions are sharing the ICR register and one specifies expanded intelligent I O services the interrupt from the other function cannot be used Priority applies when interrupts of the same level are generated MB90420G 5G A Series PERIPHERAL FUNCTIONS 1 WO Ports The I O ports function is to send data from the CPU to be output from I O pins and load input signals at the I O pins into the CPU according to the port data register PDR Port input output at I O pins can be controlled in bit units by the port direction register DDR as required The following list shows each of the functions as well as the shared peripheral function for each port Port 0 General purpose I O port shared with peripheral functions external interrupt UAR
49. 0C0H 000100H Address 2 Peripheral area 004000H EL MEM a LI 010000H 0000 Address 1 FFFFFFH ROM area FF bank image ER Parts MB90423G L Internal access memory gt lt Access prohibited Address 1 0000 Address 2 001900k FF0000u 0011004 MB90427G A 904280 0000 001900 MB90F423G 0000 001900 MB90F428G A 0000 001900 MB90V420G FE0000k 001900u MB90V420G has no built in ROM On the tool side this area may be considered a ROM decoder Note To select models without the ROM mirror function see the ROM Mirror Function Selection Module The image of the ROM data in the FF bank appears at the top of the 00 bank in order to enable efficient use of small C compiler models The lower 16 bit address for the FF bank will be assigned to the same address so that tables in ROM can be referenced without declaring a far indication with the pointer For example when accessing the address 00 000 the actual access is to address 00 ROM Here the FF bank ROM area exceeds 48 KB so that it is not possible to see the entire area in the 00 bank image Therefore because the ROM data from FF4000n to FFFFFF will appear in the image from 0040004 to 00FFFFH it is recommended that the ROM data table be stored in the area from 4000 to
50. 13 to P15 IN2 to INO General purpose input output ports Input capture ch 0 2 trigger input pins 97 to 100 1 to 8 10 to 13 99 to 100 1to2 3 to 10 12to 15 COMO to COM3 SEGO to SEG11 LCD controller driver common output pins LCD controller driver segment output pins 14to 15 16 17 P36 to P37 SEG12 to SEG13 General purpose output ports LCD controller driver segment output pins 16 to 20 22 to 24 18 to 22 24 to 26 P40 to P47 SEG14 to SEG21 General purpose input output ports LCD controller driver segment output pins 26 to 27 28 to 29 P90 to P91 SEG22 to SEG23 General purpose input output ports LCD controller driver segment output pins P50 ADTG General purpose input output ports INTO external interrupt input pin A D converter external trigger input pin 36 to 39 41 to 44 38 to 41 43 to 46 P60 to P67 General purpose input output ports A D converter input pins General purpose input output port INT1 external interrupt input pin CAN interface 1 RX intput pin General purpose input output port INT2 external interrupt input pin CAN interface 1 TX output pin MB90420G A series only General purpose input output port INT3 external interrupt input pin Continued MB90420G 5G A Series 52 to 55 54 to 57 P70 to P73
51. 23G 2 MB90423GA 2 Evaluation model Flash ROM model Mask ROM model CPU F2MC 16LX CPU System clock On chip PLL clock multiplier type x 1 x 2 x 3 x4 1 2 when PLL stopped Minimum instruction execution time 62 5 ns with 4 MHz oscillator x 4 ROM External Flash ROM 128 KB Mask ROM 128 KB RAM 6 KB 6 KB 6 KB CAN interface 2 channels Low voltage CPU operation detection reset No Yes No Packages PGA 256 QFP100 LQFP100 Emulator dedicat ed power supply No e MB90425G A Series Parameter Configuration MB90F428G MB90F428GA MB90427G MB90427GA MB90428G MB90428GA Flash ROM model Mask ROM model CPU F2MC 16LX CPU System clock On chip PLL clock multiplier type 1 x 2 x 3 x 4 1 2 when PLL stopped Minimum instruction execution time 62 5 ns with 4 MHz oscillator x 4 ROM Flash ROM 128 KB Mask ROM 64 KB Mask ROM 128 KB RAM CAN interface 6 KB 4 KB 6 KB 1 channel Low voltage CPU operation detection reset No Yes Packages QFP100 LOFP100 Emulator dedicat ed power supply When used with evaluation pod MB2145 507 use DIP switch S2 setting For details see the MB2145 507 Hardware Manual 2 7 Emulator Dedicated Power Supply Pin 1 Under development 2 Planned MB90420G 5G A Series PIN ASSIGNMENTS TOP VIEW udo
52. 77 RST B Resetinput pin P00 General purpose input output port 83 85 SIN0 G UART ch 0 serial data input pin INT4 INT4 external interrupt input pin P01 General purpose input output port 84 86 SOTO G UART ch 0 serial data output pin INT5 INT5 external interrupt input pin P02 General purpose input output port 85 87 SCKO G UART ch 0 serial clock input output pin INT6 INT6 external interrupt input pin P03 General purpose input output port 86 88 SIN1 G UART ch 1 serial data input pin INT7 INT7 external interrupt input pin T Se P04 General purpose input output port 5071 UART ch 1 serial data output pin P05 General purpose input output port 88 90 SCK1 G UART ch 1 serial clock input output pin TRG 16 bit PPG ch 0 2 external trigger input pin General purpose input output port 89 91 PPG0 G 16 bit PPG ch 0 output pin TOT1 16 bit reload timer ch 1 TOT output pin P07 General purpose input output port 90 92 PPG1 G 16 bit PPG ch 1 output pin TIN1 16 bit reload timer ch 1 TIN output pin Bd Ge P10 General purpose input output port PPG2 16 bit PPG ch 2 output pin Continued MB90420G 5G A Series Circuit type Description General purpose input output port 16 bit reload timer ch 0 TOT output pin Real time clock timer WOT output pin General purpose input output port 16 bit reload timer ch 0 TIN output pin Input capture ch 3 trigger input pin 94 to 96 96 to 98 P
53. 8x c Software interrupt RIS INT addr16 3 16 0 6x c Software interrupt IRIS INTP addr24 4 17 0 6x Software interrupt RIS INT9 1 20 0 8x c Software interrupt 8 5 RETI 11151 0 from interrupt ex ea LINK 21610 Atconstant entry save old frame pointer to stack set new frame pointer and allocate local pointer area UNLINK 115 0 Atconstant entry retrieve old frame pointer from stack RET 8 11410 c from subroutine RETP 116101 d Return from subroutine 1 5 when branching 4 when not branching 2 13 when branching 12 when not branching 3 7 a when branching 6 a when not branching 4 8 when branching 7 when not branching 5 7 when branching 6 when not branching 6 8 a when branching 7 a when not branching 7 Set to 3 x b 2 x c when an interrupt request occurs and 6 x c for return 8 Retrieve word from stack 9 Retrieve long word from stack 10 In the CBNE CWBNE instruction do not use the RWj addressing mode Note For an explanation of a to d referto Table 4 Number of Execution Cycles for Each Type of Addressing and Table 5 Correction Values for Number of Cycles Used to Calculate Number of Actual C
54. 90420G 5G A Series F2MC 16LX bus Block Diagram Main base oscillator divided by 2 211 Clock input 213 216 Time base timer 218 TBTRES 211 213 216 218 Time base interrupt WDTC 2 bit Watchdog reset Selector counter OF generator circuit To WDGRST CLR CLR internal reset generator circuit SGW Power on reset sub clock stop 210 213 214 216 Clock timer Clock input Sub base oscillator divided by 4 From power on generator RST pin From RST bit in STBYC register 37 MB90420G 5G A Series 3 Input Capture This circuit is composed of a 16 bit free run timer and four 16 bit input capture circuits 1 Input capture x 4 The input capture circuits consist of four independent external input pins and corresponding capture registers and control registers When the specified edge of the external signal input at the input pin is detected the value of the 16 bit free run timer is saved in the capture register and at the same time an interrupt can also be generated The valid edge rising edge falling edge both edges of the external signal can be selected The four input capture circuits can operate independently The interrupt can be generated from the valid edge of the external input signal 2 16 bit free run timer x 1 The 16 bit free run timer is composed of a 16 bit up count
55. AVRH DVcc and analog input do not exceed the digital power supply Vcc Once the digital power supply Vcc is switched on the analog power AVcc AVRH DVcc may be turned on in any sequence Stable supply voltage Even within the warranted operating range of Vcc supply voltage sudden fluctuations in supply voltage can cause abnormal operation The recommended stability for ripple fluctuations P P values at commercial fre quencies 50 to 60 Hz should be within 10 of the standard Vcc value and voltage fluctuations that occur during switching of power supplies etc should be limited to transient fluctuation rates of 0 1 V ms or less Power on procedures In order to prevent abnormal operation of the internal built in step down circuits voltage rise time during power on should be attained within 50 us 0 2 V to 2 7 Treatment of unused input pins If unused input pins are left open they may cause abnormal operation or latchup which may lead to permanent damage to the semiconductor Any such pins should be pulled up or pulled down through resistance of at least 2 Also any unused input output pins should be left open in output status or if found set to input status they should be treated in the same way as input pins Treatment of A D converter power supply pins Even if the A D converter is not used pins should be connected so that AVcc Vcc and AVss AVRH Vss MB90420G 5G A Series 14 Use o
56. D control status register low 16 bit reload timer 1 P50 ADTG Trigger start ADCSH L Operating clock F2MC 16LX bus MB90420G 5G A Series 10 UART The UART is a general purpose serial data communication interface for synchronous communication or asyn chronous start stop synchronized communication with external devices Functions include normal bi directional functions as well as master slave type communication functions multi processor mode master side only supported 1 UART Functions The UART is a general purpose serial data communication interface for sending and receiving of serial data with other CPU s or peripheral devices and provides the following functions Data buffer Full duplex double buffer Functions Transfer modes Clock synchronous no start stop bits Clock asynchronous start stop synchronized Baud rate Exclusive baud rate generator provides a selection of 8 rates External clock input enabled Internal clock can use internal clock feed from 16 bit reload timer Data length 7 bit asynchronous normal mode only 8 bit Signal type NRZ Non return to zero Receiving error detection Framing errors Overrun errors Parity errors not enabled in multiprocessor mode Interrupt request Receiving interrupt receiving completed receiving error detection Sending interrupt sending completed Sending receiving both
57. GO down counter register PDCRO R 3922 3923 3924 3925 PPGO cycle setting register PPGO duty setting register PCSRO PDUTO W W 16 bit PPG 0 11111111 11111111 XXX XXX XX XXXXXXXX XXXXXXXX XXXXXXXX 392864 to 3927 Disabled 3928 3929 PPG1 down counter register PDCR1 R 392Au 392Bu PPG1 cycle setting register PCSR1 W 392CH 392DH PPG1 duty setting register PDUT1 W 16 bit PPG 1 11111111 11111111 XXX XX XXX XXXXXXXX XXXXXXXX XXXXXXXX 392 to 392Fu Disabled 3930 3931 3932 3933 PPG2 down counter register PPG2 cycle setting register PDCR2 PCSR2 R W 39344 3935H PPG2 duty setting register PDUT2 W 16 bit PPG 2 11111111 11111111 XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 39364 to 3959 Disabled Continued MB90420G 5G A Series EE Address Register name Symbol Read write Peripheral function XXXXXXXX Sub second data register WTBR R W XXXXXXXX Real time XXXXX Second data register WTSR R W clock timer XXXXXX Minute data register WTMR R W XXXXXX 395 Hour data register WTHR R W XXXXX 39604 to LCD controller 396Fu LCD display RAM VRA
58. M R W driver XXXXXXXX T Disabled 3980 XXXXXXXX PWM1 compare register 0 PWC10 R W 3981 0 0 XX 3982 i XXXXXXXX PWM compare register 0 PWC20 R W tepping moir 3983H controller0 ti XX 39844 PWM1 select register 0 PWS10 R W 000000 39854 PWM2 select register 0 PWS20 R W 0000000 ge Disabled 3988 XXXXXXXX PWM1 compare register 1 PWC11 R W XX 398A i XXXXXXXX PWM2 compare register 1 PWC21 R W spp olor 398 controller XX 398 PWM1 select register 1 PWS11 R W 000000 398Du 2 select register 1 PWS21 R W 0000000 Disabled 3990 XXXXXXXX PWM1 compare register 2 PWC12 R W or XX 3992 i XXXXXXXX PWM2 compare register 2 PWC22 R W sleeping 100 97 3993 controller2 XX 39944 PWM1 select register 2 PWS12 R W 000000 3995 2 select register 2 PWS22 R W 0000000 post Disabled Continued 23 MB90420G 5G A Series Continued Address Register name Read write Peripheral function Initial value PWM1 compare register PWM 2 compare register 3 PWM1 select register 3990 2 select register 3 PWS23 R W XXXXXXXX Stepping motor controller 3 000000 0000000 399 to 9 Disabled to Area reserved for interface 0 00 to Area reserved for interface 1 3C00 to 3CFFu Area reserved
59. T PPG Port 1 General purpose I O port shared with peripheral functions PPG reload timer clock timer ICU Port General purpose I O port shared with peripheral functions LCD Port 4 General purpose I O port shared with peripheral functions LCD Port 6 General purpose I O port shared with peripheral functions A D converter Port 7 General purpose I O port shared with peripheral functions Stepping motor controller Port 8 General purpose I O port shared with peripheral functions Stepping motor controller Port 5 General purpose I O port shared with peripheral functions External interrupt CAN SG Port 9 General purpose I O port shared with peripheral functions LCD 1 List of Functions Pin name POO SINO INT4 to PO7 PPG1 P10 PPG2 to P15 INO P36 SEG12 to P37 SEG13 P40 SEG14 to P47 SEG21 P50 INTO to P57 SGA Input format CMOS hysteresis P60 ANO to P67 AN7 Analog CMOS hysteresis P70 PWM1P0to P77 PWM2M1 P80 PWM1P2to P87 PWM2M3 P90 SEG22 to P91 SEG23 CMOS hysteresis Output format Function General purpose port Peripheral function General purpose port Peripheral function General purpose port Peripheral function General purpose port Peripheral function General purpose port Peripheral function General purpose
60. XX Input capture control status 0 1 Input capture 0 1 00000000 6Bu Input capture control status 2 3 Input capture 2 3 Disabled 00000000 6CH LCDC control register lower LCRL R W LCD controller Gu LCDC control register higher LCRH R W driver 00010000 00000000 Low voltage detect reset control Low voltage LVRC register detect reset 10111000 6 ROM mirror ROMM w ROM mirror XXXXXXX1 704 to 7 Area reserved for CAN interface 1 Stepping motor PWM control register 0 controllerO 00000 0 Disabled Stepping motor PWM control register 1 PWC1 RAN controller1 00000 0 Disabled Stepping motor PWM control register 2 PWC2 R W controller2 00000 0 Disabled Stepping motor PWM control register 3 PWC3 R W controller3 00000 0 Disabled Continued MB90420G 5G A Series EE Continued Address Register name Read write Peripheral function Initial value Address match ROM correction control register detection f nction Delay interrupt release Delayed interrupt Power saving mode Power saving 00011000 Clock select control circuit 11711100 Watchdog control WDTG R W Watchdog timer XXXXX 1 1 1 Time base timer control register TBTC R W Time base timer 1 00100 Clock timer Clock timer control register WTC R W sub clock 1X000000
61. XXX XXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXX XXXXXXXX 003A3Cu 003B3C 003A3Du 00 003B3Du 003B3Fu ID register 7 XXXXXXXX XXXXX XXXXXXXX XXXXXXXX 003 40 003 40 003A41H 003 41 003 42 003B42 003 43 003 44 003843 003 44 003 45 003 45 003 46 003 46 003 47 003B47H ID register 8 ID register 9 XXXXXXXX XXXXXXXX XXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXX XXXXXXXX 003 48 003 48 003 49 008A4Au 003 49 003 4 003A4Bu 003 4 ID register 10 XXXXXXXX XXXXX XXXXXXXX XXXXXXXX 4 003 4 003A4Du 003 40 00 4 003 4 00 4 00 4 ID register 11 XXXXXXXX XXXXXXXX XXXXX XXXXXXXX 003A50u 003 50 003A51H 003851 003A52H 003 52 003A53u 003 53 ID register 12 XXXXXXXX XXXXXXXX XXXXX XXXXXXXX Continued 27 MB90420G 5G A Series Address Initial value 28 CANO 003A54k CAN1 003B54 003A55u 003 55 003 56 003 56 003A57u 003A58u 003B57u 003 58 003A59u 003 59 008A5Au 003B5AH 003A5BH 003B5Bu Register
62. ck diagram F2MC 16LX bus TQ operating clock Machine Prescaler 1 to 64 a clock frequency divider Bit timing generator SYNC TSEG1 TSEG2 IDLE SUSPND Bus Node status change Node status state 2 interrupt generator change interrupt machine UJ O 240 20 U 2 m mi NS1 0 Error Send receive BVALR sequencer TBFx Error TREQR clear Send buffer frame decision Data Receiving generator counter filter control SE TDLC RDLC IDSEL generator x BITER STFER Output p TCANR CRCER FRMER ARBLOST TX ACKER TRTRR RFWTR Send shift Stuffing register TCR TBFx set clear Eae Sending p Sending completed TDLG generator generator TIER interrupt generator competed interrupt CRCER Rh E RBFx set _ RDLC CRC generator BIER Receiving completed Receiving error check interrupt generator gt completed Receiving RBEx TBFx set clear shift register Destuffing RRTRR 9 stuffing RBFx IDSEL error check set AMSR ARBLOST Arbitration i check AMRO 0 BITER Bit error el 1 Receiving Receiving bufferx check AMR1 filter decision ACKER __ error IDR0 15 RBF DTRO 15 RAM address check RAM k e RBFx TBFx RDLC TDLC IDSEL ge
63. ctions MOVSW MOVSWI Word transfer AH AL counter RWO MOVSWD Word transfer AL counter RWO SCWEQ SCWEQI Word retrieval AH AL counter RWO SCWEQD 2 Word retrieval AL counter RWO FILSW FILSWI Word filling AH AL counter RWO m RWO value counter value n Loop count 1 5 when RWO is 0 4 8 x RWO in any other case b x RWO b x RWO when accessing different areas for the source and destination calculate b sepa 5 when RWO is 0 4 7 x for count out and 7 x n 5 when match occurs rately for each b x n 2 x RW0 c x RW0 c x RWO when accessing different areas for the source and destination calculate c separately for each 2 x RW0 Note For an explanation of a to d referto Table 4 Number of Execution Cycles for Each Type of Addressing and Table 5 Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles 95 MB90420G 5G A Series 96 ORDERING INFORMATION Part number MB90F428GAPF MB90F423GAPF MB90428GAPF MB90427GAPF MB90423GAPF MB90F428GPF MB90F423GPF MB90428GPF MB90427GPF MB90423GPF MB90F428GAPFV MB90F423GAPFV MB90428GAPFV MB90427GAPFV MB90423GAPFV MB90F428GPFV MB90F423GPFV MB90428GPFV MB90427GPFV MB90423GPFV Package Plastic QFP 100 pin FPT 100P M06 Plastic LQFP 100 pin
64. cution of instruction Reset by execution of instruction Indicates whether the instruction is a read modify write instruction a single instruction that reads data from memory etc processes the data and then writes the result to memory Instruction is a read modify write instruction Instruction is not a read modify write instruction Note A read modify write instruction cannot be used on addresses that have different meanings depending on whether they are read or written Number of execution cycles The number of cycles required for instruction execution is acquired by adding the number of cycles for each instruction a corrective value depending on the condition and the number of cycles required for program fetch Whenever the instruction being executed exceeds the two byte word boundary a program on an internal ROM connected to a 16 bit bus is fetched If data access is interfered with therefore the number of execution cycles is increased For each byte of the instruction being executed a program on a memory connected to an 8 bit external data bus is fetched If data access in interfered with therefore the number of execution cycles is increased When a general purpose register an internal ROM an internal RAM an internal I O device or an external bus is accessed during intermittent CPU operation the CPU clock is suspended by the number of cycles specified by the CG1 0 bit of the low power consumption mod
65. de External clock mode In this mode a down count event occurs when a selected valid edge rising falling both edges is input at the TINO 1 pin This function can also be used as an interval timer when an external clock with a fixed period is used 4 Counter operation Reload mode In down count operation when an underflow event transition from 0000 to FFFFu occurs the set count value is reloaded and count operation continues The function can be used as an interval timer by generating an interrupt request at each underflow event Also a toggle waveform that inverts at each underflow can be output from the TOTO 1 pin Counter clock Counter clock period Interval time 216 0 125 us 0 125 us to 8 192 ms Internal clock 23 9 0 5 us 0 5 us to 32 768 ms 25 0 2 0 us 2 0 us to 131 1 ms External clock 23 or greater 0 5 us 0 5 us or greater Machine clock cycle Figures in are values at machine clock frequency 16 MHz 39 MB90420G 5G A Series 40 5 One shot mode In down count operation the count stops when an underflow event transition from 0000 to occurs This function can generate an interrupt at each underflow While the counter is operating a rectangular wave form indicating that the count is in progress can be output form the TOTO and TOT1 pins 6 Block diagram Internal data bus TMRLRO 1 lt TMRLR1 gt 16 bit reload r
66. ded from 8 bit immediate data disp8 disp16 8 bit displacement 16 bit displacement bp Bit offset vct4 vct8 Vector number 0 to 15 Vector number 0 to 255 b Bit address rel PC relative addressing ear eam Effective addressing codes 00 to 07 Effective addressing codes 08 to 1F Register list 79 MB90420G 5G A Series Notation RW0 RW1 RW2 RW3 Table3 Effective Address Fields Address format Register direct ea corresponds to byte word and long word types starting from the left Register indirect Number of bytes in address extension RWO RW1 RW2 RW3 Register indirect with post increment RWO disp8 RW1 disp8 RW2 disp8 RW3 disp8 RW4 disp8 RWS5 disp8 RWE disp8 RW7 disp8 Register indirect with 8 bit displacement RWO disp16 RW1 disp16 RW2 disp16 RWS3 disp16 Register indirect with 16 bit displacement QRWO RW7 RW1 RW7 PC disp16 addr16 Register indirect with index Register indirect with index PC indirect with 16 bit displacement Direct address Note The number of bytes in the address extension is indicated by the symbol in the number of bytes column in the tables of instructions 80 MB90420G 5G A Series Table4 Number of Execution Cycles for Each Type of Addressing a a Number of re
67. e control register When determining the number of cycles required for instruction execution during intermittent CPU operation therefore add the value of the number of times access is done x the number of cycles suspended as the corrective value to the number of ordinary execution cycles MB90420G 5G A Series Table2 Explanation of Symbols in Tables of Instructions Meaning 32 bit accumulator The bit length varies according to the instruction Byte Lower 8 bits of AL Word 16 bits of AL Long 32 bits of AL and AH Upper 16 bits of A Lower 16 bits of A Stack pointer USP or SSP Program counter Program bank register Data bank register Additional data bank register System stack bank register User stack bank register Current stack bank register SSB or USB Direct page register DTB ADB SSB USB DPR PCB SPB DTB ADB SSB USB DPR SPB RWi RO R1 R2 R3 R4 R5 R6 R7 RWO RW1 RW2 RW3 RW4 RW5 RW6 RW7 RWj RWO RW1 RW2 RW3 RLi RLO RL1 RL2 RL3 dir Compact direct addressing addr16 addr24 ad24 0 to 15 ad24 16 to 23 Direct addressing Physical direct addressing Bit 0 to bit 15 of addr24 Bit 16 to bit 23 of addr24 io imm4 imm8 imm16 imm32 ext imm8 I O area 0000004 to 0000 4 bit immediate data 8 bit immediate data 16 bit immediate data 32 bit immediate data 16 bit data signed and exten
68. eceiving Sending Pins I shift register shift register P00 SIN0 lt P03 SIN1 gt T Sending start Receiving status judging circuit gt El OS receiving error generator circuit to CPU Internal data bus SMR0 1 register SCR0 1 SSR0 1 register register Interrupt number 50 MB90420G 5G A Series 11 CAN Controller The CAN controller is a self contained module within a 16 bit microcomputer F MC 16L X The CAN controller area network controller is the standard protocol for serial transmissions among automotive controllers and is widely used in the industry 1 CAN controller features The CAN controller has the following features Conforms to CAN specifications version 2 0 A and B Supports sending and receiving in standard frame and expanded frame format Supports data frame sending by means of remote frame receiving 16 sending receiving message buffers 29 bit ID and 8 byte data Multi level message buffer configuration Supports full bit compare full bit mask as well as partial bet mask filtering Provides two receiving mask registers for either standard frame or expanded frame format Bit speed programmable from 10 KB s to 1 MB s at machine clock 16 MHz CAN WAKE UP function The MB90420G A series has a two channel built in CAN controller The MB90425G A series has a 1 channel built in CAN controller MB90420G 5G A Series 2 Blo
69. ecuted The ROM correction function can be implemented by processing the INT9 interrupt service routine Two address registers are used each with its own compare enable bit When there is a match between the address register and program counter and the compare enable bit is set to 1 the INT9 instruction is forcibly executed by the CPU Block diagram Address latch B ROM correction AE address register Enable bit F2MC 16LX CPU core F2MC 16LX bus 59 MB90420G 5G A Series EE 17 ROM Mirror Function Select Module The ROM mirror function select module uses a select register setting to enable the contents of ROM allocated to the FF bank to be viewed in the 00 bank Block diagram F2MC 16LX bus ROM mirror function select register Address area 60 MB90420G 5G A Series ELECTRICAL CHARACTERISTICS 1 Absolute Maximum Ratings Parameter Power supply voltage Vss 6 0 Vss AVss DVss 0 V Remarks Vss 6 0 Vss 6 0 gt Vavru Vss 4 6 0 DVcc Input voltage Output voltage Vcc 0 3 Vcc 0 3 Clamp current IcLAMP 2 0 L level maximum output current lout 15 Other than P70 P77 P80 P87 love P70 77 P80 87 L level average output current 3 L level maximum total output current loLav1 Other than P70 P77
70. egative Set to 3 when byte ear is zero 12 when the result is positive and 13 when the result is negative Setto 4 a when byte eam is zero 13 a when the result is positive and 14 a when the result is negative Set to 3 when word is zero 12 when the result is positive and 13 when the result is negative Set to 3 when word ear is zero 16 when the result is positive and 19 when the result is negative Set to 4 a when word eam is zero 17 a when the result is positive and 20 a when the result is negative Notes When overflow occurs during DIV or DIVW instruction execution the number of execution cycles takes two values because of detection before and after an operation When overflow occurs during DIV or DIVW instruction execution the contents of AL are destroyed For a to d refer to Table 4 Number of Execution Cycles for Effective Address in Addressing Modes and Table 5 Correction Values for Number of Cycles for Calculating Actual Number of Cycles 87 MB90420G 5G A Series 88 Table 14 Logical 1 Instructions Byte Word 39 Instructions B Operation LH AH 1 5 2 v c A imm8 A ear A eam ear A eam A A imm8 A ear A eam ear A eam A A imm8 A ear A eam ear A eam A A ear eam oONO O lt imm8 lt A and ear byte lt A and eam ds ear
71. egister TMRO 1 lt TMR1 gt Reload signal Reload control circuit 16 bit timer register down counter Count clock generator circuit Gate input Valid clock Wait signal decision circuit Machine clock Prescaler To UART 0 1 1 lt To A D converter gt P11 TOTO 1 lt P06 TOT1 gt Internal clock Output signal generator circuit Input control circuit Clock selector Inverted P12 TINO lt PO7 TIN1 gt External clock Select signal Operation control Pa T T S or psp Function selection Timer control status register TNGSR0 1 Interrupt lt TNGSR1 gt request signal 17 11h 2 1 Channel 0 and channel 1 Figures in lt gt are for channel 1 lt 28 10h gt 2 Interrupt number MB90420G 5G A Series 5 Real Time Clock Timer The real clock timer is composed of a real time clock timer control register sub second data register second minute hour data registers 1 2 clock divider 21 bit prescaler and second minute hour counters Because the MCU oscillation frequency operates on a given real time clock timer operation a 4 MHz frequency is assumed The real time clock timer operates as a real world timer and provides real world time information Block diagram H 12 clock 21 bit WOT divider prescaler
72. enerated or EIOS can be started Because the conversion data protection function operates in an interrupt enabled state no data is lost even in continuous conversion The conversion start source may be selected from software 16 bit reload timer 1 rising edge or external trigger input falling edge Three conversion modes are available Conversion mode Single conversion operation Scan conversion operation Converts multiple consecutive channels up to 8 channels may be specified one time then stops Converts the specified channel 1 channel Single conversion mode only one time then stops Continuous conversion Converts the specified channel 1 channel Converts multiple consecutive channels up mode only repeatedly to 8 channels may be specified repeatedly Converts multiple consecutive channels up to 8 channels may be specified however pauses after conversion of each channel waits until the next start is applied Converts the specified channel 1 channel Stop conversion mode only one time then pauses waits until the next start is applied 47 MB90420G 5G A Series 48 2 Block diagram AVcc AVRH AVss AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 o o 3 Q lt Sample amp hold circuit Timer start D A converter Sequential comparator register Comparator A D data register Decoder A D control status register high A
73. er control register 16 bit compare register and prescaler The output values from this counter are used as the base time for the input capture circuits The counter clock operation can be selected from 8 options The eight internal clock settings are 0 0 2 0 4 9 8 9 16 6 32 0 64 9 128 where represents the machine clock cycle Interrupts can be generated from overflow events or from compare match events with the compare register Compare match operation requires a mode setting The counter value can be initialized to 0000 by a reset soft clear or a compare match with the compare register 3 Block diagram 38 31 1FH IVFE STOP MODE CLK2 CLK0 a Clock C 16 bit free run timer Interrupt 33 21H 16 bit compare clear register 2 4 ICLR ICRE A D startup Edge detection IN0 2 Capture data register 0 2 F EG11 EG10 EG01 EG00 Capture data register 1 3 Edge detection IN1 3 O D Interrupt 15 21 MB90420G 5G A Series 4 16 bit Reload Timer The 16 bit reload timer can either count down in synchronization with three types of internal clock signals in internal clock mode or count down at the detection of the designated edge of an external signal The user may select either function This timer defines a transition from 00004 to FFFFu as
74. esented on the data sheet Users considering application outside the listed conditions are advised to contact their FUJITSU representatives beforehand 62 MB90420G 5G A Series 3 DC Characteristics Vcc 5 0 V 10 Vss DVss AVss 0 0 V Ta 40 C to 105 C H level input voltage Parameter Conditions Remarks CMOS hysteresis input MD pin L level input voltage 0 6 Vcc CMOS hysteresis input pin Vss 0 3 MD pin Operating frequency For 16 MHz normal operation Operating frequency For 16 MHz sleep mode MB90F428G GA MB90F423G GA MB90428G GA MB90427G GA MB90423G GA MB90F428G GA MB90F423G GA MB90428G GA MB90427G GA MB90423G GA Power supply Operating frequency current 2 MHz time base timer mode Operating frequency For 8 kHz TA 25 C subclock operation Operating frequency For 8 kHz 25 C sub sleep operation Operating frequency For 8 kHz TA 25 C clock mode 1 All input pins except X0 XOA MDO MD1 MD2 pins 2 MDO MD1 MD2 pins 3 Current values are provisional and may be changed without prior notice for purposes of characteristic improve ment etc Supply current values assume external clock feed from the 1 pin and X1A pin Users must be aware that supply current levels differ depending on whether an external clock or osc
75. f external clock signals Even when an external clock is used a stabilization period is required following a power on reset or release from sub clock mode or stop mode Also when an external clock is used it should drive only the X0 pin and the X1 pin should be left open as shown in Figure 3 X0 OPEN x1 MB90420G 425G A Series Sample external clock connection Power supply pins Devices are designed to prevent problems such as latchup when multiple Vcc and Vss supply pins are used by providing internal connections between pins having the same potential However in order to reduce unwanted radiation and to prevent abnormal operation of strobe signals due to rise in ground level and to maintain total output current ratings all such pins should always be connected externally to power supplies and ground As shown in Figure 4 all Vcc power supply pins must have the same potential All Vss power supply pins should be handled in the same way If there are multiple Vcc or Vss systems the device will not operate properly even within the warranted operating range Vcc vss Power supply input pins Vcc Vss In addition care must be given to connecting the Vcc and Vss pins of this device to a current source with as little impedance as possible It is recommended that a bypass capacitor of 1 0 uF be connected between Vcc and Vss as close to the pins as possible Proper sequence of A D con
76. for CAN interface 0 3D00k to 3DFFu 3E00 to Initial value symbols 0 initial value 0 1 initial value 1 X initial value undetermined initial value undetermined none Write read symbols R W read write enabled R read only W write only Area reserved for CAN interface 1 Disabled Addresses in the area 0000 to are reserved for the principal functions of the MCU Read access attempts to reserved areas will result in an X value Also write access to reserved areas is prohibited 24 MB90420G 5G A Series I O Map for CAN Interface Address CANO 000040u CAN1 000070u 0000414 0000714 Register name Message buffer valid area Initial value 00000000 00000000 000042 000072 000043u 000044 000073u 000074 000045 000075 Transmission request register Transmission cancel register 00000000 00000000 00000000 00000000 000046u 000076u 000047u 000077u Transmission completed register 00000000 00000000 000048u 000078u 0000491 00004 000079u 00007 00004 00007 Receiving completed register Remote request receiving register 00000000 00000000 00000000 00000000 00004 00007 000040 00007Du Receiving overrun register 00000000 00000000 00004 00007
77. gister accesses Number of execution cycles for each type of addressing for each type of addressing Operand 00 to 07 i Listed in tables of instructions Listed in tables of instructions 08 to 08 RWj OC to OF 10 to 17 RWi disp8 18 to 1B QRWj disp16 1 RW7 1 RW1 RW7 1E PC disp16 1F addr16 Note a is used in the number of states column and column B correction value in the tables of instructions lt Table5 Compensation Values for Number of Cycles Used to Calculate Number of Actual Cycles b byte c word d long iss Access Access Access Operand Internal register Internal memory even address Internal memory odd address Even address on external data bus 16 bits Odd address on external data bus 16 bits External data bus 8 bits Notes e b and are used in the number of states column and column B correction value in the tables of instructions e When the external data bus is used it is necessary to add in the number of wait cycles used for ready input and automatic ready Table 6 Correction Values for Number of Cycles Used to Calculate Number of Program Fetch Cycles Instruction Byte boundary Word boundary Internal memory 2 External data bus 16 bits 3 External data bus 8 bits 3 Notes When t
78. he external data bus is used it is necessary to add in the number of wait cycles used for ready input and automatic ready Because instruction execution is not slowed down by all program fetches in actuality these correction values should be used for worst case calculations 81 MB90420G 5G A Series Table 7 Transfer Instructions Byte 41 Instructions Mnemonic Re cree LH AH 1 S A dir A addr16 N N G eS a a RLi disp8 A imm4 RLi disp8 imm4 co po pno no 0 I ONOOO0O0 00 T T TTTTTTTT A dir A addr16 N Co A RWi disp8 RLi disp8 ow N wo A RWi disp8 A RLi disp8 KKK X X X XX X gt X NNNNNNNNNN ann dir addr16 Ri A ear A eam A io A RLi disp8 A Ri ear Ri eam ear Ri eam Ri Ri imm8 io imm8 dir Zimm8 ear imm8 eam fimm8 AL AH byte dir A byte addr16 A byte Ri lt A byte ear A 5 A NN m byte eam lt A byte io A byte RLi disp8 A i i ow www byte Ri lt ear byte byte ear Ri byte eam lt Ri byte Ri i
79. illator is useed Continued 63 MB90420G 5G A Series 64 Continued Parameter Power supply current Pin name Vcc 5 0 V 10 Vss DVss AVss 0 0 V Ta 40 C to 105 Conditions 25 stop mode MB90F428G MB90F423G MB90428G MB90427G MB90423G MB90F428GA MB90F423GA MB90428GA MB90427GA MB90423GA Input leakage current All input pins Vcc DVcc AVcc Vss lt Vi lt Vcc 5 5 V Input capacitance 1 Other than Vcc Vss DVcc DVss Avcc Avss C P70 to P77 P80 to P87 Input capacitance 2 Pull up resistance P70 to P77 P80 to P87 RST MDO MD1 Pull down resistance MD2 Output H voltage 1 Other than P70 to P77 P80 to P87 Vcc 4 5 V lou 4 0 mA Output H voltage 2 P70 to P77 P80 to P87 Vcc 4 5 V lou 30 0 mA Output L voltage 1 Other than P70 to P77 P80 to P87 Vcc 4 5 V lo 4 0 mA Output L voltage 2 P70 to P77 P80 to P87 Vcc 4 5 V lo 30 0 mA 3 Current values are provisional and may be changed without prior notice for purposes of characteristic improve ment etc Supply current values assume external clock feed from the 1 pin and X1A pin Users must be aware that supply current levels differ depending on whether an external clock or oscillator is useed Continued MB90420G 5G A Series
80. mer have the following circuit configuration Watchdog timer Watchdog counter control register watchdog reset circuit Time base timer 18 bit timer interval interrupt control circuit Clock timer 15 bit timer interval interrupt control circuit 1 Watchdog timer function The watchdog timer is composed of a 2 bit watchdog counter that uses the carry signal from the 18 bit time base timer or 15 bit clock timer as a clock source plus a control register and watchdog reset control circuit After startup this function will reset the CPU if not cleared within a given time 2 Time base timer function The time base timer is an 18 bit free run counter time base counter synchronized with the internal count clock base oscillator divided by 2 with an interval timer function providing a selection of four interval times Other functions include a timer output for an oscillator stabilization wait time and clock feed to the watchdog timer or other operating clocks Note that the time base timer uses the main clock regardless of the setting of the MCS bit or SCS bit in the CKSCR register 3 Clock timer function The clock timer provides functions including a clock source for the watchdog timer a sub clock base oscillator stabilization wait timer and an interval timer to generate an interrupt at fixed intervals Note that the clock timer uses the sub clock regardless of the setting of the MCS bit or SCS bit in the CKSCR register MB
81. ming Value Parameter Symbol Conditions Unit ap wah wa mono s Jul Trigger input timing 0 8 Vcc 0 8 Vcc 0 6 Vcc IRQO IRQ7 0 6 Vcc 71 MB90420G 5G A Series 72 7 Low voltage detection Parameter Detection voltage Pin name Hysteresis width Power supply voltage fluctuation ratio Detection delay time Conditions Vss AVss 0 0 V TA 40 C to 105 C Remarks During voltage drop During voltage rise Internal reset MB90420G 5G A Series 5 A D Conversion Block 1 Electrical Characteristics Vcc 5 0 V 10 Vss AVss 0 0 V Ta 40 C to 105 C Parameter Resolution Pin name Remarks Total error Non linear error Differential linear error Zero transition voltage Full scale transition voltage ANO to AN7 ANO to AN7 1LSB AVRH AVss 1024 Sampling time 1 Compare time 2 A D conversion time Analog port input current AN0 to AN7 Vavss VAIN VAvcc Analog input current Reference voltage AN0 to AN7 AVRH Power supply current AVcc 4 Reference voltage feed current AVRH 5 0 V AVRH 4 Inter channel variation ANO to AN7 1 At For 16 MHz tsmr 32 x tcp 2 000
82. mm8 i m Ri Ri eam ea byte io lt imm8 byte byte byte io dir imm8 ear imm8 eam imm8 2 3 2 2 24 2 2 2 2 3 2 3 1 2 2 3 a 2 3 2 2 2 2 2 3 3 3 3 Co O oo p5 nm mmoo occo byte Ri ear Ri eam byte ear eam ear byte Ri eam Note For an explanation of a to d refer to Table 4 Number of Execution Cycles for Each Type of Addressing and Table 5 Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles N NARON de 82 MB90420G 5G A Series Table8 Transfer Instructions Word Long Word 38 Instructions Operation MOVW A dir MOVW A addr16 MOVW A SP MOVW A RWi MOVW A ear MOVW A eam MOVW A io MOVW A A MOVW A imm16 MOVW GRWi disp8 MOVW A RLi disp8 NN m BOO 8 O1 N 355 RWi disp8 RLi disp8 dir A addr16 SP lt word RWi A word ear lt A word eam lt word io A word RWi disp8 lt A word RLi disp8 A
83. name ID register 13 ID register 14 XXXXXXXX XXXXXXXX XXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXX XXXXXXXX 003A5Cu 003 5 003A5Du 003B5Du 003B5Eu 003A5Fu 003B5Fu ID register 15 XXXXXXXX XXXXX XXXXXXXX XXXXXXXX 003A60k 003 60 1 003 61 DLC register 0 ne NN XXXX 003A62H 003B62 003A63u 003 63 003 64 003A65u 003B65u DLC register 1 DLC register 2 XXXX XXXX XXXX XXXX 003A66u 003 66 003A67 003B67 DLC register 3 XXXX XXXX 003A68u 003 68 003 69 003 69 003 6 003B6Bu DLC register 4 DLC register 5 DLCR5 XXXX XXXX XXXX XXXX 003A6C 003 6 003A6Dk 003B6Du DLC register 6 DLCR6 XXXX XXXX 003 6 003A6Fu 003B6Fu DLC register 7 DLCR7 XXXX XXXX 70 003 70 71 003 71 DLC register 8 DLCR8 XXXX XXXX 003A72u 003B72u 003 73 003 73 DLC register 9 DLCR9 XXXX XXXX 003A74H 003B74 75 003B75u DLC register 10 DLCR10
84. nerator LEIR 52 MB90420G 5G A Series 12 LCD Controller Driver The LCD controller driver has a built in 16 x 8 bit display data memory and controls the LCD display by means of four common outputs and 24 segment outputs A selection of three duty outputs are available This block can drive an LCD liquid crystal display panel directly 1 LCD controller driver functions The LCD controller driver provides functions for directly displaying the contents of display data memory display RAM on the LCD panel by means of segment output and common output LCD drive voltage divider resistance is built in External divider resistance can also be connected Up to 4 common outputs COMO to COM3 and 24 segment outputs SEGO to SEG23 be used 16 byte display data memory display RAM is built in The duty can be selected at 1 2 1 3 1 4 limited by bias setting Drives the LCD directly O Recommended mode x Use prohibited Note When the SEG12 to SEG23 pins have been selected as general purpose ports by the LCRH setting they cannot be used for segment output 53 MB90420G 5G A Series 2 Block diagram VO V2 V3 Divider resistance LCDC control register L LCRL 4 COMO Time base Prescaler Timing Lt COM1 timer output controller Common H COM2 o driver S 8 5 3 24
85. on Indicates the ability of the A D converter to discriminate in analog conversion 10 bit resolution indicates that analog voltage can be resolved into 2 1024 levels Total error Expresses the difference between actual and logical values It is the total value of errors that can come from offset error gain error non linearity error and noise Linearity error Expresses the deviation between actual conversion characteristics and a straight line connecting the device s zero transition point 00 0000 0000 00 0000 0001 and full scale transition point 11 1111 1110 lt 11 1111 1111 Differential linearity error Expresses the deviation of the logical value of input voltage required to create a variation of 1 SLB in output code 10 bit A D converter conversion characteristics 11 1111 1111 11 1111 1110 11 1111 1101 11 1111 1100 1 LSB x Vor 5 5 8 a Linearity error 00 0000 0011 00 0000 0010 00 0000 0001 00 0000 0000 VNT V N 1 T VEST Analog input 1 LSB VEST Vor 1022 3 1 LSB x N Vor LSB Linearity error 1LSB LSB Differential linearity error STEN 1 LSB 1 LSB 75 MB90420G 5G A Series EXAMPLE CHARACTERISTICS 76 TA 25 40 99 R lt
86. or long A A or long A A xor Note For an explanation of a to d referto Table 4 Number of Execution Cycles for Each Type of Addressing and Table 5 Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles Table 16 Sign Inversion Instructions Byte Word 6 Instructions NEG A byte A lt 0 A NEG ear byte ear 0 ear NEG eam byte eam 0 eam word A 0 A word ear 0 ear word eam 0 eam Note For an explanation of a to d referto Table 4 Number of Execution Cycles for Each Type of Addressing and Table 5 Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles Table 17 Normalize Instruction Long Word 1 Instruction Operation KE A R0 oa Shift until first digit is 1 byte an lt Current shift count 1 4 when the contents of the accumulator are all zeroes 6 RO in all other cases shift count Note For an explanation of a to d refer to Table 4 Number of Execution Cycles for Each Type of Addressing and Table 5 Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles 89 MB90420G 5G A Series iii Table 18 Shift Instructions Byte Word Long Word 18
87. r byte eam long A word ear Quotient word A Remainder word ear long A word eam Quotient word A Remainder word eam byte AH byte AL word A A ear byte A byte ear word A A eam byte A byte eam word A A word AH AL long A A ear 0 word A word ear long A A eam word A word eam long A Set to 3 when the division by 0 8 or 18 for an overflow and 18 for normal operation Set to 3 when the division by 0 10 or 21 for an overflow and 22 for normal operation Set to 4 a when the division by 0 11 a or 22 a for an overflow and 23 a for normal operation Positive dividend Set to 4 when the division by 0 10 or 29 for an overflow and 30 for normal operation Negative dividend Set to 4 when the division by 0 11 or 30 for an overflow and 31 for normal operation Positive dividend Set to 4 a when the division by 0 11 a or 30 a for an overflow and 31 a for normal operation Negative dividend Set to 4 a when the division by 0 12 a or 31 a for an overflow and 32 a for normal operation When the division by 0 b for an overflow and 2 x b for normal operation When the division by 0 c for an overflow and 2 x c for normal operation Set to 3 when byte AH is zero 12 when the result is positive and 13 when the result is n
88. r16 bp b 1 bit 1 WBTS io bp 0 Wait until io bp b WBTC io bp Wait until io bp b 0 1 8 when branching 7 when not branching 2 7 when branching 6 when not branching 3 10 when condition is satisfied 9 when not satisfied 4 Undefined count 5 Until condition is satisfied Note For an explanation of a to d referto Table 4 Number of Execution Cycles for Each Type of Addressing and Table 5 Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles Table 23 Accumulator Manipulation Instructions Byte Word 6 Instructions Mnemonic B Operation LH AH SWAP byte A 0 to 7 A 8 to 15 SWAPW XCHW A T word AH lt gt AL EXT byte sign extension EXTW word sign extension ZEXT byte zero extension ZEXTW word zero extension Note For an explanation of a to d referto Table 4 Number of Execution Cycles for Each Type of Addressing and Table 5 Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles MB90420G 5G A Series SCEQ SCEQI Byte retrieval AH AL counter RWO SCEQD Byte retrieval AH AL counter RWO FISL FILSI Byte filling lt AL counter RWO Mnemonic Operation MOVS MOVSI Byte transfer AH AL counter RWO MOVSD Byte transfer lt AL counter RWO Table24 String Instructions 10 Instru
89. rectly connected to the four ends of two motor coils They are designed to operate together with the PWM pulse generators and selector logic circuits to control motor rotation A synchronization mechanism assures synchronization of the two PWM pulse gener ators Block diagram Machine clock Output enable Prescaler ER PWM1 pulse generator Selector mE EN PWM PWM1Mn T PWM1 compare register PWM1 selector register OE2 Output enable CK PWM2Pn PWM2 pulse generator Selector EN PWM PWM2Mn PWM2 compare register PWM2 select register n 0 3 57 MB90420G 5G A Series 58 15 Sound Generator The sound generator is composed of a sound control register frequency data register amplitude data register decrement grade register tone count register PWM pulse generator frequency counter decrement counter and tone pulse counter Block diagram Clock input pulse generator CO E EN PWM Reload Frequency Cl counter CO EN Amplitude data register DEC Frequency data register LI Toggle flip flop Decrement counter Tone pulse counter SGA SGO Tone count register IRQ MB90420G 5G A Series 16 Address Match Detect Function If the address setting is the same as the ROM correction address register an INT9 instruction is ex
90. u 003D1 Ak 003 1 003D1Bu Acceptance mask register 1 XXXXXXXX XXXXX XXXXXXXX XXXXXXXX 003 00 to 003A1FH 003 00 to 003B1FH General purpose RAM XXXXXXXX to XXXXXXXX 003A20k 003B20 003A21 003 21 003A22H 003A23u 003B22 003B23 ID register 0 XXXXXXXX XXXXXXXX XXXXX XXXXXXXX 003 24 003 24 003A25u 003B25 003A26k 003B26 003A27 003B27 ID register 1 XXXXXXXX XXXXXXXX XXXXX XXXXXXXX 003 28 003 29 003 28 003 29 003B2Ak 003A2Bu 003B2Bu ID register 2 XXXXXXXX XXXXXXXX XXXXX XXXXXXXX 003A2C 003 2 003A2Du 003B2Du 003 2 003A2FH 003B2F ID register 3 XXXXXXXX XXXXXXXX XXXXX XXXXXXXX 003A30k 003 30 003A31H 003 31 00 2 003B32 003 33 ID register 4 XXXXXXXX XXXXXXXX XXXXX XXXXXXXX Continued MB90420G 5G A Series Address CANO CAN1 Initial value Register name 003B34 003A35u 003 35 003A36u 003 36 003A37 003A38u 003B37 003 38 003A39u 003 39 003B3AH 003A3BH 003 ID register 5 ID register 6 XXXXXXXX XXXXX
91. verter dedicated GND supply pin 33 35 AVRH A D converter Vref input pin Vref AVss Continued MB90420G 5G A Series Continued Circuit type Description Test mode input pins Connect to Vcc Text mode input pin Connect to Vss External capacitor pin Connect an 0 1 uF capacitor between this pin and Vss Power supply input pins 9 40 79 11 42 81 Vss GND power supply pins Type C in the flash ROM models 10 MB90420G 5G A Series 1 0 CIRCUIT Circuit Remarks x1 T lt Standby control signal Oscillation feedback resistance approx 1 MQ W de Hysteresis input Pull up resistance attached approx 50 kQ hysteresis input C ANY de Hysteresis input Hysteresis input NW Hyteresis input Pull down resistance attached approx 50 kQ hysteresis input No pull down resistance on flash models E ANN LCDC output W Do Hysteresis input CMOS output LCDC output Hysteresis input Continued 11 MB90420G 5G A Series 12 Continued Circuit Analog input Hysteresis input Remarks CMOS output Hysteresis input Analog input Hysteresis input CMOS output Hysteresis input e Pe Erde High current v
92. verter power supply analog input A D converter power AVcc AVRH and analog input ANO AN7 must be applied after the digital power supply Vcc is switched on When power is shut off the A D converter power supply and analog input must be cut off before the digital power supply is switched on Vcc In both power on and shut off care should be taken that AVRH does not exceed AVcc Even when pins which double as analog input pins are used as input ports be sure that the input voltage does not exceed AVcc There is no problem if analog power supplies and digital power supplies are turned off and on at the same time MB90420G 5G A Series Handling the power supply for high current output buffer pins DVcc DVss Always apply power to high current output buffer pins DVcc DVss after the digital power supply Vcc is turned on Also when switching power off always shut off the power supply to the high current output buffer pins DVcc DVss before switching off the digital power supply Vcc There will be no problem if high current output buffer pins and digital power supplies are turned off and on at the same time Even when high current output buffer pins are used as general purpose ports the power for high current output buffer pins DVcc DVss should be applied to these pins Pull up pull down resistance The MB90420G 5G series does not support internal pull up pull down resistance If necessary use external components
93. wer case letters Replaced when described in assembler Numbers after lower case letters Indicate the bit width within the instruction code Indicates the number of bytes Indicates the number of cycles m When branching n When not branching See Table 4 for details about meanings of other letters in items Indicates the number of accesses to the register during execution of the instruction It is used calculate a correction value for intermittent operation of CPU Indicates the correction value for calculating the number of actual cycles during execution of the instruction Table 5 The number of actual cycles during execution of the instruction is the correction value summed with the value in the column Operation Indicates the operation of instruction LH Indicates special operations involving the upper 8 bits of the lower 16 bits of the accumulator Z Transfers 0 X Extends with a sign before transferring Transfers nothing Indicates special operations involving the upper 16 bits in the accumulator Transfers from AL to AH No transfer 2 Transfers 00 AH Transfers 00 or FF to AH by signing and extending AL Indicates the status of each of the following flags interrupt enable S stack T sticky bit N negative Z zero V overflow and C carry Changes due to execution of instruction No change S Set by exe
94. ycles 92 MB90420G 5G A Series Table 21 PUSHW A PUSHW AH PUSHW PS PUSHW rist POPW A POPW AH POPW PS POPW rlst JCTX A AND CCR imm8 OR CCR MOV 8 MOV ILM 8 MOVEA RWi ear MOVEA RWi eam MOVEA A ear MOVEA A eam ADDSP timm8 ADDSP imm16 MOV MOV brg2 A NOP ADB DTB PCB SPB NCC 1 PCB ADB SSB USB and SPB DTB DPR Other Control Instructions Byte Word Long Word 28 Instructions o ch ch 0 0 0 0 0 0 0 0 4 Pop count x or push count 5 Pop count or push count Note For an explanation of a to d referto Table 4 Number of Execution Cycles for Each Type of Addressing and Table 5 Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles Operation lt SP 2 SP A lt SP 2 SP lt AH lt SP 2 SP PS P 2n SP lt rlst word lt SP SP lt SP 2 SP SP 2 SP SP 2 SP SP lt SP 2n Context switch instruction byte CCR CCR and imm8 byte CCR CCR or imm8 byte RP imm8 byte ILM imm8 word RWi ear word RWi lt word A ear word A eam word SP SP ext imm8 word SP SP imm16 byte A brgl byte brg2 A No operation

FUJITSU SEMICONDUCTOR MB90420G/5G (A) Series handbook

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