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FUJITSU SEMICONDUCTOR MB90340 Series handbook

1. 44 90340 Series List of Message Buffers DLC Registers and Data Registers 1 Address 007 60 1 007 60 2 007 60 007 61 007C61u 007E61H Register DLC register 0 Abbreviation Access Initial Value XXXXXXXX 007 62 007 62 007E62u 007 63 007 64 007 63 007 64 007 007 4 007 5 007C65u 007 5 DLC register 1 DLC register 2 XXXXXXXX XXXXXXXX 007 66 007 66 007 007 67 007 67 007 67 DLC register 3 XXXXXXXX 007 68 007 68 007 68 007 69 007 007 69 007 6 007 69 007 6 007A6Bu 007 6 007 6 DLC register 4 DLC register 5 XXXXXXXX XXXXXXXX 007 6 007 6 007 6 007A6Du 007C6Du 007E6Du DLC register 6 XXXXXXXX 007 007 6 007 007 6 007 70 007C6FH 007 70 007 6 007 70 007 71 007 71 007 71 DLC register 7 DLC register 8 DLCR8 XXXXXXXX XXXXXXXX 007 72 007 72 007 72 007 73 007 73 007 73 DLC register 9 DLCR9 XXXXXXXX 007 74 007 74 007 74 007A75u 007 76
2. o o o ep a cacaananannaoannn5 nununnununnarinunsasalircz 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 P01 ADO1 INT9 76 50 1 PO2 ADO2 INT10 77 49 MD2 P03 AD03 INT11 78 48 P75 AN21 INT5 P04 AD04 INT12 79 47 P74 AN20 INT4 P05 ADO5 INT13 80 46 P73 AN19 INT3 P06 ADO6 INT14 81 45 P72 AN18 INT2 P07 ADO7 INT15 82 44 P71 AN17 INT1 P10 ADOB TIN1 83 43 P70 AN16 INTO P11 ADO9 TOT1 84 42 Vss P12 AD10 SIN3 NT11R 85 41 P67 AN7 PPGE F P13 AD11 SOT3 86 40 P66 AN6 PPGC D P14 AD12 SCK3 87 39 P65 AN5 PPGA B 88 38 P64 AN4 PPG8 9 Vss 89 LQFP 100 37 P63 AN3 PPG6 7 x1 90 36 P62 AN2 PPG4 5 91 35 P61 AN1 PPG2 3 P15 AD13 SIN4 92 34 P60 ANO PPGO 1 P16 AD14 SOT4 93 33 Avss P17 AD15 SCK4 94 32 AVRL P20 A16 PPG9 8 95 31 AVRH P21 A17 PPGB A 96 30 Avec P22 A18 PPGD C 97 29 P57 AN15 DAO1 P23 A19 PPGF E 98 28 P56 AN14 DA00 P24 A20 INO 99 e 27 P55 AN13 P25 A21 IN1 100 26 P54 AN12 TOT3 123456789 12 13 14 15 16 17 18 19 20 21 22 23 24 25 s 10 fr CN 5s 10 8 1 NN S 5555552 225555526566 52 0 000 2 lt lt 922255 2 lt AJAA xogg9grax zzzz ANDY ASITEA cr o 5555 22800 Z c
3. When using sub clock Whem selecting the PLL clock the range of clock frequency is limitted Use this product within range as mentioned in Relation among external clock frequency and machine clock frequency tcF tcR Clock Timing 55 90340 Series a Guaranteed operation range Guaranteed A D Converter operation range Guaranteed PLL operation range Power supply voltage Vcc 1 5 4 24 Machine clock fce MHz Guaranteed operation range of MB90340 series Guaranteed oscillation frequency range x6 x4 x3 x2 x1 Internal clock fce MHz x12 PLL off 3 4 8 12 16 24 External clock fc MHz When using the oscillation circuit the maximum oscillation clock frequency is 16 MHz External clock frequency and Machine clock frequency 56 90340 Series 2 Reset Standby Input Ta 40 C to 105 C Vcc 5 0 V 10 Vss AVss 0 0 Parameter Remarks 500 Under normal operation In Stop mode Sub Clock mode Sub Sleep mode and Watch mode Reset input Oscillation time of oscillator time 100 us 100 In Time Timer mode Oscillation time of oscillator is the time that the amplitude reaches 90 Inthe crystal oscillator the oscillation time is between several ms and to tens of ms FAR ceramic oscillators the oscillation time is between hundreds of us to severa
4. FUJITSU SEMICONDUCTOR 16 bit Proprietary Microcontroller CMOS F2MC 16LX 90340 Series MB90F342 C S MB90F343 C S MB90F345 C S MB90F346A S MB90F346CA S MB90F347A S MB90F347CA S MB90F349 C S MB90341 C S MB90342 C S MB90346A S MB90346CA S MB90347A S MB90347CA S MB90348 C S MB90349 C S MB90V340 S DESCRIPTION The MB90340 series with up to 2 FULL CAN interfaces and FLASH ROM is especially designed for automotive and industrial applications Its main feature are the on board CAN Interfaces which conform to V2 0 Part A and Part B while supporting a very flexible message buffer scheme and so offering more functions than a normal full CAN approach With the new 0 35 um CMOS technology Fujitsu now offers on chip FLASH ROM program memory up to 512 Kbytes The power supply 3 V is supplied to the internal MCU core from an internal regulator circuit This creates a major advantage in terms of EMI and power consumption The internal PLL clock frequency multiplier provides an internal 42 ns instruction cycle time from an external 4 MHz clock The unit features an 8 channel Output Compare Unit and 8 channel Input Capture Unit with 2 separate 16 bit free running timers 4 UARTs constitute additional functionality for communication purposes Controller Area Network CAN License of Robert Bosch GmbH Note F MC stands for FUJITSU Flexible Microcontroller a registered trad
5. 007 12 007D12H 007F12H 007 13 007D13u 007 13 Acceptance mask select register XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 007 14 007014 007 14 007 15 007D15H 007F15H 007 16 007 17 007D16H 007D17H 007 16 007 17 Acceptance mask register O XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 007B18u 007018 007 18 007 19 007D19H 007 19 007 1 007D1Au 007F1An 007 1 007D1Bu 007F1Bu Acceptance mask register 1 XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX Address 90340 Series List of Message Buffers ID Registers 1 007 00 to 007 1 1 007 00 to 007C1Fu 007 00 to 007 1 Register General purpose RAM Abbreviation Access Initial Value XXXXXXXX to XXXXXXXX 007 20 007 20 007 20 007 21 007 21 007 21 007 22 007 23 007 22 007 23 007 22 007 23 ID register O XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 007 24 007 24 007 24 007 25 007 25 007 25 007 26 007 26 007 26 007 27 007 27 007 27 ID register 1 XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 007 28 007A29H 007 28 007 29 007 28 007 29 007 2 007 2 007
6. ADO9 TOT1 General purpose I O The register can be set to select whether to use a pull up resistor This function is enabled in single chip mode I O pin for 8th bit of the external address data bus This function is enabled when the external bus is enabled Event input pin for the reload timer 1 General purpose I O The register can be set to select whether to use a pull up resistor This function is enabled in single chip mode I O pin for 9th bit of the external address data bus This function is enabled when the external bus is enabled Output pin for the reload timer 1 P12 AD10 SIN3 General purpose register can be set to select whether to use a pull up resistor This function is enabled in single chip mode pin for 10th bit of the external address data bus This function is enabled when the external bus is enabled Serial data input pin for UART3 Sub external interrupt request input pin for INT11 P13 AD11 5 General purpose register can be set to select whether to use a pull up resistor This function is enabled in single chip mode I O pin for 11th bit of the external address data bus This function is enabled when the external bus is enabled Serial data output pin for UART3 P14 AD12 SCK3 General purpose I O The register can be set to select whether to use a pull up res
7. Timer 0 clock input FRCKO corresponds to ICU 0 1 2 3 OCU 0 1 2 3 Timer 1 clock input FRCK1 corresponds to ICU 4 5 6 7 4 5 6 7 MB90V340 S 16 bit Output Compare 8 channels Signals an interrupt when 16 bit Timer match output compare registers A pair of compare registers can be used to generate an output signal 16 bit Input Capture 8 channels Rising edge falling edge or rising amp falling edge sensitive Signals an interrupt upon external event 8 16 bit Programmable Pulse Generator 8 channels Supports 8 bit and 16 bit operation modes Sixteen 8 bit reload counters Sixteen 8 bit reload registers for L pulse width Sixteen 8 bit reload registers for H pulse width A pair of 8 bit reload counters can be configured as one 16 bit reload counter or as 8 bit prescaler plus 8 bit reload counter Operation clock freq fsys fsys 2 fsys 2 15 5 23 fsys 2 or 128 us fosc 4 MHz fsys Machine clock frequency fosc Oscillation clock frequency CAN Interface External Interrupt 16 channels 2 channels MB90F342 C S MB90F343 C S MB90F345 C S MB90341 C S MB90342 C S MB90F346A S MB90F346CA S MB90F347A S MB90F347CA S MB90F349 C S MB90346A S MB90346CA S MB90347A S 90347 8 MB90348 C S MB90349 C S 1channel 3 channels Conforms to CAN Specification Version 2 0 Part A and B Automatic re transmission in cas
8. 06 MB90F345PFV MB90F345SPFV MB90F345CPFV MB90F345CSPFV MB90F346APF MB90F346ASPF MB90F346CAPF MB90F346CASPF 100 pin Plastic LQFP 100 05 100 pin Plastic QFP 100 06 MB90F346APFV MB90F346ASPFV MB90F346CAPFV MB90F346CASPFV 100 pin Plastic LQFP 100 5 Continued 71 90340 Series Part number Package Remarks MB90F347APF MB90F347ASPF MB90F347CAPF MB90F347CASPF 100 pin Plastic QFP 100 06 MB90F347APFV MB90F347ASPFV MB90F347CAPFV MB90F347CASPFV 100 pin Plastic LQFP 100 05 MB90F349PF MB90F349SPF MB90F349CPF MB90F349CSPF 100 pin Plastic QFP 100 06 MB90F349PFV MB90F349SPFV MB90F349CPFV MB90F349CSPFV 100 pin Plastic LQFP 100 05 MB90341PF MB90341SPF MB90341CPF MB90341CSPF 100 pin Plastic QFP 100 06 MB90341PFV MB90341SPFV MB90341CPFV MB90341CSPFV 100 pin Plastic LQFP 100 05 MB90342PF MB90342SPF MB90342CPF MB90342CSPF 100 pin Plastic QFP 100 06 MB90342PFV MB90342SPFV MB90342CPFV MB90342CSPFV 100 pin Plastic LQFP 100 05 Continued Continued Part number Package MB90340 Series Remarks MB90346APF MB90346ASPF MB90346CAPF MB90346CASPF
9. 8 XXXXXXXX Data register 15 8 bytes tg XXXXXXXX to to to 007 007CFFu 007 47 48 90340 Series a INTERRUPT FACTORS INTERRUPT VECTORS INTERRUPT CONTROL REGISTER Interrupt cause Reset DMA ch number Interrupt vector Address FFFFDCu Interrupt control register Address INT9 instruction FFFFD8 Exception 4 CAN 0 RX CAN 0 TX NS CAN 1 Input Capture 6 FFFFCCH FFFFC8H CAN 1 TX NS Input Capture 7 4 0000 0 0000 1 CAN 2 RX CO 2 TX NS FFFFBCH 0000 2 16 bit Reload Timer 0 8 16 bit Reload Timer 1 16 bit Reload Timer 2 16 bit Reload Timer 3 FFFFACH 0000B3H 0000 4 PPG 0 1 4 5 8 PPG 2 3 6 7 FFFFA4n 0000B5H 8 9 C D PPG A B E F Time Base Timer FFFF9CH FFFF98H External Interrupt 0 to 8 to 11 FFFF94n 0000 6 0000 7 Watch Timer FFFF90H External Interrupt 4 to 7 12to 15 0000B8H A D Converter FFFFS8H Timer 0 Timer 1 Input Capture 4 5 12C1 FFFF84u Output Compare 0 1 4 5 7 0000 9 0000 Input Capture 0 to FFFF78 Output Compare 2 3 6 7
10. FFFF74 0000 UART 0 RX FFFF7OH UART 0 TX FFFF6CH 0000 UART 1 RX UART 3 RX FFFF68H UART 1 TX UART 3 TX FFFF64 0000BDH Continued 90340 Series Continued Interrupt control register Number Address Number Address UART 2 RX UART 4 RX FFFF60u 0000 UART 2 TX UART 4 TX FFFF5Cu Flash Memory FFFF58u Interrupt vector Interrupt cause 0000BFu Delayed interrupt FFFF54H Y1 Usable Y2 Usable with 2 5 stop function N Unusable Notes The peripheral resources sharing the ICR register have the same interrupt level When two peripheral resources share the ICR register only one can use Extended Intelligent Service at a time When either of the two peripheral resources sharing the ICR register specifies Extended Intelligent I O Service the other one cannot use interrupts 49 50 90340 Series ELECTRICAL CHARACTERISTICS 1 Absolute Maximum Ratings Parameter Power supply voltage Vss 6 0 Vss AVss 0 V Vss 6 0 Vcc 1 Vss 6 0 AVcc gt AVRH AVcc gt AVRL AVRH 2 AVRL Input voltage Vss 6 0 2 Output voltage Vss 6 0 2 Maximum Clamp Current lcLAMP 44 0 4 Total Maximum Clamp Current Y lcrwe 4 L level maximum output current loL 15 8 L level
11. 007 75 007C76u 007 75 007 76 007 77 007 77 007 77 DLC register 10 DLC register 11 DLCR10 DLCR11 XXXXXXXX XXXXXXXX 007 78 007 78 007 78 007 79 007 79 007 79 DLC register 12 DLCR12 XXXXXXXX 007 7 007 7 007 7 007 7 007 7 007 7 DLC register 13 DLCR13 XXXXXXXX 007 7 007 7 007 7 007A7Du 007C7Du 007E7Du DLC register 14 DLCR14 XXXXXXXX 007 7 007 7 007 7 007 7 007 7 007 7 DLC register 15 DLCR15 XXXXXXXX 45 46 90340 Series List of Message Buffers DLC Registers and Data Registers 2 Address CANO 007 80 to 007 87 1 007 80 to 007 87 Register Abbreviation CAN2 007 80 to 007 87 Data register 0 8 bytes Access Initial Value XXXXXXXX to XXXXXXXX 007 88 to 007A8FH 007 90 to 007A97u 007 88 to 007C8Fu 007 90 to 007 97 007 88 to 007 8 007 90 to 007 97 Data register 1 8 bytes Data register 2 8 bytes XXXXXXXX to XXXXXXXX XXXXXXXX to XXXXXXXX 007 98 to 007A9Fu 007 98 to 007C9Fu 007 98 to 007 9 Data register 3 8 bytes XXXXXXXX to XXXXXXXX 007 to 007 7 007
12. 100 pin Plastic QFP 100 06 MB90346APFV MB90346ASPFV MB90346CAPFV MB90346CASPFV 100 pin Plastic LQFP 100 05 MB90347APF MB90347ASPF MB90347CAPF MB90347CASPF 100 pin Plastic QFP 100 06 MB90347APFV MB90347ASPFV MB90347CAPFV MB90347CASPFV 100 pin Plastic LQFP 100 5 MB90348PF 903485 90348 MB90348CSPF 100 pin Plastic QFP 100 06 MB90348PFV MB90348SPFV MB90348CPFV MB90348CSPFV 100 pin Plastic LQFP 100 05 MB90349PF 903495 90349 MB90349CSPF 100 pin Plastic QFP 100 06 MB90349PFV 903495 90349 MB90349CSPFV 100 pin Plastic LQFP 100 5 MB90V340 299 pin Ceramic PGA PGA 299C A01 For evaluation 73 74 90340 Series a PACKAGE DIMENSIONS 100 pin Plastic QFP 100 06 Note 1 These dimensions do not include resin protrusion Note 2 Pins width and pins thickness including plating thickness Note 3 Pins width do not include tie bar cutting remainder 2002 FUJITSU LI
13. Non linearity Deviation between a line across zero transition line 00 0000 0000 gt 00 0000 0001 error and full scale transition line 11 1111 1110 gt 11 1111 1111 and actual conversion characteristics Differential Deviation of input voltage which is required for changing output code by 1 LSB from an ideal linearity error value Total error Difference between an actual value and an ideal value A total error includes zero transition error full scale transition error and linear error Zero reading Input voltage which results in the minimum conversion value voltage Full scale Input voltage which results in the maximum conversion value reading voltage Total error 3FF 3FE Actual conversion 3 115 LSB characteristics 1 LSB x N 1 0 5 LSB VNT Actually measured value Digital output i Actual conversion 002 e i characteristics Ideal characteristics 0 5 LSB AVRL AVRH Analog input 1 LSB x 1 0 5 LSB Total error of digital output N LSB 1 LSB Ideal value eo Vor Ideal value AVRL 0 5 LSB V Vest Ideal value AVRH 1 5 LSB V Vnr A voltage at which digital output transitions from 1 to V Continued 68 90340 Series Continued Non linearity error Differential linearity error Ideal characteristics Actua
14. P36 RDY OUT6 P37 CLK OUT7 100 06 P40 X0A P41 X1A Vss P42 IN6 RX1 INT9R P43 IN7 TX1 P44 FRCKO P45 FRCK1 P46 P47 P50 AN8 SIN2 P51 AN9 SOT2 P52 AN10 SCK2 P53 AN11 TIN3 P54 AN12 TOT3 P55 AN13 P56 AN14 MB90F342 F343 F345 F346A F347A F349 341 342 346A 347A 348 349 X1A MB90F342S F343S F345S F346AS F347AS F349S 341 S 342S 346AS 347AS 348S 349S 40 41 P75 INT5 74 P73 INT3 P72 INT2 P71 INT1 P70 INTO Vss P67 AN7 PPGE F P66 AN6 PPGC D P65 AN5 PPGA B P64 AN4 PPG8 9 P63 AN3 PPG6 7 P62 AN2 PPG4 5 P61 AN1 PPG2 3 P60 ANO PPGO 1 AVss AVRL AVRH AVcc P57 AN15 Continued 10 90340 Series a P14 AD12 SCK3 Vcc Vss 1 P15 AD13 P16 AD14 P17 AD15 P20 A16 PPG9 8 P21 A17 PPGB A P22 A18 PPGD C P23 A19 PPGF E P24 A20 INO P25 A21 IN1 LQFP 100 12 13 14 15 16 17 18 19 20 21 39 38 37 36 35 34 33 32 31 30 29 28 27 26 22 23 24 25 P26 A22 IN2 P27 A23 IN3 P30 ALE IN4 P31 RD IN5 P32 WRL WR INT10R P33 WRH P34 HRQ OUT4 P35 HAK OUT5 EE o0 552z252 E 2 2 gt 9 T Ese ES 2 a o N vr 100 05 P43 1N7 TX1 P44 FRCKO P45 FRCK1 P46 P47 P50 AN8 SIN2 P51 AN9 SOT2 P52 AN10 SCK2 P53 AN11 TIN3 Continued TOP VIEW FE z EER r Bale Ss E E 5
15. To reduce unnecessary radiation prevent malfunctioning of the strobe signal due to the rise of ground level and observe the standard for total output current be sure to connect the Vcc and Vss pins to the power supply and ground externally Connect Vcc and Vss to the device from the current supply source at a low impedance As a measure against power supply noise connect a capacitor of about 0 1 uF as a bypass capacitor between Vcc and Vss in the vicinity of Vcc and Vss pins of the device oVss Vcc Vss Vss MB90340 cc Series Vss Vss Vcc 7 Pull up down resistors The MB90340 Series does not support internal pull up down resistors Port 0 to Port 3 built in pull up resistors Use external components where needed Crystal Oscillator Circuit Noises around X0 or X1 pins may be possible causes of abnormal operations Make sure to provide bypass capacitors via shortest distance from X1 pins crystal oscillator or ceramic resonator and ground lines and make sure to the utmost effort that lines of oscillation circuit not cross the lines of other circuits It is highly recommended to provide a printed circuit board art work surrounding XO and X1 pins with a ground area for stabilizing the operation Turning on Sequence of Power Supply to A D Conver
16. 9 9 ZEEOR 0 00 E 5 5 SxSEFEFEE OOOO K ESSMESESE ALEX 2222 2 202665 lt 000044 226509206622 STON Gio x43 OQ G o o rx dQG 0x Ow HOR co r 8 lt f coc c 0 gt gt gt 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 P01 ADO1 INT9 6 50 MD1 P02 ADO2 INT10 49 MD2 P03 AD03 INT11 48 P75 INT5 P04 AD04 INT12 47 P74 INT4 P05 ADO5 INT13 46 P73 INT3 P06 ADO6 INT14 45 P72 INT2 P07 ADO7 INT15 44 P71 INT1 P10 AD08 TIN1 43 P70 INTO P11 AD09 TOT1 42 Vss P12 AD10 SIN3 NT11R 41 P67 AN7 PPGE F P13 AD11 SOT3 40 P66 AN6 PPGC D P65 AN5 PPGA B P64 AN4 PPG8 9 P63 AN3 PPG6 7 P62 AN2 PPG4 5 P61 AN1 PPG2 3 P60 ANO PPGO 1 AVss AVRL AVRH AVcc P57 AN15 P56 AN14 P55 AN13 P54 AN12 TOT3 1 MB90F342 F343 F345 F346A F347A F349 341 342 346A 347A 348 349 X1A MB90F3425 F3435 F3455 F346AS F347AS5 F3495 3415 3425 346AS 347AS 3483 349S P40 P41 90340 Series a MB90F342C S MB90F343C S MB90F345C S 90 346 S MB90F347CA S MB90F349C S MB90341C S MB90342C S MB90346CA S MB90347CA S MB90348C S MB90349C S cc ES EE 522 Hq 5 roo p 2222 STETS ZEFORZZ 2 2272 SEEQaEE
17. AD13 92 34 P60 ANO PPGO 1 P16 AD14 93 33 AVss P17 AD15 94 32 AVRL P20 A16 PPG9 8 95 31 AVRH P21 A17 PPGB A 96 30 Avec P22 A18 PPGD C 97 29 P57 AN15 P23 A19 PPGF E 98 28 P56 AN14 P24 A20 INO 99 o 27 P55 AN13 P25 A21 IN1 100 26 P54 AN12 TOT3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 i0 E T 5 Oo D x x TD THT ANNOY 22226 552 95 5 522552 seere Sas i 55 5 852 25 59524645522 5 iol 6299 T 2 2 5 COPS z a a 3 ic a a a FPT 100P MO5 MB90F342C F343C F345C F346CA F347CA F349C 341C 342C 346CA 347CA 348C 349C X1A MB90F342CS F343CS F345CS F346CAS F347CAS F349CS 341 CS 342CS 346CAS 347CAS 348CS 349CS P40 P41 12 90340 Series DESCRIPTION LQFP100 QFP100 Pin name Circuit type Function Oscillation output Oscillation input RST Reset input 75 to 82 77 to 84 to P07 ADOO to ADO7 INT8 to INT15 General purpose The register can be set to select whether to use a pull up resistor This function is enabled in single chip mode pins for 8 lower bits of the external address data bus This function is enabled when the external bus is enabled External interrupt request input pins for INT8 to INT 15 P10 ADO08 TIN1 P11
18. Compare Control Status 2 Output Compare Control Status 3 Output Compare 2 3 0000XX00 0 00000 Output Compare Control Status 4 Output Compare Control Status 5 Output Compare 4 5 0000XX00 0XX00000 Output Compare Control Status 6 Output Compare Control Status 7 Output Compare 6 7 0000XX00 0XX00000 Continued Address Register Timer Control Status 0 Abbrevia tion TMCSRO Access Timer Control Status 0 TMCSRO 90340 Series Resource name 16 bit Reload Timer 0 Initial value 00000000 XXXX0000 Timer Control Status 1 TMCSR1 Timer Control Status 1 Timer Control Status 2 TMCSR1 TMCSR2 Timer Control Status 2 TMCSR2 16 bit Reload Timer 1 16 bit Reload Timer 2 00000000 XXXX0000 00000000 XXXX0000 Timer Control Status 3 TMCSR3 Timer Control Status 3 TMCSR3 16 bit Reload Timer 3 00000000 XXXX0000 A D Control Status O ADCSO A D Control Status 1 A D Data 0 ADCS1 ADCRO A D Data 1 ADCR1 ADC Setting 0 ADSRO ADC Setting 1 ADSR1 A D Converter 000XXXXO0 0000000X 00000000 XXXXXX00 00000000 00000000 Reserved 70 to 8 ROM Mirror ROMM ROM Mirror Reserved for CAN Interface 0 1 Refer to CAN CONTROLLERS XXXXXXX1 90H to 9 Reserved 9 DMA Descriptor Channel Select DCSR R W 9CH
19. Condition Internal clock operation output pins are 80 pF 1 TTL Remarks Serial clock H pulse width SCKO to SCK4 Serial clock L pulse width SCKO to SCK4 SCK SOT delay time SCKO to SCK4 SOTO to SOT4 Valid SIN gt SCKT SCKO to SCK4 SINO to SIN4 SCK T Valid SIN hold time SCKO to SCK4 SINO to SIN4 External clock operation output pins are 80 pF 1 TTL Refer to 1 Clock timing rating for tce internal operating clock cycle time Notes AC characteristic in CLK synchronized mode is load capacity value of pins when testing e tce is the machine cycle Unit ns SCK SOT SIN Internal Shift Clock Mode 90340 Series SCK SOT SIN External Shift Clock Mode 9 Trigger Input Timing Parameter Input pulse width INTO to INT15 INTOR to INT15R ADTG INTO to INT15 INTOR to INT15R ADTG Ta 40 to 105 C Vcc 4 5 V to 5 5 V Vss 0 V Condition 65 90340 Series 10 Timer Related Resource Input Timing Ta 40 to 105 C 4 5 V to 5 5 V Vss 0 V o Value Symbol Condition Unit Min Max tnwu TINO to TINS Input pulse width 4 tcp ns triw INO to IN7 TINO to TIN3 INO to IN7 11 Tim
20. DMA Status L DSRL R W 9 DMA Status DSRH R W DMA 00000000 00000000 00000000 9 ROM Correction Control Status 0 Delayed Interrupt release PACSRO DIRR ROM Correction O Delayed Interrupt 00000000 XXXXXXXO Low power Mode Control LPMCR Low Power Controller 00011000 Alu Clock Selection CKSCR Low Power Controller 11111100 2 ASH Reserved amp DMA Stop Status DSSR DMA 00000000 5 Automatic ready function select reg ARSR External address output control reg HACR 7 Bus control signal selection register ECSR External Memory Access 0011XX00 00000000 0000000X A8u Watchdog Control WDTC Watchdog Timer XXXXX111 9 Time Base Timer Control TBTC Time Base Timer 1 00100 Continued 33 34 90340 Series Address Register Watch Timer Control register Abbrevia tion WTC Access R R W Resource name Watch Timer Initial value 1 001000 Reserved DMA Enable L DERL R W DMA Enable H Flash Control Status FlashDevices only Otherwise reserved DERH FMCS R W R R W Flash Memory 00000000 00000000 000X0000 Reserved Interrupt control register 00 ICROO W R W Interrupt control register 01 ICRO1 W R W Interrupt control register 02 IC
21. PRLH1 R W Resource name 16 bit Programable Pulse Generator 0 1 Initial value XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 7904 Reload L PRLL2 7905 Reload PRLH2 R W 7906 Reload L PRLL3 R W 7907 Reload PRLH3 R W 16 bit Programable Pulse Generator 2 3 XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 7908 Reload L PRLL4 7909 Reload PRLH4 R W 790 Reload L PRLL5 R W 790 Reload PRLH5 R W 16 bit Programable Pulse Generator 4 5 XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 790 Reload L PRLL6 790Du Reload H PRLH6 R W 790 Reload L PRLL7 R W 790 Reload H PRLH7 R W 16 bit Programable Pulse Generator 6 7 XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 7910H Reload L PRLL8 7911 Reload PRLH8 R W 7912H Reload L PRLL9 R W 7913 Reload PRLH9 R W 16 bit Programable Pulse Generator 8 9 XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 7914 Reload L PRLLA 7915u Reload H PRLHA R W 7916 Reload L PRLLB 79174 Reload H PRLHB R W 16 bit Programable Pulse Generator A B XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 79184 Reload L PRLLC 79194 Reload H PRLHC R W 791 Reload L PRLLD R W 791 Reload PRLHD
22. R W 16 bit Programable Pulse Generator C D XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 791Cu Reload L PRLLE 791Du Reload H PRLHE R W 791 Reload L PRLLF R W 791 Reload PRLHF R W 16 bit Programable Pulse Generator E F XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 7920u Input Capture 0 IPCPO 7921H Input Capture 0 IPCPO 7922H Input Capture 1 IPCP1 7923H Input Capture 1 IPCP1 Input Capture 0 1 XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX Continued Address 7924 Register Input Capture 2 Abbrevia tion IPCP2 Access D 79254 Input Capture 2 IPCP2 79264 Input Capture 3 IPCP3 79274 Input Capture 3 IPCP3 MB90340 Series Resource name Input Capture 2 3 Initial value XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 79284 Input Capture 4 IPCP4 79294 Input Capture 4 IPCP4 792 Input Capture 5 IPCP5 792 Input Capture 5 IPCP5 Input Capture 4 5 XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 792 Input Capture 6 IPCP6 792Du Input Capture 6 IPCP6 792 Input Capture 7 IPCP7 792 Input Capture 7 IPCP7 D Y Input Capture 6 7 XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 7930 Output Compare 0 OCCPO D 79314 Output Compare 0 OCCPO 7
23. Reg 000000XX Extended Status Control Register ESCR1 00000100 Baud Rate Register 0 BGR10 00000000 Baud Rate Register 1 BGR11 00000000 PPG 0 operation mode control register PPGCO W R W 16 bit Programable 0X000XX1 PPG 1 operation mode control register PPGC1 W R W Pulse 0X000001 PPG 0 and PPG 1 clock select register 1 R W Generator 0 1 000000X0 Reserved PPG 2 operation mode control register PPGC2 W R W 16 bit Programable 0X000XX1 PPG 3 operation mode control register PPGC3 W R W Pulse 0X000001 PPG 2 and PPG 3 clock select register PPG23 R W Generator 2 3 000000 0 Reserved PPG 4 operation mode control register PPGC4 W R W 16 bit Programable 0X000XX1 PPG 5 operation mode control register PPGC5 W R W Pulse 0X000001 PPG 4 and PPG 5 clock selectregister PPG45 R W Generator 4 5 000000 0 ROM Correction Control Status 1 PACSR1 R W ROM Correction 1 00000000 PPG 6 operation mode control register PPGC6 W R W 0X000XX1 16 bit Programable PPG 7 operation mode control register PPGC7 W R W Pulse 0X000001 PPG 6 and PPG 7 clock select register PPG67 R W Generator 6 7 000000X0 Reserved Continued 31 90340 Series a 32 Address Register PPG 8 operation mode control register Abbrevia tion Access PPGC8 W R W PPG 9 operation mode control register PPGC9 W R W PPG 8 and PPG 9 clock select register
24. XXXXXXXX Port 0 direction register Port 0 00000000 Port 1 direction register Port 2 direction register Port 1 00000000 00000000 Port 3 direction register 00000000 Port 4 direction register 00000000 Port 5 direction register 00000000 Port 6 direction register 00000000 Port 7 direction register Port 8 direction register DDR8 00000000 00000000 Port 9 direction register DDR9 00000000 Port A direction register DDRA 00000100 Reserved Port 0 Pullup control register PUCRO 00000000 Port 1 Pullup control register PUCR1 00000000 Port 2 Pullup control register PUCR2 00000000 Port 3 Pullup control register PUCR3 00000000 Continued 90340 Series a Abbrevia tion 20H Serial Mode Register SMRO W R W 00000000 Serial Control Register SCRO W R W 00000000 Reception Transmission Data Register oo 00000000 Serial Status Register 8880 00001000 Address Register Access Resource name Initial value Extended Communication Control Reg ECCRO 000000XX Extended Status Control Register ESCRO 00000100 Baud Rate Register 0 BGROO 00000000 Baud Rate Register 1 BGRO1 00000000 Serial Mode Register SMR1 00000000 Serial Control Register SCR1 00000000 Reception Transmission Data Register 2 00000000 Serial Status Register SSR1 00001000 Extended Communication Control
25. average output current loLav L level maximum overall output current L level average overall output current 8 H level maximum output current lou H level average output current H level maximum overall output current 8 H level average overall output current Xlouav Power consumption Po MB90F347 Operating temperature Ta Storage temperature Continued 90340 Series Continued 1 Set AVcc and Vcc to the same voltage Make sure that AVcc does not exceed Vcc and that the voltage at the analog inputs does not exceed AVcc when the power is switched on 2 Vi and Vo should not exceed Vcc 0 3 V Vi should not exceed the specified ratings However if the maximun current to from an input is limited by some means with external components the rating supercedes the Vi rating 3 Applicable to pins POO to P07 P10 to P17 P20 to P27 P30 to P37 P40 to P47 P50 to P57 P60 to P67 P70 to P77 P80 to P87 P90 to P97 PAO to PA1 4 e Applicable to pins POO to P07 P10 to P17 P20 to P27 P30 to P37 P40 to P47 P50 to P57 P60 to P67 P70 to P77 P80 to P87 P90 to P97 PAO to PA1 Use within recommended operating conditions Use at DC voltage current The B signal should always be applied a limiting resistance placed between th
26. export under the Foreign Exchange and Foreign Trade Law of Japan the prior authorization by Japanese government will be required for export of those products from Japan FO307 O FUJITSU LIMITED Printed in Japan
27. input pins for sub clock devices without S suffix P42 ING RX1 INT9R General purpose l O Data sample input pin for input capture ICU6 RX input pin for CAN1 Interface MB90F342 F343 F345 341 342 only Sub external interrupt request input pin for INT10 P43 TX1 General purpose l O Data sample input pin for input capture ICU7 TX Output pin for MB90F342 F343 F345 341 342 only P44 SDAO FRCKO General purpose l O Serial data I O pin for 12C 0 devices with C suffix Input for the 16 bit Timer 0 P45 SCLO FRCK1 General purpose l O Serial clock I O pin for 2 0 devices with C suffix Input for the 16 bit Timer 1 P46 SDA1 General purpose l O Serial data I O pin for I2C 1 devices with C suffix General purpose l O Serial clock I O pin for 12C 1 devices with C suffix General purpose I O Analog input pin for the A D converter Serial data input pin for UART2 General purpose I O Analog input pin for the A D converter Serial data output pin for UART2 General purpose I O Analog input pin for the A D converter Clock I O pin for UART2 General purpose I O Analog input pin for the A D converter Event input pin for the reload timers 3 Continued 90340 Series Pin No LQFP1007 QFP100 Pin
28. register 8 007 42 007C424 007 42 XXXXXXXX 007A434 007 43 007E434 XXXXXXXX 007 44 007 44 007 44 XXXXXXXX 007 45 007 45 007 45 XXXXXXXX ID register 9 007A464 007 46 007E464 XXXXXXXX 007A474 007C474 007 47 XXXXXXXX 007 48 007 48 007 48 XXXXXXXX 007 49 007C494 007 49 XXXXXXXX ID register 10 007A4An 007C4Au 007E4A4 XXXXXXXX 007 4 007 4 007 4 XXXXXXXX 007 4 007 4 007E4C XXXXXXXX 007 40 007 40 007 40 XXXXXXXX ID register 11 007 4 007 4 007E4En XXXXXXXX 007 4 007 4 007 4 XXXXXXXX 007 50 007 50 007 50 XXXXXXXX 007 51 007 51 007 1 XXXXXXXX ID register 12 007A524 007C524 007 52 XXXXXXXX 007A534 007C534 007 XXXXXXXX 007A544 007 54 007E54u XXXXXXXX 007A554 007 55 007 55 XXXXXXXX ID register 13 007A564 007 56 007E56x XXXXXXXX 007 57 007 57 007 57 XXXXXXXX 007 58 007 58 007E58x XXXXXXXX 007A594 007C594 007 59 XXXXXXXX ID register 14 007 007 5 007 5 XXXXXXXX 007 5 007 5 007 XXXXXXXX 007 007 5 007 5 XXXXXXXX 007 5 007 5 007 XXXXXXXX ID register 15 007 007 5 007 XXXXXXXX 007A5FH 007 5 007 5 XXXXXXXX Register Abbreviation Access Initial Value
29. 00 7989 798 798 clock control register ICCR1 Interface 1 00011111 798 to 79C1u 79 2 Clock Modulator Control Register CMCR R R W Clock Modulator 0001X000 79C3u to 790 Address Register Access Resource name Initial value Reserved Reserved Reserved Reserved Reserved Continued 39 40 90340 Series Continued Address 79 0 Abbrevia tion PADRO Register ROM Correction Address 0 Access Resource name R W 79 1 ROM Correction Address 0 PADRO R W 79 2 ROM Correction Address 0 PADRO R W 79 ROM Correction Address 1 PADR1 R W 79 4 ROM Correction Address 1 PADR1 R W ROM Correction 0 79E5H ROM Correction Address 1 PADR1 R W 79E6H ROM Correction Address 2 PADR2 R W 79 7 ROM Correction Address 2 PADR2 R W 79 8 PADR2 ROM Correction Address 2 R W Initial value XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 79 9 to 79EFH Reserved 79 ROM Correction Address 3 PADR3 79 1 ROM Correction Address 3 PADR3 79 2 ROM Correction Address 3 PADR3 79 ROM Correction Address 4 PADR4 79 4 ROM Corr
30. 007Du 00007 00008Du 00008 0000EDh 00007 00008 0000 0000EFH Receive overrun register Reception interrupt enable register 00000000 00000000 00000000 00000000 41 42 90340 Series Address 007 00 1 007D00u 007 00 007 01 007001 007 01 Register Control status register List of Control Registers 2 Abbreviation Access Initial Value OXXXXOX1 00XXX000 007B02u 007D02u 007F02u 007 03 007 04 007003 007004 007 03 007 04 007 05 007005 007 05 Last event indicator register Receive transmit error counter 000X0000 XXXXXXXX 00000000 00000000 007 06 007D06u 007 06 007 07 007007 007 07 Bit timing register 11111111 1111111 007 08 007008 007 08 007 09 007 007D09u 00700 007 09 007 007 00700 007 IDE register Transmit RTR register XXXXXXXX XXXXXXXX 00000000 00000000 007 0 00700 007 007B0D 007D0Du 007FODH Remote frame receive waiting register XXXXXXXX XXXXXXXX 007BOEu 007DOEH 007 007BOFH 007DOFu 007FOFH Transmit interrupt enable register 00000000 00000000 007 10 007 11 007010 007011 007 10 007 11
31. 2 007 2 007 2 007 2 ID register 2 XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 007 2 007 2 007 2 007A2Du 007C2Du 007E2Du 007 2 007 2 007 2 007C2Fu 007 2 007 2 ID register 3 XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 007 0 007 30 007 0 007 1 007 1 007 1 007 2 007 2 007 2 007 007C33H 007 ID register 4 XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 007 4 007A35H 007C34u 007C35H 007 4 007 5 007 007C36H 007 007 7 007C37u 007 7 ID register 5 XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 007 8 007C38H 007 8 007 9 007 39 007 9 007 007 007 007 007 007 ID register 6 XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 007A3Ch 007 007 007 007 007E3Dh 007 007 007 007 007C3Fu 007 ID register 7 XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 43 90340 Series a List of Message Buffers ID Registers 2 Address CAN1 007 40 007 40 007 40 XXXXXXXX 007A41u 007 41 007 41 XXXXXXXX ID
32. 2003 FUJITSU LIMITED 1000075 4 6 Dimensions in mm inches Note The values in parentheses are reference values 75 90340 Series a FUJITSU LIMITED Rights Reserved The contents of this document are subject to change without notice Customers are advised to consult with FUJITSU sales representatives before ordering The information such as descriptions of function and application circuit examples in this document are presented solely for the purpose of reference to show examples of operations and uses of Fujitsu semiconductor device Fujitsu does not warrant proper operation of the device with respect to use based on such information When you develop equipment incorporating the device based on such information you must assume any responsibility arising out of such use of the information Fujitsu assumes no liability for any damages whatsoever arising out of the use of the information Any information in this document including descriptions of function and schematic diagrams shall not be construed as license of the use or exercise of any intellectual property right such as patent right or copyright or any other right of Fujitsu or any third party or does Fujitsu warrant non infringement of any third party s intellectual property right or other right by using such information Fujitsu assumes no liability for any infringement of the intellectual property rights or other rights of third parties which w
33. 48 7949 Register Timer 0 Reload 0 Abbrevia tion TMRO TMRLRO Access R W Resource name 16 bit Reload Timer 0 Initial value XXXXXXXX XXXXXXXX 794 794 Timer 1 Reload 1 TMR1 R W 16 bit Reload Timer 1 XXXXXXXX XXXXXXXX 794 794Du Timer 2 Reload 2 TMR2 TMRLR2 R W 16 bit Reload Timer 2 XXXXXXXX XXXXXXXX 794 794 Timer 3 Reload 3 TMR3 TMRLR3 R W 16 bit Reload Timer 3 XXXXXXXX XXXXXXXX 7950 Serial Mode Register SMR3 7951 Serial Control Register SCR3 7952 Reception Transmission Data Register RDR3 TDR3 7953 Serial Status Register SSR3 7954 Extended Communication Control Reg ECCR3 7955H Extended Status Control Register ESCR3 7956 Baud Rate Register 0 BGR30 7957 Baud Rate Register 1 BGR31 00000000 00000000 00000000 00001000 000000XX 00000100 00000000 00000000 7958 Serial Mode Register SMR4 7959 Serial Control Register SCR4 795 Reception Transmission Data Register RDR4 TDR4 795 Serial Status Register SSR4 795 Extended Communication Control Reg ECCR4 RW R W 7950 Extended Status Control Register ESCR4 R W 795En Baud Rate Register 0 BGR40 R W 795Fu Baud Rate Register 1 BGR41 R
34. 932 Output Compare 1 7933 Output Compare 1 1 D Output Compare 0 1 XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 7934 Output Compare 2 OCCP2 7935 Output Compare 2 OCCP2 D 7936 Output Compare 3 OCCP3 7937 Output Compare 3 OCCP3 Output Compare 2 3 XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 7938 Output Compare 4 OCCP4 D 7939 Output Compare 4 OCCP4 793An Output Compare 5 OCCP5 D 793 Output Compare 5 OCCP5 D Output Compare 4 5 XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 793 Output Compare 6 OCCP6 793Du Output Compare 6 OCCP6 D 793En Output Compare 7 OCCP7 793 Output Compare 7 OCCP7 Output Compare 6 7 XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 7940 Timer Data 0 TCDTO 7941 Timer Data 0 TCDTO 7942 Timer Control 0 510 D 7943 Timer Control 0 TCCSHO D Timer 0 00000000 00000000 00000000 OXXXXXXX 7944 Timer Data 1 TCDT1 7945u Timer Data 1 TCDT1 D 7946 Timer Control 1 TCCSL1 7947 Timer Control 1 TCCSH1 1 00000000 00000000 00000000 OXXXXXXX Continued 37 38 90340 Series Address 79
35. ADTG INT12R P77 AN23 INT7 P76 AN22 INT6 RST MDO MD1 MD2 80 79 78 77 76 75 74 73 72 71 81 82 83 84 85 86 87 88 89 90 91 92 93 94 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 QFP 100 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 N2 N3 N4 N5 P24 A20 P25 A21 P26 A22 P27 A23 P30 ALE 1 MB90V340 X1A 90 34065 P40 P41 P31 RD P32 WRL WR RX2 INT10R P33 WRH TX2 P34 HRQ OUT4 P35 HAK OUT5 P36 RDY OUT6 P37 CLK OUT7 P40 X0A P41 X1A Vcc Vss P42 IN6 RX1 INT9R P43 IN7 TX1 P44 SDAO FRCKO P45 SCLO FRCK1 100 06 P46 SDA1 P47 SCL1 P50 AN8 SIN2 P51 AN9 SOT2 P52 AN10 SCK2 P53 AN 11 TINS P54 AN12 TOT3 P55 AN13 P56 AN14 DA00 P75 AN21 INT5 P74 AN20 INT4 P73 AN19 INT3 P72 AN18 INT2 P71 AN17 INT1 P70 AN16 INTO Vss P67 AN7 PPGE F P66 AN6 PPGC D P65 AN5 PPGA B P64 AN4 PPG8 9 P63 AN3 PPG6 7 P62 AN2 PPG4 5 P61 AN1 PPG2 3 P60 ANO PPGO 1 AVss AVRL AVRH AVcc P57 AN15 DA01 Continued 90340 Series a Continued TOP VIEW TE E 5 E MANTO 2 STETS 2 FEOGZ2Z 5 555 5026562525 5 QV0V0V0VVEEXA Oo 0L0T aNxnr gt 0O90O OLDTOQN E 8 lt lt DO
36. AO Interface SCL1 SCLO 2ch External Interrupt DMAC Clock 1 Only for devices without S Suffix Monitor 2 Only for devices with C Suffix 3 Supported by MB90341 C S 342 C S F342 C S F343 C S F345 C S only FRCKO IN7 to INO OUT7 to OUTO FRCK1 RX1 8 TXO TX1 3 TIN3 to TINO TOT3 to TOTO AD15 to ADOO A23 to A16 ALE INT15 to INT8 INT15R to INT8R INT to INTO CKOT 28 90340 Series MEMORY 90 340 ROM FF bank 0000 ROM FE bank FDFFFFH ROM FD bank 0000 FCFFFFH 0000 FBFFFFH ROM FC bank ROM FB bank FBO000H FAFFFFH 0000 FOFFFFH ROM FA bank ROM F9 bank FSFFFFH ROM F8 bank F80000H OOFFFFH ROM 008000H Image of FF bank 007FFFH Peripheral 007900H 0078FFH RAM 30 K 000100H 0000 000000 gt lt No access Peripheral MB90F345 C S CS FFFFFFH ROM FF bank FF0000H FEFFFFH ROM FE bank 0000 FDFFFFH ROM FD bank FD0000H FCFFFFH ROM FC bank 0000 FBFFFFH ROM FB bank 0000 FAFFFFH ROM FA bank 0000 9 ROM F9 bank F90000H SFFFFH bank F80000H OOFFFFH ROM Image of FF bank 007FFFH Peripheral 007900H 008000H 0050FFH 000100H AAA 0990EF H Per
37. GF to PPGO SDA1 SDAO SCL1 SCLO 8 16 bit Clock Controller RAM 30 K Prescaler 5 ch UART 5 ch 10 bit ADC PPG 16 ch 12C Interface 2 ch Only for MB90V340 without 5 Suffix 16LX 16 lt Timer 0 Input Capture 8 ch Output Compare 8 ch Timer 1 Controller 3 ch 16 bit Reload Timer 4 ch External Bus Interface External Interrupt Clock Monitor to INO OUT7 to 0970 RX2 to TX2 to TXO TIN3 to TINO TOT3 to TOTO AD15 to A23 to A16 48 INT15 to INT8 INT15R to INT8R 4 7 to INTO CKOT 90340 Series MB90F342 C S MB90F343 C S MB90F345 C S MB90F346A S MB90F346CA S MB90F347A S MB90F347CA S MB90F349 C S MB90341 C S MB90342 C S MB90346A S MB90F346CA S MB90347A S MB90347CA S MB90348 C S MB90349 C S X0 X1 1 XOA X1A Clock 16LX RST Controller CPU RAM 2 6 K 16 K IO Timer 0 20K Input Capture ROM Flash 8 ch 64 K 128 K 256 K 384 K Output 512K Compare 8ch ae Timer 1 SOT3 to SOTO CAN ART SCK3 to SCKO y ch Controller SIN3 to SINO 1 ch 2 ch 3 16 bit Reload AVSS Timer 4 ch AN15 to ANO 10 bit ADC AN23 to 16 16 24 ch AVRH AVRL a ADTG a e External 2 Interface 8 16 bit PPG 16 ch PPGF to PPGO SDA1 SD
38. Hysteresis inputs Upo Automotive inputs Standby control for input shutdown Analog input Analog output CMOS level output lo 4 mA 4 D A analg output CMOS hysteresis inputs With the standby time input shutdown function Automotive input With the standby time in put shutdown function A D analog input p I Power supply input protection circuit A D converter reference voltage power supply input pin with the protection circuit Flash devices do not have a protection circuit against Vcc for pin AVRH Continued 21 22 90340 Series A Continued Circuit CMOS inputs Automotive inputs Standby control for input shutdown Remarks CMOS level output lo 4 mA lon 4 mA CMOS inputs With the standby time input shutdown function Automotive input With the standby time input shutdown function pull up control Nout CMOS inputs Automotive inputs lso TTL input Standby control for input shutdown CMOS inputs Automotive inputs Standby control for input shutdown Analog input CMOS level output lo 4 mA lon 4 mA CMOS inputs With the standby
39. MB90F346CA S MB90F347A S MB90F347CA S MB90F349 C S MB90341 C S 90342 5 MB90346A S MB90346CA S MB90347A S MB90347CA S 90348 5 MB90349 C S F2MC 16LX CPU MB90V340 S System clock On chip PLL clock multiplier x1 x2 x3 x4 x6 1 2 when PLL stops Minimum instruction execution time 42 ns 4 MHz osc PLL x 6 Boot block Flash memory 512 Kbytes MB90F345 C 384 Kbytes MB90F343 C 256 Kbytes MB90F342 C MB90349 C S MB90F347A S MB90F347CA S MB90341 C S MB90348 C S MB90347A S MB90347CA S MB90F346A S MB90F346CA S MB90346A S MB90346CA 5 S S S MB90F349 C S MB90342 C S External 128 Kbytes 64 Kbytes 20 Kbytes 16 Kbytes MB90F343 C S MB90F345 C S MB90F342 C S MB90F349 C S MB90341 C S MB90342 C S MB90348 C S MB90349 C S MB90F347A S MB90F347CA S MB90347A S MB90347CA MB90F346A MB90346CA 6 Kbytes 30 Kbytes 2 Kbytes S S S MB90F346CA S MB90346A S S Emulator specific power supply Yes Technology 0 35 um CMOS with on chip voltage regulator for internal power supply 0 35 um CMOS with on chip voltage regulator for internal power supply Flash memory with On chip charge pump for programming voltage Operating voltage range 3 5 V 5 5 V at normal operating not using A D converter 4 0 V 5 5 V atusing A D convert
40. MITED F100008S c 5 5 2 23 90 0 40 941 016 20 00 0 20 787 008 DAA EE 1 ET CEI I i Fe 0 10 004 cro E 17 90 0 40 E C C 705 016 Ey E 14 00 0 20 EL 551 008 INDEX gt E Details of A part 171 EE ON 3 095 102354010 1182008 CET OM 0 65 026 0 32 0 05 0 17 0 06 f 9 0 13 005 007 002 A 0 80 0 20 0 25 0 20 031 008 010 008 0 88 0 15 Stand off L 035 006 Dimensions in mm inches Note The values in parentheses are reference values Continued 90340 Series Continued 100 pin Plastic LQFP 100 05 Note 1 These dimensions do not include resin protrusion Note 2 Pins width and pins thickness include plating thickness Note 3 Pins width do not include tie bar cutting remainder 16 00 0 20 630 008 SQ P 14 00 0 10 551 004 5 HAAR HAHA AR AH AE ES 0 08 003 mm Details of part 0 20 008 INDEX Mounting height 0 00 10 EI Y c Ee 2 DOE M 0200087 a 0 604015 0 50 020 2040 05 ieee 024 006 MOERORE gt 0 08 003 Ea 1
41. PPG89 R W Resource name 16 bit Programable Pulse Generator 8 9 Initial value 0X000XX1 0X000001 000000X0 PPG A operation mode control register Reserved PPGCA W R W PPG B operation mode control register PPGCB W R W PPG A and PPG B clock select register PPGAB R W 16 bit Programable Pulse Generator A B 0X000XX1 0X000001 000000X0 Reserved PPG C operation mode control register PPGCC W R W PPG D operation mode control register PPG C and PPG D clock select register PPGCD W R W PPGCD R W 16 bit Programable Pulse Generator C D 0X000XX1 0X000001 000000X0 Reserved PPG E operation mode control register PPGCE W R W PPG F operation mode control register PPGCF W R W PPG E and PPG clock select register PPGEF R W 16 bit Programable Pulse Generator E F 0X000XX1 0X000001 000000X0 Input Capture Control Status 0 1 Reserved Input Capture Edge 0 1 Input Capture 0 1 00000000 XXXOXOXX Input Capture Control Status 2 3 Input Capture Edge 2 3 Input Capture 2 3 00000000 XXXXXXXX Input Capture Control Status 4 5 Input Capture Edge 4 5 Input Capture Control Status 6 7 Input Capture Edge 6 7 Input Capture 4 5 Input Capture 6 7 00000000 XXXXXXXX 00000000 XXX000XX Output Compare Control Status 0 Output Compare Control Status 1 Output Compare 0 1 0000XX00 0 00000 Output
42. R Data hold time 15 WR WA T gt Address valid time Bes 10 516 tor 2 10 WR ALE f time ALE ice 2 15 WR f time R CLK 2 15 TWLCH CLK 24V tWHLH ALE 24V tavwe gt lt TWLWH WR WRL WRH 0 8 V A23 to A16 AD15 to ADOO Write data 61 90340 Series 6 Ready Input Timing Ta 40 C to 85 C Vcc 4 5 V to 5 5 Vss 0 0 V Machine Clock lt 16 MHz Sym Test Rated Value RDY setup time tryHs RDY 45 RDY hold time RDY 0 Note If the RDY setup time is insufficient use the auto ready function CLK ALE RDY When WAIT is not used RDY When WAIT is used VIL 62 90340 Series a 7 Hold Timing Ta 40 C to 85 Vcc 4 5 to 5 5 Vss 0 0 V Machine Clock lt 16 MHz Parameter Condition Remarks Pin floating HAK 4 time HAK f time Pin valid time Note There is more than 1 cycle from when HRQ reads in until the HAK is changed HAK Each pin 63 90340 Series 8 UARTO 1 2 3 4 Parameter Serial clock cycle time Ta 40 C to 105 C Vcc 4 5 to 5 5 Vss 0 SCKO to SCK4 SCK SOT delay time SCKO to SCK4 SOTO to SOT4 64 Valid SIN gt SCKT f gt Valid SIN hold time SCKO to SINO to SIN4 SCKO to SCK4 SINO to SIN4
43. RO2 W R W Interrupt control register 03 Interrupt control register 04 ICRO3 ICRO4 W R W W R W Interrupt control register 05 5 W R W Interrupt control register 06 ICRO6 W R W Interrupt control register 07 ICRO7 W R W Interrupt control register 08 ICRO8 W R W Interrupt control register 09 Interrupt control register 10 ICRO9 ICR10 W R W W R W Interrupt control register 11 ICR11 W R W Interrupt control register 12 ICR12 W R W Interrupt control register 13 ICR13 W R W Interrupt control register 14 ICR14 W R W Interrupt control register 15 D A Converter data O ICR15 DATO W R W D A Converter data 1 DAT1 D A Control 0 DACRO D A Control 1 Interrupt controller D A Converter 00000111 00000111 00000111 00000111 00000111 00000111 00000111 00000111 00000111 00000111 00000111 00000111 00000111 00000111 00000111 00000111 XXXXXXXX XXXXXXXX XXXXXXXO XXXXXXXO Reserved External Interrupt Enable 0 ENIRO External Interrupt Request 0 External Interrupt Level 0 ELVRO External Interrupt Level 0 ELVRO External Interrupt 0 00000000 XXXXXXXX 00000000 00000000 Continued External Interrupt Enable 1 Abbrevia tion ENIR1 Access R W External Interrupt Request 1 EIRR1 R W Ext
44. S Sa Sof mnur or 63 oooo0 SCFEFE OOOO XETYESESAA 5602656626022 2 lt lt lt lt ora SASS SNS AFANS SH GHIHAHKH SRS 5 lt 00090000 9 9o o o d a aadcataanohoaoanar gt saonaonaaaoaonaaltssS 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 P04 ADO4 INT12 50 P75 AN21 INT5 PO5 ADOS INT13 49 P74 AN20 INT4 PO6 ADO6 INT14 48 P73 AN19 INT3 PO7 ADO7 INT15 47 P72 AN18 INT2 P10 ADO8 TIN1 46 P71 AN17 INT1 P11 ADO9 TOT1 45 0 P70 AN16 INTO P12 AD10 SINS NT11R 44 Vss P13 AD11 SOT3 43 P67 AN7 PPGE F P14 AD12 SCK3 42 P66 AN6 PPGC D QFP 100 41 P65 AN5 PPGA B Vss P64 AN4 PPG8 9 1 39 P63 AN3 PPG6 7 P62 AN2 PPG4 5 P15 AD13 37 P61 AN1 PPG2 3 P16 AD14 36 P60 ANO PPGO 1 P17 AD15 35 AVss P20 A16 PPG9 8 34 AVRL P21 A17 PPGB A AVRH P22 A18 PPGD C 32 Avec P23 A19 PPGF E 31 P57 AN15 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 22 MON Non 720777 AA ZZZZZZOHCEEREXILL Ox EIA gt gt gt E E 00D0DO5 lt 00OFOZZ lt lt 55 2 gt 2 gt c lt 2 2 TIC av o
45. W 00000000 00000000 00000000 00001000 000000XX 00000100 00000000 00000000 7960uto 796 Reserved 796 Clock output enable register CLKR R W Clock Monitor XXXX0000 796Du Reserved 796En CAN Direct Mode Register CDMR R W CAN clock sync XXXXXXXO 796Fu CAN RX TX redirect register CANSWR CAN 0 1 XXXXXX00 Continued 90340 Series a Abbrevia tion 79704 bus status register IBSRO 00000000 79714 12 bus control register IBCRO 00000000 7972 ITBALO 00000000 2 10 bit slave address register 79734 ITBAHO 00000000 79744 ITMKLO Interface 0 11111111 12C 10 bit address mask register 7975 ITMKHO 00111111 7976 12 7 bit slave address register ISBAO 00000000 79774 12 7 bit address mask register ISMKO 01111111 79784 12 data register IDARO 00000000 7979 797 797 1 clock control register ICCRO Interface 0 00011111 797Cu to 797 7980 bus status register IBSR1 00000000 79814 bus control register IBCR1 00000000 7982 ITBAL1 00000000 10 bit slave address register 7983 1 00000000 7984 ITMKL1 Interface 1 11111111 10 bit address mask register 7985 00111111 7986 12 7 bit slave address register ISBA1 00000000 79874 12C 7 bit address mask register ISMK1 01111111 79884 12 data register IDAR1 000000
46. apa y aa E e n 100 05 MB90V340 X1A MB90V340S P40 P41 90340 Series MB90F342 S MB90F343 S MB90F345 S MB90F346A S MB90F347A S MB90F349 S MB90341 S 90342 S MB90346A 5 MB90347A 8 90348 8 90349 5 PO4 ADO4 INT12 PO5 ADO5 INT13 P06 ADOG INT14 PO7 ADO7 INT15 P10 ADOB TIN1 P11 ADO9 TOT1 P12 AD10 SIN3 NT11R P13 AD11 SOT3 P14 AD12 SCK3 Vec Vss xi P15 AD13 P16 AD14 P17 AD15 P20 A16 PPG9 8 21 17 P22 A18 PPGD C P23 A19 PPGF E P03 AD03 1NT11 P02 ADO2 INT10 P01 ADO1 INT9 P00 ADOO INT8 PA1 TXO PAO RXO INT8R P97 0UT3 P96 0UT2 P95 0UT1 94 00 0 P93 PPG7 6 TOP VIEW P92 PPG5 4 P91 PPG3 2 P90 PPG1 0 Vss Vcc P87 SCK1 P86 SOT1 P85 SIN1 P84 SCKO INT15R P83 SOTO TOT2 P82 SINO TIN2 INT14R P81 TOTO CKOT INT13R P80 TINO ADTG INT12R P77 INT7 P76 INT6 RST MDO MD1 MD2 80 79 78 77 76 75 74 73 72 71 81 82 83 84 85 86 87 88 89 90 91 92 93 94 70 69 68 67 66 65 64 63 62 61 QFP 100 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 121314151617 18 19 20 21 22 23 24 25 26 27 28 29 30 24 20 25 21 2 26 22 27 23 N3 4 5 OR P31 RD P32 WRLX WRX INT1 P33 WRH P34 HRQ OUT4 P35 HAK OUT5
47. as high as internal capacitor If output impedance of an external circuit is too high a sampling period for an analog voltage may be insufficient Analog input Analog input circuit model R CM L Note Use the values in the figure only as a guideline 4 5 V lt lt 5 5 V R 2 52 C 10 7 pF 4 0 V lt lt 4 5 V R 13 6 Cz 10 7 pF 8 Flash Memory Program Erase Characteristics Parameter Conditions Remarks Excludes programming Sector erase time 1 15 5 prior to erasure Ta 25 Excludes programming Chip erase ime Voc 5 0 a prior to erasure Word 16 bit width __ 16 3 600 us Except for the over head programming time time of the system Programs Erase cycle 10 000 cycle 70 90340 Series a ORDERING INFORMATION Part number Package Remarks MB90F342PF MB90F342SPF MB90F342CPF MB90F342CSPF 100 pin Plastic QFP 100 06 MB90F342PFV MB90F342SPFV MB90F342CPFV MB90F342CSPFV 100 pin Plastic LQFP 100 05 MB90F343PF MB90F343SPF MB90F343CPF MB90F343CSPF MB90F343PFV MB90F343SPFV MB90F343CPFV MB90F343CSPFV 100 pin Plastic QFP 100 06 100 pin Plastic LQFP 100 05 MB90F345PF MB90F345SPF MB90F345CPF MB90F345CSPF 100 pin Plastic QFP 100
48. ct whether to use a pull up resistor This function is enabled in single chip mode Read strobe output pin for the data bus This function is enabled when the external bus is enabled Data sample input pin for input capture ICU5 General purpose l O The register can be set to select whether to use a pull up resistor This function is enabled either in single chip mode or with the WR WRL pin output disabled Write strobe output pin for the data bus This function is enabled when both the external bus and the WR WRL pin output are en abled WRL is used to write strobe 8 lower bits of the data bus in 16 bit access while WR is used to write strobe 8 bits of the data bus in 8 bit access RX input pin for CAN2 Interface MB90V340 only Sub external interrupt request input pin for INT10 General purpose l O The register can be set to select whether to use a pull up resistor This function is enabled either in single chip mode or with the WRH pin output disabled Write strobe output pin for the 8 higher bits of the data bus This function is enabled when the external bus is enabled when the external bus 16 bit mode is selected and when the WRH output pin is enabled TX Output pin for CAN2 MB90V340 only General purpose l O The register can be set to select whether to use a pull up resistor This function is enabled either in single chip mode or with the hold function disabled Hold request input pin This
49. e e PC interface up to 2 channels devices with C suffix only Up to 400 kbit s transfer rate e DTP External interrupt up to 16 channels CAN wakeup up to 2 channels e Module for activation of expanded intelligent I O service El 20S DMA and generation of external interrupt Delay interrupt generator module Generates interrupt request for task switching 8 10 bit A D converter 16 24 channels Resolution is selectable between 8 bit and 10 bit Activation by external trigger input is allowed Conversion time 3 us at 24 MHz machine clock including sampling time e Program patch function Address matching detection for 6 address pointers e Internal voltage regulator Supports 3 V MCU core offering low EMI and low power consumption figures e Programmable input levels Automotive CMOS Schmiitt initial level is Automotive in Single chip mode TTL level initial level for External bus mode e ROM security function Protects the content of ROM MASK ROM device only e External bus interface e Clock monitor function PC license Purchase of Fujitsu components conveys a license under the Philips Patent Rights to use these com ponents in an 2 system provided that the system conforms to the Standard Specification as defined by Philips 90340 Series PRODUCT LINEUP Part Number Parameter MB90F342 C S MB90F343 C S MB90F345 C S MB90F346A S
50. e B signal and the microcontroller The value of the limiting resistance should be set so that when the B signal is applied the input current to the microcontroller pin does not exceed rated values either instantaneously or for prolonged periods Note that when the microcontroller drive current is low such as in the power saving modes the B input potential may pass through the protective diode and increase the potential at the Vcc pin and this may affect other devices Note that if a B signal is input when the microcontroller power supply is off not fixed at 0 V the power supply is provided from the pins so that incomplete operation may result e Note that if the B input is applied during power on the power supply is provided from the pins and the resulting supply voltage may not be sufficient to operate the power on reset Care must be taken not to leave the B input pin open e Sample recommended circuits Input output equivalent circuits Protective diode C de Limiting resistance input 0 V to 16 V WARNING Semiconductor devices can be permanently damaged by application of stress voltage current temperature etc in excess of absolute maximum ratings Do not exceed these ratings 51 90340 Series 2 Recommended Conditions Vss AVss 0 V Parameter Remarks Under normal operation Under normal operation when not using the A D converter and
51. e of error Automatic transmission responding to Remote Frame Prioritized 16 message buffers for data and ID s Supports multiple messages Flexible configuration of acceptance filtering Full bit compare Full bit mask Two partial bit masks Supports up to 1 Mbps Can be used rising edge falling edge starting up by H L level input external interrupt expanded inteligent I O services EITOS and DMA D A converter 2 channels Up to100 kHz Subclock for low power operation devices with S suffix with subclock devices without S suffix without subclock Ports Virtually all external pins can be used as general purpose l O port All push pull outputs Bit wise settable as input output or peripheral signal Settable in pin wise of 8 as CMOS schmitt trigger automotive inputs default TTL input level settable for external bus 32 pin only for external bus Continued 90340 Series Continued Part Number Parameter MB90F342 C S MB90F343 C S MB90F345 C S MB90F346A S MB90F346CA S MB90F347A S MB90F347CA S MB90F349 C S MB90341 C S 90342 5 MB90346A S MB90346CA S MB90347A S MB90347CA S 90348 5 MB90349 C S Supports automatic programming Embedded Algorithm s Write Erase Erase Suspend Resume commands A flag indicating completion of the algorithm Number of erase cycles 10 000 times Data retention time 10 years Boot block con
52. ection Address 4 PADR4 ROM Correction 1 79 5 ROM Correction Address 4 PADR4 79 ROM Correction Address 5 PADR5 79F7H ROM Correction Address 5 PADR5 79F8u ROM Correction Address 5 PADR5 XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 79 9 to 79 Reserved 7A00 to Reserved for CAN Interface 0 Refer to CONTROLLERS 7B00H to 7BFFu Reserved for CAN Interface 0 Refer to CAN CONTROLLERS 7 00 7 Reserved for CAN Interface 1 Refer to CAN CONTROLLERS 7D00 to 7DFFH Reserved for CAN Interface 1 Refer to CONTROLLERS 7E00 to Reserved for CAN Interface 2 Refer to CAN CONTROLLERS 7 00 to Reserved for CAN Interface 2 Refer to Notes Initial value of X represents unknown value Addresses in the range 00004 to which are not listed in the table are reserved for the primary functions of the MCU A read access to these reserved addresses results reading X and any write access should not be performed CONTROLLERS CONTROLLERS controller has the following features Conforms to CAN Specification Version 2 0 Part A and 90340 Series Supports transmission reception in standard frame and exte
53. ed 12 Port inputs if CMOS hysteresis input levels are selected RST input 5 hysteresis MD input pin Port inputs if CMOS hysteresis input levels are selected except UART SIN input pins and input pins Port inputs if AUTOMOTIVE input levels are selected Port inputs if TTL input levels are selected UART SIN inputs if CMOS input levels are selected 2 Port inputs if CMOS hysteresis input levels are selected RST input 5 hysteresis MD input pin Normal outputs Vcc 4 5 4 0 mA 12C current outputs Vcc 4 5 lou 3 0 mA Normal outputs Vcc 4 5 lo 4 0 mA current outputs Vcc 4 5 lo 3 0 mA Continued 53 90340 Series Continued Sym Parameter bol Input leak current Ta 40 C to 105 5 0 10 Vss AVss 0 Condition Vcc 5 5 V Vss lt Vi lt Pull up resistance P00 to P07 P10 to P17 P20 to P27 P30 to P37 RST Pull down resistance MD2 Except Flash devices Power supply current IcTSPLL6 Vcc 5 0 Internal frequency 24 MHz At normal operation MB90F347 Vcc 5 0 Internal frequency 24 MHz At writing FLASH memory MB90F347 Vcc 5 0 Internal frequency 24 MHz At erasing FLASH memory MB90F347 Vcc 5 0 Inter
54. emark of FUJITSU LIMITED PACKAGES 100 pin Plastic QFP 100 pin Plastic LQFP 100 06 100 05 FUJITSU 90340 Series FEATURES e Clock Built in PLL clock frequency multiplication circuit Selection of machine clocks PLL clocks is allowed among frequency division by two on oscillation clock and multiplication of 1 to 6 times of oscillation clock for 4 MHz oscillation clock 4 MHz to 24 MHz Operation by sub clock up to 50 kHz 100 kHz oscillation clock divided two is allowed devices without S suffix only Minimum execution time of instruction 42 ns when operating with 4 2 oscillation clock and 6 time multi plied PLL clock 16 Mbyte CPU memory space 24 bit internal addressing e Instruction system best suited to controller Wide choice of data types bit byte word and long word Wide choice addressing modes 23 types Enhanced multiply divide instructions and RETI instructions Enhanced high precision computing with 32 bit accumulator e Instruction system compatible with high level language C language and multitask Employing system stack pointer Enhanced various pointer indirect instructions Barrel shift instructions e Increased processing speed 4 byte instruction queue Powerful interrupt function Powerful 8 level 34 condition interrupt feature Up to 16 external interrupts are supported e Au
55. er Flash programming 4 5 V 5 5 V at using external bus 5 V t 1096 Temperature range Package 40 C to 105 C QFP 100 LQFP 100 PGA 299 UART 4 channels 5 channels Wide range of baud rate settings using a dedicated reload timer Special synchronous options for adapting to different synchronous serial protocols LIN functionality working either as master or slave LIN device 400 kbit s devices with C suffix 2ch devices without C suffix 2 channel A D Converter devices with C suffix 24ch devices without C suffix 16ch 10 bit or 8 bit resolution Conversion time Min 3 us include sample time per one channel 24 input channels 16 bit Reload Timer 4 channels Operation clock frequency fsys 2 fsys 2 fsys 2 fsys Machine clock frequency Supports External Event Count function Continued Part Number Parameter 16 bit Timer 2 channels 90340 Series MB90F342 C S MB90F343 C S MB90F345 C S MB90F346A S MB90F346CA S MB90F347A S MB90F347CA S MB90F349 C S MB90341 C S MB90342 C S MB90346A S MB90346CA S MB90347A S MB90347CA S 90348 5 MB90349 C S Signals an interrupt when overflowing Supports Timer Clear when a match with Output Compare Channel 0 4 Operation clock freq fsys fsys 2 fsys 2 15 5 23 fsys 2 fsys 25 fsys 2 fsys 2 fsys 2 Machine clock freq
56. er Related Resource Output Timing Ta 40 to 105 C Vcc 4 5 V to 5 5 V Vss 0 0 V Value Parameter Symbol Condition Unit Min Max TOTO to CLK TOTO to 24V PPGO to PPGF 0 8 V tro 66 5 A D Converter Parameter Resolution Ta 40 C to 105 C 3 0 V lt AVRH AVRL Vcc 5 0 V 10 Vss AVss 0 Symbol 90340 Series Total error Nonlinearity error Differential nonlinearity error Zero reading voltage ANO to AN23 AVRL 1 5 AVRL 0 5 AVRL 2 5 Full scale reading voltage Compare time ANO to AN23 3 5 AVRH 1 5 AVRH 0 5 16 500 4 5 V lt 5 5 V 4 0 lt AVcc lt 4 5 V Sampling time 4 5 V lt 5 5 V 4 0 V AVcc lt 4 5 V Analog port input current ANO to AN23 Analog input voltage range Reference voltage range ANO to AN23 AVRL 2 7 AVcc 0 AVRH 2 7 Power supply current 7 5 Reference voltage current Offset between input channels When not operating A D converter this is the current Vcc ANO to AN23 Note The accuracy gets worse as AVRH AVRL becomes smaller AVRH 5 0 V 67 90340 Series a 6 Definition of A D Converter Terms Resolution Analog variation that is recognized by an A D converter
57. ernal Interrupt Level 1 ELVR1 External Interrupt Level 1 External Interrupt 1 Source Select ELVR1 EISSR MB90340 Series Resource name External Interrupt 1 Initial value 00000000 XXXXXXXX 00000000 00000000 00000000 PLL Subclock Control register PSCCR XXXX0000 DMA Buffer Addrss Pointer L BAPL DMA Buffer Addrss Pointer M BAPM DMA Buffer Addrss Pointer H BAPH DMA Control I O Register Address Pointer L DMACS IOAL I O Register Address Pointer Data Counter L DCTL Data Counter H DCTH XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX Address Register Serial Mode Register SMR2 Serial Control Register Reception Transmission Data Register SCR2 RDR2 TDR2 Serial Status Register SSR2 Extended Communication Control Reg ECCR2 Extended Status Control Register ESCR2 Baud Rate Register 0 BGR20 EOu to Baud Rate Register 1 BGR21 Reserved for CAN Interface 2 Refer to M CAN CONTROLLERS 00000000 00000000 00000000 00001000 000000XX 00000100 00000000 00000000 FOH to FFu External Continued 35 36 90340 Series Address 7900 Reload L Register Abbrevia tion PRLLO Access R W 7901H Reload H PRLHO R W 79021 Reload L PRLL1 R W 79034 Reload H
58. figuration Erase can be performed on each block Block protection with external programming voltage Flash Security Feature for protecting the content of the Flash except for MB90F346A S and MB90F346CA S MB90V340 S ROM Security Protects the content of ROM MASK ROM device only 1 The devices other than MB90F342 C S MB90F345 C S MB90F346A S MB90F346CA 5 MB90F347A S MB90F347CA S MB90F349 C S MB90346A S 90346 S MB90347A S and MB90347CA S are under development 2 It is setting of Jumper switch TOOL Vcc when Emulator MB2147 01 is used Please refer to the Emulator hardware manual about details 3 Embedded Algorithm is a trade mark of Advanced Micro Devices Inc ASSIGNMENTS MB90V340 S P04 AD04 INT12 PO5 ADO5 INT13 P06 ADO6 INT14 P07 ADO7 INT15 P10 AD08 TIN1 P11 ADO9 TOT1 P12 AD10 SIN3 NT11R P13 AD11 SOT3 P14 AD12 SCK3 Vcc Vss x1 X0 P15 AD13 SIN4 P16 AD14 SOT4 P17 AD15 SCK4 P20 A16 PPG9 8 P21 A17 PPGB A P22 A18 PPGD C P23 A19 PPGF E POS ADOS INT1 1 P02 ADO2 INT10 P01 ADO1 INT9 P00 ADOO INT8 PA1 TXO PAO RXO INT8R P97 OUT3 P96 OUT2 P95 OUT1 P94 OUTO P93 PPG7 6 TOP VIEW TVS rr 00 x E DOD GS vo o o c gt gt P85 SIN1 P84 SCKO INT15R P83 SOTO TOT2 P82 SINO TIN2 INT14R P81 TOTO CKOT INT13R MB90340 Series P80 TINO
59. function is enabled when both the ex ternal bus and the hold function are enabled Waveform output pin for output compare OCU4 General purpose l O The register can be set to select whether to use a pull up resistor This function is enabled either in single chip mode or with the hold function disabled Hold acknowledge output pin This function is enabled when both the external bus and the hold function are enabled Waveform output pin for output compare OCU6 General purpose l O The register can be set to select whether to use a pull up resistor This function is enabled either in single chip mode or with the external ready function disabled Ready input pin This function is enabled when both the external bus and the external ready function are enabled Waveform output pin for output compare OCU5 Continued 15 16 90340 Series Pin LQFP100 2 QFP100 Pin name P37 CLK OUT7 Circuit type Function General purpose The register can be set to select whether to use a pull up resistor This function is enabled either in single chip mode or with the CLK output disabled CLK output pin This function is enabled when both the external bus and CLK output are enabled Waveform output pin for output compare OCU7 11 to 12 13 to 14 P40 to P41 General purpose l O devices with S suffix X1A Oscillator
60. heral Peripheral Note The high order portion of bank 00 gives the image of the FF bank ROM to make the small model of the C compiler effective Since the low order 16 bits are the same the table in ROM can be referenced without using the far specification in the pointer declaration For example an attempt to access 000 accesses the value at FFC000n in ROM The ROM area in bank FF exceeds 32 Kbytes and its entire image cannot be shown in bank 00 The image between 8000 and FFFFFF is visible in bank 00 while the image between 0000 and FF7FFFu is visible only in bank FF 29 30 90340 Series a Register Port 0 data register Abbrevia tion Access Resource name Initial value XXXXXXXX Port 1 data register XXXXXXXX Port 2 data register XXXXXXXX Port 3 data register XXXXXXXX Port 4 data register XXXXXXXX Port 5 data register Port 6 data register Port 6 XXXXXXXX XXXXXXXX Port 7 data register Port 7 XXXXXXXX Port 8 data register Port 8 XXXXXXXX Port 9 data register Port 9 XXXXXXXX Port A data register Port A XXXXXXXX Analog Input Enable Port 5 Analog Input Enable Port 6 Port 5 A D Port 6 A D 11111111 11111111 Analog Input Enable Port 7 Port 7 A D 11111111 Input level select register O Ports XXXXXXXX Input level select register 1 Ports
61. in 14 Port 0 to port 3 output during Power on External bus mode As shown below when power is turned in External Bus mode there is a possibility that output signal of Port 0 to Port might be unstable Porto to outputs Port0 to outputs Hi Z might be unstable 15 Notes on using CAN Function To use CAN function please set 1 to DIRECT bit of CAN Direct Mode Register CDMR If DIRECT bit is set to 0 initial value wait states will be performed when accessing CAN registers Please refer to Hardware Manual of MB90340 series for detail of CAN Direct Mode Register 16 Flash security Function except for MB90F346A The security bit is located in the area of the flash memory If protection code 014 is written in the security bit the flash memory is in the protected state by security Therefore please do not write 014 in this address if you do not use the security function Please refer to following table for the address of the security bit Flash memory size Address for security bit MB90F347A Embedded 1 Mbit Flash Memory 0001 MB90F342 MB90F349 MB90F343 Embedded 3 Mbit Flash Memory F90001 MB90F345 Embedded 4 Mbit Flash Memory 80001 Embedded 2 Mbit Flash Memory 0001 25 26 90340 Series BLOCK DIAGRAMS MB90V340 S X0 X1 XOA X1A RST SOT4 to SOTO SCK4 to SCKO SIN4 to SINO AVCC AVSS AN23 to ANO AVRH AVRL ADTG DAO1 DAOO PP
62. ipheral 000000H FFFFFFH FFO000H FEFFFFH FE0000H FDFFFFH FD0000H FCFFFFH FCO000H FBFFFFH 000 FAFFFFH 0000 FOFFFFH F90000H FSFFFFH F80000H OOFFFFH 008000H 007FFFH 007900H 0050FFH 000100H 0000EFH 000000H MB90F343 C S CS ROM FF bank ROM FE bank ROM FD bank ROM FA bank ROM F9 bank ROM Image of FF bank Peripheral Peripheral 90340 Series MB90349 C S CS MB90342 C S CS MB90F349 C S CS MB90348 C S CS MB90347A CA AS CAS MB90346A CA AS CAS MB90F342 C S CS MB90341 C S CS MB90F347A CA AS CAS MB90F346A CA AS CAS FFFFFFH FFFFFFH FFFFFFH FFFFFFH ROM FF bank ROM FF bank ROM FF bank ROM FF bank 0000 FF0000H FF0000H FF0000H FEFFFFH FEFFFFH FEFFFFH ROM FE bank ROM FE bank ROM FE bank 0000 0000 FDFFFFH ROM FD bank FD0000H FCFFFFH ROM FC bank 0000 OOFFFFH OOFFFFH ROM OOFFFFH OOFFFFH ROM 0080004 Image of FF bank 008000 Image of FF bank 0080001 Image of FF bank Image of FF bank 007FFFH 007FFFH 007FFFH 007 Peripheral Peripheral Peripheral Peripheral 007900H 007900H 007900H 007900H 003FFFH ES 003FFFH RAM 16 K RAM 16 K 000100H 000100H 0018FEH RAM 6 K 0008FFH 000100H 000100 RAM 2 Peripheral Peripheral 0000 000000 No access 0000EFH 000000H 0000EFH 000000H 0000EFH 000000H Perip
63. istor This function is enabled in single chip mode I O pin for 12th bit of the external address data bus This function is enabled when the external bus is enabled Clock I O pin for UART3 Continued 13 90340 Series Pin No LQFP100 QFP100 Pin name P15 Circuit type Function General purpose I O The register can be set to select whether to use a pull up resistor This function is enabled in single chip mode pin for 13th bit of the external address data bus This function is enabled when the external bus is enabled Serial data input pin for UART4 MB90V340 only General purpose I O The register can be set to select whether to use a pull up resistor This function is enabled in single chip mode pin for 14th bit of the external address data bus This function is enabled when the external bus is enabled Serial data output pin for UART4 MB90V340 only P17 AD15 SCK4 General purpose I O The register can be set to select whether to use a pull up resistor This function is enabled in single chip mode pin for 15th bit of the external address data bus This func tion is enabled when the external bus is enabled Clock I O pin for UART4 MB90V340 only 95 to 98 97 to 100 P20 to P23 A16 to A19 PPG9 PPGB PPGD PPGF General purpose I O The register can be set to select whether to use a pull up resisto
64. l conversion characteristics ECL 1 LSB x 1 Vor N 1 Actual conversion characteristics 77 Vest actual measurement value 8 3 aipe 8 VNT actual 3 004 H measurement value gt gt V N 1 T a 003 _ Actual conversion o actual measurement characteristics value VNT 002 actual measurement value Ideal characteristics N 2 Actual conversion Qof p ag characteristics actual measurement value AVRL AVRH AVRL AVRH Analog input Analog input Vat 1 LSBx N 1 Vor i igi LSB Non linearity error of digital output N 115 LSB T T Differential linearity error of digital output N 1LSB 1 LSB LSB Vest Vor 1LSB 1022 V Vor Voltage at which digital output transits from 000 to 001 Vest Voltage at which digital output transits from to 3FFH 69 90340 Series 7 Notes on A D Converter Section Use the device with external circuits of the following output impedance for analog inputs Recommended output impedance of external circuits are Approx 1 5 or lower 4 0 lt AVcc lt 5 5 sampling period lt 0 5 us If an external capacitor is used in consideration of the effect by tap capacitance caused by external capacitors and on chip capacitors capacitance of the external one is recommended to be several thousand times
65. l ms With an external clock the oscillation time is 0 ms Under normal operation RST In Stop mode Sub Clock mode Sub Sleep mode Watch mode tRSTL RST 0 2 Vcc X Bi 0 2 Vcc 90 of amplitude X0 Internal operation clock 100 us A Oscillation time P T of oscillator Oscillation stabilization waiting time Instruction execution Internal reset 57 58 90340 Series 3 Power On Reset Parameter Symbol Condition Power on rise time Ta 40 to 105 C Vcc 5 0 V 10 Vss AVss 0 0 V Power off time Due to repetitive operation Vcc tOFF If you change the power supply voltage too rapidly a power on reset may occur We recommend that you startup smoothly by restraining voltages when changing the power supply voltage during operation as shown in the figure below Perform while not using the PLL clock However if voltage drops are within 1 V s you can operate while using the PLL clock We recommend a rise of 50 mV ms maximum Holds RAM data 4 Bus Timing Read Parameter ALE pulse width ALE Valid address ALE J time ALE A23 to A16 AD15 to ADOO ALE Address valid time ALE AD15 to ADOO Valid address RD J time A23 toA16 AD15 to RD Valid address Valid data A23 to A16 AD15 to ADOO RD J Valid da
66. nal frequency 24 MHz At Sleep mode MB90F347 Vcc 5 0 Internal frequency 2 MHz At Main Timer mode MB90F347 Vcc 5 0 Internal frequency 24 MHz At PLL Timer mode external frequency 4 MHz MB90F347 Vcc 5 0V Internal frequency 8 kHz At sub operation 25 C MB90F347 Voc 5 0V Internal frequency 8 kHz At sub sleep Ta 25 C MB90F347 Vcc 5 0V Internal frequency 8 kHz At watch mode Ta 25 C MB90F347 Vcc 5 0 At Stop mode 25 MB90F347 Input capacity Other than C AVss AVRH AVAL Vcc Vss The power supply current is measured with an external clock 90340 Series 4 AC Characteristics 1 Clock Timing Parameter Clock frequency Ta 40 C to 105 C Vcc 5 0 V 10 Vss AVss 0 Remarks When using an oscillation circuit When using an external clock Clock cycle time When using an oscillation circuit When using an external clock Input clock pulse width Duty ratio is about 30 to 70 Input clock rise and fall time tcn When using external clock Internal operating clock frequency machine clock When using main clock fce When using sub clock Internal operating clock cycle time machine clock When using main clock terL
67. name P54 AN12 TOT3 Circuit type Function General purpose l O Analog input pin for the A D converter Output pin for the reload timer 3 P55 AN13 General purpose l O Analog input pin for the A D converter P56 to P57 AN14 to AN15 DADO to DAO1 General purpose l O Analog input pin for the A D converter D A converter analog output pins MB90V340 only 34 to 41 36 to 43 P60 to P67 ANO to AN7 PPGO 2 4 6 8 A C E General purpose l O Analog input pins for the A D converter Output pins for PPGs 43 to 48 53 54 45 to 50 55 56 P70 to P77 AN16 to AN23 INTO to INT7 General purpose 1 Analog input pins for the A D converter devices with C suffix External interrupt request input pins for INTO to INT7 P80 TINO ADTG INT12R General purpose l O Event input pin for the reload timers O Trigger input pin for the A D converter Sub external interrupt request input pin for INT12 P81 TOTO CKOT INT13R General purpose I O Output pin for the reload timer O Output pin for the clock monitor Sub external interrupt request input pin for INT13 P82 SINO TIN2 INT14R P84 SCKO INT15R General purpose I O Serial data input pin for UARTO Event input pin for the reload timers 2 Sub external inte
68. nded frame formats e 29 bit ID and 8 byte data e Multi level message buffer configuration buffer as ID acceptance mask e Two acceptance mask registers in either standard frame format or extended frame formats Bit rate programmable from 10 Kbits s to 2 Mbits s when input clock is at 16 MHz Address CANO 000070 1 000080 Register Abbreviation CAN2 0000714 000072 000081 000082 0000 0 0000 1 0000 2 000073 000083 0000 Supports transmitting of data frames by receiving remote frames 16 transmitting receiving message buffers List of Control Registers 1 Message buffer valid register Transmit request register BVALR Access R W Provides full bit comparison full bit mask acceptance register O acceptance register 1 for each message Initial Value 00000000 00000000 00000000 00000000 000074 0000844 0000 4 000075 000085u 0000 5 Transmit cancel register 00000000 00000000 0000764 0000864 0000 6 000077 000078 000087 000088 0000 7 0000 8 000079 000089 0000 9 Transmission complete register Receive complete register 00000000 00000000 00000000 00000000 00007 00008 0000 00007 00008 0000 Remote request receiving register 00000000 00000000 00007 00008 0000 00
69. not Power supply voltage Flash programming When External bus is used Maintains RAM data in stop mode Use a ceramic capacitor or capac itor of better AC characteristics Capacitor at the Vcc should be greater than this capacitor Smooth capacitor Operating temperature Cs 777 C Pin Connection Diagram WARNING The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device All of the device s electrical characteristics are warranted when the device is operated within these ranges Always use semiconductor devices within their recommended operating condition ranges Operation outside these ranges may adversely affect reliability and could result in device failure No warranty is made with respect to uses operating conditions or combinations not represented on the data sheet Users considering application outside the listed conditions are advised to contact their FUJITSU representatives beforehand 52 90340 Series a 3 DC Characteristics Ta 2 40 C to 105 C Vcc 5 0 V 10 Vss AVss 0 Parameter Condition Remarks Port inputs if CMOS hysteresis input levels are selected except UART SIN input pins and input pins Port inputs if AUTOMOTIVE input levels are selected Port inputs if TTL input levels are selected UART SIN inputs if CMOS input levels are select
70. ould result from the use of information contained herein The products described in this document are designed developed and manufactured as contemplated for general use including without limitation ordinary industrial use general office use personal use and household use but are not designed developed and manufactured as contemplated 1 for use accompanying fatal risks or dangers that unless extremely high safety is secured could have a serious effect to the public and could lead directly to death personal injury severe physical damage or other loss 1 nuclear reaction control in nuclear facility aircraft flight control air traffic control mass transport control medical life support system missile launch control in weapon system or 2 for use requiring extremely high reliability submersible repeater and artificial satellite Please note that Fujitsu will not be liable against you and or any third party for any claims or damages arising in connection with above mentioned uses of the products Any semiconductor devices have an inherent chance of failure You must protect against injury damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy fire protection and prevention of over current levels and other abnormal operating conditions If any products described in this document represent goods or technologies subject to certain restrictions on
71. r In external bus mode the pin is enabled as a general purpose I O port when the corresponding bit in the external address output control register HACR is 1 Output pins for A16 to A19 of the external address bus When the corresponding bit in the external address output control register HACR is O the pins are enabled as high address output pins A16 to A19 Output pins for PPGs P24 to P27 A20 to A23 INO to IN3 General purpose I O The register can be set to select whether to use a pull up resistor In external bus mode the pin is enabled as a general purpose I O port when the corresponding bit in the external address output control register HACR is 1 Output pins for A20 to A23 of the external address bus When the corresponding bit in the external address output control register HACR is 0 the pins are enabled as high address output pins A20 to A23 Data sample input pins for input captures ICUO to ICU3 14 P30 General purpose I O The register can be set to select whether to use a pull up resistor This function is enabled in single chip mode Address latch enable output pin This function is enabled when the external bus is enabled Data sample input pin for input capture ICU4 Continued 90340 Series Pin No LQFP1007 QFP100 Pin name Circuit type Function General purpose register can be set to sele
72. rks e CMOS level output lo 4 mA 4 mA CMOS hysteresis inputs With the standby time input shutdown function Automotive input With the standby time input shutdown function pull up control Do Hysteresis inputs TW Do Automotive inputs Ino TTL input Standby control for input shutdown CMOS level output lo 4 mA 4 CMOS hysteresis inputs With the standby time input shutdown function Automotive input With the standby time input shutdown function TTL input With the standby time input shutdown function Programmalble pullup resistor 50 kQ approx Hysteresis inputs Automotive inputs Standby control for input shutdown e CMOS level output lo 3 mA lon 3 mA CMOS hysteresis inputs With the standby time input shutdown function Automotive input With the standby time input shutdown function Continued 777 do Circuit Nout Hysteresis inputs Do Automotive inputs Standby control for input shutdown Analog input 90340 Series Remarks e CMOS level output lo 4 mA 4 mA CMOS hysteresis inputs With the standby time input shutdown function Automotive input With the standby time in put shutdown function A D analog input TIT c Nout
73. rrupt request input pin for INT14 General purpose I O Serial data output pin for UARTO Output pin for the reload timer 2 General purpose I O Clock I O pin for UARTO Sub external interrupt request input pin for INT15 General purpose I O Serial data input pin for UART1 General purpose I O Serial data output pin for UART1 Continued 17 90340 Series a Continued Pin No LQFP1007 62 QFP100 64 Pin name P87 SCK1 Circuit type Function General purpose l O Clock I O pin for UART1 65 to 68 67 to 70 P90 to P93 PPG1 3 5 7 General purpose I O Output pins for PPGs 69 to 72 71 to 74 P94 to P97 OUTO to OUT3 General purpose l O Waveform output pins for output compares to OCU3 This function is enabled when the OCU enables waveform output PAO RXO INT8R General purpose I O RX input pin for CANO Interface Sub external interrupt request input pin for INT8 PA1 TXO General purpose l O TX Output pin for CANO Vcc power input pin for analog circuits Reference voltage input for the A D Converter This power supply must be turned on or off while a voltage higher than or equal to AVRH is applied to AVcc Lower reference voltage input for the A D Converter Vss power input pin for analog circuits Input pins for specifying the operating mode The pins m
74. ta input RD AD15 to ADOO AN Data hold time RD AD15 to ADOO f time RD ALE Address valid time RD A23 to A16 Valid address CLK f time A23 to A16 AD15 to ADOO CLK RD CLK f time RD CLK ALE RD time ALE RD Condition MB90340 Series tcr 2 10 40 to 85 C Voc 4 5 V to 5 5 V Vss 0 0 V Machine Clock lt 16 MHz Remarks tcr 2 15 tcr 2 15 15 5 tce 2 40 tce 2 20 2 50 0 tcr 2 15 2 10 2 15 tcr 2 15 ter 2 15 59 60 90340 Series CLK A23 to A16 AD15 to ADOO tavcH 24 24V TAVLL gt lt 2 4 24 24 0 8 V TRLRH 24 0 8 V e tRHAX 2 4 2 4V 0 0 8 V 24 24 0 8 V j VIH VIH Address Read data 0 8 V 0 8 V VIL VIL 90340 Series a 5 Bus Timing Write Ta 40 C to 85 Vcc 4 5 V to 5 5 Vss 0 0 V Machine Clock x 16 MHz Parameter Condition Remarks NI A23 to A16 Valid address WR 4 time AD15 to ADOO tor 15 WR WR pulse width WR 3 tce 2 20 Valid data output WR 7 AD15 to ADOO 32 20 WR W
75. ter and Analog Inputs Make sure to turn on the A D converter power supply AVcc AVRH AVRL and analog inputs ANO to AN23 after turning on the digital power supply Vcc Turn off the digital power after turning off the A D converter supply and analog inputs In this case make sure that the voltage not exceed AVRH or AVcc turning on off the analog and digital power supplies simultaneously is acceptable 10 Connection of Unused Pins of A D Converter if A D Converter is used Connect unused pins of A D converter to AVcc Vcc AVss AVRH AVRL Vss 90340 Series 11 Notes on Energization To prevent the internal regulator circuit from malfunctioning set the voltage rise time during energization at 50 or more us 0 2 V to 2 7 V 12 Stabilization of power supply voltage A sudden change in the supply voltage may cause the device to malfunction even within the specified supply voltage operating range Therefore the Vcc supply voltage should be stabilized For reference the supply voltage should be controlled so that Vcc ripple variations peak to peak value at commercial frequencies 50 Hz to 60 Hz fall below 10 of the standard supply voltage and the coefficient of fluctuation does not exceed 0 1 V ms at instantaneous power switching 13 Initialization In the device there are internal registers which are initialized only by a power on reset To initialize these registers turn on the power aga
76. time input shutdown function Automotive input With the standby time input shutdown function TTL input With the standby time input shutdown function Programmable pullup registor 50 kQ approx CMOS level output lo 4 mA lou 2 4 mA CMOS inputs With the standby time input shutdown function Automotive input With the standby time input shutdown function A D analog input 90340 Series HANDLING DEVICES Special care is required for the following when handling the device Preventing latch up Treatment of unused pins Using external clock Precautions for when not using a sub clock signal Notes on during operation of PLL clock mode Power supply pins Vcc Vss Pull up down resistors Crystal Oscillator Circuit Turning on Sequence of Power Supply to A D Converter and Analog Inputs Connection of Unused Pins of A D Converter Notes on Energization Stabilization of power supply voltage Initialization 0 to port3 output during Power on External bus mode Notes on using CAN Function Flash security Function 1 Preventing latch up CMOS IC chips may suffer latch up under the following conditions A voltage higher than Vcc or lower than Vss is applied to an input or output pin A voltage higher than the rated voltage is applied between Vcc and Vss The AVcc power supply is applied before the Vcc voltage Latch up may increase the power supply current drastically causing thermal damage
77. to 007CA7u 007 to 007EA7u Data register 4 8 bytes XXXXXXXX to XXXXXXXX 007AA8u to 007 007 8 to 007CAFH 007EA8H to 007EAFH Data register 5 8 bytes XXXXXXXX to XXXXXXXX 007 to 007AB7H 007 to 007CB7u 007 to 007EB7H Data register 6 8 bytes XXXXXXXX to XXXXXXXX 007AB8u to 007 007CB8u to 007 007EB8H to 007 Data register 7 8 bytes XXXXXXXX to XXXXXXXX 007A ACO 00760 007005 Q m aw SS 007 7 007 7 007EC7H 8 bytes XXXXXXXX 7A 00 ACB 00708 007ECE a 007 007 007ECFu 8 bytes XXXXXXXX 007ADOs 007CD0 007005 mM RS 007AD74 007CD7 007ED7 8 bytes XXXXXXXX 00708 00708 007085 m aw RS 007 007 007EDFu 8 bytes XXXXXXXX 007 007050 007 0 ms m mM 007 7 007 7 007 7 8 bytes XXXXXXXX 007AE84 007 8 007 XXXXXXXX to to to iu Do 13 DTR13 R W to 007 007 007 y XXXXXXXX 90340 Series a List of Message Buffers DLC Registers and Data Registers 3 Address CAN1 007 007 007 pata vecister 14 XXXXXXXX to to to 9 to 8 bytes XXXXXXXX Register Abbreviation Access Initial Value 007 7 007CF7u 007EF7u 007 AF8u 007CF8u 007
78. to the device For the same reason also be careful not to let the analog power supply voltage AVcc AVRH exceed the digital power supply voltage 2 Handling unused pins Leaving unused input pins open result in misbehavior or latch up and possible permanent damage of the device Therefore they must be pulled up or pulled down through resistors this case those resistors should be more than 2 Unused bidirectional pins should be set to the output state and can be left open or the input state with the above described connection 3 Using external clock To use external clock drive the pin and leave X1 pin open MB90340 Series o X0 Open X1 4 Precautions for when not using a sub clock signal If you do not connect pins and X1A to an oscillator use pull down handling on the pin and leave the X1A pin open 23 24 90340 Series 5 Notes on during operation of PLL clock mode If the PLL clock mode is selected the microcontroller attempt to be working with the self oscillating circuit even when there is no external oscillator or external clock input is stopped Performance of this operation however cannot be guaranteed Power supply pins Vcc Vss If there are multiple and Vss pins from the point of view of device design pins to be of the same potential are connected the inside of the device to prevent such malfunctioning as latch up
79. tomatic data transfer function independent of CPU Expanded intelligent I O service function EIOS up to 16 channels up to 16 channels e Low power consumption standby mode Sleep mode a mode that halts CPU operating clock Time base timer mode a mode that operates oscillation clock sub clock time base timer and clock timer only Watch mode a mode that operates sub clock and clock timer only Stop mode a mode that stops oscillation clock and sub clock CPU blocking operation mode e Process CMOS technology e1 O port General purpose input output port CMOS output 80 ports devices without S suffix 82 ports devices with S suffix e Timer Time base timer clock timer watchdog timer 1 channel 8 16 bit PPG timer 8 bit X 16 channels or 16 bit X 8 channels 16 bit reload timer 4 channels 16 bit input output timer 16 bit free run timer 2 channel FRTO ICU 0 1 2 3 OCU 0 1 2 3 FRT1 ICU 4 5 6 7 OCU 4 5 6 7 90340 Series 16 bit input capture ICU 8 channels 16 bit output compare OCU 8 channels e Full CAN interface up to 2 channels Compliant with Ver2 0A and Ver2 0B CAN specifications Flexible message buffering mailbox and FIFO buffering can be mixed CAN wake up function e UART LIN SCI up to 4 channels Equipped with full duplex double buffer Clock asynchronous or clock synchronous serial transmission is availabl
80. ust be directly connected to Vcc or Vss Input pin for specifying the operating mode The pins must be directly connected to Vcc or Vss Power 3 5 V to 5 5 V input pins 1 FPT 100P M06 2 FPT 100P M05 18 Power 0V input pins This is the power supply stabilization capacitor pin It should be connected to a higher than or equal to 0 1 uF ceramic capaci tor CIRCUIT Circuit 90340 Series Remarks X1 Standby control signal Oscillation circuit High speed oscillation feedback resistor approx 1 X1A Do Xout d Standby control signal Oscillation circuit Low speed oscillation feedback resistor approx 10 R E i a ANA Rig Mask ROM and EVA device CMOS Hysteresis input pin Flash device e CMOS input pin Pull down Resistor Hysteresis AIN Do Do inputs Mask ROM and EVA device CMOS Hysteresis input pin Pull down resistor valule approx 50 Flash device CMOS input pin No Pull down Pull up Resistor Hysteresis inputs CMOS Hysteresis input pin Pull up resistor valule approx 50 kQ Continued 19 90340 Series 20 Circuit Hysteresis inputs Automotive inputs Standby control for input shutdown Rema
81. x lt 06005 3565 52909 855255 eo E cr ia D 5 9 100 06 MB90F342C F343C F345C F346CA F347CA F349C 341 C 342C 346CA 347CA 348C 349C MB90F342CS F343CS F345CS F346CAS F347CAS F349CS 341 CS 342CS 346CAS 347CAS 348CS 349CS P40 P41 Continued 11 90340 Series a Continued TOP VIEW FE gt Balk SG e B ESSERE Zz 5 cese ZEECRZzZzZ Sotmnronnar 5 ST SS SBD DR EEE 55255265299 x lt fooooaaag lt 8 amp o O O Oo 000c000606060060060606 gt gt 0000000000il 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 P01 ADO1 INT9 76 50 P02 ADO2 INT10 77 49 0 P03 ADO3 INT1 1 78 48 0 P75 AN21 INT5 PO4 ADO4 INT12 79 47 0 P74 AN20 INT4 PO5 ADOS INT13 80 46 0 P73 AN19 INT3 PO6 ADOG INT14 81 45 P72 AN18 INT2 P07 ADO7 INT15 82 44 P71 AN17 NT1 P10 AD08 TIN1 83 43 P70 AN16 INTO P11 ADOS TOT1 84 42 vss P12 AD10 SIN3 NT11R 85 41 P67 AN7 PPGE F P13 AD11 SOT3 86 40 0 P66 AN6 PPGC D P14 AD12 SCK3 87 LQFP 100 39 P65 AN5 PPGA B 88 38 P64 AN4 PPG8 9 Vss 89 37 P63 AN3 PPG6 7 90 36 P62 AN2 PPG4 5 91 35 P61 AN1 PPG2 3 P15

FUJITSU SEMICONDUCTOR MB90340 Series handbook

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