ST STG4160 handbook
Contents
1. max min 180 54 g4 TAPE WIDTH A mm IST 17 19 Revision history STG4160 7 18 19 Revision history Table 10 Document revision history Date Revision Changes 11 Sep 2008 1 Initial release 19 Feb 2009 2 Updated loy values in Table 6 DC specifications STG4160 Please Read Carefully Information in this document is provided solely in connection with ST products STMicroelectronics NV and its subsidiaries ST reserve the right to make changes corrections modifications or improvements to this document and the products and services described herein at any time without notice All ST products are sold pursuant to ST s terms and conditions of sale Purchasers are solely responsible for the choice selection and use of the ST products and services described herein and ST assumes no liability whatsoever relating to the choice selection or use of the ST products and services described herein No license express or implied by estoppel or otherwise to any intellectual property rights is granted under this document If any part of this document refers to any third party products or services it shall not be deemed a license grant by ST for the use of such third party products or services or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoever of such third pa2. ATI STG4160 Low voltage 0 5 Q single SPDT switch with break before make feature and 15 kV contact ESD protection Features m Wide operating voltage range Vcc opr 1 65 to 4 8 V m Low power dissipation lec 0 2 pA max at TA 85 C m Low ON resistance Ron 0 75 Q Ta 25 C at Voc 2 25V Ron 0 50 Q Ta 25 C at Voc 3 0V Ron 0 40 Q Ta 25 C at Voc 4 3V m Separate supply voltage for switch and control pins m Latch up performance exceeds 100mA per JESD 78 Class Il m ESD performance tested on common pin D pin 15 kV IEC 61000 4 2 ESD contact discharge 8kV HBM JESD22 A114 B Class Il m ESD performance tested on S1 and S2 pin 8kVIEC 61000 4 2 ESD contact discharge m ESD performance test on all other pins 4kV HBM JESD22 A114 B Class ll 400 V machine model JESD22 A115 A 1500 V charged device model JESD22 C101 Applications m Mobile phones Flip chip 8 Description The STG4160 is a high speed CMOS low voltage single analog SPDT single pole dual throw switch or 2 1 multiplexer demultiplexer switch fabricated in silicon gate C MOS technology It is designed to operate from 1 65 to 4 8 V making this device ideal for portable applications It offers low ON resistance 0 40 Q typ at Vcc 4 3 V The SEL inputs are provided to control the switches The switch S1 is ON connected to common port D when the SEL input is held hig
3. 0 50 0 65 0 8 Q 3 7 lg TOO IRA 0 45 0 55 07 4 3 0 40 0 5 0 65 1 8 40 NS 2 25 Vs 0 V to 20 ARon a 3 1 65 4 3 Voc 10 ma channels 1 3 7 i 100 mA 10 4 3 10 1 8 10 17 2 0 d 2 25 Vs 0 V to 300 430 550 Hala MINER M 3 1 65 4 3 Voc 150 190 270 ma 37 is 100 mA 140 180 230 4 3 140 180 220 Sn OFF state Vs 0 3 to 4 0 lopp leakage 4 3 4 3 S 30 30 300 300 nA Auge Vp 0 3 to 4 0 Sn ON state Vs 0 3 to 4 0 lon leakage 4 3 4 3 V _ 30 30 300 300 nA current p pel D ON state Vs open lo leakage 4 3 4 3 s 0p 30 30 300 300 nA current Vo 0to 4 0 6 19 ky STG4160 Electrical characteristics Table 6 DC specifications continued Value Vcc VL Di A Symbol Parameter V V Test condition Ty 25 C 40 to 85 C Unit Min Typ Max Min Max Quiescent 7 _ VseL Voc or E lec supply current 1 65 4 3 1 65 4 3 GND 0 05 0 05 0 2 0 2 pA SEL leakage _ _ VseL 4 3Vor _ IseL cuen 1 65 4 3 1 65 4 3 GND 0 2 0 2 2 2 uA 1 ARon Ronmmax Ronin 2 Flatness is defined as the difference between the maximum and minimum value of on resistance as measured over the specified analog signal ranges Table 7 AC electrical characteristics C 35 pF RL 509 t t lt 5 ns Test conditions Value
4. PSSS nl SAL 1 E i I I I I i Sta o Vout 50 2 i I I I I I I 32 Nom A I Y I I I A IN GND i gt o s I Vs gig L fcd icis DA id ni Md emis Ad A tt ly i it 1 GND CS00381 Figure 9 Test circuit Vee PULSE GENERATOR RL SC08630 1 C 2 5 85 pF or equivalent includes jig capacitance 2 RL 2 50 Q or equivalent 3 Ry Zour of pulse generator typically 50 Q 12 19 2 STG4160 Test circuits Figure 10 Break before make time delay Veo sil D I Vour Vin 50 50 wo e GND 0814140 0314120 Figure 11 Switching time and charge injection VaEN 0 V RGEN 0Q R 1 MQ C 100 pF GND ton 90 90 IN D 7 Vour AV our l o Q AVgur XC dh e gp 814130 CSOB710 Figure 12 Turn ON turn OFF delay time Voc Voc SI GND Spa E IN Ll L Vin GND 0514150 CS08720 Y 13 19 Package mechanical data STG4160 6 14 19 Package mechanical data In order to meet environmental requirements ST offers these devices in ECOPACK packages These packages have a Lead free second level interconnect The category of second Level Interconnect is marked on the package and on the inner box label in compliance with JEDEC Standard JESD97 The maximum ratings related
5. S2 Independent channel 4 VL Logic supply voltage 5 Voc Positive supply voltage 6 SEL Control 7 D Common channel 8 GND Ground 0 V IST 3 19 Logic diagram STG4160 2 4 19 Logic diagram Figure 2 Functional diagram S1 D S2 SEL Figure 3 Circuit equivalent logic D S2 S1 SEL Table 3 Truth table SEL Switch S1 Switch S2 H ON OFF 1 L OFF 1 ON 1 High impedance STG4160 Maximum ratings 3 Y Maximum ratings Stressing the device above the rating listed in the Absolute maximum ratings table may cause permanent damage to the device These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not implied Exposure to Absolute maximum rating conditions for extended periods may affect device reliability Refer also to the STMicroelectronics SURE Program and other relevant quality documents Table 4 Absolute maximum ratings Symbol Parameter Value Unit Voc Supply voltage 0 5 to 5 5 V VL Logic supply voltage 0 5 to 5 5 V VI DC input voltage 0 5 to Voc 0 5 V Vic DC control input voltage 0 5 to V 5 5 V Vo DC output voltage 0 5 to Vcc 0 5 V likc DC input diode current on control pin Vsg lt 0 V 50 mA lik DC input diode current Vse
6. to soldering conditions are also marked on the inner box label ECOPACK is an ST trademark ECOPACK specifications are available at www st com Figure 13 Flip chip 8 package outline E f ui a z A O A I E 3 4 Ng Al see note 1 Bottom view pini ma FXICCC U ni lt L OU lt L D Top view 1 Drawing not to scale STG4160 Package mechanical data Table 9 Flip chip 8 mechanical data Millimeters Symbol Min Typ Max A 0 535 0 58 0 625 Al 0 18 0 205 0 23 A2 0 355 0 375 0 395 0 215 0 255 0 295 D 1 85 1 9 1 95 D1 1 5 0 45 0 5 0 55 E 0 85 0 9 0 95 E1 0 45 0 5 0 55 SE 0 25 f 0 19 0 2 0 21 ccc 0 08 Figure 14 Flip chip 8 footprint 1 5 O BIOOO GRID PLACEMENT AREA 0 22 15 19 Package mechanical data STG4160 Figure 15 Flip chip 8 tape and reel 4 00 0 10 1 50 10 4 00 0 10 1 75 10 10 L Figure 16 Tape orientation User direction of feed _ gt AM00745V1 n ST STG4160 Package mechanical data Figure 17 Reel information o 3 n A E u a 3 j lI ll n SEE DETAIL e SECTION B B SEE DETAIL K K DETAIL SCALE 5 000 max min max 14 4 7 9 10 9
7. Symbol Parameter Voc VL TA 25 C 40 to 85 C Unit V v Min Typ Max Min Max 1 65 1 95 0 18 t t Propagation 2 3 2 7 1 65 0 14 BE PLH PHL delay 30 33 43 0 12 3 6 4 3 0 12 1 65 1 95 70 123 160 2 3 2 7 465 e Vcc 48 62 80 toN TURN ON time 4 3 RL 50 Q ns 3 3 6 i C 30 pF 33 43 56 4 3 29 38 49 1 65 1 95 36 45 60 TURN OFF 2 3 2 7 465 VYs Vee 35 47 62 torr time a 3 RL 500 ns 3 3 6 i C 30 pF 30 40 51 4 3 29 38 50 1 65 1 95 10 42 Break before 23 27 C 35 pF 10 29 A 1 65 _ to make time 43 R 50 O ns s cc 4 3 5 12 ky 7 19 Electrical characteristics STG4160 Table 7 AC electrical characteristics C 35 pF RL 50 Q t t lt 6 ns continued Test conditions Value Symbol Parameter Vee VL Ta 25 C 40 to 85 C Unit v V Min Typ Max Min Max 1 65 1 95 75 Q Charge 23 27 165 CL 1nF 98 C injection 380 33 3 Veen 0V 133 3 6 4 3 162 Vs 1 Vnus 77 f 100 kHz Vs 1V OIRR Off isolation 165 43 43 S AMS 67 dB f 1 MHz Vs 1Vrms f 5 MHz 39 Vs 1Vrms f 100 kHz d Vs 1V Xtalk Crosstalk 1 65 4 3 4 3 9 RMS 67 dB f 1 MHz Vs 1Vams f 5 MHz 50 RL 600Q C 50 pF Total harmonic THB n 2 3 4 3 43 Vs Vcc 0 01 o f 600 Hz to 20 kHz 3dB Bandwidth 5 BW switch ON 1 65 4 3 4 3 RL 50 0 50 MHz 1 OFF isolation 20 logo VD VS Vp output Vs input to off swi
8. h and OFF high impedance state exists between the two ports when SEL is held low The switch S2 is ON connected to common Port D when the SEL input is held low and OFF high impedance state exist between the two ports when SEL is held high Additional key features are fast switching speed break before make delay time and ultra power consumption All inputs and outputs are equipped with protection circuits against static discharge giving them ESD immunity and transient excess voltage Table 1 Device summary Order code Package Packing STG4160BJR Flip chip 8 Tape and reel February 2009 Rev 2 1 19 www st com Contents STG4160 Contents 1 Pin Settings Tr 3 1 1 Fin COMMOCIONS ss la TT 3 1 2 Pin description ee OR AA e a DERE ee 3 2 Logic diagram cir a A UU 8 da NC a 4 3 Maximum ratings io a AA a 5 4 Electrical characteristics leeeeeee 6 5 Test CIFGUIES 00 caca eee RR EROR eee i ORE NC S OS NN ee 10 6 Package mechanical data lssss s ss 14 7 REVISION history uino exkeesasauszaaa a wee 16 2 19 SI STG4160 Pin settings 1 Pin settings 1 1 Pin connections Figure 1 STG4160 pin connections Bump View Top View u O O vec s 216 Os GND ew JO Ofo s2 st GND VL CS00028 1 2 Pin description Table 2 Pin assignment Pin number Symbol Name and function 1 S1 Independent channel 2 GND Ground 0 V 3
9. lectronics All other names are the property of their respective owners 2009 STMicroelectronics All rights reserved STMicroelectronics group of companies Australia Belgium Brazil Canada China Czech Republic Finland France Germany Hong Kong India Israel Italy Japan Malaysia Malta Morocco Singapore Spain Sweden Switzerland United Kingdom United States of America www st com 19 19 4
10. lt OV 50 mA lok DC output diode current 20 mA lo DC output current 300 mA lop DC output current peak pulse at 1ms 10 duty cycle 500 mA Icc Or lann DC Voc or ground current 100 mA Pp Power dissipation at Ta 70 C 1 500 mW Tstg Storage temperature 65 to 150 C TL Lead temperature 10 sec 260 C 1 Derate above 70 C by 18 5 mW C Table 5 Recommended operating conditions Symbol Parameter Value Unit Voc Supply voltage 1 65 to 4 8 V VL Logic supply voltage 1 65 to Voc V VI Input voltage 0 to Voc V Vic Control input voltage Oto VL V Vo Output voltage 0 to Vec V Top Operating temperature 40 to 85 C avdv Put rise and fall time control VL 1 65 to 2 7 V 0 to 20 ns V input VL 3 0 to 4 8 V 0 to 10 1 V pin should not be left floating 5 19 Electrical characteristics STG4160 4 Electrical characteristics Table 6 DC specifications Value Vcc VL o o i Symbol Parameter V V Test condition Ty 25 C 40 to 85 C Unit Min Typ Max Min Max 1 65 1 95 1 25 1 25 23 27 1 75 1 75 Yi oe wae 1 65 4 3 V input voltage 3 0 3 6 2 34 2 34 4 3 2 80 2 80 1 65 1 95 0 6 0 6 2 3 2 7 0 8 0 8 Vie EA 1 65 4 3 V input voltage 3 0 3 6 1 05 1 05 4 3 1 5 1 5 1 8 1 5 25 3 7 2 25 Vs 0 V to 0 75 1 0 1 3 RoN ON resistance 3 1 65 4 3 Vcc
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12. tch 8 19 2 STG4160 Electrical characteristics Table 8 Capacitive characteristics Test condition Value Symbol Parameter Ved VL Ty 25 C 40 to 85 C Unit V V Min Typ Max Min Max Control pin CseL input 1 8 43 1 8 4 3 VL Voc 30 pf capacitance C Sn port 18 43 18 43 V V 94 pf SN capacitance i I5 CC D port capacitance _ n Cp when the switch 1 87 43 1 8 4 3 VL Vcc 227 pf is enabled IST 9 19 Test circuits STG4160 5 Test circuits Figure 4 ON resistance los Voc O st D VS l s2 0 IN GND o0 e e O GND CS14071 Figure 5 Bandwidth Voc EAN DO UBL USE EE 7 I I I I D Sto o Vour I I 500 I I I g om A I T pes I I Vs CJ V NE Ll o m Poe oedema E FRS i GND CS00371 n ST STG4160 Test circuits Figure 6 OFF leakage Yoo S OFF D oFF Cp MN A A 1 SS Vo TO s2 IN Voc gt o ee GND CS14081 Figure 7 Channel to channel crosstalk Vac S1 D Vout O 500 EE CS14091 11 19 Test circuits STG4160 Figure 8 OFF isolation Yoo
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ST STG4160 handbook